Multi-chip parallel power module

Abstract

The invention provides a multi-chip parallel power module. The multi-chip parallel power module comprises a substrate, power chips, connecting pieces, power terminals, signal terminals and a plastic package body, the power chip is arranged on the substrate and comprises an upper bridge chip set and a lower bridge chip set which are arranged at intervals in the length direction of the substrate, each of the upper bridge chip set and the lower bridge chip set comprises two columns of chip sets which are arranged at intervals in the width direction of the substrate, and each column of chip set comprises at least two chip units which are arranged at intervals in the length direction; the two groups of connecting pieces are arranged on the sides, away from the substrate, of the power chips, the two groups of connecting pieces correspond to the upper bridge chip set and the lower bridge chip set respectively, the periphery of each group of connecting pieces is connected with the corresponding chip units in parallel, and the middle of each group of connecting pieces is located between the two rows of chip sets and connected with the corresponding power terminals. The multi-chip parallel power module provided by the invention is simple in structure, can give consideration to current-sharing balance and space utilization rate, and improves the performance efficiency of the module.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a multi-chip parallel power module. Background Technology

[0002] Power modules are industrial products composed of power semiconductor devices combined according to their circuit functions and then encapsulated. Their core functions are power conversion and control. They are widely used in new energy vehicle drive systems, photovoltaic inverters, wind power generation converters, and base station power supplies, and are also compatible with frequency converters and other equipment in the consumer electronics, industrial control, and home appliance industries.

[0003] To achieve higher output current and power density, parallel connection of multiple chips has become a common solution. However, current power modules with multiple chips in parallel face the challenge of current sharing. Inconsistent parameters between parallel branches can easily lead to uneven current distribution, causing uneven heating between chips. Localized overheating of the module may lead to thermal failure, and the overall output current capability of the module is limited by the hottest chip, affecting the module's application. In addition, the layout of multiple chips in parallel increases the space occupied, affecting the module's size design. Therefore, there is an urgent need for a multi-chip parallel power module that balances current sharing and space utilization. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a multi-chip parallel power module to solve or partially solve the above-mentioned technical problems.

[0005] This application provides a multi-chip parallel power module, comprising: a substrate, power chips, connectors, power terminals, signal terminals, and a molding compound; the power chips are disposed on the substrate and include an upper bridge chip set and a lower bridge chip set spaced apart along the length direction of the substrate, each of the upper and lower bridge chip sets including two rows of chip groups spaced apart along the width direction of the substrate, each row of chip groups including at least two chip units spaced apart along the length direction; the power terminals include an output terminal located at the first short side of the substrate, and a position... The positive and negative input terminals are located at the second short side of the substrate; the connectors are in two sets, both disposed on the side of the power chip away from the substrate, and the two sets of connectors correspond to the upper bridge chip set and the lower bridge chip set respectively. The outer periphery of each set of connectors is connected in parallel with the corresponding chip unit; the middle part of each set of connectors is located between the two columns of chip sets, the middle part of the connector corresponding to the upper bridge chip set is connected to the output terminal, and the middle part of the connector corresponding to the lower bridge chip set is connected to the negative input terminal.

[0006] Furthermore, the signal terminal includes a first gate terminal, a first source terminal, a first drain terminal, a second gate terminal, a second source terminal, and a second drain terminal; the first gate terminal, the first source terminal, and the first drain terminal are all located at the first short side, and the second gate terminal, the second source terminal, and the second drain terminal are all located at the second short side.

[0007] Furthermore, the signal terminal also includes a first detection terminal and a second detection terminal, both of which are located at the first short side; a temperature sensor is provided on the substrate, and the temperature sensor is connected to the first detection terminal and the second detection terminal respectively.

[0008] Furthermore, the chip unit includes a substrate, a source, a gate, and a drain. The source and the gate are both located on the side of the substrate away from the substrate, and the drain is located on the side of the substrate close to the substrate. The substrate includes a first conductive layer, an insulating layer, and a second conductive layer stacked together. The first conductive layer is disposed close to the power chip, and the drain is connected to the first drain terminal or the second drain terminal through the first conductive layer.

[0009] Furthermore, the connector is connected to the source terminal of the chip unit, and a lead is connected to the connector, which is connected to the first source terminal or the second source terminal.

[0010] Furthermore, both the upper bridge chip set and the lower bridge chip set include four chip units, and the arrangement direction of the chip units in the upper bridge chip set is the same as or perpendicular to the arrangement direction of the chip units in the lower bridge chip set.

[0011] Furthermore, in the upper bridge chip set or the lower bridge chip set, adjacent columns of the chip sets are arranged aligned or staggered.

[0012] Furthermore, each set of connectors is an integral symmetrical structure, and the structures of the two sets of connectors are the same or different; or, each set of connectors includes two oppositely arranged connecting units, each connecting unit is a symmetrical structure, and the structures of the two connecting units are the same or different, and the structures of the two sets of connectors are the same or different.

[0013] Furthermore, each set of connectors is an X-shaped structure, with its four branches connected to the four chip units respectively, and its middle section connected to the substrate between the two rows of chip groups; or, each set of connectors is an O-shaped structure, with its outer periphery connected to the four chip units respectively, and its middle section connected to the substrate between the two rows of chip groups; or, each set of connectors is a T-shaped structure, with its crossbeams connected to the four chip units respectively, and its longitudinal beam extending to the edge of the substrate and connected to the power terminal.

[0014] Furthermore, each set of connectors includes two opposing C-shaped structures. The body of each C-shaped structure is connected to two chip units, and the two extensions of each C-shaped structure are connected to the substrate between the two columns of chip groups. Alternatively, each set of connectors includes opposing C-shaped and Y-shaped structures. The body of each C-shaped structure is connected to two chip units, and the two extensions of the C-shaped structure are connected to the substrate between the two columns of chip groups. The two forks of the Y-shaped structure are connected to two chip units, and the legs of the Y-shaped structure are connected to the substrate between the two columns of chip groups.

[0015] As can be seen from the above description, this application provides a multi-chip parallel power module, including: a substrate, power chips, connectors, power terminals, signal terminals, and a molding compound; the power chips are disposed on the substrate, including an upper bridge chip set and a lower bridge chip set spaced apart along the length direction of the substrate, each of the upper and lower bridge chip sets including two rows of chip groups spaced apart along the width direction of the substrate, each row of chip groups including at least two chip units spaced apart along the length direction; the power terminals include an output terminal located at the first short side of the substrate, and a positive input terminal and a negative input terminal located at the second short side of the substrate; there are two sets of connectors, both disposed on the side of the power chips away from the substrate, the two sets of connectors corresponding to the upper bridge chip set and the lower bridge chip set respectively, and the outer periphery of each set of connectors is connected in parallel with the corresponding chip unit; the middle part of each set of connectors is located between the two rows of chip groups, the middle part of the connector corresponding to the upper bridge chip set is connected to the output terminal, and the middle part of the connector corresponding to the lower bridge chip set is connected to the negative input terminal. By optimizing the arrangement of the upper and lower bridge chip sets, space utilization can be improved. By connecting the outer periphery of the connector to each chip unit in parallel, and the middle of the connector to the corresponding power terminal, parallel branches with similar paths can be easily formed, ensuring consistency in current path and heat dissipation, guaranteeing current sharing, and thus significantly improving the module's system efficiency, current carrying capacity, and service life. With each chip unit located on the outer periphery of the connector, and the current concentrating in the middle of the connector, the module's integration can be further enhanced. This multi-chip parallel power module has a simple structure, is easy to manufacture, and can balance current sharing and space utilization, improving the module's performance efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a three-dimensional structural diagram of a multi-chip parallel power module according to an embodiment of this application.

[0018] Figure 2 for Figure 1 An exploded view of the structure of a multi-chip parallel power module.

[0019] Figure 3 This is a schematic diagram of the connection structure of the first type of substrate in the embodiments of this application.

[0020] Figure 4 for Figure 3 A schematic diagram of the drive circuit path of the middle substrate.

[0021] Figure 5 for Figure 3 A schematic diagram of the converter circuit path on the middle substrate.

[0022] Figure 6 This is a schematic diagram of the connection structure of the second type of substrate in the embodiments of this application.

[0023] Figure 7 for Figure 6 A schematic diagram of the drive circuit path of the middle substrate.

[0024] Figure 8 for Figure 6 A schematic diagram of the converter circuit path on the middle substrate.

[0025] Figure 9 This is a schematic diagram of the connection structure of the third type of substrate in the embodiments of this application.

[0026] Figure 10 This is a schematic diagram of the connection structure of the fourth type of substrate in the embodiments of this application.

[0027] Figure 11 This is a schematic diagram of the connection structure of the fifth type of substrate in the embodiments of this application.

[0028] Figure 12 This is a schematic diagram of the connection structure of the sixth type of substrate in the embodiments of this application.

[0029] Figure 13 This is a schematic diagram of the connection structure of the seventh type of substrate in the embodiments of this application.

[0030] Figure 14 for Figure 3 A schematic diagram of the middle connector.

[0031] Figure 15 for Figure 6 A schematic diagram of the middle connector.

[0032] Reference numerals: 1. Substrate; 1-1. First short side; 1-2. Second short side; 2. Power chip; 2-1. Upper bridge chip assembly; 2-2. Lower bridge chip assembly; 3. Connector; 3-1. Support; 3-2. Crossbeam; 3-3. Longitudinal beam; 3-4. Body; 3-5. Extension; 3-6. Fork; 3-7. Leg; 4. Power terminal; 5. Signal terminal; 6. Molded enclosure; 7. Temperature sensor; 8. Lead-out portion. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0034] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by a person skilled in the art to which this application pertains. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0035] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] The following describes specific embodiments in conjunction with... Figures 1 to 15 The technical solution of this application will be described in detail below.

[0039] Some embodiments of this application provide a multi-chip parallel power module, such as... Figures 1 to 3As shown, the system includes: a substrate 1, a power chip 2, a connector 3, a power terminal 4, a signal terminal 5, and a molding compound 6. The power chip 2 is disposed on the substrate 1 and includes an upper bridge chip set 2-1 and a lower bridge chip set 2-2 spaced apart along the length direction of the substrate 1. Both the upper bridge chip set 2-1 and the lower bridge chip set 2-2 include two rows of chip groups spaced apart along the width direction of the substrate 1. Each row of chip groups includes at least two chip units spaced apart along the length direction. The power terminal 4 includes an output terminal AC located at the first short side 1-1 of the substrate 1 and an output terminal AC located at the second short side 1-1 of the substrate 1. The positive input terminal DC+ and the negative input terminal DC- are located at edge 1-2; the connector 3 consists of two sets, both disposed on the side of the power chip 2 away from the substrate 1. The two sets of connector 3 correspond to the upper bridge chip set 2-1 and the lower bridge chip set 2-2, respectively. The outer periphery of each set of connector 3 is connected in parallel with the corresponding chip unit; the middle part of each set of connector 3 is located between the two columns of chip sets. The middle part of the connector 3 corresponding to the upper bridge chip set 2-1 is connected to the output terminal AC, and the middle part of the connector 3 corresponding to the lower bridge chip set 2-2 is connected to the negative input terminal DC-.

[0040] like Figure 1 and Figure 2 The diagram shows the structure of a multi-chip parallel power module. The multi-chip parallel power module includes a substrate 1, power chips 2, connectors 3, power terminals 4, signal terminals 5, and a molding compound 6. The substrate 1 serves as a load-bearing component and enables electrical connections. The power chip 2, located on one side of the substrate 1, is also called a power semiconductor device and is a specific type of chip capable of handling higher voltages and currents. The connector 3, located on the side of the power chip 2 away from the substrate 1, is used for electrical connections. The connector 3 can be made of metal sheets or other forms, such as aluminum wire, copper wire, aluminum-clad copper wire, aluminum strip, or copper strip, etc. The power terminals 4, located on the side of the substrate 1 closest to the power chip 2, are used for power transmission. The signal terminals 5, also located on the side of the substrate 1 closest to the power chip 2, are used for signal transmission. The molding compound 6, located on the side of the connector 3 away from the substrate 1, covers the substrate 1, connectors 3, power chips 2, some of the power terminals 4, and some of the signal terminals 5, sealing the power module.

[0041] like Figure 3As shown in the figure, the L direction is the length direction of substrate 1, the W direction is the width direction of substrate 1, the short side below substrate 1 is the first short side 1-1, the short side above substrate 1 is the second short side 1-2, the output terminal AC is set on the first short side 1-1, and the positive input terminal DC+ and the negative input terminal DC- are set on the second short side 1-2.

[0042] The upper bridge chip assembly 2-1 and the lower bridge chip assembly 2-2, spaced apart along the length of the substrate 1, present a symmetrical structure. Each chip assembly includes two rows of chip groups spaced apart along the width of the substrate 1, providing space for the subsequent connection of the connector 3. Each row of chip groups includes at least two chip units spaced apart along the length. By optimizing the chip layout, space utilization can be improved, the overall module size can be effectively reduced, and not only costs can be reduced, but production yield can also be improved.

[0043] Connector 3 corresponds to the chip set and is connected in parallel to the corresponding chip unit, such as... Figure 5 As shown, on the one hand, an upper bridge circuit is formed by sequentially connecting the positive input terminal DC+, substrate 1, upper bridge chip set 2-1, connector 3, and output terminal AC, as indicated by the blue dashed line in the figure; on the other hand, a lower bridge circuit is formed by sequentially connecting the output terminal AC, substrate 1, lower bridge chip set 2-2, connector 3, and negative input terminal DC-, as indicated by the red dashed line in the figure. Their respective commutation (power) paths are short, have basically the same length, and are in opposite directions, which significantly reduces the parasitic inductance inside the module, helps to improve switching performance and system efficiency, and ensures excellent electrical and thermal performance while achieving high power density.

[0044] More importantly, this layout ensures the consistency of the branch paths in the upper and lower bridge circuits, improving dynamic and static current sharing characteristics. By setting the outer periphery of connector 3 to connect in parallel with each chip unit, and the middle part of connector 3 to connect with the corresponding power terminal 4, it is convenient to form parallel branches with similar paths, achieving consistency in current path and heat dissipation, ensuring current sharing effect, and thus significantly improving the system efficiency, current carrying capacity, and service life of the module. With each chip unit located on the outer periphery of connector 3, and the current concentrating in the middle of connector 3, the integration of the module can be further improved.

[0045] This multi-chip parallel power module has a simple structure and is easy to manufacture. It can balance current sharing and space utilization, thereby improving the module's performance and efficiency.

[0046] In some embodiments, such as Figure 3As shown, the signal terminal 5 includes a first gate terminal G1, a first source terminal S1, a first drain terminal D1, a second gate terminal G2, a second source terminal S2, and a second drain terminal D2; the output terminal AC is located at one end of the first short side 1-1, the first gate terminal G1, the first source terminal S1, and the first drain terminal D1 are all located at the first short side 1-1, and the first drain terminal D1 is located at the other end of the first short side 1-1; the positive input terminal DC+ and the negative input terminal DC- are both located near one end of the second short side 1-2, the second gate terminal G2, the second source terminal S2, and the second drain terminal D2 are all located at the second short side 1-2, and the second drain terminal D2 is located at the other end of the second short side 1-2.

[0047] A first drain terminal D1 is set at one end of the first short side 1-1, and an output terminal AC is set at the other end. The first gate terminal G1 and the first source terminal S1 can be randomly set between them. A positive input terminal DC+ or a negative input terminal DC- is set at one end of the second short side 1-2, and a second drain terminal D2 is set at the other end. The second gate terminal G2 and the second drain terminal D2 can be randomly set between them.

[0048] The positive input terminal DC+ and the negative input terminal DC- are arranged side-by-side on the same plane. Their width is determined by the current carrying capacity and the lower limit of the laser welding process, jointly constraining the minimum size of the module in the width direction. This greatly simplifies the laser welding process of the external copper busbar, enhancing module assembly efficiency and structural robustness. The drain terminal is located on the outermost side of the module, requiring only a single-sided electrical clearance, effectively reducing the overall module size, lowering the risk of delamination in the plastic encapsulation, and thus improving production yield. The electrical clearance can be, for example, greater than or equal to 3mm, and is not specifically limited. The distance between the positive input terminal DC+ and the negative input terminal DC- can be set to 3mm, the distance between the second drain terminal D2 and the second gate terminal G2 can be set to 3mm, and the distance between the first drain terminal D1 and the first detection terminal T1 can be set to 3mm. The distances of other terminals can be set even smaller, for example, 1.5mm, maximizing the compression of the module width while ensuring safe spacing.

[0049] In some embodiments, such as Figure 3 As shown, the signal terminal 5 further includes a first detection terminal T1 and a second detection terminal T2. The first detection terminal T1 and the second detection terminal T2 are both located at the first short side 1-1 and between the first drain terminal D1 and the output terminal AC. A temperature sensor 7 is provided on the substrate 1, and the temperature sensor 7 is connected to the first detection terminal T1 and the second detection terminal T2 respectively.

[0050] Temperature sensor 7 is, for example, an NTC (Negative Temperature Coefficient) thermistor. The temperature sensor 7 is packaged in a surface mount form, which, compared to conventional glass packaging, has a shorter heat transfer path, faster response speed, higher sensitivity, and occupies less area, thus saving more space.

[0051] like Figure 3 As shown, a first detection terminal T1 and a second detection terminal T2 are provided at the first short side 1-1 for temperature detection. The first detection terminal T1 and the second detection terminal T2 can be set between the output terminal AC and the first drain terminal D1 as needed to improve integration. The module has a built-in temperature sensor 7, and drain terminals are led out from the outermost side of the substrate 1 for real-time monitoring of the source-drain voltage drop to achieve short-circuit protection. This integrated design eliminates the need for external circuitry, enhancing module functionality and improving measurement accuracy and reliability.

[0052] In some embodiments, such as Figure 3 As shown, the chip unit includes a substrate, a source, a gate, and a drain. The source and the gate are both located on the side of the substrate away from the substrate 1, and the drain is located on the side of the substrate closer to the substrate 1. The substrate 1 includes a first conductive layer, an insulating layer, and a second conductive layer stacked together. The first conductive layer is disposed close to the power chip 2, and the drain is connected to the first drain terminal D1 or the second drain terminal D2 through the first conductive layer.

[0053] like Figure 3 As shown, the chip unit is a three-terminal semiconductor power device, including a source, a gate, and a drain. The source and gate are disposed away from substrate 1, while the drain is disposed close to substrate 1. Figure 2 As shown, substrate 1 includes a first conductive layer, an insulating layer, and a second conductive layer stacked together. The conductive layer is, for example, a copper-clad layer, and the insulating layer is, for example, a ceramic layer. The thicknesses of the two conductive layers can be the same or different. The first conductive layer achieves electrical isolation by forming a pattern through etching trenches. The drain of the chip unit is connected to the first conductive layer to achieve a drive circuit connection. The power terminal 4 is also connected to the first conductive layer to achieve a commutation circuit (power circuit) connection. Connection methods include, but are not limited to, soldering, silver sintering, etc.

[0054] In some embodiments, such as Figure 3 As shown, the gate is connected to the first gate terminal G1 or the second gate terminal G2 via a bonding wire, further improving the integration density.

[0055] In some embodiments, such as Figure 3 and Figure 4As shown, the connector 3 is connected to the source of the chip unit, and a lead-out portion 8 is connected to the connector 3. The lead-out portion 8 is connected to the first source terminal S1 or the second source terminal S2.

[0056] The module layout and connection methods in related technologies may introduce a large parasitic inductance of the drive circuit (the stray inductance Lg of the drive circuit superimposed on the stray inductance Ls of the power circuit) due to differences in the path, thereby aggravating the gate oscillation effect and potentially causing the chip to mis-circuit or even the module to short-circuit and fail.

[0057] In this embodiment, a lead-out portion 8 is connected to the connector 3. The lead-out portion 8 can be, for example, a bonding wire, or alternatively, aluminum wire, copper wire, aluminum-clad copper wire, aluminum strip, or copper strip. The chip unit is connected to the source electrode via the connector 3, and the lead-out portion 8 is connected to the connector 3. The source electrode is also connected to the lead-out portion 8, thus achieving the connection between the chip unit and the power terminal 4, forming a drive circuit as follows: Figure 4 As shown by the red line, the current is input from the gate terminal and output from the source terminal. By setting the lead-out section 8, the drive circuit and the power circuit are physically decoupled. The drive current is mainly concentrated inside the lead-out section 8, isolated from the connector 3. In this way, the stray inductance Lg of the drive circuit will not be superimposed on the stray inductance Ls of the power circuit. This design isolates the parasitic coupling path between the drive circuit and the power circuit, thereby significantly reducing the stray inductance of the drive circuit. This not only suppresses gate oscillation but also ensures the switching synchronization of each parallel chip unit, further consolidating the current sharing effect and switching efficiency.

[0058] Meanwhile, the optimized drive signal is directly led out through lead-out section 8, forming a shorter current path. The shortened path further minimizes stray inductance in the circuit, effectively suppressing gate voltage oscillations and switching waveform overshoot caused by stray inductance, and improving the stability and response speed of gate control.

[0059] In some embodiments, the output terminal AC and the first source terminal S1 are an integrated structure, and / or the negative input terminal DC- and the second source terminal S2 are an integrated structure.

[0060] like Figure 3 As shown, the power terminal 4 and the source terminal are integrated into a metal sheet structure, which further improves the integration and facilitates connection.

[0061] In some embodiments, such as Figure 3 , Figure 12 and Figure 13 As shown, both the upper bridge chip set 2-1 and the lower bridge chip set 2-2 include four chip units. The arrangement direction of the chip units in the upper bridge chip set 2-1 is the same as or perpendicular to the arrangement direction of the chip units in the lower bridge chip set 2-2.

[0062] like Figure 3 As shown, in this embodiment, the length direction of the chip unit is perpendicular to the length direction of the substrate 1, which can effectively reduce the length of the substrate 1, and the layout is more symmetrical and has a high degree of integration.

[0063] like Figure 13 As shown, in this embodiment, the length direction of the chip units is parallel to the length direction of the substrate 1. Although the layout is relatively symmetrical, it is still different from the previous embodiment. Figure 3 The embodiment significantly increases the length of substrate 1, and additional groove patterns need to be formed on substrate 1 for the gate connection of the chip unit, which also increases the width of substrate 1. Figure 3 The example takes up a large amount of space.

[0064] like Figure 12 As shown, in this embodiment, the length direction of the chip units in the upper bridge chip set 2-1 is parallel to the length direction of the substrate 1, and the length direction of the chip units in the lower bridge chip set 2-2 is perpendicular to the length direction of the substrate 1. Similarly, relative to... Figure 3 The embodiment increases the length of substrate 1, and requires additional etched patterns on substrate 1 for the gate connection of the chip units in the upper bridge chip assembly 2-1, which also increases the width of substrate 1. Figure 3 The embodiment occupies a large space and has poor layout symmetry, which affects both current equalization and inductance.

[0065] In some embodiments, such as Figure 3 and Figure 11 As shown, in the upper bridge chip set 2-1 or the lower bridge chip set 2-2, adjacent columns of the chip sets are arranged aligned or staggered.

[0066] like Figure 3 As shown, the chipsets in this embodiment are all aligned, occupy less space, have high integration, and have a relatively symmetrical layout, which is conducive to current sharing among the parallel branches.

[0067] like Figure 11 As shown, the chipset in this embodiment is arranged in an interleaved manner, relative to... Figure 3 The embodiment slightly extends the length of the substrate 1 and weakens the layout symmetry. It places higher demands on the connector 3 and the groove pattern, making it difficult to ensure that the paths of each parallel branch are completely consistent, and the current sharing effect is relatively affected.

[0068] In some embodiments, such as Figure 3 , Figure 6 , Figure 10 , Figure 12 As shown, each set of connectors 3 is an integral symmetrical structure, and the structures of the two sets of connectors 3 may be the same or different.

[0069] like Figure 3 , Figure 6 , Figure 10 , Figure 12 As shown, connector 3 is an integrated symmetrical structure, which physically ensures that the current paths of each parallel chip unit in the assembly have extremely low and consistent parasitic parameters. This directly translates into excellent static and dynamic current sharing characteristics, effectively suppressing local overheating and performance bottlenecks caused by current imbalance. Furthermore, it ensures that the gate drive circuit structure of each parallel chip branch remains basically consistent, guaranteeing that the timing and impedance characteristics of the drive signal reaching each chip are basically matched. This results in near-synchronous switching times for each parallel chip unit in the assembly, leading to a more uniform distribution of switching losses. This characteristic not only optimizes dynamic current sharing performance and avoids instantaneous current imbalance caused by switching time differences, but also effectively reduces gate crosstalk between chips, suppressing the superposition effect of gate oscillations from a mechanistic perspective, and ensuring the reliability of the module during high-speed switching operation.

[0070] like Figure 3 , Figure 6 , Figure 10 As shown, the two sets of connectors 3 have identical structures, thus achieving complete reuse of the manufacturing mold and significantly reducing manufacturing costs and process complexity. Furthermore, it ensures that the current paths of all chip units have extremely low and consistent parasitic parameters, guaranteeing the stability of the module application.

[0071] like Figure 12 As shown, the structural size of the connector 3 corresponding to the upper bridge chip set 2-1 is larger than that of the connector 3 corresponding to the lower bridge chip set 2-2, in order to adapt to the layout requirements of the chip unit. However, compared with the embodiment where the connector 3 structure is consistent, the current sharing effect is relatively affected.

[0072] In some embodiments, such as Figure 9 and Figure 11 As shown, each set of connectors 3 includes two connecting units arranged opposite each other. Each connecting unit is a symmetrical structure. The structures of the two connecting units are the same or different, and the structures of the two sets of connectors 3 are the same or different.

[0073] like Figure 9 and Figure 11 As shown, connector 3 includes two oppositely arranged connection units to accommodate the layout requirements of chip cells. Each connection unit has a symmetrical structure to ensure consistent connection to chip cells within the same chipset. Figure 9 As shown, the two connecting units have different structures, which can improve space utilization. Figure 11 As shown, the two connecting units have the same structure, allowing for complete reuse in mold making. The two sets of connecting parts 3 in the module may have the same or different structures, which can be selected according to requirements.

[0074] In some embodiments, such as Figure 3 As shown, each of the connectors 3 is an X-shaped structure. The four branches 3-1 of the X-shaped structure are respectively connected to the four chip units, and the middle part of the X-shaped structure is connected to the substrate 1 between the two columns of chip groups.

[0075] like Figure 3 As shown, the first conductive layer of substrate 1 includes a first pattern a, a second pattern b, a third pattern c, a fourth pattern d, a fifth pattern e, a sixth pattern f, a seventh pattern g, and an eighth pattern h. The first pattern a is connected to the positive input terminal DC+, the chipset on the left side of the upper bridge, the sixth pattern f, and the first drain terminal D1. The second pattern b is connected to the connector 3 of the lower bridge. The third pattern c is connected to the fifth pattern e, the second gate terminal G2, and the chipset on the right side of the lower bridge. The fourth pattern d is connected to the lower bridge chip assembly 2-2, the output terminal AC, and the first source terminal S1. The fifth pattern e is connected to the third pattern c and the chipset on the left side of the lower bridge. The sixth pattern f is connected to the chipset on the right side of the upper bridge and the first pattern a. The seventh pattern g is connected to the chipset on the left side of the upper bridge, the eighth pattern h, and the first gate terminal G1. The eighth pattern h is connected to the seventh pattern g and the chipset on the right side of the upper bridge.

[0076] In this embodiment, the connectors 3 are all X-shaped metal sheet structures, which can achieve mold sharing and significantly reduce mold opening and manufacturing costs. Figure 4 As shown, the driving circuit forming the dashed line in the figure further reduces the size of substrate 1.

[0077] In this embodiment, the temperature sensor 7 is placed at the corner, near the upper bridge chip assembly 2-1, and connected to the corresponding detection end through a bonding wire. This allows its heat conduction path to form a better coupling with the heat source of the power chip 2, which avoids measurement inaccuracies caused by direct impact from the high-temperature heat source and can quickly respond to the average temperature change of the module, achieving a high balance between protection speed and measurement accuracy.

[0078] like Figure 5 As shown, this embodiment forms an upper bridge circuit consisting of a positive input terminal DC+, a first pattern a and a sixth pattern f, an upper bridge chip set 2-1, an upper bridge connector 3, a fourth pattern d, and an output terminal AC, and a lower bridge circuit consisting of an output terminal AC, a fourth pattern d, a lower bridge chip set 2-2, a lower bridge connector 3, a second pattern b, and a negative input terminal DC-. The overall commutation loop is short, the paths are similar, and the stray inductance is low. The paths of each chip unit are symmetrical, so that the current path parameters flowing through each parallel chip unit are highly consistent, thereby achieving excellent static and dynamic current sharing performance.

[0079] like Figure 14As shown, the X-shaped connectors 3 are distributed in a centrally symmetrical manner. The four branches 3-1 of the X-shaped structure can be connected to the four chip units respectively, and the middle part of the X-shaped structure can be connected to the substrate 1 between the two rows of chips. To ensure welding quality and balance stress, both the welding part and the bending part of the connector 3 are provided with an opening structure.

[0080] In some embodiments, such as Figure 10 As shown, each of the connectors 3 is an O-shaped structure. The outer periphery of the O-shaped structure is connected to the four chip units respectively, and the middle part of the O-shaped structure is connected to the substrate 1 between the two columns of chip groups.

[0081] like Figure 10 As shown, the first conductive layer of substrate 1 includes a first pattern a, a second pattern b, a third pattern c, a fourth pattern d, a fifth pattern e, a sixth pattern f, a seventh pattern g, and an eighth pattern h. The specific connection method of the patterns is shown in the figure, which will not be described in detail here.

[0082] In this embodiment, the connectors 3 are all O-type metal sheet structures, which can realize mold sharing. The outer periphery of the O-type structure is connected to the four chip units respectively, and the middle part of the O-type structure is connected to the substrate 1 between the two rows of chip groups. However, there are two connection areas in the middle of the connector 3, which will increase the welding cost.

[0083] In some embodiments, such as Figure 6 As shown, each of the connecting members 3 is a T-shaped structure. The crossbeam 3-2 of the T-shaped structure is connected to the four chip units respectively. The longitudinal beam 3-3 in the middle of the T-shaped structure extends to the edge of the substrate 1 and is connected to the power terminal 4.

[0084] like Figure 6 As shown, the first conductive layer of substrate 1 includes only the first pattern a, the second pattern b, the third pattern c, the fourth pattern d, and the fifth pattern e. The specific connection method of the patterns is shown in the figure, which will not be described in detail here.

[0085] In this embodiment, the connectors 3 are all T-shaped metal sheet structures, which can achieve mold sharing and significantly reduce mold opening and manufacturing costs. Figure 7 As shown, the driving circuit forming the dashed line in the figure further reduces the size of substrate 1.

[0086] like Figure 8As shown, this embodiment forms an upper bridge circuit consisting of a positive input terminal DC+, a first pattern a, an upper bridge chip set 2-1, an upper bridge connector 3, a fourth pattern d, and an output terminal AC, and a lower bridge circuit consisting of an output terminal AC, a fourth pattern d, a lower bridge chip set 2-2, a lower bridge connector 3, a second pattern b, and a negative input terminal DC-. The overall commutation loop is short, the paths are similar, and the stray inductance is low. The paths of each chip unit are symmetrical, so that the current path parameters flowing through each parallel chip unit are highly consistent, thereby achieving excellent static and dynamic current sharing performance.

[0087] like Figure 15 As shown, the T-shaped connectors 3 are distributed in an axially symmetrical manner. The crossbeams 3-2 of the T-shaped structure can be connected to four chip units respectively. Specifically, four connecting structures can be extended from the crossbeams 3-2 to connect with the corresponding chip units. The longitudinal beams 3-3 in the middle of the T-shaped structure can extend to the edge of the substrate 1 and connect with the power terminals 4. This can save some of the groove patterns on the substrate 1, reduce the difficulty of patterning, and further reduce the size of the substrate 1.

[0088] like Figure 15 As shown, in addition to the opening structures in the welded and bent sections, the connector 3 can also incorporate a strip-shaped slotted structure in the longitudinal beam 3-3. This design, in conjunction with the openings in the welded and bent sections, forms a three-dimensional interlocking network that runs through the critical area of ​​the connector 3. When the material of the molding compound 6 is injected, it passes through these structures to form multi-dimensional "mechanical rivets," thereby providing a more uniform and stronger anchoring force at the interface between the connector 3 and the molding compound 6, effectively suppressing interface delamination caused by CTE (coefficient of thermal expansion) mismatch.

[0089] In some embodiments, such as Figure 11 As shown, each set of connectors 3 includes two C-shaped structures arranged opposite each other. The body 3-4 of each C-shaped structure is connected to two chip units respectively, and the two extensions 3-5 of each C-shaped structure are connected to the substrate 1 between the two rows of chip groups respectively.

[0090] like Figure 11 As shown, the first conductive layer of substrate 1 includes a first pattern a, a second pattern b, a third pattern c, a fourth pattern d, a fifth pattern e, a sixth pattern f, a seventh pattern g, and an eighth pattern h. The specific connection method of the patterns is shown in the figure, which will not be described in detail here.

[0091] In this embodiment, the connectors 3 are all C-shaped metal sheet structures, which can realize mold sharing. The body 3-4 of each C-shaped structure is connected to two chip units respectively, and the two extensions 3-5 of each C-shaped structure are connected to the substrate 1 between the two rows of chips. However, there are four connection areas in the middle of the connector 3, which will increase the welding cost. In addition, the two C-shaped structures are misaligned, which will affect the current sharing effect.

[0092] In some embodiments, such as Figure 9 As shown, each set of connectors 3 includes a C-shaped structure and a Y-shaped structure arranged opposite to each other. The body 3-4 of the C-shaped structure is connected to two chip units respectively, and the two extensions 3-5 of the C-shaped structure are connected to the substrate 1 between the two rows of chip groups. The two forks 3-6 of the Y-shaped structure are connected to two chip units respectively, and the legs 3-7 of the Y-shaped structure are connected to the substrate 1 between the two rows of chip groups.

[0093] like Figure 9 As shown, the first conductive layer of substrate 1 includes a first pattern a, a second pattern b, a third pattern c, a fourth pattern d, a fifth pattern e, a sixth pattern f, a seventh pattern g, and an eighth pattern h. The specific connection method of the patterns is shown in the figure, which will not be described in detail here.

[0094] In this embodiment, each set of connectors 3 includes a C-shaped metal sheet structure and a Y-shaped metal sheet structure arranged opposite to each other. The structural differences result in higher mold costs. The body 3-4 of the C-shaped structure is connected to two chip units respectively, and the two extensions 3-5 of the C-shaped structure are connected to the substrate 1 between the two rows of chip groups respectively. The two forks 3-6 of the Y-shaped structure are connected to two chip units respectively, and the legs 3-7 of the Y-shaped structure are connected to the substrate 1 between the two rows of chip groups. However, there are three connection areas in the middle of the connector 3, which increases the welding cost. In addition, the differences in the connection units will affect the current sharing effect.

[0095] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0096] Furthermore, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the apparatus may be shown in block diagram form. This is to prevent the embodiments of this application from being difficult to understand, and it also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In setting forth specific details to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0097] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0098] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A multi-chip parallel power module, characterized in that, include: Substrate, power chip, connectors, power terminals, signal terminals, and encapsulation; The power chip is disposed on the substrate and includes an upper bridge chip set and a lower bridge chip set spaced apart along the length direction of the substrate. Both the upper bridge chip set and the lower bridge chip set include two columns of chip groups spaced apart along the width direction of the substrate. Each column of the chip group includes at least two chip units spaced apart along the length direction. The power terminal includes an output terminal located on the first short side of the substrate, and a positive input terminal and a negative input terminal located on the second short side of the substrate. The connectors are in two sets, each disposed on the side of the power chip away from the substrate. The two sets of connectors correspond to the upper bridge chip set and the lower bridge chip set, respectively. The outer periphery of each set of connectors is connected in parallel to the corresponding chip unit. The middle part of each set of connectors is located between the two rows of chip sets. The middle part of the connector corresponding to the upper bridge chip set is connected to the output terminal, and the middle part of the connector corresponding to the lower bridge chip set is connected to the negative input terminal.

2. The multi-chip parallel power module according to claim 1, characterized in that, The signal terminal includes a first gate terminal, a first source terminal, a first drain terminal, a second gate terminal, a second source terminal, and a second drain terminal; the first gate terminal, the first source terminal, and the first drain terminal are all located at the first short side, and the second gate terminal, the second source terminal, and the second drain terminal are all located at the second short side.

3. The multi-chip parallel power module according to claim 2, characterized in that, The signal terminal also includes a first detection terminal and a second detection terminal, both of which are located at the first short side; a temperature sensor is provided on the substrate, and the temperature sensor is connected to the first detection terminal and the second detection terminal respectively.

4. The multi-chip parallel power module according to claim 2, characterized in that, The chip unit includes a substrate, a source, a gate, and a drain. The source and the gate are both located on the side of the substrate away from the substrate, and the drain is located on the side of the substrate closer to the substrate. The substrate includes a first conductive layer, an insulating layer, and a second conductive layer stacked together. The first conductive layer is disposed close to the power chip, and the drain is connected to either the first drain terminal or the second drain terminal through the first conductive layer.

5. The multi-chip parallel power module according to claim 4, characterized in that, The connector is connected to the source of the chip unit, and a lead is connected to the connector, which is connected to either the first source terminal or the second source terminal.

6. The multi-chip parallel power module according to claim 1, characterized in that, Both the upper bridge chip set and the lower bridge chip set include four chip units. The arrangement direction of the chip units in the upper bridge chip set is the same as or perpendicular to the arrangement direction of the chip units in the lower bridge chip set.

7. The multi-chip parallel power module according to claim 6, characterized in that, In the upper bridge chip set or the lower bridge chip set, adjacent columns of the chip sets are arranged aligned or staggered.

8. The multi-chip parallel power module according to claim 6, characterized in that, Each set of connectors is an integral symmetrical structure, and the structures of the two sets of connectors may be the same or different. Alternatively, each set of connectors may include two oppositely arranged connecting units, each connecting unit being a symmetrical structure, the two connecting units having the same or different structures, and the two sets of connectors having the same or different structures.

9. The multi-chip parallel power module according to claim 8, characterized in that, Each of the connectors is an X-shaped structure, with the four branches of the X-shaped structure connected to the four chip units respectively, and the middle part of the X-shaped structure connected to the substrate between the two columns of chip groups; Alternatively, each of the connectors is an O-type structure, with the outer periphery of the O-type structure connected to the four chip units respectively, and the middle part of the O-type structure connected to the substrate between the two columns of chip groups; Alternatively, each set of connectors may be a T-shaped structure, with the crossbeam of the T-shaped structure connected to the four chip units respectively, and the longitudinal beam in the middle of the T-shaped structure extending to the edge of the substrate and connected to the power terminal.

10. The multi-chip parallel power module according to claim 8, characterized in that, Each set of connectors includes two C-shaped structures arranged opposite each other. The body of each C-shaped structure is connected to two chip units respectively, and the two extensions of each C-shaped structure are connected to the substrate between the two columns of chip groups respectively. Alternatively, each set of connectors includes a C-shaped structure and a Y-shaped structure arranged opposite to each other. The body of the C-shaped structure is connected to two of the chip units respectively, and the two extensions of the C-shaped structure are connected to the substrate between the two columns of the chip group. The two forks of the Y-shaped structure are connected to two of the chip units respectively, and the legs of the Y-shaped structure are connected to the substrate between the two columns of the chip group.

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