Substrate and preparation method thereof, and chip carrier plate

Abstract

According to the substrate, the preparation method thereof and the chip carrier plate provided by the embodiment of the invention, the substrate is used in the chip carrier plate, the substrate comprises a body part, a permeation part and a conductive part, the body part is provided with an opening, the opening is provided with a side wall and an end wall, and the side wall is conductive; the permeation part has conductivity, is arranged in the opening and at least partially permeates into the end wall, so that the end wall has conductivity; the conductive part is filled in the open hole, and the conductive part abuts against the side wall and the end wall. The embodiment of the invention provides a substrate, a preparation method thereof and a chip carrier plate, which can be used for conveniently electroplating and forming a conductive part at a hole opening position of the substrate, so that the conductive part is more uniform in a through hole, the effectiveness of the conductive part is ensured, and the overall product quality is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a substrate and its preparation method, and a chip carrier. Background Technology

[0002] With the development of high-performance chips, chip integration is increasing and interconnect density is becoming denser, leading to higher demands from users for chip products. Through-glass via (TGV) technology, as a key technology for next-generation advanced chip packaging, possesses excellent high-frequency electrical characteristics and strong mechanical stability, making it highly promising for applications in radio frequency devices, microelectromechanical systems (MEMS), and optoelectronic system integration.

[0003] Currently, traditional organic substrates can no longer meet the requirements in terms of flatness, fine circuitry, and signal transmission speed. During the packaging process, glass substrates can withstand higher temperatures better than organic substrates, and their coefficient of thermal expansion is similar to that of silicon, thus reducing stress warping problems caused by thermal mismatch. Furthermore, the higher flatness and lower roughness of the glass surface allow for denser wiring. Glass substrates have extremely low dielectric constant and dielectric loss, which can improve signal transmission speed and signal integrity. At the same time, their excellent chemical stability effectively resists environmental corrosion from moisture, acids, and alkalis.

[0004] However, for high-end glass substrates, when the depth-to-diameter ratio (the ratio of hole depth to hole diameter) of the glass via reaches 10:1 or higher, electroplating is required to form a conductive part at the via. When physical vapor deposition (PVD) technology is used to deposit a titanium or copper seed layer first, it is difficult for the metal to enter the hole, especially the middle part of the hole. As a result, after electroplating, defects such as uneven filling, voids or bubbles in the conductive part are easily caused. Summary of the Invention

[0005] In order to overcome the technical problems mentioned in the above technical background, the present application provides a substrate and its preparation method, and a chip carrier, which can facilitate the electroplating of conductive parts at the opening positions of the substrate, making the conductive parts more uniform in the through holes, ensuring the effectiveness of the conductive parts, and improving the overall product quality.

[0006] In a first aspect, this application provides a substrate for use in a chip carrier. The substrate includes a body portion, a permeation portion, and a conductive portion. The body portion has an opening, the opening having a sidewall and an end wall, the sidewall being conductive. The permeation portion is conductive, disposed in the opening and at least partially permeating the end wall to make the end wall conductive. The conductive portion is filled in the opening and abuts against the sidewall and the end wall.

[0007] As one embodiment of this application, the body portion has a first surface and a second surface disposed opposite to each other in its own thickness direction, the opening includes a first hole and a second hole, the opening of the first hole is located on the first surface and the opening of the second hole is located on the second surface, the first hole and the second hole extend toward each other and share the end wall, the first hole has a first side wall and the second hole has a second side wall, and the conductive portion is respectively filled in the first hole and the second hole; Preferably, the plane containing the end wall is parallel to the first surface and the second surface; Preferably, the surface of the conductive portion facing away from the end wall is flush with the first surface and the second surface.

[0008] As one embodiment of this application, the maximum extension depth of the first hole and the second hole are equal, and the end wall is located at half the thickness of the body portion; Preferably, the first hole and the second hole extend toward each other along the thickness direction; Preferably, the first hole and the second hole are symmetrically distributed about the plane containing the end wall.

[0009] As one embodiment of this application, the thickness of the end wall does not exceed one three-hundredth of the thickness of the body portion; Preferably, the thickness of the end wall does not exceed 1 micrometer.

[0010] In one embodiment of this application, the permeation portion includes a first permeation layer and a second permeation layer, the first permeation layer and the second permeation layer are stacked and permeate the end wall, and the sum of the thickness of the first permeation layer and the thickness of the second permeation layer is not less than the thickness of the end wall; Preferably, the thickness of the first permeable layer and the thickness of the second permeable layer are each not less than half the thickness of the end wall.

[0011] In one embodiment of this application, the permeation portion includes a first portion and a second portion. The first portion permeates into the end wall to make the end wall conductive, and the second portion permeates into the side wall to make the side wall conductive.

[0012] In one embodiment of this application, the orthographic projection of the end wall on the body portion is located within the orthographic projection of the opening of the hole on the body portion, and the side wall extends from the opening of the hole toward the end wall. Preferably, the cross-section of the opening in the thickness direction of the body portion includes a trapezoidal structure.

[0013] Secondly, this application provides a method for preparing a substrate, comprising: A body portion is provided, on which an opening is formed, the opening having sidewalls and endwalls; A permeation portion is formed on the body portion, the permeation portion is conductive, and at least a portion of the permeation portion is located in the opening and permeates into the end wall; A conductive portion is formed on the side of the permeation portion away from the body portion, and the conductive portion at least fills the opening and abuts against the side wall and the end wall.

[0014] As one embodiment of this application, a body portion is provided, and an opening is formed on the body portion, the opening having a side wall and an end wall. The step includes: forming a first hole and a second hole on opposite sides of the body portion, the first hole and the second hole sharing the end wall. The step of forming a conductive portion on the side of the permeation portion away from the body portion, wherein the conductive portion at least fills the opening and abuts against the side wall and the end wall, includes: forming the conductive portion on the permeation portions of the first hole and the second hole respectively, wherein the conductive portion fills the first hole and the second hole respectively.

[0015] Thirdly, this application provides a chip carrier board, including a redistribution layer and a substrate as described above. The redistribution layer is disposed on at least one side of the substrate in its thickness direction. The redistribution layer includes multiple layers of traces and insulating portions disposed between the traces. The insulating portions are provided with vias, and the traces of adjacent layers are connected through the vias. The traces in the redistribution layer closest to the substrate are connected to the conductive portions.

[0016] This application provides a substrate and its preparation method, as well as a chip carrier. By setting openings on the substrate and retaining the end walls of the openings, a permeation portion is permeated into the end walls of the openings to make the end walls conductive. This makes both the side walls and end walls of the openings conductive. Electroplating is performed using the conductivity of the side walls and end walls to form conductive portions. Under the action of the end walls of the openings, the formed conductive portions have better adhesion points, and the conductive portions can more fully fill the openings. The end walls can provide better support for the conductive portions, thereby facilitating the electroplating process of the conductive portions. The structure of the formed conductive portions is more uniform in the openings, ensuring the forming quality and conductivity effectiveness of the conductors. At the same time, the conductivity of the conductive portions and end walls meets the conductivity requirements of the substrate at the opening locations, providing a reliable guarantee for the subsequent formation of traces on the substrate and connection with the conductive portions, ultimately improving the overall structural quality of the chip carrier. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a substrate in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of another substrate structure in an embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the structure of another substrate in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the structure of another substrate in the embodiments of this application.

[0022] Figure 5 This is a schematic diagram of the structure of another substrate in the embodiments of this application.

[0023] Figure 6 This is a flowchart illustrating a substrate fabrication method according to an embodiment of this application.

[0024] Figure 7 This is a schematic diagram of the fabrication process of a substrate according to an embodiment of this application.

[0025] Figure 8 This is a schematic diagram of the fabrication process of a substrate according to an embodiment of this application.

[0026] Figure 9 This is a schematic diagram of the fabrication process of a substrate according to an embodiment of this application.

[0027] Figure 10 This is a schematic diagram of the structure of a chip carrier board in an embodiment of this application.

[0028] Figure label: 100 - Substrate; Z - Thickness direction; 10 - Body portion; 10a - First surface; 10b - Second surface; 11 - Opening; 11a - Sidewall; 11b - Endwall; 1 - First hole; 2 - Second hole; 20 - Penetration portion; 21 - First penetration layer; 22 - Second penetration layer; 23 - First part; 24 - Second part; 30 - Conductive part; 200 - Redistribution layer; 201 - Trace; 202 - Insulating part; 1000 - Chip carrier. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0032] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0033] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0034] With the development of high-performance chips, the integration level of chips is getting higher and higher, the interconnection density is getting denser and denser, and users' requirements for chip products are also increasing.

[0035] Currently, traditional organic substrates can no longer meet the requirements in terms of flatness, fine circuitry, and signal transmission speed. During the packaging process, glass substrates can withstand higher temperatures better than organic substrates, and their coefficient of thermal expansion is similar to that of silicon, thus reducing stress warping problems caused by thermal mismatch. Furthermore, the higher flatness and lower roughness of the glass surface allow for denser wiring. Glass substrates have extremely low dielectric constant and dielectric loss, which can improve signal transmission speed and signal integrity. At the same time, their excellent chemical stability effectively resists environmental corrosion from moisture, acids, and alkalis.

[0036] Currently, it is necessary to form through-holes on the substrate and electroplate conductive parts at the through-hole locations to make the substrate conductive at the through-hole locations to meet the conductivity requirements of the traces in the redistribution layer. However, the applicant has found that for high-end glass substrates, when the aspect ratio (the ratio of hole depth to hole diameter) of the glass through-hole reaches 10:1 or higher, electroplating is required at the through-hole locations to form conductive parts. When physical vapor deposition (PVD) technology is used to deposit a titanium or copper seed layer first, it is difficult for the metal to enter the hole, especially in the middle part of the hole. This can easily lead to defects such as uneven filling, voids, or bubbles in the conductive parts after electroplating.

[0037] To overcome the aforementioned technical problems, embodiments of this application provide a substrate and its preparation method, as well as a chip carrier, which facilitates the electroplating of conductive portions at the opening locations of the substrate, making the conductive portions more uniform in the through holes, ensuring the effectiveness of the conductive portions, and improving the overall product quality.

[0038] like Figures 1 to 3 As shown, this application embodiment provides a substrate 100 for use in a chip carrier 1000. The substrate 100 includes a body portion 10, a permeation portion 20, and a conductive portion 30. The body portion 10 has an opening 11, which has a sidewall 11a and an endwall 11b. The sidewall 11a is conductive. The permeation portion 20 is conductive and is disposed in the opening 11 and at least partially permeates into the endwall 11b to make the endwall 11b conductive. The conductive portion 30 is filled in the opening 11 and abuts against the sidewall 11a and the endwall 11b.

[0039] In this embodiment, the chip carrier 1000 is used to connect the chip and the circuit board. The chip carrier 1000 can conduct electricity between the chip and the circuit board through the intermediate conductive structure. At the same time, the chip carrier 1000 can support the chip, thereby improving the connection strength between the chip and the circuit board.

[0040] Optionally, in this embodiment, the body portion 10 of the substrate 100 in the chip carrier 1000 can be made of glass, or of course, organic material. An opening 11 needs to be provided on the body portion 10 to house the conductive portion 30. The opening 11 can be formed by laser induction and wet etching. The conductive portion 30 can be made of copper pillar material. This application is not limited to this, as long as it can ensure that the body portion 10 transmits electrical signals through the conductive portion 30 at the opening 11.

[0041] It should be noted that the opening 11 on the body part 10 in this embodiment has a side wall 11a and an end wall 11b. That is to say, the opening 11 in this embodiment can be understood as a blind hole structure. The side wall 11a and the end wall 11b need to be conductive so that the electroplating process can be performed on the side wall 11a and the end wall 11b to form the conductive part 30, so that the conductive part 30 fills the opening 11.

[0042] Since the opening 11 has an end wall 11b that is conductive, during the electroplating process, the end wall 11b in this embodiment can also serve as a seed layer for electroplating to form the conductive part 30. Compared with the prior art, which only uses the side of the through hole for electroplating, the end wall 11b of the opening 11 in this embodiment further provides an attachment point for the formation of the conductive part 30, solving the problem that the conductive part 30 cannot be fully attached by relying solely on the side. This makes the formed conductive part 30 more complete and uniform, meeting the requirements of deep hole electroplating. At the same time, the end wall 11b can provide better support for the formed conductive part 30.

[0043] In this embodiment, the substrate 100 needs to have the ability to conduct current up and down at the opening 11 position in order to complete the transmission of electrical signals between the chip and the circuit board. Therefore, in addition to the conductive part 30 having conductivity at the opening 11 position, the end wall 11b of the opening 11 also needs to have conductivity to ensure that the electrical signal passes through the entire substrate 100.

[0044] Optionally, in this embodiment, the conductivity of the end wall 11b is achieved by providing a permeation portion 20 at the position of the opening 11. Specifically, the permeation portion 20 itself is conductive, and it permeates into the end wall 11b to make the end wall 11b conductive. For example, the permeation portion 20 can be high-energy metal ions, typically Ti or Cu ions, which are injected into the end wall 11b by means of metal ion implantation, such as typically accelerating the metal ion energy to >1000keV. When the permeation portion 20 has fully permeated into the end wall 11b, the end wall 11b also becomes conductive.

[0045] It should be noted that when the permeation part 20 permeates into the end wall 11b, in order to make the end wall 11b as a whole have sufficient conductivity, the depth of the permeation part 20 needs to reach the thickness of the entire end wall 11b to cover the bottom of the entire opening 11. This application does not make any special limitation on the specific type of permeation part 20 or the specific process method. The purpose is to make the end wall 11b have conductivity so that the body part 10 can conduct electricity through at the opening 11.

[0046] Regarding the conductivity at the sidewall 11a position in the opening 11, optionally, the sidewall 11a can be formed at the same position using the forming process of the permeation portion 20 to make the sidewall 11a conductive. Alternatively, a conductive seed layer can be formed at the sidewall 11a position by means of physical vapor deposition (PVD). This application does not impose any special limitations on the conductive forming process at the sidewall 11a position, as long as it can ensure that the sidewall 11a position is conductive to complete the subsequent electroplating process.

[0047] This application provides a substrate 100. By providing an opening 11 on the substrate 100 and retaining the end wall 11b of the opening 11, a penetration portion 20 is penetrated into the end wall 11b of the opening 11 to make the end wall 11b conductive. This makes both the side wall 11a and the end wall 11b of the opening 11 conductive. Electroplating is performed using the conductivity of the side wall 11a and the end wall 11b to form a conductive portion 30. Under the action of the end wall 11b of the opening 11, the formed conductive portion 30 has better adhesion points and can be more fully and completely filled. The filling material is inserted into the opening 11, and the end wall 11b can better support the conductive part 30, thereby facilitating the electroplating process of the conductive part 30. The structure of the conductive part 30 formed is more uniform in the opening 11, ensuring the forming quality and conductivity of the conductor. At the same time, the conductivity of the conductive part 30 and the end wall 11b is used to meet the conductivity requirements of the substrate 100 at the opening 11, providing a reliable guarantee for the subsequent formation of the trace 201 on the substrate 100 and its connection with the conductive part 30, ultimately improving the overall structural quality of the chip carrier board 1000.

[0048] As an optional embodiment, please refer to Figure 2 The body portion 10 has a first surface 10a and a second surface 10b disposed opposite to each other in the thickness direction Z. The opening 11 includes a first hole 1 and a second hole 2. The opening of the first hole 1 is located on the first surface 10a and the opening of the second hole 2 is located on the second surface 10b. The first hole 1 and the second hole 2 extend toward each other and share an end wall 11b. The first hole 1 has a first side wall 11a and the second hole 2 has a second side wall 11a. The conductive portion 30 is respectively filled in the first hole 1 and the second hole 2.

[0049] In this embodiment, the opening 11 is set as a first hole 1 and a second hole 2 that are vertically opposite each other. The openings of the two holes are located on the first surface 10a and the second surface 10b that are opposite to each other in the body part 10. The first hole 1 and the second hole 2 extend towards each other so that they share an end wall 11b. The end wall 11b is located in the body part 10. The end wall 11b and the first side wall 11a enclose the first hole 1 and the second side wall 11a enclose the second hole 2.

[0050] At this time, since both the first sidewall 11a and the second sidewall 11a are conductive, and the end wall 11b is also conductive under the action of the penetration portion 20, conductive portions 30 can be formed at the first sidewall 11a, the second sidewall 11a, and the end wall 11b during the electroplating process, until the conductive portions 30 fill the first hole 1 and the second hole 2. Since the first hole 1 and the second hole 2 are arranged opposite to each other, the main body 10 only needs to be inverted when electroplating the first hole 1 and the second hole 2.

[0051] After the conductive parts 30 are electroplated into the first hole 1 and the second hole 2 respectively, the upper and lower conductive parts 30 are separated by the middle end wall 11b. Since the middle end wall 11b also has conductivity under the action of the penetration part 20, the body part 10 can form a conductive path from the conductive part 30 in the first hole 1 to the end wall 11b to the conductive part 30 in the second hole 2 at the opening 11 position, ensuring that the substrate 100 realizes the conduction of the upper and lower currents.

[0052] Optionally, the plane where the end wall 11b is located is parallel to the first surface 10a and the second surface 10b, thereby providing better support for the conductive parts 30 in the upper and lower holes; the surface of the conductive part 30 on the side away from the end wall 11b is flush with the first surface 10a and the second surface 10b, so that both the upper and lower surfaces of the substrate 100 form flat surfaces, providing a stable planar foundation for the subsequent molding of the redistribution layer 200. This application is not limited in this respect, as long as the electroplating molding of the conductive part 30 can be completed using the first hole 1 and the second hole 2.

[0053] Understandably, to ensure conductivity at the end wall 11b for subsequent electroplating processes, the penetrating portion 20 in this embodiment can penetrate into the end wall 11b from one side in the first hole 1 or the second hole 2, or it can penetrate into the end wall 11b from both sides in the first hole 1 and the second hole 2, depending on whether the thickness of the end wall 11b is sufficient for the penetration capacity of the penetrating portion 20. This application does not limit this. After the end wall 11b becomes conductive, conductive portions 30 can be electroplated in the first hole 1 and the second hole 2 on both sides, thereby overcoming the problem that the seed layer and conductive portions 30 are not easy to adhere due to the large hole depth.

[0054] This application provides a substrate 100. By setting the opening 11 as a first hole 1 and a second hole 2, the opening 11 is divided into the first hole 1 and the second hole 2 by using the middle end wall 11b. This allows the electroplating process of the first hole 1 and the second hole 2 to be completed separately. By using the common end wall 11b to divide the opening 11 into two, the depth of the opening 11 is further reduced. Dividing a single hole with a large depth into two sub-holes with a smaller depth facilitates the penetration of the penetration part 20 into the end wall 11b and the adhesion of the conductive seed layer into the side wall 11a. This facilitates the completion of the electroplating process of the first hole 1 and the second hole 2, making the formed conductive part 30 more uniform and complete in the first hole 1 and the second hole 2. This reduces the difficulty of the electroplating process and improves the effectiveness and reliability of the conductive part 30.

[0055] As an optional embodiment, please refer to Figure 3 The maximum extension depth of the first hole 1 and the second hole 2 are equal, and the end wall 11b is located at half the thickness of the body portion 10.

[0056] In this embodiment, after dividing the opening 11 into the first hole 1 and the second hole 2 through the middle end wall 11b, in order to further improve the reliability of the electroplating process, the end wall 11b is set at half the thickness of the body part 10, so that the depth of the first hole 1 and the depth of the second hole 2 are equal. This facilitates bidirectional penetration of the end wall 11b by the penetration part 20, ensuring the conductivity of the end wall 11b. At the same time, the difficulty of electroplating both sides of the first hole 1 and the second hole 2 is further reduced, and there is no problem of difficulty in electroplating caused by the greater depth of one side of the hole.

[0057] Optionally, the first hole 1 and the second hole 2 extend towards each other along the thickness direction Z. That is, the first hole 1 and the second hole 2, which are opposite each other, extend in the thickness direction Z to maintain collinearity. The first hole 1 and the second hole 2 can be symmetrically distributed with the plane where the end wall 11b is located as the axis, thereby facilitating the electroplating process. This application does not impose special limitations on the specific structure of the first hole 1 and the second hole 2, as long as it can ensure that the depth of the two is the same to reduce the difficulty of the electroplating process on the upper and lower sides.

[0058] This application provides a substrate 100. By setting the depths of the first hole 1 and the second hole 2 to be equal, when electroplating the first hole 1 and the second hole 2 respectively, the process difficulty on both sides is the same, the adhesion effect at the end wall 11b position is the same and reaches the optimization, reducing the risk of poor electroplating effect caused by the larger hole depth on one side.

[0059] As an optional embodiment, the thickness of the end wall 11b does not exceed one three-hundredth of the thickness of the body portion 10.

[0060] In this embodiment, it is mainly considered that during the process of permeating the permeating part 20 into the end wall 11b, it is necessary to ensure that the permeating part 20 is sufficiently permeated in the end wall 11b so that the end wall 11b is conductive and can conduct electrical signals from the conductive parts 30 in the first hole 1 and the second hole 2. Therefore, in this embodiment, the thickness of the end wall 11b is set to not exceed one three-hundredth of the thickness of the body part 10. In other words, the thickness of the end wall 11b cannot be too thick.

[0061] Optionally, the overall thickness of the body 10 is generally controlled between 300-500 micrometers. Therefore, in this embodiment, the thickness of the end wall 11b is controlled to not exceed 1 micrometer, so that the permeation part 20 can smoothly penetrate into the end wall 11b, ensuring the conductivity effectiveness at the end wall 11b position. This application does not impose special limitations on the specific thickness of the end wall 11b, as long as it can meet the conductivity requirements and electroplating requirements at the end wall 11b position.

[0062] This application provides a substrate 100, which, by limiting the thickness of the end wall 11b relative to the body portion 10, facilitates the penetration of the penetration portion 20 into the end wall 11b, accelerates the penetration process of the penetration portion 20 into the end wall 11b, reduces the difficulty of the penetration process, and makes the end wall 11b position have reliable conductivity.

[0063] As an optional embodiment, please refer to Figure 4 The permeation section 20 includes a first permeation layer 21 and a second permeation layer 22, which are stacked and permeated in the end wall 11b. The sum of the thickness of the first permeation layer 21 and the thickness of the second permeation layer 22 is not less than the thickness of the end wall 11b.

[0064] In this embodiment, the first permeation layer 21 and the second permeation layer 22 can be understood as permeation membrane layers applied to the end wall 11b in the first hole 1 and the second hole 2, respectively. That is, a permeation process is performed at the end wall 11b position in the first hole 1 to form the first permeation layer 21 on one side of the end wall 11b; then a permeation process is performed at the end wall 11b position in the second hole 2 to form the second permeation layer 22 on the other side of the end wall 11b, until the first permeation layer 21 and the second permeation layer 22 are stacked and abutted to form a complete permeation section 20.

[0065] To ensure sufficient conductivity at the end wall 11b, in this embodiment, the first permeation layer 21 and the second permeation layer 22 formed in the end wall 11b need to fully cover the end wall 11b. That is, the sum of the thicknesses of the first permeation layer 21 and the second permeation layer 22 needs to be no less than the thickness of the end wall 11b. To improve the reliability of the conductivity of the end wall 11b, the sum of the thicknesses of the membrane layers permeated on both sides of the end wall 11b can be controlled to be greater than the thickness of the end wall 11b, so that the first permeation layer 21 and the second permeation layer 22 have a certain overlap. This application does not limit this.

[0066] Optionally, the thickness of the first permeation layer 21 and the thickness of the second permeation layer 22 are each not less than half the thickness of the end wall 11b. That is, in this embodiment, the sum of the permeation depth in the first hole 1 and the permeation depth in the second hole 2 can be controlled to exceed half the thickness of the end wall 11b, thereby ensuring that the permeation process on both sides is equally difficult and that the end wall 11b has sufficient conductivity. For example, when the thickness of the end wall 11b is 1 micrometer, the thickness of the first permeation layer 21 permeating on the first hole 1 side is controlled to be greater than 0.5 micrometers, and the thickness of the second permeation layer 22 permeating on the second hole 2 side is also controlled to be greater than 0.5 micrometers, so that the formed permeation portion 20 fully covers the end wall 11b.

[0067] This application provides a substrate 100, which achieves double-sided penetration of the end wall 11b by setting the penetration portion 20 as a first penetration layer 21 and a second penetration layer 22. This reduces the difficulty of the penetration process, accelerates the penetration speed of the end wall 11b, and ensures the sufficiency of forming the penetration portion 20 in the end wall 11b, thereby ensuring the conductivity at the end wall 11b location and reducing the risk of open circuit at the end wall 11b location.

[0068] As an optional embodiment, please refer to Figure 4 The permeation section 20 includes a first part 23 and a second part 24. The first part 23 permeates into the end wall 11b to make the end wall 11b conductive, and the second part 24 permeates into the side wall 11a to make the side wall 11a conductive.

[0069] In this embodiment, it is necessary to ensure that both the sidewall 11a and endwall 11b of the opening 11 are conductive in order to form a seed layer in preparation for subsequent electroplating. The endwall 11b can be conductive through the penetration of the first part 23 of the penetration section 20, and the sidewall 11a can be conductive through the penetration of the second part 24 of the penetration section 20.

[0070] In this way, the first part 23 and the second part 24 of the penetration section 20 can be formed by the same process. When penetrating the opening 11, the first part 23 penetrates into the end wall 11b, while the second part 24 penetrates into the side wall 11a, so that the side wall 11a and the end wall 11b of the opening 11 are simultaneously conductive. Of course, the conductivity of the side wall 11a can also be achieved by forming a conductive layer through physical vapor deposition. This application is not limited to this, but the end wall 11b must be conductive through penetration. Thus, the end wall 11b can serve as a seed layer for electroplating and can also enable circuit conduction in the opening 11.

[0071] This application provides a substrate 100. By setting the permeation portion 20 as a first portion 23 and a second portion 24, the end wall 11b and side wall 11a of the opening 11 are made conductive, thereby integrally forming the conductivity of the end wall 11b and side wall 11a. The seed layer of the opening 11 can be prepared in the same process, while meeting the conductivity requirements of the end wall 11b position, reducing the overall process difficulty and improving process efficiency.

[0072] As an optional embodiment, please refer to Figures 1 to 4 The orthographic projection of the end wall 11b on the body portion 10 is located within the orthographic projection of the opening of the hole 11 on the body portion 10, and the side wall 11a extends from the opening of the hole 11 toward the end wall 11b.

[0073] Optionally, the cross-section of the opening 11 in the thickness direction Z of the body portion 10 includes a trapezoidal structure. In this embodiment, the sidewall 11a of the opening 11 can be formed into an inclined surface, which is beneficial to completing the seed layer preparation process on the sidewall 11a, whether by physical vapor deposition or infiltration, and facilitates the formation of the seed layer at the position of the sidewall 11a. At the same time, it is beneficial to the deposition of the conductive portion 30 formed after electroplating.

[0074] When the second part 24 of the permeation section 20 permeates at the sidewall 11a, since the sidewall 11a is an inclined surface, it is easier for the sidewall 11a to face the external space. During the permeation process, the second part 24 can quickly and effectively permeate into the sidewall 11a to make the sidewall 11a conductive. This application does not impose special limitations on the specific structure of the opening 11. Of course, the opening 11 can also be set as a rectangular hole structure according to actual needs, such as... Figure 5 As shown.

[0075] This application provides a substrate 100. By setting the sidewall 11a of the opening 11 as a converging slope, it is easier to complete the preparation of the seed layer at the position of the sidewall 11a, which speeds up the preparation process of the seed layer, ensures the conductivity effectiveness of the sidewall 11a, facilitates the adhesion of the conductive part 30 after the electroplating process, reduces the overall process difficulty, and improves the efficiency of the process forming.

[0076] Please see Figure 6 This application provides a method for preparing a substrate 100, comprising: S1. Provide a body portion 10, and form an opening 11 on the body portion 10. The opening 11 has a side wall 11a and an end wall 11b. S2. A permeation portion 20 is formed on the body portion 10. The permeation portion 20 is conductive. At least a portion of the permeation portion 20 is located in the opening 11 and permeates into the end wall 11b. S3. A conductive part 30 is formed on the side of the permeation part 20 away from the main body part 10. The conductive part 30 fills at least the opening 11 and abuts against the side wall 11a and the end wall 11b.

[0077] In step S1, as Figure 7 As shown, optionally, the provided body portion 10 can be made of glass, or other organic materials, etc. This application does not impose any special limitations on the material of the processed body portion 10. In this case, an opening 11 needs to be formed on the body portion 10. Optionally, a wet etching method can be used. For example, firstly, laser irradiation can be performed on the location where a hole needs to be drilled on the body portion 10 to modify the location. Then, an etching solution is used to etch the body portion 10. The etching rate at the modified location is accelerated, thereby forming the opening 11 at that location.

[0078] The above is a feasible hole setting method provided in this embodiment. This application does not make any special limitation on the specific hole forming method 11. It can also be carried out by physical processing or mechanical processing. The hole 11 can also be formed by laser melting, focused discharge method, plasma etching method, electrochemical discharge processing method, etc. It is necessary to ensure that the hole 11 in this embodiment has a side wall 11a and an end wall 11b, that is, it is set as a blind hole structure.

[0079] Then in step S2, as Figure 8 As shown, a permeation section 20 needs to be provided at the opening 11 position on the body part 10. Optionally, the permeation section 20 can be high-energy metal ions, typically Ti or Cu ions. The implantation depth needs to cover the thickness of the entire end wall 11b of the opening 11. For example, the metal ion energy is typically accelerated to >1000keV. In short, it is necessary to ensure that the end wall 11b of the opening 11 is metallized in the depth direction so that the end wall 11b is conductive.

[0080] Finally, in step S3, as Figure 9 As shown, a conductive part 30 needs to be provided at the opening 11 of the body part 10. Optionally, the conductive part 30 can be made of copper and mainly serves to conduct electricity. Specifically, the conductive part 30 can be formed in the opening 11 by electroplating. First, a seed layer can be formed on the sidewall 11a of the opening 11 by PVD sputtering, or a conductive metal seed layer can be formed at the sidewall 11a by penetration following the above-mentioned penetration process, so that the sidewall 11a has conductivity. Then, the opening 11 is filled with the conductive part 30 by overall electroplating. Finally, the surface copper on the body part 10 is removed by chemical mechanical polishing (CMP) for subsequent processes.

[0081] As an optional embodiment, please refer to Figures 7 to 9 The step of providing a body portion 10 and forming an opening 11 on the body portion 10, the opening 11 having a side wall 11a and an end wall 11b, includes: forming a first hole 1 and a second hole 2 on opposite sides of the body portion 10, the first hole 1 and the second hole 2 sharing the end wall 11b. The step of forming a conductive portion 30 on the side of the permeation portion 20 away from the main body portion 10, wherein the conductive portion 30 fills at least in the opening 11 and abuts against the side wall 11a and the end wall 11b, includes: forming conductive portions 30 on the permeation portions 20 of the first hole 1 and the second hole 2 respectively, wherein the conductive portions 30 fill the first hole 1 and the second hole 2 respectively.

[0082] Optionally, the body portion 10 is laser-induced wet etching to create symmetrical first holes 1 and second holes 2. The etching depth needs to be controlled to ensure that the common end wall 11b in the middle does not exceed a certain thickness, preferably not exceeding 1 μm. When injecting the penetration portion 20 on both sides of the end wall 11b, it is ensured that the injection depth on one side is not less than 1 / 2 of the thickness of the end wall 11b. For example, the metal ion energy is typically accelerated to >1000keV, and the injection depth is >0.5 μm; or the thickness of the end wall 11b can be reduced, and the metal ion energy can be reduced accordingly. In short, it is necessary to ensure that the end wall 11b is metallized in the depth direction.

[0083] After electroplating processes are performed in the first hole 1 and the second hole 2 respectively, the conductive parts 30 formed are filled into the first hole 1 and the second hole 2 respectively. Based on the fact that the middle end wall 11b is also conductive, the body part 10 achieves vertical conductive connection at the opening 11 position, forming a transmission path for electrical signals, and obtaining the final required substrate 100 structure.

[0084] like Figure 10As shown, this application provides a chip carrier 1000, including a redistribution layer 200 and a substrate 100 as described above. The redistribution layer 200 is disposed on at least one side of the substrate 100 in its thickness direction Z. The redistribution layer 200 includes multiple layers of traces 201 and insulating portions 202 disposed between the traces 201. The insulating portions 202 are provided with vias and the traces 201 of adjacent layers are connected through the vias. The traces 201 in the redistribution layer 200 near the substrate 100 are connected to the conductive portion 30.

[0085] Optionally, the redistribution layer 200 in this embodiment can be disposed on both sides of the substrate 100 to conduct electricity to the chip and the circuit board respectively. The multilayer traces 201 in the redistribution layer 200 can be connected through vias on the intermediate insulating portion 202. The trace 201 closest to the substrate 100 is connected to the conductive portion 30 in the opening 11, thereby realizing the conduction between the conductive portion 30 and the redistribution layer 200. The material of the insulating portion 202 can be wet film PSPI, which is coated, or ABF material, which is formed by film lamination. This application does not limit this and can determine it according to the specific material of the insulating portion 202.

[0086] It is understood that the number of routing layers 201 in the redistribution layer 200 in this embodiment is only one example. This application does not impose any special limitations on the specific number of layers and structure of the redistribution layer 200. For example, the redistribution layer 200 can also be set as a three-layer or four-layer structure according to actual connection requirements. Under the conduction of the conductive part 30 in the middle of the substrate 100 and the end wall 11b, the electrical signal conduction of the redistribution layer 200 on the upper and lower sides of the substrate 100 is realized.

[0087] This application provides a substrate and its preparation method, as well as a chip carrier. By setting openings on the substrate and retaining the end walls of the openings, a permeation portion is permeated into the end walls of the openings to make the end walls conductive. This makes both the side walls and end walls of the openings conductive. Electroplating is performed using the conductivity of the side walls and end walls to form conductive portions. Under the action of the end walls of the openings, the formed conductive portions have better adhesion points, and the conductive portions can more fully fill the openings. The end walls can provide better support for the conductive portions, thereby facilitating the electroplating process of the conductive portions. The structure of the formed conductive portions is more uniform in the openings, ensuring the forming quality and conductivity effectiveness of the conductors. At the same time, the conductivity of the conductive portions and end walls meets the conductivity requirements of the substrate at the opening locations, providing a reliable guarantee for the subsequent formation of traces on the substrate and connection with the conductive portions, ultimately improving the overall structural quality of the chip carrier.

[0088] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A substrate, characterized in that, For use in a chip carrier, the substrate includes: The body portion has an opening, the opening having a sidewall and an endwall, the sidewall being conductive; A permeable portion having electrical conductivity is disposed in the opening and at least partially permeates the end wall to make the end wall conductive; A conductive portion is filled in the opening, and the conductive portion abuts against the side wall and the end wall.

2. The substrate according to claim 1, characterized in that, The body portion has a first surface and a second surface disposed opposite to each other in its thickness direction. The opening includes a first hole and a second hole. The opening of the first hole is located on the first surface and the opening of the second hole is located on the second surface. The first hole and the second hole extend toward each other and share the end wall. The first hole has a first side wall and the second hole has a second side wall. The conductive part is respectively filled in the first hole and the second hole. Preferably, the plane containing the end wall is parallel to the first surface and the second surface; Preferably, the surface of the conductive portion facing away from the end wall is flush with the first surface and the second surface.

3. The substrate according to claim 2, characterized in that, The first hole and the second hole have the same maximum extension depth, and the end wall is located at half the thickness of the body portion; Preferably, the first hole and the second hole extend toward each other along the thickness direction; Preferably, the first hole and the second hole are symmetrically distributed about the plane containing the end wall.

4. The substrate according to claim 1, characterized in that, The thickness of the end wall does not exceed one three-hundredth of the thickness of the body portion; Preferably, the thickness of the end wall does not exceed 1 micrometer.

5. The substrate according to claim 1, characterized in that, The permeation section includes a first permeation layer and a second permeation layer, which are stacked and permeate the end wall. The sum of the thickness of the first permeation layer and the thickness of the second permeation layer is not less than the thickness of the end wall. Preferably, the thickness of the first permeable layer and the thickness of the second permeable layer are each not less than half the thickness of the end wall.

6. The substrate according to claim 1, characterized in that, The permeation portion includes a first part and a second part, the first part permeating into the end wall to make the end wall conductive, and the second part permeating into the side wall to make the side wall conductive.

7. The substrate according to claim 1, characterized in that, The orthographic projection of the end wall on the body portion is located within the orthographic projection of the opening of the hole on the body portion, and the side wall extends from the opening of the hole toward the end wall. Preferably, the cross-section of the opening in the thickness direction of the body portion includes a trapezoidal structure.

8. A method for preparing a substrate, characterized in that, include: A body portion is provided, on which an opening is formed, the opening having sidewalls and endwalls; A permeation portion is formed on the body portion, the permeation portion is conductive, and at least a portion of the permeation portion is located in the opening and permeates into the end wall; A conductive portion is formed on the side of the permeation portion away from the body portion, and the conductive portion at least fills the opening and abuts against the side wall and the end wall.

9. The preparation method according to claim 8, characterized in that, The step of providing a body portion and forming an opening on the body portion, the opening having a side wall and an end wall, includes: forming a first hole and a second hole on opposite sides of the body portion, the first hole and the second hole sharing the end wall; The step of forming a conductive portion on the side of the permeation portion away from the body portion, wherein the conductive portion at least fills the opening and abuts against the side wall and the end wall, includes: forming the conductive portion on the permeation portions of the first hole and the second hole respectively, wherein the conductive portion fills the first hole and the second hole respectively.

10. A chip carrier board, characterized in that, include: The substrate as described in any one of claims 1 to 7; A redistribution layer is disposed on at least one side of the substrate in its thickness direction. The redistribution layer includes multiple layers of traces and insulating portions disposed between the traces. The insulating portions are provided with vias, and the traces of adjacent layers are connected through the vias. The traces in the redistribution layer closest to the substrate are connected to the conductive portions.

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