Three-dimensional memory device and method for forming three-dimensional memory device

Abstract

In a particular aspect, a memory device includes a stack structure and a contact structure. The stacked structure includes alternating first layers and first dielectric layers. The first layer in the first portion of the stacked structure includes a second dielectric layer. The first layer in the second portion of the stacked structure includes a conductive layer. The contact structures extend into the first portion of the stack structure in the first direction and are respectively connected to corresponding ones of the conductive layers. The contact structures are divided into one or more groups based on contact depths of the contact structures in the first direction. The one or more groups include a first group including at least a first subset of the contact structures. A first subset of the contact structures in the first group includes a first set of contact shoulders located in the first stack pair.

Description

Technical Field

[0001] This invention relates to three-dimensional (3D) storage devices and methods for manufacturing the same. Background Technology

[0002] By improving process technology, circuit design, programming algorithms, and manufacturing processes, the size of planar memory cells can be reduced to even smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Therefore, the memory density of planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can solve the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals traveling to and from the memory array. Summary of the Invention

[0004] In one aspect, the storage device includes a stacked structure and contact structures. The stacked structure includes alternating first layers and first dielectric layers. The first layer in a first portion of the stacked structure includes a second dielectric layer, and the first layer in a second portion adjacent to the first portion of the stacked structure includes a conductive layer. Contact structures extend into the first portion of the stacked structure in a first direction and are respectively connected to corresponding conductive layers from the conductive layers. Based on the contact depth of the contact structures in the first direction, the contact structures are divided into one or more groups. The one or more groups include a first group, which includes at least a first subset of contact structures associated with a first subset of contact depths within a first depth range. The first subset of contact structures in the first group includes a first set of contact shoulders located in a first stacked pair, and the first stacked pair includes a first of a first dielectric layer and a first of a second dielectric layer.

[0005] In some implementations, a first subset of the contact structures in the first group includes a first contact structure. The first contact structure includes a vertical contact member and a lateral contact member connected to the vertical contact member. The vertical contact member extends along a first direction, and the lateral contact member is connected to one of the corresponding conductive layers.

[0006] In some implementations, the vertical contact member includes a first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment. The first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

[0007] In some implementations, in a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment also connected to the first contact shoulder.

[0008] In some implementations, the vertical contact member of the first contact structure further includes a second contact shoulder located within a first depth range. The second contact shoulder is connected to the second vertical contact segment, and the depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

[0009] In some implementations, the vertical contact member further includes a third vertical contact segment. The second contact shoulder connects to the second and third vertical contact segments.

[0010] In some implementations, the first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0011] In some implementations, the first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder. In a second direction, the size of the first end and the size of the second end of the first vertical contact segment are smaller than the size of the first vertical contact segment between the first end and the second end in the second direction.

[0012] In some implementations, the first contact structure further includes a spacer surrounding the vertical contact member, a filler surrounded by the vertical contact member, and a contact pad covering the filler and connected to the vertical contact member.

[0013] In some implementations, the depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction. The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

[0014] In some implementations, the spacer includes a first spacer segment, a spacer shoulder, and a second spacer segment. The spacer shoulder connects to the first spacer segment and the second spacer segment and is located in a first stack pair.

[0015] In some implementations, the first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0016] In some implementations, one or more groups further include a second group, which includes a second subset of contact structures associated with a second subset of contact depths within the second depth range. The second depth range differs from the first depth range.

[0017] In some implementations, a second subset of the contact structures in the second group includes a second set of contact shoulders located in a second stacked pair, which includes a second in the first dielectric layer and a second in the second dielectric layer. The second stacked pair is different from the first stacked pair.

[0018] In some implementations, the second part of the stacked structure includes a first sub-part and a second sub-part separate from the first sub-part, and the first part of the stacked structure is located between the first sub-part and the second sub-part and connected to the first sub-part and the second sub-part.

[0019] In some implementations, the first part of the stacked structure includes a third sub-part and a fourth sub-part separate from the third sub-part, and the second part of the stacked structure is located between and connected to the third and fourth sub-parts.

[0020] In some implementations, the storage device also includes peripheral circuitry connected to the contact structure.

[0021] In some implementations, the peripheral circuitry includes a device layer containing transistors and contact structures connected to the device layer.

[0022] In some implementations, one or more groups further include: a third group, comprising a third subset of contact structures associated with a third subset of contact depths within a third depth range; and a fourth group, comprising a fourth subset of contact structures associated with a fourth subset of contact depths within a fourth depth range. The first contact depth of the first contact structure in the first group is greater than the second contact depth of the second contact structure in the second group. The second contact depth of the second contact structure in the second group is greater than the third contact depth of the third contact structure in the third group. The third contact depth of the third contact structure in the third group is greater than the fourth contact depth of the fourth contact structure in the fourth group. In a second direction perpendicular to the first direction, the first contact structure is arranged, followed by the second contact structure, the third contact structure, and the fourth contact structure.

[0023] In another aspect, the storage device includes a stacked structure, a first set of contact structures, and a second set of contact structures. The stacked structure includes alternating first layers and first dielectric layers. The first layer in a first portion of the stacked structure includes a second dielectric layer, and the first layer in a second portion adjacent to the first portion of the stacked structure includes a conductive layer. The first set of contact structures extends in a first direction into the first portion of the stacked structure and is respectively connected to a first subset of the conductive layers. The first set of contact structures each has a first contact depth within a first depth range and includes a first set of contact shoulders located in the first stacked pair. The second set of contact structures extends in a first direction into the first portion of the stacked structure and is respectively connected to a second subset of the conductive layers. The second set of contact structures each has a second contact depth within a second depth range and includes a second set of contact shoulders located in a second stacked pair different from the first stacked pair.

[0024] In some implementations, the first stack pair includes a first dielectric layer and a first dielectric layer. The second stack pair includes a second dielectric layer and a second dielectric layer.

[0025] In some implementations, the first set of contact structures includes a first contact structure. The first contact structure includes a vertical contact member and a lateral contact member connected to the vertical contact member. The vertical contact member extends along a first direction, and the lateral contact member is connected to one of a first subset of the conductive layers.

[0026] In some implementations, the vertical contact member includes a first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment. The first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

[0027] In some implementations, in a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment connected to the first contact shoulder.

[0028] In some implementations, the vertical contact member of the first contact structure further includes a second contact shoulder located within a first depth range. The second contact shoulder is connected to the second vertical contact segment, and the depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

[0029] In some implementations, the vertical contact member further includes a third vertical contact segment. The second contact shoulder connects to the second and third vertical contact segments.

[0030] In some implementations, the first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0031] In some implementations, the first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder. In a second direction, the size of the first end and the size of the second end of the first vertical contact segment are smaller than the size of the first vertical contact segment between the first end and the second end.

[0032] In some implementations, the first contact structure further includes a spacer surrounding the vertical contact, a filler surrounded by the vertical contact, and a contact pad covering the filler and connected to the vertical contact.

[0033] In some implementations, the depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction. The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

[0034] In some implementations, the spacer includes: a first spacer segment, a spacer shoulder, and a second spacer segment. The spacer shoulder connects to the first spacer segment and the second spacer segment and is located in a first stack pair.

[0035] In some implementations, the first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0036] In some implementations, the second part of the stacked structure includes a first sub-part and a second sub-part separate from the first sub-part, and the first part of the stacked structure is located between the first sub-part and the second sub-part and connected to the first sub-part and the second sub-part.

[0037] In some implementations, the first part of the stacked structure includes a third sub-part and a fourth sub-part separate from the third sub-part, and the second part of the stacked structure is located between and connected to the third and fourth sub-parts.

[0038] In some implementations, the storage device also includes peripheral circuitry connected to the first group and the second group of contact structures.

[0039] In some implementations, the peripheral circuitry includes a device layer containing transistors, and a first set of contact structures and a second set of contact structures are connected to the device layer.

[0040] In some implementations, the storage device further includes: a third group of contact structures associated with a third contact depth within a third depth range; and a fourth group of contact structures associated with a fourth contact depth within a fourth depth range. The first contact depth of the first contact structure in the first group is greater than the second contact depth of the second contact structure in the second group. The second contact depth of the second contact structure in the second group is greater than the third contact depth of the third contact structure in the third group. The third contact depth of the third contact structure in the third group is greater than the fourth contact depth of the fourth contact structure in the fourth group. In a second direction perpendicular to the first direction, the first contact structure is arranged, followed by the second, third, and fourth contact structures.

[0041] In another aspect, a method for forming a storage device is disclosed. The method includes: forming a stacked structure comprising alternating first and second dielectric layers, and forming contact structures extending into the stacked structure in a first direction. Based on the contact depth of the contact structures in the first direction, the contact structures are divided into one or more groups. The one or more groups include a first group, which includes at least a first subset of contact structures associated with a first subset of contact depths within a first depth range. The first subset of contact structures includes a first set of contact shoulders located in a first stacked pair, and the first stacked pair includes a first of a first dielectric layer and a first of a second dielectric layer.

[0042] In some implementations, forming a contact structure includes: forming a first set of contact holes for a first group in a stacked structure, and forming a first subset of contact structures in the first set of contact holes.

[0043] In some implementations, forming a first set of contact holes includes: forming a barrier layer on a stacked structure, and etching the barrier layer and the stacked structure using a first mask to form a first set of openings for a first group in the stacked structure. The first set of openings has a first depth in a first direction, and the bottom of the first set of openings is located in the first stack pair.

[0044] In some implementations, forming the first set of contact holes further includes using a second mask to etch the stacked structure at one or more first openings from the first set of openings to form one or more second openings that further extend into the stacked structure.

[0045] In some implementations, the first set of contact holes includes a first contact hole, which includes a first of one or more first openings and a first of one or more second openings. A first sidewall shoulder is formed at the bottom of the first of the one or more first openings.

[0046] In some implementations, the stacked structure includes a first portion and a second portion adjacent to the first portion. Contact structures extend into the first portion of the stacked structure. The method further includes performing a gate line replacement process to replace a portion of the second dielectric layer in the second portion of the stacked structure with a conductive layer. Contact structures extend into the first portion of the stacked structure and are respectively connected to corresponding conductive layers from the conductive layers.

[0047] In some implementations, a first subset of the contact structures in the first set includes a first contact structure comprising a spacer, a vertical contact member, and a lateral contact member. Forming the first subset of contact structures in the first set of contact holes includes forming the first contact structure in the first contact hole by at least the following manner: forming a spacer on the sidewall of the first contact hole; forming a lateral contact member below the bottom of the first contact hole; and forming a vertical contact member on the sidewall of the spacer to connect to the lateral contact member. The lateral contact member is connected to one of the conductive layers.

[0048] In some implementations, the vertical contact member includes: a first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment. The first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

[0049] In some implementations, in a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment connected to the first contact shoulder.

[0050] In some implementations, the first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0051] In some implementations, the first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder. The size of the first end and the second end of the first vertical contact segment in the second direction are smaller than the size of the first vertical contact segment between the first end and the second end in the second direction.

[0052] In some implementations, the spacer includes: a first spacer segment, a spacer shoulder, and a second spacer segment. The spacer shoulder connects to the first spacer segment and the second spacer segment and is located in a first stack pair.

[0053] In some implementations, a spacer shoulder is formed on a first sidewall shoulder, and a first contact shoulder is formed on the spacer shoulder.

[0054] In some implementations, the first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by a first direction and a second direction perpendicular to the first direction.

[0055] In some implementations, one or more groups further include a second group, which includes a second subset of contact structures associated with a second subset of contact depths within the second depth range. The second depth range differs from the first depth range.

[0056] In some implementations, forming the contact structure further includes: forming a second set of contact holes for the second set in the stacked structure, and forming a second subset of contact structures in the second set of contact holes.

[0057] In some implementations, a second subset of the contact structures in the second set includes a second set of contact shoulders located in a second stacked pair, which includes a second in the first dielectric layer and a second in the second dielectric layer. The second stacked pair is distinct from the first stacked pair. Forming the second set of contact holes includes etching the barrier layer and the stacked structure using a third mask to form a second set of openings in the stacked structure. The second set of openings has a second depth in a first direction, and the bottom of the second set of openings is located in the second stacked pair. Forming the second set of contact holes further includes etching the stacked structure at one or more third openings in the second set of openings using a second mask during the formation of one or more second openings to form one or more fourth openings that further extend into the stacked structure.

[0058] In some implementations, the second set of contact holes includes a second contact hole comprising a first of one or more third openings and a first of one or more fourth openings. A second sidewall shoulder is formed at the bottom of the first of the one or more third openings.

[0059] In some implementations, forming the first set of contact holes further includes etching the stacked structure at the second of one or more second openings using a fourth mask to form a fifth opening that further extends into the stacked structure. Forming the second set of contact holes further includes etching the stacked structure at the second of one or more fourth openings using a fourth mask to form a sixth opening that further extends into the stacked structure. The first set of contact holes includes a third contact hole, which includes a second of one or more first openings corresponding to the second of one or more second openings, a second of one or more second openings, and a fifth opening. A third sidewall shoulder is formed at the bottom of the second of one or more second openings. The second set of contact holes includes a fourth contact hole, which includes a second of one or more third openings corresponding to the second of one or more fourth openings, a second of one or more fourth openings, and a sixth opening. A fourth sidewall shoulder is formed at the bottom of the second of one or more fourth openings.

[0060] In some implementations, a first subset of the contact structures in the first group includes a third contact structure formed in the third contact hole. The third contact structure includes a first set of contact shoulders and a first contact shoulder formed on the first sidewall shoulder. The third contact structure also includes a second contact shoulder formed on the third sidewall shoulder. The depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

[0061] In some implementations, the third contact structure also includes a contact pad. The depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction. The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

[0062] In some implementations, forming the second set of contact holes further includes: etching a barrier layer using a fifth mask to form a set of mask openings, and during the formation of one or more second openings, using a second mask to etch a stacked structure at a mask opening in the set of mask openings to form a seventh opening extending into the stacked structure. The second set of contact holes includes a fifth contact hole containing the seventh opening.

[0063] In some implementations, one of the contact structures is formed in a contact hole, which includes multiple openings formed by etching the stacked structure using multiple etch counts, and the total number of contact shoulders formed in one of the contact structures is equal to the total number of etch counts minus 1. Attached Figure Description

[0064] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0065] Figure 1 A plan view of a 3D storage device with a contact structure according to some aspects of this disclosure is shown.

[0066] Figure 2A A cross-sectional side view of a first example implementation of a contact structure according to some aspects of this disclosure is shown.

[0067] Figure 2B Some aspects of this disclosure are shown. Figure 2A A cross-sectional side view of the contact structure.

[0068] Figure 2C A cross-sectional side view of a second example implementation of a contact structure according to some aspects of this disclosure is shown.

[0069] Figure 2DA plan view showing the arrangement of contact structures in a storage device according to some aspects of this disclosure is shown.

[0070] Figure 2E Some aspects of this disclosure are shown. Figure 2D The contact depth of the contact structure in the middle.

[0071] Figure 3A A cross-sectional side view of a 3D storage device with a contact structure according to some aspects of this disclosure is shown.

[0072] Figure 3B An enlarged cross-sectional side view of a 3D storage device with a contact structure according to some aspects of this disclosure is shown.

[0073] Figure 4 A cross-sectional side view of a 3D memory device including peripheral circuitry, according to some aspects of this disclosure, is shown.

[0074] Figures 5A-5J The present disclosure illustrates a manufacturing process for forming a 3D storage device with a contact structure, based on some aspects of this disclosure.

[0075] Figure 6 This is a flowchart of a method for forming a 3D storage device with a contact structure, based on some aspects of this disclosure.

[0076] Figures 7A-7Q The present disclosure illustrates a manufacturing process for forming contact structures in a stacked structure, according to some aspects thereof.

[0077] Figure 8 The different numbers of layers to be etched using different masks are shown in some aspects of this disclosure.

[0078] Figure 9 This is a flowchart of another method for forming a 3D storage device with a contact structure, based on some aspects of this disclosure.

[0079] Figure 10 This is a flowchart of a method for forming a contact structure in a stacked structure, based on some aspects of this disclosure.

[0080] Figure 11 A block diagram of an exemplary system having a 3D storage device is shown, according to some aspects of this disclosure.

[0081] Figure 12A A diagram of an exemplary memory card having 3D storage devices is shown, according to some aspects of this disclosure.

[0082] Figure 12BA diagram of an exemplary solid-state drive (SSD) with 3D storage devices is shown, according to some aspects of this disclosure.

[0083] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0084] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically depicted in the figures, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0085] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein, depending at least in context, can be used to describe any feature, structure, or characteristic in the singular, or to describe a combination of features, structures, or characteristics in the plural. Similarly, terms such as "a," "an," or "the" are again emphasized to be understood as conveying either a singular or a plural usage, depending at least in context. Furthermore, the term "based on" can be understood not necessarily to convey a set of exclusive factors, but rather to allow for additional factors that are not necessarily explicitly described, again emphasizing that this depends at least in part in context.

[0086] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something,” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “over” means not only “above something” or “on top of something,” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0087] Furthermore, for ease of description, this document may use spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another, as illustrated in the accompanying figures. In addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0088] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0089] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend throughout the entire underlying or upper structure, or may have a range smaller than that of the underlying or upper structure. Furthermore, a layer may be a region of a homogeneous or dissimilar continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where lateral contact members and / or vertical contacts are formed) and one or more dielectric layers.

[0090] In some 3D memory devices, such as 3D NAND memory devices, memory cells for storing data are vertically stacked in a vertical channel structure via a stacking structure (e.g., memory stack). 3D memory devices typically include a stepped structure formed on one or more sides (edges) or at the center of the stacked memory structure for purposes such as word line pickup / fan-out using word line contacts falling on different steps / levels of the stepped structure. In some implementations, word line pickup / fan-out functionality can be achieved without using the stepped structure and word line contacts, thereby reducing manufacturing costs and simplifying the manufacturing process. For example, two structures—the stepped structure and the word line contacts—and their respective processes can be combined into a single contact structure in one process (e.g., a word line pickup structure), thereby reducing manufacturing costs and simplifying the process.

[0091] Specifically, in the stacked structure of memory devices, contact structures extending through alternating first and second dielectric layers can be formed. Word line pickup / fan-out functionality of the memory device can be achieved through these contact structures. During manufacturing, multiple photoresist masks can be used to etch alternating first and second dielectric layers to form contact holes for the contact structures, thereby allowing contact structures to be formed individually within these contact holes. The contact holes can have different etching depths, allowing for a different number of layers etched for each contact hole.

[0092] Theoretically, using n masks, the number of etching layers can reach up to 2. n -1, such as Figure 8 As shown in Table 2. However, in practice, this theoretical limit cannot be reached, and more masks (e.g., more than n masks) are needed to achieve 2. n -1 is the number of etching layers, such as Figure 8 As shown in Table 3, manufacturing costs can increase with the increase in the number of etched layers (e.g., due to the need for more masks and more etch cycles). On the other hand, contact holes in which contact structures are formed can be formed by combining multiple openings together, wherein the multiple openings can be formed by etching multiple times into the stacked structure using multiple masks respectively. Since multiple etchings are performed to form contact holes, the critical size (CD) of the contact structure formed in the contact holes is large. Contact structures with large CDs can occupy a large area of ​​the memory device, and the remaining area for forming channel structures in the memory device will be reduced, resulting in a lower storage density of the memory device. In addition, with the increase in etched layers, under-etching or over-etching of layers can occur, resulting in etching defects in the memory device.

[0093] For example, refer to Figure 8 Table 3 shows that etching the 507 layer may require 15 masks. Considering the thickness of each photoresist mask and the development of the photoresist mask, a single etch using photoresist masks can achieve a maximum depth of 64 layers in the stacked structure. For the contact holes formed by etching the 507 layer, 15 etches are performed using 15 masks, each forming 15 openings, which are then combined to form the contact holes. Because 15 masks are used for etching, the CD of the resulting contact structure can be large. The differences in the contours of the 15 openings formed by different etches can be significant. Over-etching or under-etching of layers may occur.

[0094] To address one or more of the aforementioned problems, this invention proposes a solution that simplifies the etching of the stacked structure in a memory device during the formation of contact holes. The solution disclosed in this invention reduces the number of etching passes and also reduces the number of masks used in the etching process. Therefore, the cutoff depth (CD) of the resulting contact structure can be reduced. This simplifies the manufacturing process of the memory device and reduces its manufacturing cost.

[0095] For example, in the solution disclosed in this invention, the contact junction can be divided into different contact groups based on the corresponding contact depth of the contact structure. The formation of contact holes in the contact structure can be divided into two steps. First, for each contact group, a set of openings can be formed by etching the stacked structure using a mask, where the set of openings can have the same depth. Then, different sets of openings with different depths can be formed for different contact groups using different masks respectively. Next, the stacked structure can be further etched using one or more additional masks through the openings across the different sets of openings, thereby forming contact holes with corresponding target depths for the contact structures respectively. In this way, the number of masks used to form contact holes can be reduced, and the process of forming contact holes can be simplified. Etching defects such as over-etching or under-etching can be reduced or eliminated. The CD of the resulting contact structure can also be reduced, thereby reducing the area occupied by the contact structure and increasing the area occupied by the channel structure. Therefore, the storage density of the memory device can be increased. The manufacturing cost of the memory device can be reduced.

[0096] Figure 1 A plan view of a 3D memory device 100 having contact structure 106 according to some aspects of this disclosure is shown. In some implementations, the 3D memory device 100 is a NAND flash memory device, wherein the memory cells are provided in the form of a NAND memory string array. It is worth noting that... Figure 1 The diagram includes an x-axis and a y-axis to show two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the word line direction of the 3D memory device 100, and the y-direction is the bit line direction of the 3D memory device 100.

[0097] like Figure 1 As shown, the 3D memory device 100 may include one or more blocks 102 arranged along the y-direction (bit line direction), separated by parallel slot structures 108 (e.g., gate line slits, GLS). In some implementations of the 3D memory device 100 as a NAND flash memory device, each block 102 is the smallest erasable cell of the NAND flash memory device. Each block 102 may also include a plurality of fingers 104 in the y-direction, separated by slot structures 108 having “H”-shaped cutouts 109.

[0098] like Figure 1 As shown, the 3D storage device 100 can be divided into at least a core array region 101 and a word line pickup region 103. An array of channel structures 110 is formed in the core array region 101, and contact structures 106 are formed in the word line pickup region 103. According to some implementations, the core array region 101 and the word line pickup region 103 are arranged along the x-direction (word line direction). It can be understood that, although... Figure 1 The diagram illustrates a core array region 101 and a word line pickup region 103. However, in other examples, the 3D storage device 100 may include multiple core array regions 101 and / or multiple word line pickup regions 103; for example, a word line pickup region 103 may be located between two core array regions 101 in the x-direction. It should also be understood that... Figure 1 Only the portion of the core array region 101 adjacent to the word line pickup region 103 is shown.

[0099] As described in more detail below, the word line pickup area 103 may include a conductive portion 105 and a dielectric portion 107 arranged along the y-direction. Figure 1 As shown, according to some implementations, contact structures 106 are disposed in the dielectric portion 107, while virtual channel structures 112 are disposed in the conductive portion 105 of the word line pickup region 103 to provide mechanical support and / or load balancing. In some implementations, the virtual channel structure 112 may also be disposed in the dielectric portion 107 of the word line pickup region 103, for example, between contact structures 106 in the x-direction. In some implementations, the virtual channel structure 112 is not disposed in the dielectric portion 107 of the word line pickup region 103, i.e., it is only disposed in the conductive portion 105 of the word line pickup region 103. Figure 1 As shown, each finger 104 of the 3D storage device 100 may include a row of contact structures 106 disposed in the dielectric portion 107 of the word line pickup region 103. It will be understood that the layout and arrangement of the contact structures 106, as well as the shape of each contact structure 106, may vary in different examples.

[0100] Figure 2A A cross-sectional side view of a first example implementation of the contact structure 106 in a storage device 100 according to some aspects of this disclosure is shown. The cross-section can be along... Figure 1 The AA direction in the dielectric portion 107 of the word line pickup area 103. Figure 2B This disclosure illustrates some aspects of the content of this disclosure. Figure 2A A cross-sectional side view of the contact structure 106 in the image. This will be described together below. Figure 2A and Figure 2BThe storage device 100 may include a stacked structure 201, which may include a first portion and a second portion adjacent to the first portion. The first portion of the stacked structure 201 may include... Figure 1 This is a portion of the stacked structure 201 in the dielectric portion 107 of the word line pickup area 103 shown. A second portion of the stacked structure 201 may include... Figure 1 The conductive portion 105 of the word line pickup region 103 shown; and (ii) another portion of the stacked structure 201 in the core array region 101. The stacked structure 201 may include alternating first layers and first dielectric layers 203.

[0101] In some implementations, the second part of the stacked structure 201 may include: (i) a first sub-part; and (ii) a second sub-part separate from the first sub-part. The first part of the stacked structure 201 may be located between the first sub-part and the second sub-part, and connected to the first sub-part and the second sub-part. In some implementations, the first part of the stacked structure 201 may include: (i) a third sub-part; and (ii) a fourth sub-part separate from the third sub-part. The second part of the stacked structure 201 may be located between the third sub-part and the fourth sub-part, and connected to the third sub-part and the fourth sub-part.

[0102] The stacked structure 201 may include a first layer and a first dielectric layer 203 that are vertically staggered. The first layer and the first dielectric layer 203 may alternate in the vertical direction (z-direction). In some implementations, the stacked structure 201 may include multiple material layer pairs stacked vertically along the z-direction, each of the material layer pairs including a first layer and a first dielectric layer 203. The number of material layer pairs in the stacked structure 201 may determine the number of memory cells in the memory device 100.

[0103] The first layer in the first portion of the stacked structure 201 may include a second dielectric layer 205. That is, the first portion of the stacked structure 201 may include alternating first dielectric layers 203 and second dielectric layers 205, such as... Figure 2A As shown. The first layer in the second part of the stacked structure 201 may include a conductive layer (e.g., Figure 3A As shown in 302). That is, the second part of the stacked structure 201 may include alternating first dielectric layers 203 and conductive layers 302, as shown in 302. Figure 3A As shown.

[0104] In some implementations, memory device 100 is a NAND flash memory device, and stacked structure 201 is a stacked memory structure through which NAND memory strings are formed. In some implementations, each conductive layer in the second portion of stacked structure 201 serves as a gate line for a NAND memory string (in the form of channel structure 110) in core array region 101, and a word line extending laterally from the gate line and terminating in a conductive portion 105 of word line pickup region 103 for word line pickup / fan-out via contact structure 106. According to some implementations, word lines (i.e., conductive layers) at different depths / layers in the second portion of stacked structure 201 extend laterally in core array region 101 and conductive portion 105 of word line pickup region 103, but are discontinuous in dielectric portion 107 of word line pickup region 103 (e.g., replaced by a second dielectric layer 205).

[0105] The conductive layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicides, or any combination thereof. The first dielectric layer 203 or the second dielectric layer 205 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first dielectric layer 203 and the second dielectric layer 205 may have different dielectric materials, such as silicon oxide and silicon nitride. In some implementations, the conductive layer includes a metal (e.g., tungsten), the first dielectric layer 203 includes silicon oxide, and the second dielectric layer 205 includes silicon nitride. For example, the first dielectric layer 203 of the stacked structure 201 may include silicon oxide across the core array region 101 and the word line pickup region 103, and the first layer of the stacked structure 201 may include tungsten in the core array region 101 and the conductive portion 105 of the word line pickup region 103, and may include silicon nitride in the dielectric portion 107 of the word line pickup region 103.

[0106] In some implementations, the stacked structure 201 may be formed on a semiconductor layer 207, such as a substrate. The substrate may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some implementations, the substrate comprises single-crystal silicon, which is part of the wafer used to fabricate the memory device 100, whether its original thickness or thinned. In some implementations, the substrate comprises, for example, polycrystalline silicon, which is a semiconductor layer replacing the wafer portion used to fabricate the memory device 100.

[0107] It is worth noting that, Figure 1 and Figure 2AThe x, y, and z axes are included to illustrate the spatial relationships of components in the memory device 100. The semiconductor layer 207 (e.g., a substrate) of the 3D memory device 100 includes two side surfaces extending laterally in the xy plane: a top surface that can form the front side of the wafer of the stacked structure 201, and a bottom surface that is opposite the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether a component (e.g., a layer or device) of the 3D memory device 100 is "above," "above," or "below" another component (e.g., a layer or device) is located "above," "above," or "below" it in the z-direction (a direction perpendicular to the xy plane) of the semiconductor layer 207 of the memory device 100. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0108] like Figure 2A As shown, according to some implementations, contact structures 106 extend vertically at different depths in the z-direction into the stacked structure 201 within the dielectric portion 107 of the word line pickup region 103. The top surfaces of different contact structures 106 can be flush with each other, while the bottom surfaces of different contact structures 106 can extend to different layers, such as different second dielectric layers 205 of the stacked structure 201. For example, contact structures 106A-106F (also collectively or individually referred to as contact structures 106) can extend along the z-direction to the first portion of the stacked structure 201 and connect from the conductive layer to the corresponding conductive layer (as follows). Figure 3A (As shown). The contact structure 106 can be divided into one or more groups based on the contact depth of the contact structure 106 in the z direction, as described in more detail below.

[0109] In some implementations, one or more groups may include a first group that includes at least a first subset of contact structures 106 associated with a first subset of contact depths within a first depth range. The first subset of contact structures 106 may include a first set of contact shoulders 212 located in a first stack pair. The first stack pair may include a first of a first dielectric layer 203 and a first of a second dielectric layer 205 (e.g., including a first dielectric layer 203A and a second dielectric layer 205A). The contact depth and depth range will be described in more detail below.

[0110] In some implementations, one or more groups may also include a second group that includes a second subset of contact structures 106 associated with a second subset of contact depths within a second depth range. The second depth range is different from the first depth range. The second subset of contact structures 106 may include a second set of contact shoulders 212 located in a second stack pair. The second stack pair is different from the first stack pair and may include a second one of the first dielectric layer 203 and a second one of the second dielectric layer 205 (e.g., including the first dielectric layer 203B and the second dielectric layer 205B). In some implementations, one or more groups may also include: (i) a third group that includes a third subset of contact structures 106 associated with a third subset of contact depths within a third depth range; and (ii) a fourth group that includes a fourth subset of contact structures 106 associated with a fourth subset of contact depths within a fourth depth range.

[0111] In some implementations, a first contact depth of a first contact structure 106 in the first group is greater than a second contact depth of a second contact structure 106 in the second group. The second contact depth of the second contact structure 106 in the second group is greater than a third contact depth of a third contact structure 106 in the third group. The third contact depth of the third contact structure 106 in the third group is greater than a fourth contact depth of a fourth contact structure 106 in the fourth group. In a second direction (i.e., the x-direction) perpendicular to the first direction, the first contact structure 106 is arranged, followed by the second contact structure 106, the third contact structure 106, and the fourth contact structure 106, as described below with reference to Figure 2D described.

[0112] For example, referring to Figure 2A , the first group may include contact structures 106A and 106B that have respective contact depths within the depth range [D2, D3], where D2 and D3 are positive integers greater than 1 and D2 < D3. Consistent with some aspects of the present disclosure, the contact depth of a contact structure may be described by the total number of layers in the stack structure 201 that the contact structure extends through. For example, the contact structure in the first group having the minimum contact depth may extend through D2 layers of the stack structure 201, and the contact structure in the first group having the maximum contact depth may extend through D3 layers of the stack structure 201. Thus, the depth range of the contact structures in the first group is [D2, D3].

[0113] Contact structure 106A may include contact shoulder 212A, and contact structure 106B may include contact shoulder 212B. Contact shoulder 212A and contact shoulder 212B may be located in a first stack pair including a first dielectric layer 203A and a second dielectric layer 205A. For example, contact shoulder 212A and contact shoulder 212B may be located in the same first dielectric layer 203A. In another example, contact shoulder 212A and contact shoulder 212B may be located in the same second dielectric layer 205A. In yet another example, contact shoulder 212A and contact shoulder 212B may be located within the first dielectric layer 203A and the second dielectric layer 205A. Contact structure 106A may also include additional contact shoulder 212C located within a depth range [D2, D3].

[0114] Reference Figure 2A and Figure 2B The contact structure 106A may have a contact depth 227 within the depth range [D2, D3]. The contact structure 106A may include a spacer 202, a vertical contact member 204, a lateral contact member 206, a filler 208, and a contact pad 210. The spacer 202 may surround the vertical contact member 204. For example, the vertical contact member 204 may be formed on the sidewall of the spacer 202. The lateral contact member 206 may be connected to the vertical contact member 204. The filler 208 may be surrounded by the vertical contact member 204. The contact pad 210 may cover the filler 208 and be connected to the vertical contact member 204. The vertical contact member 204 may extend in the z-direction. The lateral contact member 206 may extend in the y-direction to connect to a corresponding conductive layer (e.g., as follows). Figure 3A (As shown).

[0115] Vertical contact member 204 and lateral contact member 206 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, polycrystalline silicon, doped silicon, silicides, or any combination thereof. Spacer 202 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some implementations, vertical contact member 204 and lateral contact member 206 may include TiN / W, and spacer 202 may include silicon oxide. Contact pad 210 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, polycrystalline silicon, doped silicon, silicides, or any combination thereof. Filler 208 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0116] like Figure 2BAs shown, the vertical contact member 204 may include a first vertical contact segment 230, a contact shoulder 212A, a second vertical contact segment 232, a contact shoulder 212C, and a third vertical contact segment 234. The contact shoulder 212A may be connected to the first vertical contact segment 230 and the second vertical contact segment 232. The second contact shoulder 212C may be connected to the second vertical contact segment 232 and the third vertical contact segment 234.

[0117] The depth 226 of the contact shoulder 212C in the z-direction can be greater than the depth 225 of the contact shoulder 212A in the z-direction. The depth 226 of the contact shoulder 212C in the z-direction can be the distance from the contact pad 210 to the contact shoulder 212C in the z-direction. The depth 225 of the contact shoulder 212A in the z-direction can be the distance from the contact pad 210 to the contact shoulder 212A in the z-direction.

[0118] The first vertical contact segment 230 may have a first end connected to the contact shoulder 212A and a second end away from the contact shoulder 212A. The second vertical contact segment 232 may have a first end connected to the contact shoulder 212A and a second end connected to the contact shoulder 212C. The third vertical contact segment 234 may have a first end connected to the contact shoulder 212C and a second end away from the contact shoulder 212C. In the x-direction, the size 228 of the second end of the first vertical contact segment 230 is greater than the size 229 of the first end of the first vertical contact segment 230. The size 229 of the first end of the first vertical contact segment 230 connected to the contact shoulder 212A is greater than the size 240 of the first end of the second vertical contact segment 232, which is also connected to the contact shoulder 212A. The size 240 of the first end of the second vertical contact segment 232 is greater than the size 241 of the second end of the second vertical contact segment 232 connected to the contact shoulder 212C. The size 241 of the second end of the second vertical contact segment 232 is greater than the size 242 of the first end of the third vertical contact segment 234, which is also connected to the contact shoulder 212C. The size 242 of the first end of the third vertical contact segment 234 is greater than the size 243 of the second end of the third vertical contact segment 234 away from the contact shoulder 212C.

[0119] like Figure 2BAs shown, the spacer 202 may include a first spacer segment 220, a spacer shoulder 221, a second spacer segment 222, another spacer shoulder 223, and a third spacer segment 224. The spacer shoulder 221 may connect the first spacer segment 220 and the second spacer segment 222 and be in the same stack pair as the contact shoulder 212A. The contact shoulder 212A may be formed on the spacer shoulder 221. The spacer shoulder 223 may connect the second spacer segment 222 and the third spacer segment 224 and be in the same stack pair as the contact shoulder 212C. The contact shoulder 212C may be formed on the spacer shoulder 223.

[0120] Reference Figure 2A , the second group may include contact structures 106C and 106D, and the contact structures 106C and 106D have respective contact depths within the depth range [D1, D2 - 1], where D1 is a positive integer greater than 1, and D1 < D2 - 1. For example, the contact structure with the minimum contact depth in the second group may extend through D1 layers of the stack structure 201, and the contact structure with the maximum contact depth in the second group may extend through D2 - 1 layers of the stack structure 201, so the depth range of the second group is [D1, D2 - 1].

[0121] The contact structure 106C may include a contact shoulder 212F, and the contact structure 106D may include a contact shoulder 212D. The contact shoulder 212D and the contact shoulder 212F may be in a second stack pair that includes a first dielectric layer 203B and a second dielectric layer 205B. For example, the contact shoulder 212D and the contact shoulder 212F may be in the same first dielectric layer 203B. In another example, the contact shoulder 212D and the contact shoulder 212F may be in the same second dielectric layer 205B. In yet another example, the contact shoulder 212D and the contact shoulder 212F may be within the first dielectric layer 203B and the second dielectric layer 205B. The contact structure 106D may further include an additional contact shoulder 212E within the depth range [D1, D2 - 1]. The depth of the contact shoulder 212E in the z - direction may be greater than the depth of the contact shoulder 212D in the z - direction.

[0122] The third group may include contact structures 106E and 106F, which have corresponding contact depths within the depth range [1, D1-1]. For example, the contact structure with the smallest contact depth in the third group may extend through one layer of the stacked structure 201, and the contact structure with the largest contact depth in the third group may extend through layer D1-1 of the stacked structure 201, such that the depth range of the third group is [1, D1-1]. Contact structure 106E may not include any contact shoulder. Contact structure 106F may include contact shoulder 212G. The depth of contact shoulder 212G is within the depth range [1, D1-1].

[0123] Figure 2C A cross-sectional side view of a second example implementation of the contact structure 106 is shown, according to some aspects of this disclosure. Figure 2C The contact structure 106 may include the contact structure referenced above. Figures 2A-2B The components described are similar to those described herein, and similar descriptions will not be repeated herein. In some implementations, the vertical contact member 204 of the contact structure 106 may include a first vertical contact segment 230, a contact shoulder 212, and a second vertical contact segment 232. Figures 2A-2B The difference shown Figure 2C The first vertical contact segment 230 may have an arcuate shape in a cross-sectional view in a plane defined by the z and x directions. The first vertical contact segment 230 may have a first end connected to the contact shoulder 212 and a second end away from the contact shoulder 212. The size 250 of the second end of the first vertical contact segment 230 in the x direction and the size 254 of the first end of the first vertical contact segment 230 in the x direction are smaller than the size 252 between the first and second ends of the first vertical contact segment 230 in the x direction.

[0124] In some implementations, the spacer 202 may include a first spacer segment 220, a spacer shoulder 221, and a second spacer segment 222. Figures 2A-2B The difference shown Figure 2C The first spacer segment 220 may have an arcuate shape in a cross-sectional view in a plane defined by the z and x directions. The first spacer segment 220 may have a first end connected to the spacer shoulder 221 and a second end away from the spacer shoulder 221. The size of the first end of the first spacer segment 220 in the x direction and the size of the second end of the first spacer segment 220 in the x direction are smaller than the size between the first end and the second end of the first spacer segment 220 in the x direction.

[0125] Figure 2D A plan view showing the arrangement of contact structures 106 in a storage device according to some aspects of this disclosure is shown. The storage device may be... Figure 1 The storage device 100 or any other storage device disclosed herein. Figure 2D In the word line pickup area 103, the contact structure 106 can be divided into four groups: the first group includes contact structure A, the second group includes contact structure B, the third group includes contact structure C, and the fourth group includes contact structure D. Contact structures A, B, C, and D can be alternately arranged in the dielectric portion 107 of the word line pickup area 103. For example, as shown in the first row extending along the x-direction, contact structure A from the first group is set, followed by contact structure B from the second group, contact structure C from the third group, and then contact structure D from the fourth group. Then, after contact structure D from the fourth group, another contact structure A from the first group is set, followed by another contact structure B from the second group, another contact structure C from the third group, and then another contact structure D from the fourth group.

[0126] In the second row extending along the x-direction, contact structure C of the third group is set, followed by contact structure D of the fourth group, contact structure A of the first group, and then the second contact structure B of the second group. Then, after contact structure B of the second group, another contact structure C of the third group is set, followed by another contact structure D of the fourth group, another contact structure A of the first group, and then another contact structure B of the second group. It is conceivable that contact structures A, B, C, and D can be arranged in any other manner in the dielectric portion 107, and this document does not limit this arrangement.

[0127] Figure 2E Some aspects of this disclosure are shown. Figure 2D The contact depth of the contact structures in the table is specified. Specifically, Table 1 lists the different contact depths of contact structures A, B, C, and D in different groups. For example, contact structure D in the fourth group can be formed in (i) a contact hole formed by etching multiple layers in the stacked structure 201, and (ii) a lateral opening below the contact hole, for example, as follows: Figures 7M-7Q As shown. The number of etched layers for the contact hole can be in the range of 0-127, so that the contact depth of the contact structure D can be in the range of 1-128 layers (for example, the contact depth of the contact structure D = the number of etched layers for the contact hole + 1, where "1" represents the layer forming the lateral opening of the lateral contact member 206 of the contact structure D). That is, the contact depth of the contact structure D can be any one of 1-128 layers.

[0128] Similarly, in the third group, the number of etched layers for the contact holes of contact structure C can be in the range of 128-255 layers, resulting in a contact depth of 129-256 layers. In the second group, the number of etched layers for the contact holes of contact structure B can be in the range of 256-383 layers, resulting in a contact depth of 257-384 layers. In the first group, the number of etched layers for the contact holes of contact structure A can be in the range of 384-311 layers, resulting in a contact depth of 385-512 layers.

[0129] The contact depth of contact structure D is less than the contact depth of contact structure C. The contact depth of contact structure C is less than the contact depth of contact structure B. The contact depth of contact structure B is less than the contact depth of contact structure A.

[0130] Figure 3A A cross-sectional side view of a storage device 100 having a contact structure 106 according to some aspects of this disclosure is shown. A cross-section can be along... Figure 1 The core array region 101 is in the BB direction, and another cross section can be along... Figure 1 The CC direction in the text pickup area 103. For example... Figure 3A As shown, the memory device 100 may include channel structures 110 in a core array region 101. Each channel structure 110 may extend vertically through the interleaved conductive layer 302 (word line, e.g., tungsten) and the first dielectric layer 203 (e.g., silicon oxide) in the core array region 101 of the stacked structure 201 into the semiconductor layer 207. The memory device 100 may also include virtual channel structures 112 in a conductive portion 105 of a word line pickup region 103. Each virtual channel structure 112 may extend vertically through the interleaved conductive layer 302 and the first dielectric layer 203 in the core array region 101 into the semiconductor layer 207. The memory device 100 may also include slot structures 108 across the core array region 101. Each slot structure 108 may also extend vertically through the interleaved conductive layer 302 and the first dielectric layer 203 in a second portion of the stacked structure 201 into the semiconductor layer 207.

[0131] like Figure 3AAs shown, the slot structure 108 may include a slot spacer 309 that separates the conductive layers 302 (word lines) between different blocks 102. In some implementations, the slot structure 108 is an insulating structure that does not contain any contacts (i.e., does not serve as source contacts) and therefore does not introduce parasitic capacitance and leakage current with respect to the conductive layers 302 (word lines). In some implementations, the slot structure 108 is a front-side source contact that also includes a conductive portion (e.g., including W, polysilicon, and / or TiN) surrounded by the slot spacer 309. As described in detail below, the slot forming the slot structure 108 can serve as a pathway and starting point for forming the conductive layers 302 during the gate replacement process. Therefore, the slot structure 108 is surrounded by the conductive layers 302 of the core array region 101 or the conductive portions 105 of the word line pickup region 103.

[0132] like Figure 3A As shown, in some implementations, the memory device 100 further includes a plurality of drain select gate (DSG) channel structures 307, which are located above and in contact with the upper end of the channel structure 110. The memory device 100 may also include a DSG layer 304, which includes a semiconductor layer (e.g., a polysilicon layer) on a stacked structure 201 located in the core array region 101 but not in the word line pickup region 103, such as... Figure 3A As shown. Each DSG channel structure 307 may extend vertically through the DSG layer 304 to contact the upper end of the corresponding channel structure 110. In some implementations, the memory device 100 also includes a stop layer 311 (e.g., a silicon nitride layer) located on the DSG layer 304. The DSG channel structure 307 may include a semiconductor layer (e.g., polysilicon) and spacers surrounding the semiconductor layer. In some implementations, the memory device 100 includes a DSG stack comprising one or more DSG layers and one or more dielectric layers (e.g., silicon oxide layers) staggered above the stack structure 201.

[0133] like Figure 3AAs shown, the memory device 100 may further include a local contact layer located above the stop layer 311 and the stack structure 201. In some implementations, the local contact layer includes various local contacts, such as channel contacts 306 (also known as bit line contacts) located above and in contact with the DSG channel structure 307 in the core array region 101. The local contact layer may also include one or more interlayer dielectric (ILD) layers (also known as "intermetallic dielectric (IMD) layers") in which the local contacts may be formed. The channel contacts 306 in the local contact layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the local contact layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof.

[0134] The storage device 100 may include a stacked structure 201 with uniform height and contact structures 106 located in the dielectric portion 107 of the word line pickup region 103 for word line pickup / fan-out, instead of placing the stepped structure and word line contacts on different levels / steps of the stepped structure. Figure 3A As shown, the lateral contact member 206 of each contact structure 106 in the dielectric portion 107 can extend laterally in the y-direction (bit line direction) to contact the corresponding conductive layer 302 (word line) in the conductive portion 105 at the same layer of the stacked structure 201. According to some implementations, since the lateral contact member 206 contacts the vertical contact member 204 of the contact structure 106, each contact structure 106 is electrically connected to the corresponding conductive layer 302 (word line) on the cross-conductive portion 105 in the word line pickup region 103 and the core array region 101. In other words, the contact structure 106 can extend vertically through the stacked structure 201 at different depths to electrically connect to word lines at different levels, respectively, to achieve word line pickup / fan-out.

[0135] As described in detail below, during the gate replacement process, some of the second dielectric layers 205 (e.g., silicon nitride) remain intact in the dielectric portion 107 of the word line pickup region 103, and contact structures 106 are formed by etching the first dielectric layers 203 and second dielectric layers 205 in the dielectric portion 107. Thus, the contact structures 106 extend into the interleaved first dielectric layers 203 and second dielectric layers 205 and are surrounded by the first dielectric layers 203 and second dielectric layers 205 in the dielectric portion 107 of the word line pickup region 103. The bottom of each contact structure 106 may be aligned with the corresponding second dielectric layer 205 instead of the first dielectric layer 203, and the corresponding second dielectric layer 205 may be partially replaced by a lateral contact member 206 to form an electrical connection between the vertical contact member 204 of the contact structure 106 and the corresponding conductive layer 302 (word line). Therefore, in some implementations, in the dielectric portion 107 of the word line pickup area 103, the lateral contact member 206 is sandwiched between two first dielectric layers 203, rather than between two second dielectric layers 205.

[0136] exist Figure 3A In some of the implementations shown, due to their manufacturing process resulting in a relatively large critical dimension compared to word line contacts in some 3D memory devices, the contact structure 106 also includes a filler 208 surrounded by the vertical contact member 204. That is, the contact hole may not be completely filled by the spacer 202 and the vertical contact member 204, and the remaining space of the contact hole may be filled with a dielectric material as the filler 208, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0137] like Figure 3BAs shown in the enlarged view, in some implementations, the channel structure 110 includes a channel via filled with a semiconductor layer (e.g., as channel layer 354) and a composite dielectric layer (e.g., as memory layer 352). In some implementations, the channel layer 354 comprises silicon (e.g., amorphous silicon, polycrystalline silicon, or monocrystalline silicon). For example, the channel layer 354 may comprise polycrystalline silicon. In some implementations, the memory layer 352 is a composite layer comprising a tunneling layer 360, a storage layer 358 (also referred to as a "charge trapping layer"), and a barrier layer 356. The remaining space of the channel via may be partially or completely filled with a filler comprising a dielectric material (e.g., silicon oxide) and / or air gaps. The channel structure 110 may have a cylindrical shape (e.g., columnar). According to some implementations, the filler, channel layer 354, tunneling layer 360, storage layer 358, and barrier layer 356 are arranged radially from the center to the outer surface of the column in this order. The tunneling layer 360 may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 358 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 356 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In one example, the storage layer 352 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0138] like Figure 3B As shown, the memory device 100 may further include high-k gate dielectric layers 362, each gate dielectric layer 362 sandwiched between adjacent conductive layers 302 and the first dielectric layer 203 in the core array region 101 and between conductive portions 105 of the word line pickup region 103. As described in the following detailed description of the manufacturing process, the high-k gate dielectric layers 362 may be formed prior to the formation of the conductive layers 302, such that the conductive layers 302 may be formed surrounded by the high-k gate dielectric layers 362. The portion of the high-k gate dielectric layer 362 laterally located between the memory layer 352 and the conductive layer 302 of the channel structure 110 may be used as the gate dielectric of the memory cell. The high-k gate dielectric layer 362 may include a high-k dielectric material, such as alumina (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or any combination thereof.

[0139] like Figure 3B As shown, compared to other high-k gate dielectric layers 362, the portion of the high-k gate dielectric layer 362 that surrounds the conductive layer 302 (the word line portion) and contacts the lateral contact member 206 of the contact structure 106 is removed to expose the conductive layer 302, so that the lateral contact member 206 can be electrically connected to the conductive layer 302.

[0140] In some implementations, the virtual channel structure 112 has the same structure as the channel structure 110 because they are formed in the same manufacturing process. However, the virtual channel structure 112 cannot perform the same memory functions as the channel structure 110, at least because, according to some implementations, the virtual channel structure 112 does not contact any DSG channel structure 307 or any local contacts (e.g., channel contacts 306) in the local contact layer to pick up / fan out the virtual channel structure 112, such as... Figure 3A As shown. It can be understood that in some examples, the dummy channel structure 112 and the channel structure 110 can have different structures and can be formed in different manufacturing processes. For example, the dummy channel structure 112 can be filled with a dielectric material instead of a semiconductor material (such as channel layer 354). Nevertheless, both the dummy channel structure 112 and the channel structure 110 can perform the function of mechanically supporting the stacked structure 201, especially during the gate replacement process, as described in the following detailed description of the manufacturing process.

[0141] Figure 4 A cross-sectional side view of a memory device 400, including peripheral circuitry, according to some aspects of this disclosure is shown. The memory device 400 may be, for example, an example implementation of memory device 100. The cross-section may be along a path similar to... Figure 1 The direction of DD in the middle. Figure 4 It can include similar to Figure 1 , Figures 2A-2E and Figures 3A-3B The components are described herein, and similar descriptions will not be repeated here. The storage device 400 may include a semiconductor structure 460 and peripheral circuitry 430 stacked on and connected to the semiconductor structure 460.

[0142] The peripheral circuitry 430 may include a semiconductor layer 431 and a device layer 432 disposed on and in contact with the semiconductor layer 431. In some implementations, the device layer 432 includes one or more circuits, such as driver circuitry, page buffer circuitry, and logic circuitry. In some implementations, the device layer 432 includes a plurality of transistors 433 in contact with the semiconductor layer 431. The transistors 433 may include any transistor, such as a metal-oxide-semiconductor (MOS) transistor, a complementary metal-oxide-semiconductor (CMOS) transistor, or other types of transistors.

[0143] In some implementations, the peripheral circuitry 430 may further include a connection layer 434 and a bonding layer 435. The connection layer 434 may be connected to the device layer 432 to transmit electrical signals to and from the device layer 432. The connection layer 434 may be vertically positioned between the bonding layer 435 and the device layer 432. The connection layer 434 may include multiple interconnects (also referred to herein as “contacts”), including lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnects in the connection layer 434 may be coupled to transistors 433 in the device layer 432. The connection layer 434 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic interlayer dielectric (IMD) layers”) in which lateral lines and vias may be formed. That is, the interconnect layer 434 may include lateral lines and vias in multiple ILD layers. In some implementations, devices in device layer 432 are coupled to each other through interconnects in interconnect layer 434. For example, different transistors 433 may be coupled to each other through interconnect layer 434. The interconnects in interconnect layer 434 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer 434 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric materials, or any combination thereof. In some implementations, the interconnects in interconnect layer 434 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in conductive metallic materials.

[0144] Semiconductor structure 460 may be at least divided into a core array region 101 and a word line pickup region 103. In some implementations, semiconductor structure 460 may include a semiconductor layer 207 and a stacked structure 201 above the semiconductor layer 207. Stacked structure 201 may include alternating first layers and first dielectric layers 203. Stacked structure 201 may include a first portion 462 and a second portion 464 adjacent to the first portion 462. In some examples, the second portion 464 of stacked structure 201 may include a portion of stacked structure 201 in the core array region 101 and a conductive portion 105 of word line pickup region 103. The first portion 462 of stacked structure 201 may include a portion of stacked structure 201 in the dielectric portion 107 of word line pickup region 103.

[0145] The first layer of the first portion 462 may include a second dielectric layer 205, while the first layer of the second portion 464 may include a conductive layer 302. For example, the first portion 462 of the stacked structure 201 may include staggered second dielectric layers 205 and first dielectric layers 203. The second portion 464 of the stacked structure 201 may include staggered conductive layers 302 and first dielectric layers 203.

[0146] In some implementations, the semiconductor structure 460 may further include a contact structure 116 extending through the first portion 462. Peripheral circuitry 430 may be connected to the contact structure 116. The semiconductor structure 460 may also include a channel structure 110 extending through the second portion 464 into the semiconductor layer 207.

[0147] like Figure 4 As shown, the semiconductor structure 460 may further include a connection layer 408 formed on and electrically connected to the channel structure 110 to transmit electrical signals to and from memory cells formed in the channel structure 110. The connection layer 408 may also be connected to the contact structure 106. The semiconductor structure 460 may include a bonding layer 425 located above and in contact with the connection layer 408. In some implementations, the semiconductor structure 460 and the peripheral circuitry 430 may be coupled to each other via hybrid bonding. For example, the connection layer 434 of the peripheral circuitry 430 may be bonded to the connection layer 408 of the semiconductor structure 460 using bonding layers 435 and 425. The bonding contacts in each of the bonding layers 425 and 435 and the surrounding dielectric may be used for hybrid bonding.

[0148] Figures 5A-5J The manufacturing process for forming a storage device 100 having a contact structure 106 is shown according to some aspects of this disclosure. Figure 6 This is a flowchart of a method 600 for forming a storage device 100 having a contact structure 106, based on some aspects of this disclosure. Figures 5A-5J and Figure 6 They will be described together. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 6 The order shown is different from the order in which they are executed.

[0149] refer to Figure 6Method 600 begins at operation 602, wherein a stacked structure comprising an interleaved first dielectric layer and a second dielectric layer is formed. The first dielectric layer may comprise silicon oxide, and the second dielectric layer may comprise silicon nitride. In some implementations, to form the stacked structure, the first dielectric layer and the second dielectric layer are alternately deposited over a semiconductor layer, such as a substrate. The substrate may be a silicon substrate.

[0150] Method 600 proceeds to operation 604, such as... Figure 6 As shown, a channel structure extending through a first dielectric layer and a second dielectric layer is formed in a first region of the stacked structure. In some implementations, to form the channel structure, a channel via extending vertically through the stacked structure is formed, and a memory layer and a channel layer are sequentially formed above the sidewall of the channel via. In some implementations, a virtual channel structure extending through the first dielectric layer and the second dielectric layer is formed in a second region of the stacked structure during the same process of forming the channel structure. That is, a channel structure and a virtual channel structure extending through the first dielectric layer and the second dielectric layer can be formed simultaneously in the first region and the second region of the stacked structure, respectively.

[0151] like Figure 5A As shown, a stacked structure 201 is formed over a semiconductor layer 207. This stacked structure 201 includes multiple pairs of first dielectric layers 203 and second dielectric layers 205 (also referred to as stacked sacrificial layers). According to some implementations, the stacked structure 201 includes vertically interleaved first dielectric layers 203 and second dielectric layers 205. The first dielectric layers 203 and second dielectric layers 205 may be alternately deposited over the semiconductor layer 207 to form the stacked structure 201. In some implementations, each first dielectric layer 203 includes a layer of silicon oxide, and each second dielectric layer 205 includes a layer of silicon nitride. The stacked structure 201 can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0152] Channel vias 510 can be formed in the core array region 101, each of which is an opening extending vertically through the stacked structure 201. In some implementations, multiple openings are formed, such that each opening becomes a location for growing a single channel structure 110 in a subsequent process. In some implementations, the fabrication process for the channel vias 510 used to form the channel structure 110 includes wet etching and / or dry etching, such as deep-ion reactive etching (DRIE). Virtual channel vias 512 can be simultaneously formed in the word line pickup region 103 using the same wet etching and / or dry etching, such as DRIE, where the virtual channel via 512 is another opening extending vertically through the stacked structure 201.

[0153] like Figure 5B As shown, a channel structure 110 can be formed in a channel via 510 in the core array region 101 of the stacked structure 201. A memory layer (including a barrier layer, a storage layer, and a tunneling layer) and a channel layer are sequentially formed along the sidewalls and bottom surface of the channel via 510. In some implementations, the memory layer is first deposited along the sidewalls and bottom surface of the channel via 510, and then a semiconductor channel is deposited over the memory layer. Subsequently, the barrier layer, storage layer, and tunneling layer can be deposited in this order using one or more thin film deposition processes (e.g., ALD, CVD, PVD), any other suitable process, or any combination thereof to form the memory layer. The channel layer can then be formed by depositing a semiconductor material (e.g., polysilicon) on the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD), any other suitable process, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are subsequently deposited to form the memory layer and the channel layer of the channel structure 110.

[0154] In some implementations, such as Figure 5B As shown, a virtual channel structure 112 can be formed in a virtual channel via 512 in the word line pickup region 103 of the stacked structure 201, and its formation process is the same as that for forming the channel structure 110. The virtual channel structure 112 can be deposited simultaneously with the channel structure 110 using the same thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to deposit a memory layer (including a barrier layer, a storage layer, and a tunneling layer) and a channel layer. It is understood that in some examples, the virtual channel structure 112 can be formed in a process separate from the channel structure 110.

[0155] like Figure 5CAs shown, a DSG layer 304 and a stop layer 311 are formed on the core array region 101 of the stacked structure 201. The DSG layer 304 may include a semiconductor layer (e.g., a polysilicon layer), and the stop layer 311 may include a silicon nitride layer. The DSG layer 304 and the stop layer 311 may be sequentially deposited on the core array region 101 of the stacked structure 201 (but not on the word line pickup region 103) using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). A DSG channel structure 307 may be formed, extending vertically through the DSG layer 304 and the stop layer 311 to contact the upper end of the channel structure 110 but not the virtual channel structure 112, as shown. Figure 5C As shown. In order to form the DSG channel structure 307, DSG holes can be etched through the DSG layer 304 and the stop layer 311 respectively to expose the upper end of the channel structure 110, and spacers (e.g., having silicon oxide) and semiconductor layers (e.g., having polysilicon) can be sequentially deposited into the DSG holes using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to fill the DSG holes.

[0156] Method 600 continues with operation 606, such as... Figure 6 As shown, in this embodiment, all second dielectric layers in the first region and portions of the second dielectric layers in the second region of the stacked structure are replaced with conductive layers, for example, through a gate replacement process. The conductive layers may include metal.

[0157] like Figure 5D As shown, the slot 520 is an opening that extends vertically through the stop layer 311, the DSG layer 304, and the first dielectric layer 203 and the second dielectric layer 205 (also known as the stacked sacrificial layer) of the stacked structure 201 to the semiconductor layer 207. The slot 520 can also extend laterally in the x-direction (word line direction) across the core array region 101 and the word line pickup region 103, for example, corresponding to… Figure 1 The slot structure 108 is shown in the figure. In some implementations, the fabrication process for forming the slot 520 includes wet etching and / or dry etching, such as DRIE, of the first dielectric layer 203 and the second dielectric layer 205. The etching process through the stacked structure 201 may not stop at the top surface of the semiconductor layer 207 and may continue etching portions of the semiconductor layer 207 to ensure that the slot 520 extends vertically through all the first dielectric layers 203 and the second dielectric layers 205 of the stacked structure 201 from beginning to end.

[0158] like Figure 5EAs shown, a portion of the slot 520 in the core array region 101 is covered by a sacrificial layer 524. In some implementations, a sacrificial layer 524 (e.g., a polysilicon layer or a carbon layer), different from the first dielectric layer 203 and the second dielectric layer 205, is deposited into the slot 520 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the slot 520 (covering the first dielectric layer 203 and the second dielectric layer 205 exposed in the slot 520). The sacrificial layer 524 can then be patterned using photolithography and wet etching and / or dry etching to remove a portion of the sacrificial layer 524 in the word line pickup region 103, leaving only a portion of the sacrificial layer 524 in the core array region 101 to cover only a portion of the slot 520 in the core array region 101.

[0159] A portion of the second dielectric layer 205 in the conductive portion 105 of the word line pickup region 103 is removed by wet etching to form lateral grooves 526, leaving the remaining portion of the second dielectric layer 205 in the dielectric portion 107 of the word line pickup region 103 intact. In some implementations, a portion of the second dielectric layer 205 is wet-etched by applying a wet etchant through the portion of the gap 520 in the word line pickup region 103 not covered by the sacrificial layer 524, thereby creating staggered lateral grooves 526 between the first dielectric layers 203. The wet etchant may include phosphoric acid for etching the second dielectric layer 205 comprising silicon nitride. In some implementations, the etching rate and / or etching time are controlled to remove only a portion of the second dielectric layer 205 in the conductive portion 105, while leaving the remaining portion of the second dielectric layer 205 in the dielectric portion 107 intact. By controlling the etching time, the wet etchant does not travel indefinitely to completely remove the second dielectric layer 205 in the word line pickup region 103, thereby defining two portions in the word line pickup region 103—a dielectric portion 107 in which the second dielectric layer 205 is removed, and a dielectric portion 107 in which the second dielectric layer 205 is retained. Figure 7E As shown, since a portion of the gap 520 in the core array region 101 is covered by a sacrificial layer 524, which is resistant to the etchant that removes the second dielectric layer 205, all the second dielectric layers 205 in the core array region 101 remain intact.

[0160] like Figure 5F As shown, by removing the sacrificial layer 524 (as... Figure 5EAs shown, a portion of the slot 520 in the core array region 101 is reopened to expose the first dielectric layer 203 and the second dielectric layer 205. In some implementations, a portion of the sacrificial layer 524 in the slot 520 of the core array region 101 is selectively etched away, for example, using potassium hydroxide (KOH) to etch the sacrificial layer 524 having polysilicon, to open a portion of the slot 520 in the core array region 101.

[0161] Moreover, such as Figure 5F As shown, the horizontal groove 526 in the character line picking area 103 (such as...) Figure 5E As shown, portions of the grooves 526 and 520 are covered by a sacrificial layer 528. In some implementations, a sacrificial layer 528 (e.g., a polysilicon layer or a carbon layer) different from the first dielectric layer 203 and the second dielectric layer 205 is deposited into the lateral grooves 526 and 520 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the 520 (covering the exposed first dielectric layer 203 and the second dielectric layer 205). The sacrificial layer 528 can then be patterned using photolithography and wet etching and / or dry etching to remove portions of the sacrificial layer 528 in the core array region 101, leaving only the portion of the sacrificial layer 528 in the word line pickup region 103, to cover only portions of the lateral grooves 526 and 520 in the word line pickup region 103, but not the portion of the 520 in the core array region 101. It can be understood that the lateral recess 526 can be considered as part of the gap 520 in the word line pickup area 103. Therefore, even if only the lateral recess 526 is completely or partially filled by the sacrificial layer 528 (e.g., as shown in the image), Figure 5F As shown), the portion of the gap 520 in the word line pickup area 103 can still be considered as covered.

[0162] All second dielectric layers 205 in the core array region 101 were completely removed by wet etching. Figure 5E (As shown), to form lateral grooves 530. In some implementations, the second dielectric layer 205 is wet-etched by applying a wet etchant to portions of the gaps 520 in the core array region 101 not covered by the sacrificial layer 528, thereby creating staggered lateral grooves 530 between the first dielectric layers 203. The wet etchant may include phosphoric acid for etching the second dielectric layer 205 comprising silicon nitride. In some implementations, the etching rate and / or etching time are controlled to ensure that all of the second dielectric layer 205 in the core array region 101 is completely etched away. Figure 5FAs shown, since the portion of the gap 520 in the word line pickup area 103 is covered by the sacrificial layer 528, which is resistant to the etchant used to remove the second dielectric layer 205, the remaining portion of the second dielectric layer 205 in the dielectric portion 107 of the word line pickup area 103 remains intact.

[0163] like Figure 5G As shown, by removing the sacrificial layer 528 (as... Figure 5F As shown, the portion of the slot 520 in the word line pickup area 103 is reopened to expose the remaining portions of the first dielectric layer 203 and the second dielectric layer 205 in the word line pickup area 103. In some implementations, the sacrificial layer 528 is selectively etched away from the portion of the slot 520 in the word line pickup area 103, for example, using KOH to etch the sacrificial layer 528 having polysilicon, to open the portion of the slot 520 (and the lateral groove 526) in the word line pickup area 103.

[0164] like Figure 5H As shown, the conductive layer 302 is deposited through the slot 520 into the lateral grooves 530 and 526 in the core array region 101 (e.g., ...). Figure 5G (As shown) the conductive portion 105 of the neutral word line pickup region 103. In some implementations, a high-k gate dielectric layer 362 is deposited in the lateral recesses 526 and 530 before the conductive layer 302, such that the conductive layer 302 is deposited on and surrounded by the high-k gate dielectric layer 362, for example, corresponding to Figure 3B The example shown. The conductive layer 302 (e.g., a metal layer) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0165] like Figure 5I As shown, in gap 520 (e.g.) Figure 5H Slot spacers 309 are formed in the stacked structure 201 to form a slot structure 108 that extends vertically through the interlaced conductive layers 302 and the first dielectric layer 203 of the stacked structure 201 and laterally across the conductive portions 105 of the core array region 101 and the word line pickup region 103. Slot spacers 309 can be formed by depositing dielectrics into the slots 520 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some implementations, conductive material (e.g., as source contacts) is deposited as part of the slot structure 108 into the slots 520 following the slot spacers 309.

[0166] like Figure 6As shown, method 600 continues with operation 608, wherein a contact structure is formed in a second region of the stacked structure extending through the remaining portions of the first dielectric layer and the second dielectric layer, such that the contact structure is respectively connected to the conductive layer in the second region of the stacked structure.

[0167] like Figure 5J As shown, by executing the following reference... Figures 7A-7Q The operation described above forms a contact structure 106 in the dielectric portion 107 of the word line pickup area 103. Therefore, a contact structure 106 is formed. Figure 3A The storage device 100 shown.

[0168] Figures 7A-7Q The manufacturing process for forming the contact structure 106 in the stacked structure 201 is illustrated according to some aspects of this disclosure. By way of example, in Figures 7A-7Q The contact structure 106 formed during the manufacturing process can be divided into four groups (e.g., Figure 2D and Figure 2E (The four groups shown). About Figures 7A-7M The stacked structure 201 can form a first set of contact holes in a first group, a second set of contact holes in a second group, a third set of contact holes in a third group, and a fourth set of contact holes in a fourth group. Regarding... Figures 7N-7Q The first set of contact structures, the second set of contact structures, the third set of contact structures, and the fourth set of contact structures can be formed in the first set of contact holes, the second set of contact holes, the third set of contact holes, and the fourth set of contact holes, respectively.

[0169] The first group of contact structures may include a first set of contact shoulders 212 located in a first stack pair. The second group of contact structures may include a second set of contact shoulders 212 located in a second stack pair. The third group of contact structures may include a third set of contact shoulders located in a third stack pair. The fourth group of contact structures may include a fourth set of contact shoulders 212 located in a fourth stack pair. The first stack pair, the second stack pair, the third stack pair, and the fourth stack pair are different stack pairs.

[0170] To form the first set of contact holes in the first group, such as Figure 7A As shown, a barrier layer 702 can be formed on the stacked structure 201. For example, the barrier layer 702 may include AlO or polysilicon. The barrier layer 702 can be formed by depositing a semiconductor material (e.g., polysilicon) on the stacked structure 201 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0171] A first mask 703 may be deposited on the barrier layer 702. The first mask 703 may be a hard mask (HM). For example, the first mask 703 may include a carbon layer 704 and a silicon oxynitride (SiON) layer 706. The carbon layer 704 may be formed by depositing carbon on the barrier layer 702 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The SiON layer 706 may be formed by depositing SiON on the carbon layer 704 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0172] like Figure 7B As shown, an assembly of mask openings 708 extending through the first mask 703 (including the carbon layer 704 and the SiON layer 706) and the barrier layer 702 can be formed. In some implementations, the fabrication process for forming the mask openings 708 may include wet etching and / or dry etching, such as deep ion reactive etching (DRIE).

[0173] like Figure 7C As shown, the stacked structure 201 can be etched through the set of openings 708 in the mask to respectively target the first set 710 forming the openings in the first group of the stacked structure 201. The first mask 703 (as shown) can be removed. Figure 7B (As shown) to expose the barrier layer 702. Without loss of generality, only one mask opening 708 and one opening 710 are shown in the figure. It is contemplated that the set of mask openings 708 may include one or more mask openings 708, and the first set of openings 710 may include one or more openings 710, which is not limited herein. The first set of openings 710 may have a first depth 709 in the z-direction, and the bottom of the first set of openings 710 is located in the same first stack pair (e.g., first dielectric layer 203A and second dielectric layer 205A).

[0174] For example, the first group is Figures 2D-2E The first set of contact structures A in the middle. The first set of openings 710 is formed by etching 384 layers of stacked structure 201 through the first set of mask openings 708 respectively. That is, the first depth 709 of openings 710 can be 384 layers.

[0175] In some implementations, the fabrication process for forming the opening 710 includes wet etching and / or dry etching, such as deep-ion reactive etching (DRIE). In some implementations, a slicing process can be used to form the opening 710. As used herein, a "slicing" process is a process of increasing the depth of one or more openings extending through interlaced first and second dielectric layers by multiple etch cycles. Each etch cycle may include one or more dry and / or wet etch processes that etch a pair of first and second dielectric layers, i.e., reduce the depth by stacking the pairs.

[0176] To form a second set of contact holes, such as Figure 7D As shown, a second mask 713 can be deposited over the barrier layer 702. The second mask 713 can be a hard mask. For example, the second mask 713 may include a carbon layer 714 and a SiON layer 716. The carbon layer 714 and the SiON layer 716 can be deposited by performing processes similar to... Figure 7A The process of forming the carbon layer 704 and the SiON layer 706 in the middle is described in detail here, and similar descriptions will not be repeated here.

[0177] like Figure 7E As shown, an assembly of mask openings 718 extending through the second mask 713 (including the carbon layer 714 and the SiON layer 716) and the barrier layer 702 can be formed. In some implementations, the fabrication process for forming the mask openings 718 may include wet etching and / or dry etching, such as deep ion reactive etching (DRIE).

[0178] like Figure 7F As shown, the stacked structure 201 can be etched through the set of mask openings 718 to form a second set of openings 720 for the second group in the stacked structure 201. The second mask 713 can be removed (as shown). Figure 7E (As shown) to expose the barrier layer 702. Without loss of generality, only one mask opening 718 and one opening 720 are shown in the figure. It is contemplated that the set of mask openings 718 may include one or more mask openings 718, and a second set of openings 720 may include one or more openings 720, but this is not limited thereto. The second set of openings 720 may have a second depth 722 in the z-direction, and the bottom of the second set of openings 720 is located in the same second stack pair (e.g., first dielectric layer 203B and second dielectric layer 205B). The second set of openings 720 can be exposed by performing similar procedures as described above. Figure 7C The process of forming the first set of openings 710 in the middle will not be repeated in this article.

[0179] For example, the second group is Figures 2D-2EThe second set of contact structures B in the middle. The second set of openings 720 is formed by etching 256 layers of the stacked structure 201 through the set of mask openings 718 respectively. That is, the second depth 722 of the openings 720 can be 256 layers.

[0180] To form the third set of contact holes, such as Figure 7G As shown, a third mask 723 can be deposited over the barrier layer 702. The third mask 723 can be a hard mask. For example, the third mask 723 may include a carbon layer 724 and a SiON layer 726. The carbon layer 724 and the SiON layer 726 can be deposited by performing processes similar to... Figure 7A The process of forming the carbon layer 704 and the SiON layer 706 in the middle is described in detail here, and similar descriptions will not be repeated here.

[0181] like Figure 7H As shown, an assembly of mask openings 728 extending through the third mask 723 (including the carbon layer 724 and the SiON layer 726) and the barrier layer 702 can be formed. In some implementations, the fabrication process for forming the mask openings 728 may include wet etching and / or dry etching, such as deep ion reactive etching (DRIE).

[0182] like Figure 7I As shown, the stacked structure 201 can be etched through the set of openings 728 in the mask to form a third set of openings 730 in the third set of stacked structure 201. The third mask 723 can be removed (as shown). Figure 7H (As shown) to expose barrier layer 702. Without loss of generality, only one mask opening 728 and one opening 730 are shown in the figure. It is contemplated that the set of mask openings 728 may include one or more mask openings 728, and a third set of openings 730 may include one or more openings 730, but is not limited thereto. The third set of openings 730 may have a third depth 732 in the z-direction, and the bottom of the third set of openings 730 is located in the same third stack pair (e.g., first dielectric layer 203C and second dielectric layer 205C). The third set of openings 730 can be configured similarly to those described above for... Figure 7C The process described in the first set of openings 710 is used to form the openings, and similar descriptions will not be repeated here.

[0183] For example, the third group is Figures 2D-2E The third set of contact structures C. The third set of openings 730 is formed by etching 128 layers of stacked structure 201 through the set of mask openings 728 respectively. That is, the third depth 732 of openings 730 can be 128 layers.

[0184] In order to form a fourth group (for example, the fourth group is) Figures 2D-2EThe fourth set of contact holes in the fourth group of contact structure D in the middle, such as Figure 7J As shown, a fourth mask 733 can be deposited above the barrier layer 702. The fourth mask 733 can be a hard mask. For example, the fourth mask 733 may include a carbon layer 734 and a SiON layer 736. The carbon layer 734 and the SiON layer 736 can be deposited by performing processes similar to... Figure 7A The process of forming the carbon layer 704 and the SiON layer 706 in the middle is described in detail here, and similar descriptions will not be repeated here.

[0185] like Figure 7K As shown, an assembly of mask openings 738 extending through the third mask 733 (including the carbon layer 734 and the SiON layer 736) and the barrier layer 702 can be formed. In some implementations, the fabrication process for forming the mask openings 738 may include wet etching and / or dry etching, such as deep ion reactive etching (DRIE). The fourth mask 733 (e.g., Figure 7J (As shown) to expose the barrier layer 702.

[0186] like Figure 7L As shown, a fifth mask 740 can be deposited over the barrier layer 702. The fifth mask 740 can be a photoresist mask. The fifth mask 740 can be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0187] Regarding the first group, for one or more first openings 710 from the first set of openings 710 that need to be further extended into the stacked structure 201, one or more mask openings 742 corresponding to the one or more first openings 710 can be formed in the fifth mask 740. By way of example, in Figure 7L In the middle, the mask opening 742 is formed above the mask opening 708 and the opening 710.

[0188] Regarding the second set, for one or more first openings 720 in the second set of openings 720 that need to be further extended into the stacked structure 201, one or more mask openings 744 corresponding to the one or more first openings 720 can be formed in the fifth mask 740. By way of example, in Figure 7L In the middle, the mask opening 744 is formed above the mask opening 718 and the opening 720.

[0189] Regarding the third group, for one or more first openings 730 in the second set of openings 730 that need to be further extended into the stacked structure 201, one or more mask openings 746 corresponding to one or more first openings 730 can be formed in the fifth mask 740. By way of example, in Figure 7LIn the middle, the mask opening 746 is formed above the mask opening 728 and the opening 730.

[0190] Regarding the fourth group, for one or more mask openings 738 from the set of mask openings 738 that need to be further extended into the stacked structure 201, one or more mask openings 741 corresponding to the one or more mask openings 738 can be formed in the fifth mask 740. By way of example, in Figure 7L In the middle, the mask opening 741 is formed above the mask opening 738.

[0191] like Figure 7M As shown, the fifth mask 740 (as shown) is used. Figure 7L As shown), the stacked structure 201 can be etched at one or more first openings 710 in the first set of openings 710 to form one or more second openings 748 for the first set that further extend into the stacked structure 201. Furthermore, using a fifth mask 740 (as shown) Figure 7L As shown), the stacked structure 201 can be etched at one or more first openings 720 in the second set of openings 720 to form one or more second openings 750 for the second set extending further into the stacked structure 201. Furthermore, using a fifth mask 740 (as shown) Figure 7L As shown), the stacked structure 201 can be etched at one or more first openings 730 in the first set of openings 730 to form one or more second openings 752 for the third set, extending further into the stacked structure 201. Furthermore, using a fifth mask 740 (as shown) Figure 7L As shown, the stacked structure 201 can be etched at one or more of the mask openings 738 in the set of mask openings 738 to form one or more openings 754 for a fourth group that further extend into the stacked structure 201. The second opening 748, the second opening 750, the second opening 752, and the opening 754 can be formed by simultaneously etching the stacked structure 201 using a fifth mask 740, and can have the same depth. For example, the same depth can be any of 1 layer, 2 layers, 8 layers, 16 layers, 32 layers, or 64 layers. It is conceivable that the same depth can be any other suitable number of layers, and this document is not limited thereto. The fifth mask 740 can be removed to expose the blocking layer 702, as... Figure 7M As shown.

[0192] The first contact hole in the first set of the first group of contact holes can be formed by combining the first of one or more first openings 710 with the first of one or more second openings 748. For example, Figure 7MThe first contact holes of the first group are shown to include openings 710 and 748. A first sidewall shoulder 756 is formed at the bottom of opening 710 in the first contact holes of the first group. The first contact holes of the first group are formed by etching the stacked structure 201 twice using two masks (e.g., mask 703 and mask 740). When the first contact structure in the first group is formed in the first contact hole (as shown below) Figures 7N-7Q (As described in the present disclosure), the first contact structure may include a first contact shoulder formed on the first sidewall shoulder 756. The first contact shoulder may be in the first stack pair. Consistent with some aspects of the present disclosure, the total number of contact shoulders formed in the contact structure is equal to the total number of etches performed to form the contact hole minus 1 (e.g., total number of contact shoulders = total number of etches - 1).

[0193] The first contact hole in the second set of contact holes can be formed by combining the first of one or more first openings 720 and the first of one or more second openings 750. For example, Figure 7M The first contact hole of the second group is shown to include openings 720 and 750. A first sidewall shoulder 758 in the first contact hole of the second group is formed at the bottom of opening 720. The first contact hole of the second group is formed by etching the stacked structure 201 twice using two masks (e.g., mask 713 and mask 740). When the first contact structure of the second group is formed in the first contact hole (as shown below) Figures 7N-7Q The first contact structure may include a first contact shoulder formed on the first sidewall shoulder 758. The contact shoulder may be in the second stack pair.

[0194] The first contact hole in the third set of contact holes can be formed by combining the first of one or more first openings 730 and the first of one or more second openings 752. For example, Figure 7M The first contact hole of the third group is shown to include openings 730 and 752. A first sidewall shoulder 760 in the first contact hole of the third group is formed at the bottom of opening 730. The first contact hole in the third group is formed by etching the stacked structure 201 twice using two masks (e.g., mask 723 and mask 740). When the first contact structure of the third group is formed in the first contact hole (as shown below) Figures 7N-7Q (as described in the text), the first contact structure may include a first contact shoulder formed on the first sidewall shoulder 760. The first contact shoulder may be in the third stack pair.

[0195] The first contact hole in the fourth set of contact holes in the fourth group can be formed as the first of one or more openings 754. For example, Figure 7MThe first contact hole of the fourth group is shown as opening 754. The first contact hole in the fourth group is formed by etching the stacked structure 201 once using a mask (e.g., mask 740). No sidewall shoulders are formed in the first contact hole of the fourth group. When the first contact structure of the fourth group is formed in the first contact hole (as shown below)... Figures 7N-7Q As described in the text, the first contact structure may not have any contact shoulder.

[0196] Imagine performing something similar to the above reference. Figures 7L-7M The operation described herein can be performed by further etching the stacked structure 201 using one or more additional masks to form additional contact holes in the first, second, third, and fourth groups. For example, a sixth mask (e.g., similar to a fifth mask 740) can be deposited over the barrier layer 702. The sixth mask can be a photoresist mask. Regarding the first group, for any one or more second openings 748 that need to extend further into the stacked structure 201, a mask opening corresponding to the second of the one or more second openings 748 can be formed in the sixth mask. Regarding the second group, for any one or more second openings 750 that need to extend further into the stacked structure 201, a mask opening corresponding to the second of the one or more second openings 750 can be formed in the sixth mask. Regarding the third group, for any one or more second openings 752 that need to extend further into the stacked structure 201, a mask opening corresponding to the second of the one or more second openings 752 can be formed in the sixth mask. Regarding the fourth group, for any one or more openings 754 that need to extend further into the stacked structure 201, a mask opening corresponding to the second of the one or more openings 754 can be formed in the sixth mask.

[0197] Then, using a sixth mask, the stacked structure 201 can be etched at the second of one or more second openings 748 to form a third opening for the first group that extends further into the stacked structure 201. Furthermore, using a sixth mask, the stacked structure 201 can be etched at the second of one or more second openings 750 to form a fourth opening for the second group that extends further into the stacked structure 201. Moreover, using a sixth mask, the stacked structure 201 can be etched at the second of one or more second openings 752 to form a fifth opening for the third group that extends further into the stacked structure 201. Furthermore, using a sixth mask, the stacked structure 201 can be etched at the second opening of one or more openings 754 to form a sixth opening for the fourth group that extends further into the stacked structure 201. The third, fourth, fifth, and sixth openings can be formed by simultaneously etching the stacked structure 201 using the sixth mask, and can have the same depth. For example, the same depth can be any remaining layers among 1, 2, 8, 16, 32, or 64 layers. The sixth mask can then be removed to expose the blocking layer 702.

[0198] The second contact hole in the first set of contact holes in the first group can be formed by combining (1) the second of one or more first openings 710 corresponding to the second of one or more second openings 748, (2) the second of one or more second openings 748, and (3) a third opening. For example, the second of one or more first openings 710 corresponding to the second of one or more second openings 748 is an opening 710 located directly above the second of one or more second openings 748. For the second contact hole in the first group, a first sidewall shoulder 756 is formed at the bottom of the second of one or more first openings 710, and a second sidewall shoulder is formed at the bottom of the second of one or more second openings 748. The second contact hole in the first group is formed by etching the stacked structure 201 three times using three masks (e.g., mask 703, mask 740, and a sixth mask). When the second contact structure is formed in the second contact hole in the first group (as follows) Figures 7N-7Q The second contact structure may include a first contact shoulder and a second contact shoulder respectively formed on the first sidewall shoulder 756 and the second sidewall shoulder. The first contact shoulder may be located in the first stack pair. The second contact shoulder is located below the first stack pair.

[0199] The second contact hole in the second set of the second group of contact holes can be formed by combining (1) the second of one or more first openings 720 corresponding to the second of one or more second openings 750, (2) the second of one or more second openings 750, and (3) the fourth opening. For the second contact hole in the second group, a first sidewall shoulder 758 is formed at the bottom of the second of one or more first openings 720, and a second sidewall shoulder is formed at the bottom of the second of one or more second openings 750. The second contact hole in the second group is formed by etching the stacked structure 201 three times using three masks (e.g., mask 713, mask 740, and a sixth mask). When the second contact structure is formed in the second contact hole in the second group (as shown below) Figures 7N-7Q (As described above), the second contact shoulder structure may include a first contact shoulder and a second contact shoulder respectively formed on the first sidewall shoulder 758 and the second sidewall shoulder. The first contact shoulder may be located in the second stack pair. The second contact shoulder is located below the second stack pair.

[0200] The second contact hole in the third set of the third group of contact holes can be formed by combining (1) the second of one or more first openings 730 corresponding to the second of one or more second openings 752, (2) the second of one or more second openings 752, and (3) the fifth opening. For the second contact hole in the third group, a first sidewall shoulder 760 is formed at the bottom of the second of one or more first openings 730, and a second sidewall shoulder is formed at the bottom of the second of one or more second openings 752. The second contact hole in the third group is formed by etching the stacked structure 201 three times using three masks (e.g., mask 723, mask 740, and sixth mask). When the second contact structure is formed in the second contact hole in the third group (as shown below) Figures 7N-7Q As described above, the second contact structure may include a first contact shoulder and a second contact shoulder respectively formed on the first sidewall shoulder 760 and the second sidewall shoulder. The first contact shoulder may be located in the third stack pair. The second contact shoulder is located below the third stack pair.

[0201] The second contact hole in the fourth set of contact holes in the fourth group can be formed by combining (1) the second of one or more openings 754 and (2) the sixth opening. For the second contact hole in the fourth group, a sidewall shoulder is formed at the bottom of the second of one or more openings 754. The second contact hole in the fourth group is formed by etching the stacked structure 201 twice using two masks (e.g., mask 740 and the sixth mask). When the second contact structure is formed in the second contact hole in the fourth group (as shown below) Figures 7N-7Q(as described in the text), the second contact structure may include a contact shoulder formed on a sidewall shoulder at the bottom of the second of one or more openings 754.

[0202] like Figure 7N As shown, remove the blocking layer 702 (e.g.) Figure 7M (As shown). In some implementations, the barrier layer 702 with polysilicon is etched away using KOH. As an example, the first set of contact holes 762 is shown, for example, contact holes 762 are made of... Figure 7M Openings 710 and 748 are formed. A second set of contact holes 764 is shown. For example, contact holes 764 are formed by... Figure 7M Openings 720 and 750 are formed. A third set of contact holes 766 is shown. For example, contact hole 766 is formed by... Figure 7M Openings 730 and 752 are formed. A fourth set of contact holes 768 is shown. For example, contact hole 766 is formed by... Figure 7M The opening 754 is formed.

[0203] For each contact hole 762, 764, 766, or 768, a spacer 202 (e.g., a contact spacer) is formed on the sidewall and bottom surface of the respective contact hole, thereby covering the first dielectric layer 203 and the second dielectric layer 205 exposed from the sidewall and bottom surface of the respective contact hole. In some implementations, the spacer 202 is formed by depositing a dielectric material (e.g., silicon oxide) on the sidewall and bottom surface of the respective contact hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0204] In some implementations, for each contact hole 762, 764, 766, or 768, a portion of the spacer 202 on the bottom surface of the corresponding contact hole is removed by, for example, dry etching to expose a portion of the second dielectric layer 205 in the dielectric portion 107 of the word line pickup region 103. In some implementations, the etching rate, direction, and / or duration of the RIE are controlled to etch only a portion of the spacer 202 on the bottom surface of the corresponding contact hole, but not a portion of the spacer 202 on the sidewalls, i.e., "penetrating" the spacer 202 in the z-direction to expose only the corresponding second dielectric layer 205 from the bottom, but not other second dielectric layers 205 from the sidewalls.

[0205] like Figure 7OAs shown, for each contact hole 762, contact hole 764, contact hole 766, or contact hole 768, a portion of the second dielectric layer 205 exposed from the bottom of the respective contact hole is removed by wet etching to form a lateral opening 770, leaving the remaining portion of the second dielectric layer 205 of the same layer in the dielectric portion 107 of the word line pickup region 103 and other second dielectric layers 205 of other layers intact. The lateral opening 770 may expose the corresponding conductive layer 302 of the same layer in the conductive portion 105 of the word line pickup region 103. In some implementations, a portion of the second dielectric layer 205 is wet-etched through the contact hole using a wet etchant, thereby creating the lateral opening 770 sandwiched between two first dielectric layers 203. The wet etchant may include phosphoric acid for etching the second dielectric layer 205 comprising silicon nitride. In some implementations, the etching rate and / or etching time are controlled to remove only a portion of the second dielectric layer 205 sufficient to expose the corresponding conductive layer 302 of the same layer in the conductive portion 105. By controlling the etching time, the wet etchant does not travel indefinitely to completely remove the second dielectric layer 205 in the dielectric portion 107. Therefore, when removing the second dielectric layer 205, it is not necessary to form a virtual channel structure 112 in the dielectric portion 107 of the word line pickup region 103 to provide mechanical support. Figure 7O As shown, since the sidewalls of the corresponding contact holes are still covered by spacers 202 (e.g., silicon oxide), which resist etchants used to remove the second dielectric layer 205 (e.g., silicon nitride), the second dielectric layer 205 of the other layers in the dielectric portion 107 remains intact.

[0206] In some implementations where a high-k gate dielectric layer 362 is formed around a conductive layer 302 (e.g.) Figure 3B As shown, once the exposed portion of the second dielectric layer 205 is etched from the corresponding contact hole, the corresponding high-k gate dielectric layer 362 surrounding the corresponding conductive layer 302 on the same layer will be exposed. The exposed portion of the corresponding high-k gate dielectric layer 362 can then be etched, for example, using wet etching, to expose the corresponding conductive layer 302 on the same layer.

[0207] like Figure 7PAs shown, for each contact hole 762, contact hole 764, contact hole 766, or contact hole 768, a lateral contact member 206 is formed by depositing a conductive layer through the corresponding contact hole to fill the lateral opening 770. One or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) can be used to deposit a conductive layer such as a metal layer. The deposition rate and / or duration can be controlled to ensure that the lateral contact member 206 can contact the corresponding exposed conductive layer 302 in the same layer as the lateral opening 770. In other words, the second dielectric layer 205 exposed from the bottom of the corresponding contact hole can be partially replaced by the corresponding lateral contact member 206 in the dielectric portion 107 of the word line pickup region 103, while other second dielectric layers 205 in other layers of the dielectric portion 107 remain intact.

[0208] For each contact hole 762, contact hole 764, contact hole 766, or contact hole 768, a vertical contact member 204 is formed on the sidewall of the corresponding contact hole, and the vertical contact member 204 contacts the lateral contact member 206. The vertical contact member 204 can be formed using the same process as the lateral contact member 206, by depositing a conductive layer not only into the lateral opening 770, but also onto the sidewalls and bottom surface of the corresponding contact hole, using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0209] like Figure 7Q As shown, for each contact hole 762, contact hole 764, contact hole 766, or contact hole 768 (e.g. Figure 7P As shown, a filler 208 is formed in the respective contact hole to completely or partially fill the respective contact hole. The filler 208 (e.g., a dielectric layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some implementations, for each contact hole 762, contact hole 764, contact hole 766, or contact hole 768, a contact pad 210 is formed to cover the respective filler 208 and connect to the respective vertical contact member 204. The contact pad 210 (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Chemical mechanical polishing (CMP) can be used to remove excess portions of the conductive and dielectric layers used to form the vertical contact member 204, contact pad 210, and filler 208.

[0210] Reference Figures 7A-7Q The contact structure can be divided into 4 groups. For example, these 4 groups can be... Figures 2D-2EThe four groups shown are mask 703, mask 713, and mask 723 (each including a carbon layer and a SiON layer) and barrier layer 702. These can be used to etch the stacked structure 201 with 384, 256, and 128 layers respectively to form openings 710, 720, and 730. Mask 733 can be used to etch barrier layer 702 to form mask opening 738. Then, up to 127 additional layers (e.g., 64+32+16+8+4+2+1=127) can be etched in the stacked structure 201 from openings 710, 720, 730, and 738 using seven additional masks (e.g., including mask 740). For example, a first additional mask (e.g., mask 740) can be used to further etch 64 layers of the stacked structure 201; a second additional mask can be used to further etch 32 layers of the stacked structure 201; a third additional mask can be used to further etch 16 layers of the stacked structure 201; a fourth additional mask can be used to further etch 8 layers of the stacked structure 201; a fifth additional mask can be used to further etch 4 layers of the stacked structure 201; a sixth additional mask can be used to further etch 2 layers of the stacked structure 201; and a seventh additional mask can be used to further etch 1 layer of the stacked structure 201. Thus, corresponding contact holes are formed for the four groups. Each contact hole can be formed by up to eight etching passes. A contact structure can then be formed in the corresponding contact hole. By using the barrier layer 702, stack offset can be avoided, and the CD of the contact structure formed in the contact hole can be reduced, reducing or eliminating etching defects such as over-etching or under-etching.

[0211] Figure 8 The different numbers of layers etched using different masks according to some aspects of this disclosure are illustrated. For ten masks, Table 2 lists the corresponding number of layers (e.g., ET layers) that could theoretically be etched in the stacked structure 201 using each mask. For example, for the nth mask (n = 1, 2, ..., 10), the number of layers etched using the nth mask could be 2. n-1 Then, the total number of etched layers for the 1st to nth masks (a total of n masks) can be up to 2. n -1.

[0212] For 15 masks, Table 3 lists the corresponding number of layers etched using each mask in some cases. For example, for the nth mask (n = 1, 2, 3, 4, 5, 6, 7), the number of layers etched using the nth mask could be 2. n-1 However, for the nth mask (n = 8, 9, ..., 15), the number of layers etched using the nth mask is much less than 2. n-1 For example, for n>7, the maximum number of layers that can be etched using the nth mask is 60. Therefore, when n>7, more masks (e.g., more than n masks) are needed to achieve 22.n -1 is the total number of etched layers. For example, to etch a total of 507 layers, 15 masks are needed.

[0213] For the 11 masks, Table 4 lists the corresponding number of etched layers for each mask using the solution disclosed herein. For example, refer to... Figures 7A-7Q The first mask 703 (e.g., mask 1 in Table 4) is used to etch 384 layers in the stacked structure 201 to form Figure 7C The opening 710; the second mask 713 (e.g., mask 2 in Table 4) is used to etch 256 layers in the stacked structure 201 to form Figure 7F The opening 720; the third mask 723 (e.g., mask 3 in Table 4) is used to etch 128 layers in the stacked structure 201 to form Figure 7I The opening 730; the fourth mask 733 (e.g., mask 4 in Table 4) is used to etch the barrier layer 702 (denoted as HMEt in Table 4) to form Figure 7K The mask opening 738; and the fifth mask 740 (e.g., mask 5 in Table 4) is used to further etch 64 layers from one or more of openings 710, 720, and 730, as well as opening 738, as shown. Figures 7N-7M As shown, only 11 masks are needed to etch a total of 511 layers, which is fewer than the number of masks required in Table 3. By reducing the number of etching passes and the number of masks used to form the contact structure, the manufacturing process can be simplified, and the CD of the contact structure can be reduced.

[0214] Figure 9 This is a flowchart of another method 900 for forming a 3D memory device with a contact structure, according to some aspects of this disclosure. The 3D memory device may be memory device 100 or any other memory device disclosed herein. It is understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 9 The order shown is different from the order in which they are executed.

[0215] refer to Figure 9 Method 900 begins at operation 902, wherein a stacked structure is formed on a semiconductor layer. The stacked structure comprises alternating first and second dielectric layers. For example, this can be achieved by performing the above-referenced... Figure 5A The operation described is used to form the stacked structure 201.

[0216] like Figure 9 As shown, method 900 proceeds to operation 904, wherein a contact structure is formed extending along a first direction into the stacked structure. See below for reference. Figure 10 A method for forming a stacked structure is shown. For example, it can be achieved by performing the above-mentioned steps. Figures 7A-7Q The operation described herein forms the contact structure 106, and similar descriptions will not be repeated herein.

[0217] Figure 10 This is a flowchart of a method 1000 for forming a contact structure in a stacked structure according to some aspects of this disclosure. It is understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 10 The different execution orders shown are illustrated.

[0218] In some implementations, the contact structure can be divided into one or more groups based on the contact depth of the contact structure in the first direction. (See reference) Figure 10 Method 1000 begins at operation 1002, wherein a set of one or more contact holes is formed for one or more groups of contact structures in a first portion of the stacked structure. Each group of contact structures may include at least one subset of the contact structures.

[0219] Method 1000 proceeds to operation 1004, such as... Figure 10 As shown, one or more sets of contact structures are formed in a set of one or more contact holes. For example, a first set of contact structures can be formed in a first set of contact holes. A second set of contact structures can be formed in a second set of contact holes.

[0220] In some implementations, at operation 1002, method 1000 may include forming a first set of contact holes. Specifically, forming the first set of contact holes may include: forming a barrier layer on a stacked structure; and etching the barrier layer and the stacked structure using a first mask to form a first set of openings in the stacked structure. The first set of openings has a first depth in a first direction, and the bottom of the first set of openings is located in the middle of a first stack pair. For example, as referenced above... Figures 7A-7C The first set of openings 710 can be formed by etching the barrier layer 702 and the stacked structure 201 using a first mask 703. The first set of openings 710 has a first depth 709 in the z-direction, and the bottom of the first set of openings 710 is located in a first stack pair including a first dielectric layer 203A and a second dielectric layer 205A.

[0221] In some implementations, forming the first set of contact holes may further include etching the stacked structure at one or more first openings in the first set of openings using a second mask to form one or more second openings that further extend into the stacked structure. The first set of contact holes may include a first contact hole comprising a first of one or more first openings and a first of one or more second openings. A first sidewall shoulder is formed at the bottom of the first of the one or more first openings. For example, as referenced above. Figure 7M As described above, a mask 740 (such as...) can be used. Figure 7L (As shown) An opening 748 is formed at opening 710 to further extend into the stacked structure 201. The first contact hole in the first group may be formed by opening 710 and opening 748. A sidewall shoulder 756 is formed at the bottom of opening 710.

[0222] In some implementations, the stacked structure may include a first portion and a second portion adjacent to the first portion. Contact structures extend into the first portion of the stacked structure. Method 1000 may also include performing a gate line replacement process to replace a portion of the second dielectric layer in the second portion of the stacked structure with a conductive layer. Contact structures extend into the first portion of the stacked structure and are respectively connected to corresponding conductive layers from the conductive layer. For example, the process described above may be performed. Figures 5D-5I The operation described is for performing a gate line replacement process. For example... Figure 5J As shown, the contact structure 106 formed therein extends into the dielectric portion 107 of the word line pickup area 103 and is connected to the respective conductive layer 302.

[0223] In some implementations, the first set may include a first subset of contact structures associated with a first subset of contact depths within a first depth range. The first subset of contact structures in the first set may include a first contact structure comprising a spacer, a vertical contact member, and a lateral contact member. At operation 1004, method 1000 may include forming a first subset of contact structures in a first set of contact holes. Specifically, forming a first subset of contact structures in a first set of contact holes may include: forming a first contact structure in a first contact hole, comprising forming a spacer on a sidewall of the first contact hole; and forming a lateral contact member below the bottom of the first contact hole and forming a vertical contact member on the sidewall of the spacer to connect to the lateral contact member. The lateral contact member is connected to a corresponding conductive layer in a conductive layer. For example, a similar implementation to the above reference may be performed. Figures 7N-7Q The described operations form the first contact structure.

[0224] In some implementations, the vertical contact member may include a first vertical contact segment, a first contact shoulder in a first set of contact shoulders, and a second vertical contact segment. The first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment. The spacer may include a first spacer segment, a spacer shoulder, and a second spacer segment. The spacer shoulder is connected to the first spacer segment and the second spacer segment and is located in a first stack pair. The spacer shoulder is formed on a first sidewall shoulder, and the first contact shoulder is formed on the spacer shoulder. For example, see reference... Figure 7P Spacer shoulder 221 is formed on sidewall shoulder 756, and contact shoulder 212 is formed on spacer shoulder 221.

[0225] In some implementations, the second group may include a second subset of contact structures associated with a second subset of contact depths within a second depth range. The second depth range differs from the first depth range. At operation 1002, method 1000 may further include forming a second set of contact holes for the second group in the stacked structure; and at operation 1004, method 1000 may further include forming a second subset of contact structures, respectively, within the second set of contact holes. The second subset of contact structures in the second group may include a second set of contact shoulders located in a second stacked pair. The second stacked pair includes a second in the first dielectric layer and a second in the second dielectric layer, and is distinct from the first stacked pair.

[0226] In some implementations, forming the second set of contact holes may include etching the barrier layer and the stacked structure using a third mask to form a second set of openings in the stacked structure. The second set of openings has a second depth in a first direction, and the bottom of the second set of openings is located in the second stacked pair. For example, see reference... Figures 7D-7F An opening 720 can be formed by etching a barrier layer 702 and a stacked structure 201 using a mask 713. The opening 720 may have a second depth 722, and the bottom of the opening 720 is located in a second stack pair including a first dielectric layer 203B and a second dielectric layer 205B.

[0227] The second set of contact holes further includes: during the formation of one or more second openings, using a second mask to etch the stacked structure at one or more third openings in the second set of openings to form one or more fourth openings that further extend into the stacked structure. The second set of contact holes may include second contact holes comprising (i) a first of one or more third openings and (ii) a first of one or more fourth openings. A second sidewall shoulder is formed at the bottom of the first of the one or more third openings.

[0228] For example, refer to Figure 7L-Figure 7MDuring the formation of opening 748, mask 740 is also used to etch stacked structure 201 at opening 720 to form opening 750 that further extends into stacked structure 201. The second contact hole in the second group may include (i) opening 720 and (ii) opening 750. A sidewall shoulder 758 is formed at the bottom of opening 720.

[0229] In some implementations, forming a first set of contact holes may further include: etching a stacked structure at a second of one or more second openings using a fourth mask to form a fifth opening that further extends into the stacked structure. Forming a second set of contact holes may further include: etching a stacked structure at a second of one or more fourth openings using a fourth mask to form a sixth opening that further extends into the stacked structure. The first set of contact holes may include a third contact hole comprising (1) a second of one or more first openings corresponding to a second of one or more second openings, (2) a second of one or more second openings, and (3) a fifth opening. A third sidewall shoulder is formed at the bottom of the second of one or more second openings. The second set of contact holes may include a fourth contact hole comprising (1) a second of one or more third openings corresponding to a second of one or more fourth openings, (2) a second of one or more fourth openings, and (3) a sixth opening. A fourth sidewall shoulder is formed at the bottom of the second of one or more fourth openings.

[0230] In some implementations, a first subset of the contact structures in the first group may include a third contact structure formed in the third contact hole. The third contact structure may include (1) a first contact shoulder formed from the first set of contact shoulders and on the first sidewall shoulder; and (2) a second contact shoulder formed on the third sidewall shoulder. The depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

[0231] In some implementations, the third contact structure further includes a contact pad. The depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction. The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

[0232] In some implementations, forming the second set of contact holes further includes: etching a barrier layer using a fifth mask to form a set of mask openings; and etching a stacked structure at the mask openings in the set of mask openings using a second mask to form a seventh opening extending into the stacked structure. The second set of contact holes may include a sixth contact hole containing the seventh opening. For example, see reference... Figures 7J-7MMask 733 can be used to etch barrier layer 702 to form mask opening 738. Mask 740 can be used to etch stacked structure 201 at mask opening 738 to form opening 754, and mask 740 is also used to etch stacked structure 201 at opening 710 to form a first set of openings 748. The contact holes formed therefrom can then include opening 754.

[0233] In some implementations, one of the contact structures is formed in a contact hole, and the contact hole may include multiple openings formed by etching the stacked structure using multiple etch counts. The total number of contact shoulders formed in the contact structure may be equal to the total number of etch counts minus 1 (e.g., the number of contact shoulders = number of etch counts - 1).

[0234] Figure 11 A block diagram of an exemplary system 1100 with 3D storage devices according to some aspects of this disclosure is shown. System 1100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage devices. Figure 11 As shown, system 1100 may include a host 1108 and a memory system 1102, the memory system 1102 having one or more 3D memory devices 1104 and a memory controller 1106. The host 1108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1108 may be configured to send data to or receive data from the 3D memory device 1104.

[0235] 3D storage device 1104 can be any 3D storage device disclosed herein, such as Figure 1 , Figures 2A-2E ,and Figures 3A-3B The 3D memory device 100 is depicted in the diagram. In some implementations, each 3D memory device 1104 includes NAND flash memory. Consistent with the scope of this disclosure, contact structures can replace ladder structures and word line contacts to implement word line pickup / fan-out functionality, thereby reducing manufacturing costs and simplifying the manufacturing process.

[0236] According to some implementations, memory controller 1106 (also known as controller circuitry) is coupled to 3D storage device 1104 and host 1108 and configured to control 3D storage device 1104. For example, memory controller 1106 may be configured to operate a multi-channel structure via word lines. Memory controller 1106 may manage data stored in 3D storage device 1104 and communicate with host 1108. In some implementations, memory controller 1106 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, memory controller 1106 is designed to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs), as data storage devices for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 1106 can be configured to control the operation of the 3D storage device 1104, such as read, erase, and program operations. The memory controller 1106 can also be configured to manage various functions related to data stored or to be stored in the 3D storage device 1104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 1106 is also configured to handle error correction codes (ECCs) related to data read from or written to the 3D storage device 1104. The memory controller 1106 can also perform any other suitable functions, such as formatting the 3D storage device 1104. The memory controller 1106 can communicate with external devices (e.g., host 1108) according to specific communication protocols.For example, the memory controller 1106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0237] The memory controller 1106 and one or more 3D memory devices 1104 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 1102 can be implemented and packaged into different types of end electronic products. In one example, such as... Figure 12A As shown, the memory controller 1106 and a single 3D storage device 1104 can be integrated into the memory card 1202. The memory card 1202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1202 may also include a memory card connector 1204, which connects the memory card 1202 to a host computer (e.g., ...). Figure 11 The host 1108 in the middle is electrically coupled. In such a case Figure 12B In another example shown, the memory controller 1106 and multiple 3D storage devices 1104 can be integrated into the SSD 1206. The SSD 1206 may also include an SSD connector 1208 that connects the SSD 1206 to a host computer (e.g., Figure 11 The host 1108 is electrically coupled. In some implementations, the storage capacity and / or operating speed of the SSD 1206 is greater than that of the memory card 1202.

[0238] The description of the specific implementation described above can be easily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0239] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: A stacked structure comprising alternating first layers and first dielectric layers, wherein the first layer in a first portion of the stacked structure comprises a second dielectric layer, and the first layer in a second portion adjacent to the first portion of the stacked structure comprises a conductive layer; and A contact structure that extends in a first direction into the first portion of the stacked structure and is respectively connected to corresponding conductive layers from the conductive layers. Specifically, based on the contact depth of the contact structure in the first direction, the contact structure is divided into one or more groups. Wherein, the one or more groups include a first group, the first group comprising at least a first subset of contact structures associated with a first subset of contact depths within a first depth range, and Wherein, the first subset of the contact structures in the first group includes a first set of contact shoulders located in the first stack pair, and the first stack pair includes the first of the first dielectric layer and the first of the second dielectric layer.

2. The storage device according to claim 1, wherein, The first subset of the contact structures in the first group includes a first contact structure, and the first contact structure includes: A vertical contact member and a lateral contact member connected to the vertical contact member, wherein the vertical contact member extends along the first direction and the lateral contact member is connected to one of the corresponding conductive layers.

3. The storage device according to claim 2, wherein, The vertical contact member includes: A first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment, wherein the first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

4. The storage device according to claim 3, wherein, In a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment also connected to the first contact shoulder.

5. The storage device according to claim 3, wherein, The vertical contact member of the first contact structure further includes: A second contact shoulder located within the first depth range, wherein the second contact shoulder is connected to the second vertical contact segment, and the depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

6. The storage device according to claim 5, wherein, The vertical contact member further includes: The third vertical contact segment, wherein the second contact shoulder is connected to the second vertical contact segment and the third vertical contact segment.

7. The storage device according to claim 3, wherein, The first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

8. The storage device according to claim 7, wherein: The first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder; and In the second direction, the size of the first end of the first vertical contact segment and the size of the second end of the first vertical contact segment are smaller than the size of the first vertical contact segment between the first end and the second end in the second direction.

9. The storage device according to claim 5, wherein, The first contact structure further includes: Spacers surrounding the vertical contact member; The filler surrounded by the vertical contact member; and A contact pad that covers the filler and is connected to the vertical contact member.

10. The storage device according to claim 9, wherein: The depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction; as well as The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

11. The storage device according to claim 9, wherein, The spacer includes: A first spacer segment, a spacer shoulder, and a second spacer segment, wherein the spacer shoulder is connected to the first spacer segment and the second spacer segment and is located in the first stack pair.

12. The storage device according to claim 11, wherein, The first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

13. The storage device according to claim 1, wherein, The one or more groups also include: The second group includes a second subset of the contact structures associated with a second subset of the contact depths within a second depth range, wherein the second depth range is different from the first depth range.

14. The storage device according to claim 13, wherein, The second subset of the contact structures in the second group includes: A second set of contact shoulders located in a second stacked pair, the second stacked pair including a second in the first dielectric layer and a second in the second dielectric layer, wherein the second stacked pair is different from the first stacked pair.

15. The storage device according to any one of claims 1-14, wherein, The second part of the stacked structure includes a first sub-part and a second sub-part separate from the first sub-part, and the first part of the stacked structure is located between the first sub-part and the second sub-part and connected to the first sub-part and the second sub-part.

16. The storage device according to any one of claims 1-14, wherein, The first part of the stacked structure includes a third sub-part and a fourth sub-part separate from the third sub-part, and the second part of the stacked structure is located between the third sub-part and the fourth sub-part and connected to the third sub-part and the fourth sub-part.

17. The storage device according to any one of claims 1-16, further comprising peripheral circuitry connected to the contact structure.

18. The storage device according to claim 17, wherein, The peripheral circuitry includes a device layer containing transistors, and the contact structure is connected to the device layer.

19. The storage device according to claim 13, wherein, The one or more groups also include: The third group includes a third subset of the contact structures associated with a third subset of the contact depths within a third depth range; and The fourth group comprises a fourth subset of the contact structures associated with a fourth subset of the contact depths within a fourth depth range, wherein: The first contact depth of the first contact structure in the first group is greater than the second contact depth of the second contact structure in the second group; The second contact depth of the second contact structure in the second group is greater than the third contact depth of the third contact structure in the third group; The third contact depth of the third contact structure in the third group is greater than the fourth contact depth of the fourth contact structure in the fourth group; and In a second direction perpendicular to the first direction, the first contact structure is arranged, followed by the second contact structure, the third contact structure, and the fourth contact structure.

20. A storage device comprising: A stacked structure comprising alternating first layers and first dielectric layers, wherein the first layer in a first portion of the stacked structure comprises a second dielectric layer, and the first layer in a second portion adjacent to the first portion of the stacked structure comprises a conductive layer; A first set of contact structures, extending in a first direction into the first portion of the stacked structure and respectively connected to a first subset of the conductive layer, wherein the first set of contact structures each has a first contact depth within a first depth range and includes a first set of contact shoulders located in the first stacked pair; and A second set of contact structures extends in the first direction into the first portion of the stacked structure and is connected to a second subset of the conductive layer, wherein the second set of contact structures has a second contact depth within a second depth range and includes a second set of contact shoulders located in a second stacked pair different from the first stacked pair.

21. The storage device according to claim 20, wherein: The first stack pair includes the first of the first dielectric layers and the first of the second dielectric layers; and The second stack pair includes the second of the first dielectric layer and the second of the second dielectric layer.

22. The storage device according to claim 20 or 21, wherein, The first group of contact structures includes a first contact structure, and the first contact structure includes: A vertical contact member and a lateral contact member connected to the vertical contact member, wherein the vertical contact member extends along the first direction and the lateral contact member is connected to one of the first subset of the conductive layer.

23. The storage device according to claim 22, wherein, The vertical contact member includes: A first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment, wherein the first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

24. The storage device according to claim 23, wherein, In a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment connected to the first contact shoulder.

25. The storage device according to claim 23, wherein, The vertical contact member of the first contact structure further includes: A second contact shoulder located within the first depth range, wherein the second contact shoulder is connected to the second vertical contact segment, and the depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

26. The storage device according to claim 25, wherein, The vertical contact member further includes: The third vertical contact segment, wherein the second contact shoulder is connected to the second vertical contact segment and the third vertical contact segment.

27. The storage device according to claim 23, wherein, The first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

28. The storage device according to claim 27, wherein: The first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder; and In the second direction, the size of the first end of the first vertical contact segment and the size of the second end of the first vertical contact segment are smaller than the size of the first vertical contact segment between the first end and the second end.

29. The storage device according to claim 25, wherein, The first contact structure further includes: Spacers surrounding the vertical contact member; The filler surrounded by the vertical contact member; and A contact pad that covers the filler and is connected to the vertical contact member.

30. The storage device according to claim 29, wherein: The depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction; as well as The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

31. The storage device according to claim 29, wherein, The spacer includes: A first spacer segment, a spacer shoulder, and a second spacer segment, wherein the spacer shoulder is connected to the first spacer segment and the second spacer segment and is located in the first stack pair.

32. The storage device according to claim 31, wherein, The first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

33. The storage device according to any one of claims 20-33, wherein, The second part of the stacked structure includes a first sub-part and a second sub-part separate from the first sub-part, and the first part of the stacked structure is located between the first sub-part and the second sub-part and connected to the first sub-part and the second sub-part.

34. The storage device according to any one of claims 20-33, wherein, The first part of the stacked structure includes a third sub-part and a fourth sub-part separate from the third sub-part, and the second part of the stacked structure is located between the third sub-part and the fourth sub-part and connected to the third sub-part and the fourth sub-part.

35. The storage device according to any one of claims 20-34, further comprising peripheral circuitry connected to the first group and the second group of the contact structures.

36. The storage device according to claim 35, wherein, The peripheral circuit includes a device layer containing transistors, and the first group and the second group of the contact structures are connected to the device layer.

37. The storage device of claim 20, further comprising: The third group of contact structures associated with the third contact depth within the third depth range; as well as The fourth group of contact structures associated with the fourth contact depth within the fourth depth range, wherein: The first contact depth of the first contact structure in the first group is greater than the second contact depth of the second contact structure in the second group; The second contact depth of the second contact structure in the second group is greater than the third contact depth of the third contact structure in the third group; The third contact depth of the third contact structure in the third group is greater than the fourth contact depth of the fourth contact structure in the fourth group; as well as In a second direction perpendicular to the first direction, the first contact structure is arranged, followed by the second contact structure, the third contact structure, and the fourth contact structure.

38. A method for forming a storage device, comprising: A stacked structure comprising alternating first and second dielectric layers is formed; as well as A contact structure is formed that extends into the stacked structure in the first direction. Specifically, based on the contact depth of the contact structure in the first direction, the contact structure is divided into one or more groups. Wherein, the one or more groups include a first group, the first group including at least a first subset of the contact structures associated with a first subset of contact depths within a first depth range, and The first subset of the contact structure includes a first set of contact shoulders located in the first stack pair, and the first stack pair includes the first of the first dielectric layer and the first of the second dielectric layer.

39. The method according to claim 38, wherein, Forming the contact structure includes: In the stacked structure, a first set of contact holes is formed for the first group; and The first subset of the contact structure is formed in the first set of the contact holes respectively.

40. The method according to claim 39, wherein, The first set of contact holes includes: A barrier layer is formed on the stacked structure; and The barrier layer and the stacked structure are etched using a first mask to form a first set of openings for the first group in the stacked structure, wherein the first set of openings has a first depth in the first direction and the bottom of the first set of openings is located in the first stacked pair.

41. The method according to claim 40, wherein, The first set of contact holes also includes: The stacked structure is etched at one or more first openings from the first set of openings using a second mask to form one or more second openings that further extend into the stacked structure.

42. The method according to claim 41, wherein: The first set of contact holes includes a first contact hole, the first contact hole including a first of the one or more first openings and a first of the one or more second openings; as well as A first sidewall shoulder is formed at the bottom of the first of the one or more first openings.

43. The method according to claim 42, wherein, The stacked structure includes a first portion and a second portion adjacent to the first portion, the contact structure extends into the first portion of the stacked structure, and the method further includes: A gate line replacement process is performed to replace a portion of the second dielectric layer in the second portion of the stacked structure with a conductive layer. The contact structure extends into the first portion of the stacked structure and is respectively connected to the corresponding conductive layers from the conductive layer.

44. The method of claim 43, wherein: The first subset of the contact structures in the first group includes a first contact structure, which includes a spacer, a vertical contact member, and a lateral contact member; as well as Forming a first subset of the contact structures in a first set of contact holes includes forming the first contact structures in the first contact holes by at least the following manner: The spacer is formed on the sidewall of the first contact hole; as well as The lateral contact member is formed below the bottom of the first contact hole, and the vertical contact member is formed on the sidewall of the spacer to connect to the lateral contact member. The lateral contact member is connected to one of the conductive layers.

45. The method according to claim 44, wherein, The vertical contact member includes: A first vertical contact segment, a first contact shoulder from a first set of contact shoulders, and a second vertical contact segment, wherein the first contact shoulder is connected to the first vertical contact segment and the second vertical contact segment.

46. ​​The method according to claim 45, wherein, In a second direction perpendicular to the first direction, the size of the end of the first vertical contact segment connected to the first contact shoulder is larger than the size of the end of the second vertical contact segment connected to the first contact shoulder.

47. The method according to claim 45, wherein, The first vertical contact segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

48. The method of claim 47, wherein: The first vertical contact segment has a first end connected to the first contact shoulder and a second end located away from the first contact shoulder; and The size of the first end of the first vertical contact segment in the second direction and the size of the second end of the first vertical contact segment in the second direction are smaller than the size of the first vertical contact segment between the first end and the second end in the second direction.

49. The method according to claim 45, wherein, The spacer includes: A first spacer segment, a spacer shoulder, and a second spacer segment, wherein the spacer shoulder is connected to the first spacer segment and the second spacer segment and is located in the first stack pair.

50. The method according to claim 49, wherein, The spacer shoulder is formed on the first sidewall shoulder, and the first contact shoulder is formed on the spacer shoulder.

51. The method according to claim 49 or 50, wherein, The first spacer segment has an arcuate shape in a cross-sectional view in a plane defined by the first direction and a second direction perpendicular to the first direction.

52. The method according to claim 42, wherein, The one or more groups also include: The second group includes a second subset of the contact structures associated with a second subset of the contact depths within a second depth range, wherein the second depth range is different from the first depth range.

53. The method according to claim 52, wherein, The formation of the contact structure further includes: In the stacked structure, a second set of contact holes is formed for the second group; and The second subset of the contact structure is formed in the second set of the contact holes respectively.

54. The method according to claim 53, wherein: The second subset of the contact structures in the second group includes a second set of contact shoulders located in a second stacked pair, the second stacked pair including a second in the first dielectric layer and a second in the second dielectric layer, wherein the second stacked pair is different from the first stacked pair; and The second set of contact holes includes: The barrier layer and the stacked structure are etched using a third mask to form a second set of openings in the stacked structure, wherein the second set of openings has a second depth in the first direction, and the bottom of the second set of openings is located in the second stack pair; and During the formation of the one or more second openings, the stacked structure is etched from one or more third openings in the second set of openings using the second mask to form one or more fourth openings that further extend into the stacked structure.

55. The method according to claim 54, wherein: The second set of contact holes includes a second contact hole, the second contact hole including the first of the one or more third openings and the first of the one or more fourth openings; as well as A second sidewall shoulder is formed at the bottom of the first of the one or more third openings.

56. The method according to claim 54 or 55, wherein: The first set of contact holes also includes: The stacked structure is etched at the second of the one or more second openings using a fourth mask to form a fifth opening that further extends into the stacked structure; and The second set forming the contact holes also includes: The fourth mask is used to etch the stacked structure at the second of the one or more fourth openings to form a sixth opening that extends further into the stacked structure. The first set of contact holes includes a third contact hole, which includes a second of the one or more first openings corresponding to the second of the one or more second openings, the second of the one or more second openings, and the fifth opening, and forms a third sidewall shoulder at the bottom of the second of the one or more second openings. The second set of contact holes includes a fourth contact hole, which includes a second of one or more third openings corresponding to the second of the one or more fourth openings, the second of the one or more fourth openings, and a sixth opening, and forms a fourth sidewall shoulder at the bottom of the second of the one or more fourth openings.

57. The method according to claim 56, wherein: A first subset of the contact structures in the first group includes a third contact structure formed in the third contact hole; The third contact structure includes a first set of contact shoulders and a first contact shoulder formed on the first sidewall shoulder; as well as The third contact structure further includes a second contact shoulder formed on the third sidewall shoulder, wherein the depth of the second contact shoulder in the first direction is greater than the depth of the first contact shoulder in the first direction.

58. The method according to claim 57, wherein: The third contact structure also includes a contact pad; The depth of the second contact shoulder in the first direction is the distance from the contact pad to the second contact shoulder in the first direction; as well as The depth of the first contact shoulder in the first direction is the distance from the contact pad to the first contact shoulder in the first direction.

59. The method according to claim 53, wherein, The second set forming the contact holes also includes: The barrier layer is etched using a fifth mask to form an assembly of mask openings; and During the formation of the one or more second openings, the stacked structure is etched at the mask openings in the set of mask openings using the second mask to form a seventh opening extending into the stacked structure. The second set of contact holes includes a fifth contact hole containing the seventh opening.

60. The method of claim 38, wherein, One of the contact structures is formed in a contact hole, the contact hole comprising a plurality of openings formed by etching the stacked structure using a plurality of etch counts, and the total number of contact shoulders formed in the one of the contact structures is equal to the total number of the plurality of etch counts minus 1.

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