Chemical mechanical polishing apparatus, polishing system and method of polishing wafer

Abstract

In an embodiment, a polishing system may include a polishing table. The polishing system can further comprise a polishing pad located on the polishing table; a polishing head configured to hold the wafer in contact with the polishing pad; a capacitance sensor configured to measure a capacitance of the dielectric film on the wafer during the polishing process; and a controller electrically connected to the capacitive sensor. The controller may be configured to adjust at least one polishing parameter based on the measured capacitance; and terminating the polishing process when the measured capacitance is within a predetermined range corresponding to the target thickness of the dielectric film. The embodiment of the invention further provides a method for polishing the wafer and a chemical mechanical polishing device.

Description

Technical Field

[0001] Embodiments of this disclosure relate to chemical mechanical polishing apparatus, polishing systems, and methods for polishing wafers. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this disclosure provide a polishing system including: a polishing table; a polishing pad located on the polishing table; a polishing head configured to maintain contact between a wafer and the polishing pad; a capacitance sensor configured to measure the capacitance of a dielectric film on the wafer during a polishing process; and a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film.

[0005] Other embodiments of this disclosure provide a method for polishing a wafer, the method comprising: placing the wafer on a polishing pad of a chemical mechanical polishing (CMP) apparatus; performing a removal process on the wafer using the CMP apparatus; during the removal process, detecting the capacitance of a dielectric film on the wafer using a capacitance sensor; adjusting at least one polishing parameter based on the detected capacitance; and terminating the removal process when the detected capacitance of the wafer is within a predetermined range corresponding to a target thickness of the dielectric film.

[0006] Another embodiment of this disclosure provides a chemical mechanical polishing (CMP) apparatus comprising: a capacitance sensor integrated into a polishing head, wherein the capacitance sensor is configured to measure the capacitance of a dielectric film on a wafer during the polishing process; and a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film. Attached Figure Description

[0007] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 Various aspects of a semiconductor wafer and chemical mechanical polishing (CMP) system according to some embodiments are shown.

[0009] Figure 6 , Figure 7 and Figure 8 A top view is shown of different configurations of platform-mounted sensors in a polishing system according to some embodiments.

[0010] Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 Various configurations of a polishing system with a head-mounted sensor according to some embodiments are shown.

[0011] Figure 14 A perspective view of an exemplary complementary field-effect transistor (CFET) according to some embodiments is shown.

[0012] Figures 15 to 20 This is a view of an intermediate stage in the manufacture of a CFET according to some embodiments.

[0013] Figure 21 An operational sequence diagram of a CMP system with capacitive sensing control, according to some embodiments, is shown.

[0014] Figure 22 This is a flowchart of a process according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various components of this application. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not, in itself, indicate a relationship between the individual embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Chemical mechanical polishing (CMP) is a process in semiconductor manufacturing used to planarize surfaces and remove excess material. As semiconductor devices continue to shrink and become more complex, precise control of the CMP process becomes increasingly important. One area where this precision is particularly critical is the polishing of dielectric thin films, especially in the fabrication of complementary field-effect transistors (CFETs).

[0018] The various embodiments provide improved monitoring systems and methods, which can be used for CMP or other polishing or planarization processes. Conventional CMP processes for dielectric thin films rely on optical measurements or endpoint detection based on changes in motor current or friction. However, these methods may lack the sensitivity and accuracy required for advanced semiconductor processes, especially when dealing with ultrathin films or complex structures.

[0019] This disclosure relates to systems and methods for in-situ capacitance measurement for thin film thickness control in CMP. CMP is a process in semiconductor manufacturing used to planarize surfaces and remove excess material. However, controlling the endpoint of the CMP process, especially for dielectric thin films, is quite challenging. Conventional methods often result in over-polishing or under-polishing, which can negatively impact device performance and yield.

[0020] This disclosure solves the technical problem of accurate thickness control during CMP by introducing in-situ capacitance measurement technology. Unlike traditional optical or eddy current methods, this method allows for real-time monitoring of film thickness (such as dielectric films), eliminating the need for windows in the polishing pad that could lead to defects or scratches. The capacitance measurement technology provides accurate feedback to the CMP control system, enabling precise endpoint detection and minimizing stop layer loss.

[0021] The systems and methods described in this paper offer several advantages over existing technologies. First, they provide non-destructive in-situ measurement capabilities that can be easily integrated into existing CMP equipment. Second, the capacitive sensors can be calibrated using known reference values, such as dielectric constant and pad properties, allowing for accurate thickness measurements of a wide range of materials. Third, the method is versatile and can be applied to a broad range of CMP processes, not just specific applications such as complementary field-effect transistor (CFET) fabrication.

[0022] By implementing this capacitance measurement technique, semiconductor manufacturers can achieve tighter control over dielectric film thickness, thereby meeting the increasingly stringent requirements of advanced node processes. For example, in situations where stop layer loss must be limited... In the following applications, this method enables precise control of the CMP process to meet such stringent specifications. Furthermore, the cost-effectiveness of this solution makes it a highly attractive option for improving CMP performance across various semiconductor manufacturing processes.

[0023] Figure 1 A semiconductor wafer 100 is shown, which will be polished using a chemical mechanical polishing (CMP) system. The wafer 100 includes a semiconductor substrate 102 and a layer 104 to be polished. In some cases, the semiconductor substrate 102 may include silicon, a III-V semiconductor material, or other suitable semiconductor material. The semiconductor substrate 102 can serve as the basis for various active devices and interconnect structures.

[0024] The layer to be polished 104 may be deposited on the semiconductor substrate 102 and may need to be planarized or removed by a CMP process. In some cases, the layer to be polished 104 may be a dielectric material, such as silicon oxide, silicon nitride, or a low-k dielectric material. In other cases, the layer to be polished 104 may be a conductive material, such as copper, aluminum, or tungsten. The composition of the layer to be polished 104 may depend on the specific manufacturing steps and the desired final structure. In some embodiments, the layer to be polished 104 comprises multiple layers with different compositions.

[0025] In some cases, the layer to be polished 104 may have a non-uniform thickness due to variations in the underlying structure or the process experienced during deposition. For example, the layer to be polished 104 may be formed by depositing one or more materials through an opening in the dielectric layer using a chemical vapor deposition (CVD) process. Due to variations in the CVD process and the shape of the underlying structure, the layer to be polished 104 may have a non-uniform thickness and an uneven surface.

[0026] The CMP process aims to planarize the layer 104 to be polished, thereby removing excess material and creating a smooth, uniform surface. This planarization can be critical for subsequent manufacturing steps, such as photolithography, etching, or the formation of additional layers. The in-situ capacitance measurement technique disclosed herein is particularly useful for controlling the thickness of the layer 104 to be polished during the CMP process, especially when the layer 104 to be polished is a dielectric material.

[0027] Figure 2 A perspective view of a polishing system 150 for CMP is shown. The polishing system 150 includes a polishing table 152 on which a polishing pad 154 is supported. The polishing table 152 can be configured to rotate the polishing pad 154 during the CMP process.

[0028] A polishing head 156 is positioned above a polishing pad 154 and holds a wafer 158 (sometimes referred to as workpiece 158) for the polishing operation. The polishing head 156 may include a carrier (not shown separately) configured to hold the wafer 158. In some cases, the carrier may be designed to securely hold the wafer 158 while allowing pressure to be applied during the polishing process. The polishing head 156 may include a retaining ring (not shown separately) mounted to the carrier. The retaining ring can help house the wafer 158 within the carrier and prevent it from slipping or moving during the polishing process. The polishing head 156 may be configured to apply downward pressure during the CMP process to keep the wafer 158 in contact with the polishing pad 154. In some cases, the polishing head 156 may be configured to rotate the wafer 158 on the polishing pad 154 during the CMP process.

[0029] The polishing system 150 may also include a pad conditioner (not shown separately) located on the polishing pad 154 to refresh the polishing pad 154. The pad conditioner may include a pad conditioner pad attached to a pad conditioner head. The pad conditioner head may be configured to rotate the pad conditioner pad on the surface of the polishing pad 154. The pad conditioner head may be configured to rotate the pad conditioner pad, and the polishing stage 152 may be configured to rotate the polishing pad 154 in the same or opposite directions. In some embodiments, the polishing stage 152 is configured to rotate the polishing pad 154 during the CMP process, and the pad conditioner pad does not rotate. A pad conditioner arm is attached to the pad conditioner head and configured to move the pad conditioner head and the pad conditioner pad across the polishing pad 154 in a sweeping motion. In some embodiments, the pad conditioner pad includes a substrate over which an array of abrasive particles are bonded using, for example, electroplating. The pad conditioner pad may remove accumulated wafer debris and excess polishing fluid from the polishing pad 154 during the CMP process. In some embodiments, the pad trimming pad acts as an abrasive for the polishing pad 154 to create a desired texture (such as, for example, grooves), which can be used to polish the wafer 158 in close proximity to the texture.

[0030] A platform-mounted sensor 160 is integrated into the polishing stage 152 beneath the polishing pad 154. This placement allows for non-invasive monitoring of the wafer 158 during the polishing process. The sensor 160 utilizes capacitance technology to measure the capacitance of the wafer 158 as it undergoes polishing. This capacitance measurement is based on the principle that the dielectric properties of the wafer's surface layer change as material is removed during the CMP process.

[0031] As the polishing stage 152 rotates, the platform-mounted sensor 160 periodically passes beneath the wafer 158, creating a dynamic interaction between the sensor and the wafer surface. This rotational motion allows the sensor to measure across different areas of the wafer, providing a comprehensive profile of the polishing process. Capacitance measurements are made possible by the sensor's ability to detect changes in the electric field between itself and the wafer, which are influenced by the thickness and composition of the remaining thin film on the wafer surface.

[0032] The platform-mounted sensor 160 offers several advantages. It allows for continuous, real-time monitoring of the polishing process without interfering with the physical contact between the wafer 158 and the polishing pad 154. Furthermore, the sensor's location beneath the polishing pad 154 protects it from the harsh chemical and mechanical environments of the CMP process, ensuring reliable and consistent measurements throughout operation. Moreover, this configuration enables the system to collect data across the entire wafer surface as the wafer rotates, providing an accurate representation of overall polishing uniformity.

[0033] The capacitance measurements obtained by the platform-mounted sensor 160 can be used to precisely control the endpoint of the CMP process, thereby ensuring the desired film thickness is achieved across wafer 158. This level of control is particularly important in advanced semiconductor manufacturing processes, where even angstrom-level variations in film thickness can significantly impact device performance and yield.

[0034] The polishing system 150 includes a control mechanism comprising a controller 162 electrically connected to a platform-mounted sensor 160. The controller 162 continuously monitors and processes real-time capacitance data collected by the platform-mounted sensor 160 during the CMP process. In some embodiments, the controller 162 is programmed with advanced algorithms to interpret capacitance measurements that are directly related to the thickness of the dielectric film being polished on the wafer 158.

[0035] In some embodiments, the controller 162 automatically terminates the polishing process when certain conditions are met. Specifically, the controller 162 may be configured to stop the CMP operation when the measured capacitance falls within a predetermined range. In some embodiments, this range may be calibrated to correspond to the final desired thickness of the dielectric film, taking into account factors such as the dielectric constant of the material, the initial film thickness, and the target thickness of the specific semiconductor device being manufactured.

[0036] Implementing this feedback loop between the platform-mounted sensor 160 and the controller 162 enables the system and method to achieve a higher level of accuracy in the polishing process. By continuously monitoring the capacitance in real time, the system can instantly determine the progress of polishing, thereby ensuring that the process stops at the appropriate time to achieve the desired film thickness.

[0037] This precise control is important in advanced semiconductor manufacturing processes, such as those used in the manufacture of complementary field-effect transistors (CFETs) (see, for example, the manufacturing process used in CFET manufacturing). Figures 14 to 20 In this manufacturing process, even variations in dielectric film thickness at the angstrom level can significantly impact device performance. The ability to terminate the polishing process based on real-time capacitance measurements helps minimize over-polishing or under-polishing, which can improve the uniformity and consistency of the final product across the entire wafer surface.

[0038] Furthermore, the controller 162 can be programmed with additional functions to further enhance the CMP process. For example, it can adjust polishing parameters, such as pressure, rotational speed, or polishing fluid flow rate, based on capacitance measurements, allowing for dynamic optimization of the polishing process as it progresses. This adaptive control can help compensate for variations in initial film thickness or polishing rate across different regions of the wafer, ultimately leading to improved planarization and more consistent results.

[0039] The combination of platform-mounted sensor 160 and controller 162 in polishing system 150 ensures precise control and endpoint detection of the CMP process. This can be advantageous for polishing dielectric materials or other layers where conventional endpoint detection methods may be less effective. The capacitance measurements provided by platform-mounted sensor 160 offer a non-destructive, in-situ method for monitoring the thickness and uniformity of polished layers on wafer 158.

[0040] Figure 3 A perspective view of a polishing system 170 for CMP according to some embodiments is shown. In this embodiment, system 170 includes a head-mounted sensor 172 integrated into a polishing head 156.

[0041] The head-mounted sensor 172 can be a capacitance sensor configured to measure the capacitance of the wafer 158 during the polishing process. This configuration offers advantages over platform-mounted sensor setups. Throughout the polishing process, as the sensor moves with the wafer 158, the head-mounted sensor 172 provides more consistent and continuous measurements. Furthermore, the proximity of the sensor to the wafer 158 allows for more accurate and sensitive capacitance measurements.

[0042] The head-mounted sensor 172 can be directly integrated into the polishing head 156. This integration allows for precise positioning of the sensor relative to the wafer 158, potentially improving the accuracy and reliability of capacitance measurements. In some cases, the head-mounted sensor 172 can be positioned within a carrier or retaining ring to optimize its proximity to the wafer 158.

[0043] The controller 162 can be electrically connected to the head-mounted sensor 172. The function of the controller 162 can be similar to that described above. Figure 2 The functions described herein will not be repeated here. Controller 162 can be configured to receive and process capacitance measurements from head-mounted sensor 172. Based on these measurements, controller 162 can adjust various polishing parameters or determine when to terminate the polishing process.

[0044] Figure 4 A polishing system 180 for CMP is shown. Polishing system 180 is similar to polishing system 150 described above, but includes sensors adjacent to polishing stage 152 for monitoring functions during the CMP process.

[0045] The polishing system 180 includes a first sensor 182 and a second sensor 184 configured to measure capacitance during the polishing process. The first sensor 182 and the second sensor 184 are not mounted to the polishing stage 152 or the polishing head 156, but are adjacent to the polishing stage 152. In this embodiment, the wafer 158 can be removed from the polishing stage 152 for capacitance measurement. In some embodiments, the wafer 158 can be removed to periodically measure capacitance to ensure that the polishing process stops when the wafer 158 and / or the polished film reaches a desired thickness. The controller 162 may function similarly to the above. Figure 2 The functionality described herein will not be repeated here. This arrangement allows capacitance to be detected at multiple locations across the 158-sided surface of the wafer.

[0046] Figure 5 It shows Figure 2 Side view of the polishing system 150. Figure 5The polishing system 150 also shows a polishing slurry distributor 164. The polishing slurry distributor 164 can be provided on the polishing pad 154 to deposit polishing slurry 166 onto the polishing pad 154. The polishing stage 152 can be configured to rotate the polishing pad 154, which allows the polishing slurry 166 to be distributed between the wafer 158 and the polishing pad 154.

[0047] Polishing slurry 166 plays a crucial role in the CMP process. In some cases, the composition of polishing slurry 166 may depend on the type of material present in the layer 104 to be polished that needs to be polished or removed. Polishing slurry 166 may include reactants, abrasives, surfactants, and solvents.

[0048] The reactants in the polishing slurry 166 can be chemical substances, such as oxidants or reducing agents, which can chemically react with the material of the wafer 158 to assist the polishing pad 154 in grinding or removing the material. The abrasives in the polishing slurry 166 can include any suitable microparticles, and the combination of the microparticles with the polishing pad 154 can be configured to polish or planarize the wafer 158.

[0049] In some cases, the polishing slurry 166 may include a surfactant. The surfactant can be used to help disperse the reactants and abrasive within the polishing slurry 166 and to prevent or otherwise reduce abrasive agglomeration during the CMP process. The remainder of the polishing slurry 166 may include a solvent. The solvent can be used to bind the reactants, abrasive, and surfactant, and the solvent allows the mixture to move and disperse onto the polishing pad 154.

[0050] Before performing a removal process on wafer 158, polishing slurry distributor 164 can be configured to deposit polishing slurry 166 onto polishing pad 154. This ensures that the polishing slurry 166 is properly distributed between wafer 158 and polishing pad 154 before the polishing process begins. The rotation of polishing stage 152 and polishing pad 154 can further assist in uniformly distributing the polishing slurry 166 across the surface of wafer 158 during the polishing process.

[0051] Integrating the polishing slurry distributor 164 into the polishing system 150 allows for precise control over the amount and duration of polishing slurry deposition 166. In some cases, the controller 162 can be configured to control the operation of the polishing slurry distributor 164, coordinating the deposition of polishing slurry with other aspects of the polishing process, such as the rotation of the polishing stage 152 and the movement of the polishing head 156.

[0052] The polishing system 150 may include capacitance measurement technology to monitor the thickness of the film to be polished (also referred to as the target film) during the CMP process. In some embodiments, two electrodes may be positioned on either side of the film to measure its capacitance. For example, as... Figure 5As shown, one electrode can be mounted on the polishing head 156, and the other electrode can be mounted on the platform-mounted sensor 160.

[0053] Capacitance measurements can be performed using techniques that involve applying direct current or alternating current and a test voltage. The test voltage can vary depending on the specific method used, and in some cases, it can range from approximately 1 mV to 10 V. Because CMP processes typically only reduce the thickness of the polished film, the system can separate the film's capacitance from the total system capacitance.

[0054] By measuring the change in capacitance over time, the system can determine the amount of reduction in film thickness. This measurement technique can be applied at the start of the CMP process, enabling continuous monitoring of the target film thickness throughout the polishing operation. Controller 162 can use this real-time thickness data to ensure effective process control, thereby adjusting polishing parameters as needed.

[0055] In some embodiments, capacitance measurements may be performed periodically during the polishing process. The frequency of these measurements may be adjusted based on factors such as the initial film thickness, the desired final thickness, and the overall polishing rate.

[0056] It should be noted that although this instruction manual focuses on Figure 5 The embodiments shown herein are examples of similar capacitance measurement techniques that can be applied to other embodiments disclosed herein. Specific implementations may vary depending on the sensor configuration (e.g., platform-mounted sensor, head-mounted sensor, or adjacent sensor), but the fundamental principle of using capacitance changes to monitor film thickness remains consistent across different embodiments.

[0057] Figure 6 A top view of the polishing system 150 configuration is shown. In this configuration, the platform-mounted sensor 160 is rectangular in shape in the top view and extends radially across a portion of the polishing table 152. The platform-mounted sensor 160 can be positioned to intersect the path of the polishing head 156 during operation.

[0058] Compared to other sensor shapes, the rectangular shape of the platform-mounted sensor 160 allows for a larger sensing area. In some cases, this increased sensing area can provide more comprehensive capacitance measurements of the wafer 158 during the polishing process.

[0059] The platform-mounted sensor 160, arranged radially across the polishing stage 152, allows the sensor to take measurements at various points along the radius of the wafer 158 as the polishing stage 152 rotates. This configuration allows for the detection of capacitance changes across different areas of the wafer 158, potentially providing insight into the uniformity of the polishing process.

[0060] Positioning the platform-mounted sensor 160 to intersect the path of the polishing head 156 ensures that the sensor passes under the wafer 158 during each rotation of the polishing stage 152. In some cases, this arrangement allows for continuous monitoring of the wafer 158 throughout the CMP process.

[0061] A rectangular platform-mounted sensor 160 can be integrated into a polishing stage 152 beneath the polishing pad 154. This integration allows for capacitance measurements through the polishing pad 154 without interfering with the physical contact between the polishing pad 154 and the wafer 158.

[0062] Figure 7 A top view of the polishing system 150 configuration is shown. In this configuration, multiple platform-mounted sensors 160 are arranged in a linear configuration across the polishing stage 152. The platform-mounted sensors 160 are square in shape in the top view and are positioned along the horizontal axis of the polishing stage 152.

[0063] The platform-mounted sensor 160 can be arranged to monitor different positions across the polishing stage 152 during operation. Compared to sensors of other shapes, the square shape of the platform-mounted sensor 160 provides a larger sensing area. In some cases, this increased sensing area can improve the accuracy and sensitivity of capacitance measurements. The square shape also allows for more efficient use of space on the polishing stage 152, potentially enabling the integration of a larger number of sensors.

[0064] The sensor 160, positioned along the horizontal axis of the polishing stage 152, allows for measurements to be taken across the entire diameter of the wafer 158 during each rotation of the polishing stage 152. In some cases, this can provide a more comprehensive view of the polishing progress across the surface of the wafer 158.

[0065] The linear arrangement of the platform-mounted sensors 160 also facilitates the detection of variations in the thickness of the layer to be polished across different regions of the wafer 158. By comparing the measurements from the different sensors as the wafer 158 passes through them, the controller 162 can identify and compensate for non-uniformities in the polishing process.

[0066] In some cases, multiple platform-mounted sensors 160 can be used in conjunction with controller 162 to implement zone-based polishing control. Controller 162 can use capacitance measurements from different sensors to adjust polishing parameters, such as pressure or rotation speed, for specific zones of wafer 158. This can help achieve more uniform material removal across the entire surface of wafer 158.

[0067] The multiple sensor configuration of the platform-mounted sensor 160 can also provide redundancy for the measurement system. In some cases, if one sensor fails or provides unreliable data, the remaining sensors can continue to provide sufficient information to the controller 162 to maintain effective control of the CMP process.

[0068] Figure 8 A top view of the polishing system 150 configuration is shown. In this configuration, multiple platform-mounted sensors 160 are arranged in a linear configuration across the polishing stage 152. The platform-mounted sensors 160 are circular in shape in the top view and are positioned along a horizontal axis that intersects the polishing stage 152 and the polishing head 156.

[0069] The circular shape of the platform-mounted sensor 160 offers several advantages for capacitance measurements during the polishing process. In some cases, the circular shape allows for a more uniform sensing area as the polishing stage 152 rotates, potentially resulting in more consistent measurements across the wafer surface.

[0070] The linear arrangement of the platform-mounted sensors 160 enables monitoring across different locations on the polishing stage 152 during operation. This configuration allows for capacitance measurements at various points along the wafer radius as the polishing stage 152 rotates. In some cases, this arrangement can provide a more comprehensive profile of the layer to be polished across the wafer surface.

[0071] In some embodiments, the platform-mounted sensors 160 are spaced apart at a fixed interval along a horizontal axis. This spacing can be optimized to provide adequate coverage of the wafer surface during the polishing process. In some cases, the spacing between the platform-mounted sensors 160 can be adjusted based on factors such as wafer size, required measurement resolution, or specific requirements of the polishing process.

[0072] The configuration of multiple circular platform-mounted sensors 160 can enhance capacitance measurements during the polishing process in several ways. First, using multiple sensors allows for simultaneous measurements at different locations across the wafer surface, potentially improving the accuracy and reliability of thickness monitoring. Second, the circular shape of the sensors provides consistent measurements regardless of the rotational position of the polishing stage 152.

[0073] In some cases, the controller can be configured to process data from multiple platform-mounted sensors 160 to create a more comprehensive polishing progress map. This could involve comparing measurements from different sensors, calculating average readings, or using advanced algorithms to interpret capacitance data and make real-time adjustments to the polishing process.

[0074] Figure 9A side view of a polishing system 170 with a head-mounted sensor 172 and a polishing slurry dispenser 164 is shown. The polishing system 170 includes a polishing stage 152 that supports a polishing pad 154. A polishing head 156 is positioned above the polishing pad 154 and holds a wafer 158 for polishing operations.

[0075] Figure 10 A top view of the polishing system 170 configuration is shown. In this configuration, a head-mounted sensor 172 is rectangular in shape in the top view and is integrated into the polishing head 156. The head-mounted sensor 172 extends across a portion of the polishing head 156 and can be positioned to measure capacitance during the polishing process.

[0076] The rectangular shape of the head-mounted sensor 172 offers several advantages for capacitance measurements during the polishing process. In some cases, the rectangular shape can allow for a larger sensing area compared to sensors of other shapes, potentially resulting in more comprehensive measurements across the surface of wafer 158.

[0077] The rectangular head-mounted sensor 172 configuration provides flexibility in sensor design and placement within the polishing head 156. In some cases, the size and position of the head-mounted sensor 172 can be optimized based on factors such as the size of the wafer 158, the required measurement resolution, or the specific requirements of the polishing process.

[0078] Figure 11 A top view of the polishing system 170 configuration is shown. In this configuration, the head-mounted sensor 172 is X-shaped in the top view. The head-mounted sensor 172 can be integrated into the polishing head 156 and can be configured to measure capacitance during polishing operations.

[0079] The X-shaped design of the head-mounted sensor 172 offers several advantages for capacitance measurements during the polishing process. In some cases, the X-shape allows for a larger sensing area compared to sensors of other shapes, potentially improving the accuracy and sensitivity of capacitance measurements. The X-shape also enables simultaneous measurements at multiple points across the surface of wafer 158. In some cases, the X-shaped sensor can rotate with the polishing head 156, providing capacitance measurements at various orientations relative to wafer 158.

[0080] In some cases, controller 162 can be configured to process capacitance measurements from X-head mounted sensor 172. Controller 162 can use these measurements to monitor the progress of the polishing process and adjust polishing parameters as needed. The X-shape of the sensor can provide data from multiple directions, potentially allowing for more comprehensive monitoring of the polishing process.

[0081] The X-shape of the head-mounted sensor 172 demonstrates the flexibility of sensor design that can be employed in the polishing system 170. Although this configuration is shown as an X-shaped sensor, other shapes can also be used, depending on the specific requirements of the polishing process and the desired measurement characteristics.

[0082] Figure 12 A top view of a polishing system 170 configuration is shown. In this configuration, a head-mounted sensor 172 is integrated into the polishing head 156, and in the top view, the head-mounted sensor 172 has a spoke-like shape extending radially from the center of the polishing head 156. The spoke-like shape of the head-mounted sensor 172 can provide several advantages for capacitance measurements during the polishing process. In some cases, the radial arrangement of the sensor can allow measurements to be taken at multiple points across the radius of the wafer 158, potentially providing a more comprehensive profile of the layer to be polished.

[0083] The radial arrangement of the head-mounted sensor 172 allows for the detection of capacitance changes across different areas of wafer 158. In some cases, this configuration can provide insight into the uniformity of the polishing process from the center to the edge of wafer 158.

[0084] The spoke-like shape of the head-mounted sensor 172 also provides flexibility in sensor design. In some cases, the number and length of the spokes can be optimized based on factors such as the size of the wafer 158, the required measurement resolution, or the specific requirements of the polishing process.

[0085] In some cases, controller 162 can be configured to independently process capacitance measurements from different spokes of head-mounted sensor 172. Controller 162 can use these measurements to monitor the polishing process progress across different areas of wafer 158 and adjust polishing parameters as needed.

[0086] Figure 13 A top view of the polishing system 170 configuration is shown. In this configuration, the head-mounted sensor 172 has a circular shape in the top view and is integrated within the polishing head 156. The arrangement shows the relative positions of these components from a top view perspective, with the dashed line indicating the central axis of the circular platform.

[0087] The circular shape of the head-mounted sensor 172 offers several advantages for capacitance measurements during the polishing process. In some cases, the circular shape allows for uniform sensing across the wafer surface as the polishing head 156 rotates. This uniformity facilitates more consistent and accurate measurements of the layer being polished.

[0088] In some cases, the controller can be configured to process capacitance measurements from the circular head-mounted sensor 172 as the polishing head 156 moves across the polishing table 152. The controller can use these measurements to monitor the progress of the polishing process and adjust the polishing parameters as needed.

[0089] The circular head-mounted sensor 172 configuration provides flexibility in sensor design and placement within the polishing head 156. In some cases, the size and position of the head-mounted sensor 172 can be optimized based on factors such as wafer size, required measurement resolution, or specific requirements of the polishing process.

[0090] exist Figures 2 to 13 In the illustrated embodiment, the CMP system includes a single polishing head (e.g., polishing head 156) and a single polishing pad (e.g., polishing pad 154). In some embodiments, the CMP system of this disclosure may include multiple polishing heads and / or multiple polishing pads. In embodiments where the CMP system includes multiple polishing heads and a single polishing pad, multiple workpieces (e.g., wafers 100 or 158) can be polished simultaneously. In embodiments where the CMP system includes a single polishing head and multiple polishing pads, the CMP process may be a multi-step process, with each polishing pad having a different abrasiveness. In such embodiments, a first polishing pad may be used to remove bulk material from the workpiece, a second polishing pad may be used for overall planarization of the workpiece, and a third polishing pad may be used for buffing the surface of the workpiece.

[0091] The disclosed embodiments present a CMP method for solving the challenge of precisely controlling dielectric film thickness. This system monitors the dielectric film thickness during the CMP process using in-situ capacitance measurements, enabling more accurate endpoint detection and better control of the final film thickness. This method is particularly advantageous for advanced semiconductor manufacturing processes, such as those where precise control of the dielectric layer is crucial.

[0092] The disclosed CMP system includes a capacitance sensor that can be integrated into either the polishing stage or the polishing head. This sensor measures the capacitance of the wafer during the polishing process, providing real-time feedback on the thickness of the dielectric film being polished. The controller processes this capacitance data and uses it to adjust polishing parameters or determine when to terminate the polishing process.

[0093] In some embodiments, a method of operating the disclosed system includes: placing a wafer on a polishing pad of a CMP apparatus; performing a removal process on the wafer using the CMP apparatus; detecting the capacitance of the wafer during the removal process using a capacitance sensor; adjusting polishing parameters based on the detected capacitance. These parameters may include polishing pressure, polishing speed, or polishing slurry composition; and terminating the removal process when the detected wafer capacitance is within a predetermined range, indicating that a desired film thickness has been achieved.

[0094] Capacitive sensors can be designed to simultaneously measure plateau capacitance and film capacitance, subtracting the plateau capacitance to obtain the dielectric film capacitance. In some cases, the sensor can be hybrid or portable to achieve optimal capacitance measurement.

[0095] This CMP method offers several advantages over traditional methods. It provides non-contact, non-destructive measurements that can be performed continuously during polishing. The system is particularly suitable for dielectric materials and can be easily integrated into existing CMP equipment. By enabling more precise control of the polishing process, this method can help reduce device performance variations and increase overall semiconductor manufacturing yield.

[0096] Figures 14 to 20 A description of forming complementary field-effect transistor (CFET) structures is provided. Because the disclosed CMP system and method have very strict specifications for the planarization process in its fabrication, the disclosed CMP system and method can be used to form CFET structures. However, the disclosed CMP system and method are not limited to CFETs, but can be used for other types of devices, such as FinFETs, nanoFETs, etc.

[0097] Figure 14 Examples of CFET 210 (including FET (transistor) 210U and 210L) according to some embodiments are shown. Figure 14 This is a 3D view, in which some components of the CFET are omitted for clarity.

[0098] A CFET comprises multiple vertically stacked FETs. For example, a CFET may include a lower nanostructure FET 210L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 210U of a second device type (e.g., p-type / n-type). The nanostructure FETs 210U and 210L include a semiconductor nanostructure 226 (including a lower semiconductor nanostructure 226L and an upper semiconductor nanostructure 226U), wherein the semiconductor nanostructure 226 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 226L is used for the lower nanostructure FET 210L, and the upper semiconductor nanostructure 226U is used for the upper nanostructure FET 210U. In other embodiments, a CFET may also be applied to other types of transistors (e.g., FinFETs, etc.).

[0099] A gate dielectric 278 surrounds a corresponding semiconductor nanostructure 226. A gate electrode 280 (including a lower gate electrode 280L and an upper gate electrode 280U) is located above the gate dielectric 278. Source / drain regions 262 (including a lower source / drain region 262L and an upper source / drain region 262U) are disposed on opposite sides of the gate dielectric 278 and the corresponding gate electrode 280. Depending on the context, the source / drain regions may refer individually or collectively to either the source or the drain. Isolation components (not shown) may be formed to separate the desired source / drain regions of the source / drain regions 262 from the desired gate electrodes of the gate electrodes 280.

[0100] Figure 14 A reference cross section used in subsequent figures is further illustrated. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 226 of the CFET and in the direction of current flow, for example, between the source / drain regions 262 of the CFET. This reference cross section can be referenced in subsequent figures for clarity.

[0101] Figures 15 to 20 A cross-sectional view of an intermediate stage in the formation of a CFET according to some embodiments is shown (e.g.) Figure 14 (As shown). Figures 16 to 20 It shows the path along with Figure 14 A vertical cross-sectional view of a section similar to the vertical reference section A-A'.

[0102] exist Figure 15The invention provides a wafer including a substrate 220. The substrate 220 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, etc. An insulating layer is provided on the substrate, such as a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 220 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0103] Semiconductor strips 228 are formed extending upward from semiconductor substrate 220. Each semiconductor strip 228 includes semiconductor strip 220' (a patterned portion of semiconductor substrate 220) and multilayer stack 22. Hereinafter, the stacked components of multilayer stack 22 are referred to as nanostructures. Specifically, multilayer stack 22 includes pseudo-nanostructures 224A and 224B, a lower semiconductor nanostructure 226L, and an upper semiconductor nanostructure 226U. Pseudo-nanostructures 224A and 224B can be further collectively referred to as pseudo-nanostructure 224, and the lower semiconductor nanostructure 226L and upper semiconductor nanostructure 226U can be further collectively referred to as semiconductor nanostructure 226.

[0104] The pseudo-nanostructure 224A is formed of a first semiconductor material, and the pseudo-nanostructure 224B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 220. The first and second semiconductor materials have high etch selectivity relative to each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 224B can be removed at a faster rate than the pseudo-semiconductor layer 224A.

[0105] Semiconductor nanostructures 226 (including lower semiconductor nanostructures 226L and upper semiconductor nanostructures 226U) are formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 220. The lower semiconductor nanostructure 226L and upper semiconductor nanostructure 226U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 224 have high etch selectivity relative to the third semiconductor material of the semiconductor nanostructure 226. Therefore, in subsequent processes, the pseudo-nanostructure 224 can be selectively removed without significantly removing the semiconductor nanostructure 226. In some embodiments, the pseudo-semiconductor nanostructure 224A is formed of or includes silicon-germanium, the semiconductor layer 226 is formed of silicon, and the pseudo-semiconductor nanostructure 224B can be formed of germanium or silicon-germanium (with a higher atomic percentage of germanium than semiconductor nanostructure 224A).

[0106] The lower semiconductor nanostructure 226L will provide the channel region for the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 226U will provide the channel region for the upper nanostructure FET of the CFET. The semiconductor nanostructure 226 immediately above / below (e.g., in contact with) the pseudo-nanostructure 224B can be used for isolation and can serve as or not serve as the channel region of the CFET. The pseudo-nanostructure 224B will subsequently be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0107] To form the semiconductor strip 228, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (as described and shown above) can be deposited over the semiconductor substrate 220. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 220 to define the semiconductor strip 228, which includes semiconductor fins 220', pseudo-nanostructures 224, and semiconductor nanostructures 226. The semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, as well as the semiconductor substrate 220. Etching can be performed using any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0108] For example Figure 15 As shown, an STI region 232 is formed over a substrate 220 and between adjacent semiconductor strips 228. The STI region 232 may include a dielectric pad and a dielectric material located above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide (such as silicon oxide), a nitride (such as silicon nitride), or a combination thereof. Forming the STI region 232 may include depositing a dielectric layer and performing a planarization process (such as a CMP process, a mechanical polishing process, etc.) to remove excess dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, the STI region 232 comprises silicon oxide formed by an FCVD process followed by an annealing process. The dielectric layer is then recessed to define the STI region 232. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 228 (including the multilayer stack 22) protrudes above the remaining STI region 232.

[0109] After forming the STI region 232, a dummy gate stack 242 can be formed above and along the sidewalls of the upper portion of the semiconductor strip 228 (the portion protruding above the STI region 232). Forming the dummy gate stack 242 may include forming a dummy dielectric layer 236 on the semiconductor strip 228. The dummy dielectric layer 236 may be formed of, for example, silicon oxide, silicon nitride, combinations thereof, or may include, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 238 is formed above the dummy dielectric layer 236. The dummy gate layer 238 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The dummy gate layer 238 can be made of conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), etc. A mask layer 240 is formed over the planarized dummy gate layer 238 and can include, for example, silicon nitride, silicon oxynitride, etc. Next, the mask layer 240 can be patterned using photolithography and etching processes to form a mask, and then the dummy gate layer 238, and possibly a dummy dielectric layer 236, can be etched and patterned using this mask. The remaining portions of the mask layer 240, dummy gate layer 238, and dummy dielectric layer 236 form a dummy gate stack 242.

[0110] exist Figure 16 In this process, gate spacers 244 and source / drain grooves 246 are formed. Figure 16 It is along Figure 14 The image shows a cross-sectional view taken from line AA. First, a gate spacer 244 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 242. The gate spacer 244 can be formed by conformally forming one or more dielectric layers, followed by anisotropic etching of the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., and can be formed by deposition processes such as CVD, ALD, etc.

[0111] Subsequently, source / drain recesses 246 are formed in semiconductor strip 228. Source / drain recesses 246 are formed by etching, and they can extend through the multilayer stack 22 and into semiconductor strip 220'. The bottom surface of the source / drain recesses 246 can be horizontal above, below, or flush with the top surface of the isolation region 232. During the etching process, gate spacers 244 and dummy gate stacks 242 mask portions of semiconductor strip 228. Etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recesses 246 when they reach a desired depth.

[0112] exist Figure 17 In this process, internal spacers 254 and dielectric isolation layers 256 are formed. Forming the internal spacers 254 and dielectric isolation layers 256 may include an etching process that laterally etches the pseudo-nanostructure 224A and removes the pseudo-nanostructure 224B. The etching process may be isotropic and selective for the material of the pseudo-nanostructure 224, thereby allowing the pseudo-nanostructure 224 to be etched at a faster rate than the semiconductor nanostructure 226. The etching process may also be selective for the material of the pseudo-nanostructure 224B, thereby allowing the pseudo-nanostructure 224B to be etched at a faster rate than the pseudo-nanostructure 224A. In this way, the pseudo-nanostructure 224B can be completely removed between the lower semiconductor nanostructure 226L (collectively referred to as) and the upper semiconductor nanostructure 226U (collectively referred to as), without completely removing the pseudo-nanostructure 224A. In embodiments where pseudo-nanostructure 224B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, pseudo-nanostructure 224A is formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 226 is formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. This is because the pseudo-gate stack 242 surrounds the sidewalls of semiconductor nanostructure 226 (see...). Figure 15 The dummy gate stack 242 can support the upper semiconductor nanostructure 226U, so that the upper semiconductor nanostructure 226U will not collapse when the dummy nanostructure 224B is removed. Furthermore, although the sidewalls of the dummy nanostructure 224A are shown as straight after etching, these sidewalls can be recessed or raised.

[0113] An internal spacer 254 is formed on the sidewall of the recessed pseudo-nanostructure 224A, and a dielectric isolation layer 256 is formed between the upper semiconductor nanostructure 226U (collectively referred to as the upper semiconductor nanostructure 226L (collectively referred to as the lower semiconductor nanostructure 226L). As described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 246, and the pseudo-nanostructure 224A will be replaced by the corresponding gate structure. The internal spacer 254 acts as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 254 can be used to prevent subsequent etching processes (such as etching processes for forming the gate structure) from damaging the subsequently formed source / drain regions. On the other hand, the dielectric isolation layer 256 is used to isolate the upper semiconductor nanostructure 226U (collectively referred to as the upper semiconductor nanostructure 226U) from the lower semiconductor nanostructure 226L (collectively referred to as the lower semiconductor nanostructure 226L). Furthermore, the intermediate semiconductor nanostructure (the semiconductor nanostructure 226 in contact with the dielectric isolation layer 256) and the dielectric isolation layer 256 can define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0114] The internal spacer 254 and dielectric isolation layer 256 can be formed by conformally depositing an insulating material in the source / drain trench 246, on the sidewalls of the pseudo-nanostructure 224A, and between the upper semiconductor nanostructure 226U and the lower semiconductor nanostructure 226L, and then etching the insulating material. The insulating material can be a non-low-k dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonate, silicon oxycarbonate, silicon oxynitride, etc. The insulating material can be formed by deposition processes such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. When etching the insulating material, the insulating material has a portion retained in the sidewalls of the pseudo-nanostructure 224A (thus forming the internal spacer 254) and a portion retained between the upper semiconductor nanostructure 226U and the lower semiconductor nanostructure 226L (thus forming the dielectric isolation layer 256).

[0115] like Figure 17 As shown, a lower epitaxial source / drain region 262L and an upper epitaxial source / drain region 262U are formed. The lower epitaxial source / drain region 262L is formed in the lower portion of the source / drain recess 246. The lower epitaxial source / drain region 262L is in contact with the lower semiconductor nanostructure 226L, but not with the upper semiconductor nanostructure 226U. An internal spacer 254 electrically insulates the lower epitaxial source / drain region 262L from the pseudo-nanostructure 224A, which will be replaced by a replacement gate in a subsequent process.

[0116] The lower epitaxial source / drain region 262L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 262L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon, which is doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 262L is a p-type source / drain region, the corresponding material can include silicon or silicon-germanium, which is doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 262L can be in-situ doped and can be implanted with or without corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 262L, the upper semiconductor nanostructure 226U can be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 226U. After growing the lower epitaxial source / drain region 262L, the mask on the upper semiconductor nanostructure 226U can then be removed.

[0117] Due to the epitaxial process used to form the lower epitaxial source / drain regions 262L, the upper surface of the lower epitaxial source / drain regions 262L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 262L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 262L of the same FET to merge.

[0118] A first contact etch stop layer (CESL) 266 and a first ILD 268 are formed above the lower epitaxial source / drain region 262L. The first CESL 266 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 268, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 268 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 268 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0119] The formation process may include depositing a conformal CESL layer, depositing material for the first ILD 268, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 268 is first etched, leaving the first CESL 266 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 266 above the recessed first ILD 268. After recessing, the sidewalls of the upper semiconductor nanostructure 226U are exposed.

[0120] Then, an upper epitaxial source / drain region 262U is formed in the upper portion of the source / drain recess 246. The upper epitaxial source / drain region 262U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 226U. The material of the upper epitaxial source / drain region 262U can be selected from the same candidate group of materials forming the lower source / drain region 262L, depending on the desired conductivity type of the upper epitaxial source / drain region 262U. The conductivity type of the upper epitaxial source / drain region 262U can be opposite to that of the lower epitaxial source / drain region 262L. For example, the upper epitaxial source / drain region 262U can be doped in the opposite way to the lower epitaxial source / drain region 262L. The upper epitaxial source / drain region 262U can be in-situ doped and / or implanted with n-type or p-type dopants. After the epitaxial process, adjacent upper source / drain regions 262U can remain separated, or adjacent upper source / drain regions 262U can be merged.

[0121] After forming the epitaxial source / drain region 262U, a second CESL 270 and a second ILD 272 are formed. The materials and formation methods can be similar to those of the first CESL 266 and the first ILD 268, respectively, and will not be discussed in detail here. The formation process may include depositing layers of CESL 270 and ILD 272, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 272, the gate spacer 244, and the dummy gate stack 242 are coplanar (within the range of process variations). The planarization process may remove the mask 240, or it may retain the hard mask 240 without removal.

[0122] Figure 18 and Figure 19A gate replacement process is illustrated to replace the dummy gate stack 242 and dummy nanostructure 224A with a gate stack 290. The gate replacement process includes first removing the remaining portions of the dummy gate stack 242 and dummy nanostructure 224A. The dummy gate stack 242 is removed in one or more etching processes, thereby defining a trench between the gate spacers 244 and exposing the upper portion of the semiconductor strip 228. The remaining portions of the dummy nanostructure 224A are then removed by etching, thereby causing the trench to extend between the semiconductor nanostructures 226. In the etching process, the dummy nanostructure 224A is etched at a faster rate than the semiconductor nanostructure 226, the dielectric isolation layer 256, and the internal spacers 254. The etching can be isotropic. For example, when the dummy nanostructure 224A is formed of silicon germanium and the semiconductor nanostructure 226 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0123] Then, a gate dielectric 278 is deposited on the exposed semiconductor nanostructure 226 and in the trench between the gate spacers 244. The gate dielectric 278 is conformally formed on the exposed surfaces of the trenches (removed gate stack 242 and pseudo nanostructure 224A), including the semiconductor nanostructure 226 and the gate spacers 244. In some embodiments, the gate dielectric 278 surrounds all (e.g., four) sides of the semiconductor nanostructure 226. Specifically, the gate dielectric 278 may be formed on the top surface of the fin 220'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 226; and the sidewalls of the gate spacers 244. The gate dielectric 278 may include oxides (such as silicon oxide or metal oxides), silicates (such as metal silicates), combinations thereof, multilayers thereof, etc. The gate dielectric 278 may include high-k materials having a k value greater than about 7.0, such as silicates or metal oxides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 278 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove portions of the gate dielectric 278 above the second ILD 272. Although a single-layer gate dielectric 278 is shown, the gate dielectric 278 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0124] like Figure 18As shown, a lower gate electrode 280L is formed on a gate dielectric 278 surrounding the lower semiconductor nanostructure 226L and the upper semiconductor nanostructure 226U. For example, in this stage before the lower gate electrode 280L is removed from the upper semiconductor nanostructure 226U, the lower gate electrode 280L surrounds the lower semiconductor nanostructure 226L and the upper semiconductor nanostructure 226U. The lower gate electrode 280L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 280L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0125] The lower gate electrode 280L is formed of a material suitable for the type of lower nanostructure FET device. For example, the lower gate electrode 280L may include one or more work function adjustment layers formed of a material suitable for the type of lower nanostructure FET device. In some embodiments, the lower gate electrode 280L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 280L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 280L may include a dipole inducing element suitable for the type of lower nanostructure FET device. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0126] The lower gate electrode 280L can be formed by conformally depositing one or more gate electrode layers, followed by planarization and recessing of the gate electrode layers. This can be achieved through the above-described process. Figures 1 to 13 The CMP system and method disclosed herein perform a planarization process, wherein Figure 18 The structure is wafer 100 or 158. In some embodiments, the CMP process can remove excess lower gate electrode 280L on the gate dielectric 278 above the second ILD 272. For example... Figure 18 As shown, the CMP process needs to stop at endpoint 284 without removing the gate dielectric 278. In some embodiments, the disclosed CMP process may remove 5 angstroms or less of the gate dielectric 278 above the second ILD 272. Precise stopping of the disclosed CMP process is required to provide a uniform topography for subsequent recessing steps of the lower gate electrode 280L, thereby allowing for better control of the recessing steps and preventing over-etching or leaving excessive lower gate electrode 280L in the trench.

[0127] Following the planarization process, the lower gate electrode 280L can be recessed to approximately the level of the isolation layer 256. The recessing process can include any acceptable etching process, such as dry etching, wet etching, or combinations thereof, to perform the recessing process and retract the gate electrode layer. The etching can be isotropic. Etching the lower gate electrode 280L can expose the upper semiconductor nanostructure 226U.

[0128] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 280L. The isolation layer acts as an isolation component between the lower gate electrode 280L and the subsequently formed upper gate electrode 280U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 226U.

[0129] exist Figure 19 In this embodiment, an upper gate electrode 280U is formed on the aforementioned isolation layer (if present) or the lower gate electrode 280L. The upper gate electrode 280U is disposed between the upper semiconductor nanostructures 226U. In some embodiments, the upper gate electrode 280U surrounds the upper semiconductor nanostructures 226U. The upper gate electrode 280U may be formed from the same candidate materials and candidate processes as those used to form the lower gate electrode 280L. The upper gate electrode 280U is made of a material suitable for the upper nanostructure FET device type. For example, the upper gate electrode 280U may include one or more work function adjustment layers formed of a material suitable for the upper nanostructure FET device type. Although a single-layer gate electrode 280U is shown, the upper gate electrode 280U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0130] Additionally, a removal process is performed to align the top surfaces of the upper gate electrode 280U and the second ILD 272. The removal process for forming the gate dielectric 278 can be the same as the removal process for forming the upper gate electrode 280U. In some embodiments, planarization processes, such as CMP, etch-back processes, combinations thereof, etc., can be utilized. After the planarization process, the top surfaces of the upper gate electrode 280U, the gate dielectric 278, the second ILD 272, and the gate spacer 244 are substantially coplanar (within the range of process variations). Each corresponding pair of gate dielectric 278 and gate electrode 280 (including the upper gate electrode 280U and / or the lower gate electrode 280L) can be collectively referred to as a “gate structure” 290 (including the upper gate structure 290U and the lower gate structure 290L). Each gate structure 290 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 226 (see [link to documentation]). Figure 14The lower gate structure 290L can also extend along the sidewalls and / or top surface of the semiconductor fin 220'.

[0131] For example Figure 19 As shown, a gate mask 292 is formed over a gate stack 242. The formation process may include: recessing the gate stack 290; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.; and performing a planarization process to remove excess dielectric material over the second ILD 272.

[0132] exist Figure 20 In the process, a silicide region 94 and a source / drain contact plug 96U are formed through the second ILD 272 to electrically couple to the upper epitaxial source / drain region 262U and / or the lower epitaxial source / drain region 262L. An etch stop layer (ESL) 304 and a third ILD 306 are formed. In some embodiments, the ESL 304 may include a dielectric material with high etch selectivity relative to the etch of the third ILD 306, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 306 can be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., and the material can be deposited by any suitable method, such as CVD, PECVD, etc.

[0133] Subsequently, an upper gate contact plug 308 and a source / drain contact plug 310 are formed to contact the upper gate electrode 280U and the upper source / drain contact plug 96U, respectively. The active devices shown in the figure are collectively referred to as device layer 312.

[0134] A front interconnect structure 314 is formed on device layer 312. The front interconnect structure 314 includes a dielectric layer 316 and layers of conductive components 318 / 320 located within the dielectric layer 316. The dielectric layer 316 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 316 may also include a passivation layer located above the low-k dielectric material, which is formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 316 may also include a polymer layer.

[0135] Conductive components 318 / 320 may include wires 318 and vias 320 that can be formed using an inlay process. Conductive components 318 / 320 may include metal wires 318 and metal vias 320, the metal wires 318 and metal vias 320 including a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. Aluminum pads may also be present above the metal wires and vias, and the aluminum pads are electrically connected to the metal wires and vias. Depending on how the corresponding die is packaged, the top surface components in conductive component 318 may include bonding pads, metal pillars, solder areas, etc.

[0136] In some embodiments, a back-side interconnect structure may be formed. The back-side interconnect structure provides electrical connections to the lower gate structure 290L and the lower epitaxial source / drain region 262L via the back side of device layer 312 (e.g., the side opposite to the front interconnect structure 314). The back-side interconnect structure may be similar to the front interconnect structure 314 described above and will not be described further here. In some embodiments, connections to the lower gate structure 290L and the lower epitaxial source / drain region 262L may be achieved via contacts (sometimes referred to as contact plugs), and the back-side interconnect structure may be omitted.

[0137] Figure 21 A diagram illustrating the operational sequence of a CMP system with capacitive sensing control according to some embodiments is shown. The diagram depicts the interactions between the various components of a polishing system 150, including a polishing stage 152, a polishing pad 154, a polishing head 156, a wafer 158, sensors 160 / 172 (which may be platform-mounted or head-mounted), and a controller 162.

[0138] Step 1 begins with the polishing system 150 placing the wafer onto the polishing pad using a polishing head. In Step 2, the polishing stage 152 initiates the rotation of the polishing pad 154, thereby starting the CMP process.

[0139] As polishing occurs, step 3 shows that the sensors (160 / 172) continuously measure the capacitance of wafer 158, as described in the reference above. Figure 5 As described. In step 4, the sensor sends the capacitance data to the controller 162 in real time.

[0140] Then, the controller performs three processing steps: step 5 involves processing the capacitance data and interpreting it as dielectric film thickness; in step 6, the controller compares the processed data with a predetermined acceptable range; and in step 7, when the capacitance measurement falls within the specified range, the controller signals to terminate the polishing process.

[0141] Finally, in step 8, upon receiving a termination signal, the system stops platform rotation and lifts the polishing head, ending the CMP operation.

[0142] The schematic diagram illustrates the communication flow between components, using dashed lines to represent ongoing monitoring and solid arrows to indicate direct commands or actions. This sequence diagram provides a visual representation of the control loops and decision-making processes involved in a capacitance-sensing-based CMP system, showing how the various components interact to achieve endpoint detection and process control. The step-by-step nature of the diagram helps to clarify the temporal sequence of operations in the CMP process and the causal relationships between different actions.

[0143] Figure 22 This is a flowchart of process 2200 according to some embodiments. In some embodiments, Figure 22 One or more process steps can be performed by the polishing system 150 / 170 / 180.

[0144] like Figure 22 As shown, process 2200 may include placing the wafer on a polishing pad of a chemical mechanical polishing (CMP) apparatus (step 2202). For example, as described above, polishing systems 150 / 170 / 180 may place the wafer on a polishing pad of a CMP apparatus. Also as... Figure 22 As shown, process 2200 may include performing a wafer removal process using a CMP apparatus (step 2204). For example, as described above, polishing systems 150 / 170 / 180 may use a CMP apparatus to perform a wafer removal process. Figure 22 As further shown, process 2200 may include detecting the capacitance of the dielectric film on the wafer using a capacitance sensor during the removal process (step 2206). For example, as described above, polishing systems 150 / 170 / 180 use a capacitance sensor to detect the capacitance of the dielectric film on the wafer during the removal process. Also as... Figure 22 As shown, process 2200 may include adjusting at least one polishing parameter based on detected capacitance (step 2208). For example, as described above, polishing systems 150 / 170 / 180 may adjust at least one polishing parameter based on detected capacitance. Figure 22 As further shown, process 2200 may include terminating the removal process (step 2210) when the detected capacitance of the wafer is within a predetermined range corresponding to the target thickness of the dielectric film. For example, as described above, polishing system 150 / 170 / 180 may terminate the removal process when the detected capacitance of the wafer is within a predetermined range corresponding to the target thickness of the dielectric film.

[0145] although Figure 22 Exemplary steps of process 2200 are shown, but in some embodiments, process 2200 may include steps other than those shown. Figure 22The steps shown can have more steps, fewer steps, different steps, or steps arranged differently. Alternatively, two or more steps of process 2200 can be performed in parallel.

[0146] In one embodiment, the polishing system may include a polishing stage. The polishing system may also include a polishing pad located on the polishing stage, a polishing head configured to maintain contact between the wafer and the polishing pad, a capacitance sensor configured to measure the capacitance of a dielectric film on the wafer during the polishing process, and a controller electrically connected to the capacitance sensor. The controller may be configured to adjust at least one polishing parameter based on the measured capacitance, and to terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film.

[0147] The embodiments may further include one or more of the following features: In the polishing system, a capacitive sensor is integrated into the polishing table. In the polishing system, a capacitive sensor is integrated into the polishing head. In the polishing system, the capacitive sensor may include multiple sensors arranged in a linear configuration, a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. The polishing system may include a polishing slurry distributor configured to deposit polishing slurry onto a polishing pad. In the polishing system, the capacitive sensor has a shape selected from rectangular, square, or circular. In the polishing system, at least one polishing parameter may include polishing pressure, polishing speed, or polishing slurry composition.

[0148] In one embodiment, a method may include placing a wafer on a polishing pad of a chemical mechanical polishing (CMP) apparatus. The method may further include: performing a removal process on the wafer using the CMP apparatus; during the removal process, detecting the capacitance of a dielectric film on the wafer using a capacitance sensor; adjusting at least one polishing parameter based on the detected capacitance; and terminating the removal process when the detected capacitance of the wafer is within a predetermined range corresponding to a target thickness of the dielectric film.

[0149] The embodiments may also include one or more of the following features: In the method, a capacitance sensor is integrated into the polishing stage of the CMP apparatus. In the method, a capacitance sensor is integrated into the polishing head of the CMP apparatus. In the method, the capacitance sensor may include multiple sensors arranged in a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. In the method, at least one polishing parameter may include polishing pressure, polishing speed, or polishing slurry composition. In the method, detecting capacitance may include measuring capacitance at multiple locations across the surface of the wafer. The method may include depositing polishing slurry onto a polishing pad prior to performing a removal process.

[0150] In one embodiment, the CMP apparatus may include a capacitance sensor integrated into the polishing head, wherein the capacitance sensor is configured to measure the capacitance of a dielectric film on the wafer during the polishing process. The CMP apparatus may also include a controller electrically connected to the capacitance sensor, wherein the controller is configured to adjust at least one polishing parameter based on the measured capacitance, and to terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film.

[0151] The embodiments may also include one or more of the following features: In the CMP apparatus, the capacitance sensor may include multiple sensors arranged in a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. In the CMP apparatus, the capacitance sensor is configured to measure capacitance at multiple locations across the surface of the wafer. In the CMP apparatus, at least one polishing parameter may include polishing pressure or polishing speed. In the CMP apparatus, the capacitance sensor has a shape selected from rectangular, square, or circular. In the CMP apparatus, the capacitance sensor may include at least three sensors arranged at equal intervals.

[0152] Some embodiments of this application provide a polishing system comprising: a polishing table; a polishing pad located on the polishing table; a polishing head configured to maintain contact between a wafer and the polishing pad; a capacitance sensor configured to measure the capacitance of a dielectric film on the wafer during a polishing process; and a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film. In embodiments, the capacitance sensor is integrated into the polishing table. In embodiments, the capacitance sensor is integrated into the polishing head. In embodiments, the capacitance sensor includes a plurality of sensors arranged in a linear configuration, a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. In embodiments, the polishing system further includes a polishing slurry dispenser configured to deposit polishing slurry onto the polishing pad. In embodiments, the capacitance sensor has a shape selected from rectangular, square, or circular. In embodiments, at least one polishing parameter includes polishing pressure, polishing speed, or polishing slurry composition.

[0153] Other embodiments of this application provide a method for polishing a wafer, the method comprising: placing the wafer on a polishing pad of a chemical mechanical polishing (CMP) apparatus; performing a removal process on the wafer using the CMP apparatus; during the removal process, detecting the capacitance of a dielectric film on the wafer using a capacitance sensor; adjusting at least one polishing parameter based on the detected capacitance; and terminating the removal process when the detected capacitance of the wafer is within a predetermined range corresponding to a target thickness of the dielectric film. In embodiments, the capacitance sensor is integrated into the polishing stage of the CMP apparatus. In embodiments, the capacitance sensor is integrated into the polishing head of the CMP apparatus. In embodiments, the capacitance sensor includes a plurality of sensors arranged in a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. In embodiments, at least one polishing parameter includes polishing pressure, polishing speed, or polishing slurry composition. In embodiments, detecting capacitance includes measuring capacitance at multiple locations across the surface of the wafer. In embodiments, the method for polishing a wafer further includes depositing a polishing slurry onto the polishing pad prior to performing the removal process.

[0154] Further embodiments of this application provide a chemical mechanical polishing (CMP) apparatus comprising: a capacitance sensor integrated into a polishing head, wherein the capacitance sensor is configured to measure the capacitance of a dielectric film on a wafer during a polishing process; and a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film. In embodiments, the capacitance sensor includes a plurality of sensors arranged in a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration. In embodiments, the capacitance sensor is configured to measure capacitance at multiple locations across the surface of the wafer. In embodiments, at least one polishing parameter includes polishing pressure or polishing speed. In embodiments, the capacitance sensor has a shape selected from rectangular, square, or circular. In embodiments, the capacitance sensor includes at least three sensors arranged at equal intervals.

[0155] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other operations and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A polishing system, comprising: a polishing table; a polishing pad positioned on the polishing table; a polishing head configured to hold a wafer in contact with the polishing pad; a capacitance sensor configured to measure a capacitance of a dielectric film on the wafer during a polishing process; and a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film. The capacitance sensor is integrated into the polishing table. The capacitance sensor is integrated into the polishing head.

2. The polishing system of claim 1, wherein, The capacitance sensor comprises a plurality of sensors arranged in one of a linear configuration, a cross-shaped pattern configuration, a radial pattern configuration, or a circular pattern configuration.

3. The polishing system of claim 1, wherein, 5. The polishing system of claim 1, further comprising a polishing fluid dispenser configured to deposit a polishing fluid onto the polishing pad.

4. The polishing system of claim 1, wherein, The capacitance sensor has a shape selected from a rectangle, a square, or a circle. The at least one polishing parameter comprises a polishing pressure, a polishing speed, or a polishing fluid composition.

6. The polishing system of claim 1, wherein, 8. A method of polishing a wafer, comprising:

7. The polishing system of claim 1, wherein, positioning a wafer on a polishing pad of a chemical mechanical polishing apparatus; performing a removal process on the wafer using the chemical mechanical polishing apparatus; detecting a capacitance of a dielectric film on the wafer using a capacitance sensor during the removal process; adjusting at least one polishing parameter based on the detected capacitance; and terminating the removal process when the detected capacitance of the wafer is within a predetermined range corresponding to a target thickness of the dielectric film. The capacitance sensor is integrated into a polishing table of the chemical mechanical polishing apparatus.

10. A chemical mechanical polishing apparatus, comprising: a capacitance sensor integrated into a polishing head, wherein the capacitance sensor is configured to measure a capacitance of a dielectric film on a wafer during a polishing process; and 9. The method of claim 8, wherein, a controller electrically connected to the capacitance sensor, wherein the controller is configured to: adjust at least one polishing parameter based on the measured capacitance; and terminate the polishing process when the measured capacitance is within a predetermined range corresponding to a target thickness of the dielectric film. ​ ​ ​

Images