2.5 D packaging structure of photoelectric chip and packaging method thereof

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a 2.5 D packaging structure of a photoelectric chip and a packaging method of the 2.5 D packaging structure. The first adapter plate is arranged on the upper surface of the first substrate, and a first connecting area and a second connecting area are arranged on the upper surface of the first adapter plate; the at least one first-class electronic chip is arranged on the upper surface of the first connection area and is electrically connected with the first adapter plate; the second adapter plate is arranged on the upper surface of the second connecting area and is electrically connected with the first adapter plate; the reinforced connection layer is arranged on the upper surface of the first substrate; according to the packaging structure with the composite interposer structure and the polishing method of the packaging structure provided by the invention, the flatness of the whole packaging structure is comprehensively improved from the structure and through a polishing process, and particularly, the connection stability between a photon chip with high connection density and an adapter plate can be improved.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a 2.5D packaging structure for an optoelectronic chip and its packaging method. Background Technology

[0002] With the rapid development of technologies such as big data, artificial intelligence, and 5G communication, higher demands are being placed on hybrid packaging structures for optoelectronic chips that offer high bandwidth, low power consumption, and high integration. Hybrid optoelectronic packaging, by integrating photonic chips and electronic chips into the same package, achieves efficient conversion and transmission of optical and electrical signals, and has become an important development direction in the "Beyond Moore's Law" field. In particular, silicon photonic chips (also known as photonic chips), due to their compatibility with CMOS processes, low power consumption, and high bandwidth, show broad application prospects in data centers, high-performance computing, and other fields.

[0003] Traditional 2.5D packaging technology typically uses a silicon interposer as the interconnect carrier between optical and electrical chips, achieving vertical interconnection through through-silicon vias (TSVs). However, with increasing chip integration, issues such as mismatched coefficients of thermal expansion and stress concentration between multiple layers in the package structure become increasingly prominent. This leads to warpage during package fabrication, severely impacting packaging yield and reliability. Furthermore, the package is prone to significant deformation during fabrication, especially in wafer-level mass production. This not only affects the alignment accuracy and connection reliability between multilayer structures but also restricts further improvements in packaging yield and long-term stability.

[0004] To address the aforementioned issues, the applicant disclosed a hybrid packaging structure for optoelectronic chips based on multi-layer reinforcement layers in CN119471934B. By setting a connection structure including a silicon interposer and multi-layer reinforcement layers on a first substrate, staggered packaging of optical and electrical chips is achieved, which alleviates the problem of uneven stress to a certain extent and supports wafer-level processing.

[0005] However, in practical applications, the applicant still faces a major challenge in effectively controlling the overall deformation of the package during mass production, especially in achieving the goals of lower warpage and higher flatness.

[0006] Therefore, there is an urgent need for an optimized packaging solution that can better accommodate wafer-level mass production processes and fundamentally improve the flatness and dimensional stability of the package, thereby meeting the stringent requirements of next-generation high-performance optoelectronic chips for packaging technology. Summary of the Invention

[0007] The purpose of this invention is to provide a 2.5D packaging structure for an optoelectronic chip and a packaging method thereof, so as to partially alleviate or solve the above-mentioned problems and reduce the warpage of the packaging structure.

[0008] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a packaging method for a 2.5D packaging structure of an optoelectronic chip, the 2.5D packaging structure of the optoelectronic chip comprising: First substrate; A first adapter plate is disposed on the upper surface of the first substrate. A first connection area and a second connection area are disposed on the upper surface of the first adapter plate. A first conductive post is formed in the first adapter plate. At least one Class I electronic chip is disposed on the upper surface of the first connection area and electrically connected to the first adapter plate; The second adapter plate is disposed on the upper surface of the second connection area and electrically connected to the first adapter plate, and a second conductive post is formed in the second adapter plate; A reinforced connection layer is disposed on the upper surface of the first substrate for covering the first adapter plate, the type of electronic chip, and the second adapter plate; At least one photonic chip is flip-chip mounted on the upper surface of the second adapter plate and forms an electrical path with the electronic chip through the second conductive post. The encapsulation method includes: S100 provides the first substrate; S200, a first adapter plate is disposed on the upper surface of the first substrate; S300, with at least one Class I electronic chip in the first connection area and a second adapter board in the second connection area; S400, a first reinforcing material is filled into the layer containing the first adapter board, the electronic chip, and the second adapter board to form a reinforced connection layer; S500, the reinforced connection layer is ground and thinned until the top of the second conductive post is exposed from the surface of the second adapter plate; S600, a photonic chip is disposed on the upper surface of the second adapter plate, and the photonic chip is electrically connected to the second conductive post.

[0009] As an improvement, the second adapter plate includes at least an X element, the second conductive post includes at least a Y element, and the reinforcing connection layer and the second adapter plate are formed with a multi-layer heterogeneous structure in the height direction. The multi-layer heterogeneous structure includes at least: a reinforcing material layer, a first hybrid layer and a second hybrid layer arranged sequentially from top to bottom. The first hybrid layer includes at least a first reinforcing material and element X; the second hybrid layer includes at least a first reinforcing material, element X, and element Y. In S500, the step of grinding and thinning the reinforced bonding layer includes: S510, the reinforcing material layer is polished using the first process; S520, the first mixed layer is polished using the second process; S530, the second mixed layer is polished using a third process.

[0010] As an improvement, the first process parameters of the first to third processes include at least: the mesh size of the grinding wheel, the spindle speed, and the feed rate; wherein, in the first, second, and third processes, the mesh size of the grinding wheel gradually increases, and in the first, second, and third processes, the spindle speed and feed rate gradually decrease.

[0011] As an improvement, the first adapter plate and the second adapter plate are selected from at least one of silicon adapter plates and glass adapter plates.

[0012] As an improvement, it also includes: S540, which is polished using a preset polishing process.

[0013] As an improvement, the polishing process is a chemical mechanical polishing (CMP) process, and the second process parameters of the polishing process include at least: the pH value of the polishing solution, the polishing temperature, pressure and rotation speed.

[0014] As an improvement, the following steps are included before executing S200: S150, the first adapter plate is polished by the second process and the third process in sequence. In the second process, the grit number of the polishing wheel is smaller than that of the polishing wheel in the third process. The spindle speed and feed rate in the second process are both greater than those in the third process.

[0015] As an improvement, at least one second substrate is further disposed on the upper surface of the first substrate, and at least one type II electronic chip is disposed on the upper surface of the second substrate. The type II electronic chip is electrically connected to the substrate through a conductive structure. The type I electronic chip is a wDAC chip, and the type II electronic chip is at least one of xADC and xDAC chips.

[0016] As an improvement, the first adapter board is provided with a first bonding structure, the second adapter board is provided with a second bonding structure, the second adapter board and the electronic chip are connected to the first adapter board through the first bonding structure, and the photonic chip is connected to the second adapter board through the second bonding structure.

[0017] A second aspect of the present invention is to provide a 2.5D packaging structure for an optoelectronic chip, comprising: First substrate; A first adapter plate is disposed on the upper surface of the first substrate, and a first conductive post is formed in the first adapter plate; A first adapter plate is disposed on the upper surface of the first substrate. A first connection area and a second connection area are disposed on the upper surface of the first adapter plate. A first conductive post is formed in the first adapter plate. At least one Class I electronic chip is disposed on the upper surface of the first connection area and electrically connected to the first adapter plate; A reinforced connection layer is disposed on the upper surface of the first substrate for covering the first adapter plate, the type of electronic chip, and the second adapter plate; At least one photonic chip is flip-chip mounted on the upper surface of the second adapter plate and forms an electrical path with the electronic chip through the second conductive post. The reinforced connection layer and the second adapter plate are formed with a multi-layer heterogeneous structure in the height direction. The multi-layer heterogeneous structure includes at least: a reinforcing material layer, a first hybrid layer and a second hybrid layer arranged sequentially from top to bottom; the first hybrid layer includes at least the materials of the first reinforcing material and the second adapter plate; the second hybrid layer includes at least the materials of the first reinforcing material, the second adapter plate and the second conductive post.

[0018] The principle and beneficial technical effects of this invention are as follows: Regarding the aforementioned staggered packaging structure (CN119471934B), this application provides a packaging structure with a composite interposer structure (including a first adapter board and a second adapter board), as well as a polishing method for the packaging structure. This method comprehensively improves the flatness of the entire packaging structure from the structure itself and through the polishing process, and in particular, it can improve the connection stability between the photonic chip with high connection density and the adapter board.

[0019] Specifically, by partially replacing the large area of ​​molding compound in the prior art with a second adapter plate, and utilizing the superior stiffness and thermal expansion coefficient matching between the silicon (or glass) adapter plate and the molding compound, the warpage of the package during processing and use is fundamentally reduced structurally. Furthermore, this application also performs layered grinding and polishing on the multilayer heterogeneous structure, adapting different grinding wheel grit numbers, spindle speeds and feed rates to different material layers, and finally combining it with CMP polishing with controllable pH value, achieving a highly flattened and non-destructive bonding surface, providing a guarantee for high-precision and high-yield flip bonding of photonic chips.

[0020] In other words, this application uses a two-level interconnect architecture of "first adapter board + second adapter board" and a multi-layered combined polishing process of "first process, second process, third process, etc." to dually control the degree of warpage from both structural and process perspectives. Even in the case of high-density interconnection between photonic chips and adapter boards, it can ensure that all connection points in the high-density configuration can be conductive, thereby achieving higher-density integrated circuit packaging. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0022] Figure 1 This is a schematic diagram of the 2.5D packaging structure of the optoelectronic chip in an exemplary embodiment of the present invention; Figure 2 This is a schematic diagram of the 2.5D packaging structure of the optoelectronic chip in another exemplary embodiment of the present invention; Figure 3 This is a schematic diagram of a multilayer heterostructure in an embodiment of the present invention; Figure 4 This is a flowchart of the packaging method for the 2.5D packaging structure of the optoelectronic chip in an embodiment of the present invention.

[0023] The markings in the diagram are as follows: 1. First substrate; 2. First adapter plate; 201. First conductive pillar; 3. Type I electronic chip; 4. Second adapter plate; 401. Second conductive pillar; 5. Reinforcing connection layer; 6. Photonic chip; 7. Second substrate; 8. First bonding structure; 9. Second bonding structure; 10. Type II electronic chip; 11. First reinforcing layer; 12. Second reinforcing layer; 13. Third reinforcing layer; 14. Fourth reinforcing layer; 15. Reinforcing material layer; 16. First hybrid layer; 17. Second hybrid layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" may be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," and "connected," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0027] Example 1 This invention provides a 2.5D packaging structure for an optoelectronic chip, see [link to relevant documentation]. Figure 1 ,include: A first substrate 1 (preferably an ABF substrate, i.e., an Ajinomoto Build-up Film substrate) serves as the mechanical support and electrical foundation of the entire packaging structure; a first adapter plate 2 is disposed on the upper surface of the first substrate 1, and a first connection area and a second connection area are disposed on the upper surface of the first adapter plate 2, and a first conductive post 201 is formed in the first adapter plate 2; at least one Class I electronic chip 3 is disposed on the upper surface of the first adapter plate 2 (especially the first connection area) and electrically connected to the first adapter plate 2; a second adapter plate 4 is disposed on the upper surface of the first adapter plate 2 (especially the second connection area) and electrically connected to the first adapter plate 2, and a second conductive post 401 is formed in the second adapter plate 4.

[0028] A reinforcing connection layer 5 is disposed on the upper surface of the first substrate 1 to cover the first adapter plate 2, the first type of electronic chip 3, and the second adapter plate 4. Specifically, the reinforcing connection layer 5 can be a molding compound formed by molding and curing epoxy molding compound (EMC), disposed on the upper surface of the first substrate 1, completely covering the sides of the first adapter plate 2, the first type of electronic chip 3, and the second adapter plate 4, thereby improving the stability of the packaging structure.

[0029] At least one photonic chip 6 (preferably a silicon photonic chip) is flip-chip disposed on the upper surface of the second adapter plate 4, and forms an electrical path with the electronic chip 3 through the second conductive post 401; wherein, the reinforcing connection layer 5 and the second adapter plate 4 form a multilayer heterostructure in the height direction, the multilayer heterostructure including at least: a reinforcing material layer 15, a first hybrid layer 16 and a second hybrid layer 17 arranged sequentially from top to bottom (see Figure 3 The first hybrid layer includes at least the first reinforcing material and the material of the second adapter plate 4; the second hybrid layer includes at least the first reinforcing material, the material of the second adapter plate 4, and the material of the second conductive post 401.

[0030] In some embodiments, the first adapter plate 2 and the second adapter plate 4 are selected from at least one of silicon adapter plates and glass adapter plates.

[0031] In some embodiments, the first conductive post 201 and the second conductive post 401 may be through-silicon vias (TSVs).

[0032] For example, the reinforcing connection layer 5 is an epoxy molding compound layer (referred to as molding layer), the first adapter plate 2 is a silicon adapter plate, the first conductive post 201 is a through silicon via (TSV), and correspondingly, the reinforcing material layer is a molding layer of a single material, the first hybrid layer is a composite layer of molding layer and silicon material, and the second hybrid layer is a composite layer composed of molding layer, silicon material and copper material.

[0033] In some embodiments, at least one second substrate 7 is further disposed on the upper surface of the first substrate 1, located on the side or adjacent area of ​​the first adapter plate 2; at least one type II electronic chip 10 is disposed on the upper surface of the second substrate 7, the type II electronic chip 10 is electrically connected to the substrate through a conductive structure, the type I electronic chip 10 is a weighted digital-to-analog converter (wDAC) chip, and the type II electronic chip 10 is at least one of a programmable analog-to-digital converter (xADC) and a programmable digital-to-analog converter (xDAC) chip.

[0034] In some embodiments, the first adapter plate 2 is provided with a first bonding structure 8, and the second adapter plate 4 is provided with a second bonding structure 9. The second adapter plate 4 and the electronic chip 3 are connected to the first adapter plate 2 through the first bonding structure 8, and the photonic chip 6 is connected to the second adapter plate 4 through the second bonding structure 9. The bonding structure is a conductive structure capable of conducting electricity, such as a conductive bump.

[0035] In some embodiments, see Figure 2 A first reinforcing layer 11 is filled between the first adapter plate 2 and the first substrate 1; a second reinforcing layer 12 is filled between the first adapter plate 2 and the second adapter plate 4; a third reinforcing layer 13 is filled between the second adapter plate 4 and the photonic chip 6; and a fourth reinforcing layer 14 is filled between the electronic chip and the first adapter plate 2. All of the first to fourth reinforcing layers 14 are filled with reinforcing material (referring to a material that can adhere to the surface to be packaged and has a certain strength after curing).

[0036] In summary, this application introduces a second adapter board 4, which works with the first adapter board 2 to form a two-level interconnect architecture (i.e., a composite interposer layer), and uses rigid silicon material to replace large-area molding compound, thereby fundamentally suppressing package warpage.

[0037] Example 2 See Figure 4 This embodiment provides a packaging method for a 2.5D packaging structure of an optoelectronic chip, based on the 2.5D packaging structure of the optoelectronic chip in Embodiment 1, including the following steps: S100 provides the first substrate; S200, a first adapter plate is disposed on the upper surface of the first substrate; S300, with at least one Class I electronic chip in the first connection area and a second adapter board in the second connection area; S400, a first reinforcing material is filled into the layer containing the first adapter board, the electronic chip, and the second adapter board to form a reinforced connection layer; S500, the reinforced connection layer is ground and thinned until the top of the second conductive pillar is exposed from the upper surface of the second adapter plate, thereby ensuring that the second adapter plate can conduct signals with other structures (such as photonic chips); S600, a photonic chip is disposed on the upper surface of the second adapter plate, and the photonic chip is electrically connected to the second conductive post.

[0038] In some embodiments, the second adapter plate includes at least an X element, the second conductive post includes at least a Y element, and the reinforcing connection layer and the second adapter plate are formed with a multi-layer heterogeneous structure in the height direction (or vertical direction). The multi-layer heterogeneous structure includes at least: a reinforcing material layer, a first hybrid layer and a second hybrid layer arranged sequentially from top to bottom. The first hybrid layer includes at least a first reinforcing material and element X; the second hybrid layer includes at least a first reinforcing material, element X and element Y; wherein, element X may be a material element such as silicon or glass, and element Y may be a conductive material element such as copper or tungsten.

[0039] In S500, the step of grinding and thinning the reinforced bonding layer includes: S510, the reinforcing material layer is polished using the first process; S520, the first mixed layer is polished using the second process; S530, the second mixed layer is polished using a third process.

[0040] In some embodiments, the first process parameters of the first to third processes (i.e., the first process, the second process, and the third process) include at least: the grit size of the grinding wheel, the spindle speed, and the feed rate; wherein, in the first process, the second process, and the third process, the grit size of the grinding wheel gradually increases, and in the first process, the second process, and the third process, the spindle speed and the feed rate gradually decrease. Here, "spindle speed" refers to the number of revolutions per minute of the grinding equipment spindle (the shaft on which the grinding wheel is mounted); "feed rate" refers to the speed at which the grinding wheel moves on the working surface, or the speed at which the workpiece carried by the worktable is pushed towards the grinding wheel.

[0041] In some embodiments, the encapsulation method further includes: S540, performing polishing treatment using a preset polishing process. The polishing process is a chemical mechanical polishing (CMP) process, and the second process parameters of the polishing process include at least: the pH value of the polishing solution, polishing temperature, pressure, and rotation speed.

[0042] In other words, a multi-layered polishing solution is provided for multi-layered heterogeneous structures. Different polishing wheel grit numbers, spindle speeds and feed rates are adapted to different material layers, and finally combined with CMP polishing with controllable pH value, a highly flattened and non-destructive bonding surface is achieved.

[0043] In other words, this application provides a multi-stage grinding method of "coarse + fine" for multilayer heterogeneous structures. First, before grinding and thinning, the thickness of the packaging structure and the distribution of thickness of each layer of the internal mechanism are calculated and measured based on the packaging scheme information to set the grinding amount. Then, coarse grinding is performed, using a coarse grinding wheel with a smaller mesh size inside the machine. At this time, the rotation speed and feed rate are relatively high. Further, when grinding and thinning to the silicon interface, the process switches to a medium grinding wheel with a relatively larger mesh size, and the rotation speed and feed rate are appropriately reduced. When grinding and thinning is about to reach the silicon and copper interface, the process automatically switches to a fine grinding wheel for fine grinding and thinning in the same machine. At this time, the spindle speed and feed rate are slower. Further, chemical mechanical polishing (CMP) is performed on the silicon substrate surface to further thin the silicon substrate and flatten the surface. CMP (Chemical Motion Process) can remove the grinding damage layer and roughness on the surface of silicon substrates, ensuring surface flatness and smoothness so that subsequent etching processes can be carried out uniformly, and also helps to improve the quality of subsequent metallization processes.

[0044] In some embodiments, before performing S200, the following steps are also included: In step S150, the first adapter board is polished sequentially using a second process and a third process. In the second process, the grit number of the polishing wheel is smaller than that in the third process. The spindle speed and feed rate in the second process are both greater than those in the third process. The second process in this step can be the same as the second process in step S520, and the third process in this step can be the same as the third process in step S530. That is, for the double-layer structure of the first adapter board (taking a silicon adapter board as an example, where the first layer is a silicon layer and the second layer is a mixture of silicon and copper), this application also provides a multi-layer polishing process to improve the connection stability of the basic structure (e.g., the substrate and the first adapter board).

[0045] In summary, regarding the aforementioned staggered packaging structure (CN119471934B), this application provides a packaging structure with a composite interposer structure (including a first adapter board and a second adapter board), as well as a polishing method for the packaging structure. This method comprehensively improves the flatness of the entire packaging structure from the structure itself and through the polishing process, and in particular, it can improve the connection stability between the photonic chip with high connection density and the adapter board.

[0046] Specifically, by partially replacing the large area of ​​molding compound in the prior art with a second adapter plate, and utilizing the superior stiffness and thermal expansion coefficient matching between the silicon (or glass) adapter plate and the molding compound, the warpage of the package during processing and use is fundamentally reduced structurally. Furthermore, this application also performs layered grinding and polishing on the multilayer heterogeneous structure, adapting different grinding wheel grit numbers, spindle speeds and feed rates to different material layers, and finally combining it with CMP polishing with controllable pH value, achieving a highly flattened and non-destructive bonding surface, providing a guarantee for high-precision and high-yield flip bonding of photonic chips.

[0047] In other words, this application uses a two-level interconnect architecture of "first adapter board + second adapter board" and a multi-layered combined polishing process of "first process, second process, third process, etc." to dually control the degree of warpage from both structural and process perspectives. Even in the case of high-density interconnection between photonic chips and adapter boards, it can ensure that all connection points in the high-density configuration can be conductive, thereby achieving higher-density integrated circuit packaging.

[0048] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0049] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A packaging method of a 2.5D packaging structure of an optoelectronic chip, characterized in that, The 2.5D packaging structure of the optoelectronic chip comprises: a first substrate; a first adapter plate arranged on the upper surface of the first substrate, the upper surface of the first adapter plate being provided with a first connection area and a second connection area, and the first adapter plate being provided with a first conductive column; at least one electronic chip of a first type arranged on the upper surface of the first connection area and electrically connected with the first adapter plate; a second adapter plate arranged on the upper surface of the second connection area and electrically connected with the first adapter plate, the second adapter plate being provided with a second conductive column; a reinforced connection layer arranged on the upper surface of the first substrate and used for covering the first adapter plate, the electronic chip of the first type and the second adapter plate; at least one photonic chip flip-chip arranged on the upper surface of the second adapter plate and electrically connected with the electronic chip of the first type through the second conductive column; The packaging method comprises: S100, providing a first substrate; S200, arranging a first adapter plate on the upper surface of the first substrate; S300, arranging at least one electronic chip of a first type on the first connection area and arranging a second adapter plate on the second connection area; S400, filling a first reinforcing material on the layer where the first adapter plate, the electronic chip of the first type and the second adapter plate are located to form a reinforced connection layer; S500, performing a grinding and thinning process on the reinforced connection layer until the top end of the second conductive column is exposed from the upper surface of the second adapter plate; S600, arranging a photonic chip on the upper surface of the second adapter plate so that the photonic chip is electrically connected with the second conductive column.

2. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, The second adapter plate comprises at least an element X, the second conductive column comprises at least an element Y, the reinforced connection layer and the second adapter plate form a multi-layer heterostructure in the height direction, and the multi-layer heterostructure comprises at least a reinforced material layer, a first mixed layer and a second mixed layer arranged in sequence from top to bottom; The first mixed layer comprises at least a first reinforcing material and the element X, and the second mixed layer comprises at least the first reinforcing material, the element X and the element Y; In S500, the step of performing a grinding and thinning process on the reinforced connection layer comprises: S510, performing grinding on the reinforced material layer by using a first process; S520, performing grinding on the first mixed layer by using a second process; S530, performing grinding on the second mixed layer by using a third process.

3. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 2, wherein, The first process parameter of the first to third processes comprises at least the mesh number of a grinding wheel, the spindle speed and the feed speed, wherein the mesh number of the grinding wheel gradually increases in the first process, the second process and the third process, and the spindle speed and the feed speed gradually decrease in the first process, the second process and the third process. 4.The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, The first adapter plate and the second adapter plate are selected from at least one of a silicon adapter plate and a glass adapter plate. 5.The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, Further comprising: S540, performing polishing by using a preset polishing process.

6. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 5, wherein, The polishing process is a chemical mechanical polishing process, and the second process parameter of the polishing process comprises at least the PH value of a polishing liquid, the polishing temperature, the pressure and the rotation speed.

7. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, Before S200 is performed, further comprising the step of: S150, sequentially polish the first adapter plate by using a second process and a third process, wherein the mesh number of the polishing wheel in the second process is less than the mesh number of the polishing wheel in the third process, and the spindle speed and the feed speed in the second process are greater than the spindle speed and the feed speed in the third process.

8. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, The upper surface of the first substrate is further provided with at least one second substrate, and the upper surface of the second substrate is provided with at least one second electronic chip, and the first electronic chip and the second electronic chip are electrically connected through a conductive structure.

9. The packaging method of the 2.5D packaging structure of optoelectronic chips according to claim 1, wherein, The first bonding structure is arranged on the first adapter plate, and the second bonding structure is arranged on the second adapter plate.

10. A 2.5D packaging structure of optoelectronic chips, characterized in that, The first substrate is provided with: The first adapter plate is arranged on the upper surface of the first substrate, and the upper surface of the first adapter plate is provided with a first connection area and a second connection area, and the first adapter plate is formed with a first conductive column; At least one first electronic chip is arranged on the upper surface of the first connection area and is electrically connected with the first adapter plate; The second adapter plate is arranged on the upper surface of the first adapter plate and is electrically connected with the first adapter plate, and the second adapter plate is formed with a second conductive column; The reinforcing connection layer is arranged on the upper surface of the first substrate and is used for covering the first adapter plate, the first electronic chip and the second adapter plate; At least one photonic chip is flip-chip arranged on the upper surface of the second adapter plate and forms an electrical path with the first electronic chip through the second conductive column; The reinforcing connection layer and the second adapter plate form a multi-layer heterostructure in the height direction, and the multi-layer heterostructure at least includes: from top to bottom, a reinforcing material layer, a first mixed layer and a second mixed layer; the first mixed layer at least includes a first reinforcing material and a material of the second adapter plate; the second mixed layer at least includes a first reinforcing material, a material of the second adapter plate and a material of the second conductive column. ​

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