A power modulation method and system suitable for all-solid-state power supplies

Abstract

The application discloses a power modulation method and system of a full solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and dividing the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments to obtain a time-level number corresponding relationship, and generating a corresponding switch action time sequence matrix; the row index of the switch action time sequence matrix corresponds to the level number, and the odd columns store the turn-on time parameters of the corresponding switch devices under the corresponding level number, and the even columns store the turn-off time parameters of the corresponding switch devices; the switch action time sequence matrix is converted into period counting based on the main clock of the FPGA, and the FPGA generates corresponding driving pulse signals according to the time sequence data, so as to control the switch devices in the full solid-state power supply and perform power modulation. The switch of the solid-state power supply is controlled with high real-time performance and high precision, and the effect of arbitrary waveform power modulation is realized.

Description

Technical Field

[0001] This invention belongs to the field of pulse power technology, and more specifically, relates to a power modulation method and system applicable to an all-solid-state power supply. Background Technology

[0002] Solid-state power supplies have found widespread application in industrial processing, medical equipment, scientific research, and many other fields due to their high repetition rate, long lifespan, and flexible controllability. However, as modern applications place increasingly higher demands on the power level, integration, waveform parameter adjustment range, and output waveform quality of power modulation systems, the number of semiconductor switching devices inside solid-state power supplies has increased significantly, leading to a substantial increase in the complexity of their power regulation systems. Furthermore, the limitations of existing hardware and software architectures in terms of timing control accuracy, real-time control, and waveform reconstruction capabilities are becoming increasingly apparent. This is especially true when dealing with complex, irregular, or even non-analytical target waveforms, where the implementation process is extremely cumbersome and difficult to automate through programming, becoming a bottleneck restricting the development of solid-state power supply technology towards higher performance.

[0003] Traditional power modulation methods are mostly based on analog circuits or simple digital control algorithms. They have significant shortcomings in terms of waveform generation flexibility, accuracy of multi-channel timing synchronization, operational stability under electromagnetic interference environments, and rapid diagnosis and protection of system faults. Furthermore, they exhibit serious adaptability problems when dealing with complex waveforms. Especially in complex topology systems composed of multi-level, multi-module series and parallel connections, it is often necessary to coordinate the turn-on and turn-off timing of hundreds or thousands of power switching devices. Any slight timing deviation or drive jitter can lead to output waveform distortion, reduced system efficiency, or even device damage.

[0004] Therefore, under harsh operating conditions of strong interference, high voltage, and high current, how to achieve nanosecond-level high-precision synchronous control, efficiently and flexibly generate arbitrary complex high-voltage waveforms with high fitting accuracy and programmability, and ensure long-term reliable operation of the system has become a key problem that needs to be solved in the current all-solid-state power modulation. Summary of the Invention

[0005] In view of the shortcomings of related technologies, the purpose of this invention is to provide a power modulation method and system for all-solid-state power supplies, which aims to solve the problems of low switching timing control accuracy, lack of advanced modulation strategies, and difficulty in achieving complex waveform modulation and output in current all-solid-state power modulation.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a power modulation method suitable for all-solid-state power supplies, comprising:

[0007] The NLM algorithm is used to convert the target waveform into a multi-level discrete waveform, and the multi-level discrete waveform is divided into several continuous sub-waveforms according to polarity; wherein, the number of levels is adjustable;

[0008] For each sub-waveform, all level switching moments are identified using an edge detection algorithm to obtain the time-level correspondence and generate the corresponding switching action timing matrix. The switching action timing matrix is ​​then converted into a cycle count based on the FPGA master clock. The row index of the switching action timing matrix corresponds to the level level, the odd-numbered columns store the turn-on time parameters of the corresponding switching devices at the corresponding level level, and the even-numbered columns store the turn-off time parameters of the corresponding switching devices.

[0009] The FPGA generates corresponding drive pulse signals based on the timing data to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform.

[0010] Optionally, dividing the multi-level discrete waveform into several consecutive sub-waveforms according to polarity includes:

[0011] A zero-crossing detection algorithm is used to identify all zero-crossing points in the multi-level discrete waveform that intersect with the zero-level axis.

[0012] Using the zero-crossing point as the dividing boundary, the multi-level discrete waveform is divided into multiple continuous sub-waveform segments; each sub-waveform segment is located between two adjacent zero-crossing points, and its voltage value maintains a single polarity.

[0013] Optionally, it also includes: distributing and storing the timing parameters of each switching device.

[0014] Optionally, the timing parameters of each switching device are stored in a distributed manner, including:

[0015] The total action sequence is converted into a dynamic data frame format; wherein, the data frame adopts a hierarchical field architecture, including a switch address identifier field, an action round count field, an action time sequence field, and a frame verification field; the length of the action time sequence field contained in the data frame is related to the action round count;

[0016] Based on the total number of switching devices in the main circuit layer and the address encoding rules, the on-chip memory is divided into multiple independent storage blocks; each storage block stores the timing parameters of a switching device, which are obtained by decoding the data frame; the capacity of each storage block is configured according to the maximum number of operation cycles of the stored switching device.

[0017] Optionally, upon receiving a trigger signal, all memory blocks of the on-chip memory are accessed in parallel via multiple independent address lines and data lines to directly read the timing parameters stored therein;

[0018] Based on the read timing parameters, drive pulses for the corresponding switching devices are generated in real time.

[0019] Optionally, after generating a corresponding drive pulse signal based on the timing data to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform, the method further includes:

[0020] The output waveform corresponding to the drive pulse is compared with the multi-level discrete waveform to calculate the voltage deviation of each sampling point. If the deviation of all sampling points does not exceed the set threshold, the output waveform is determined to be normal and control continues according to the current output waveform. If the deviation of any sampling point exceeds the set threshold, the output waveform is determined to be faulty and fault location and fault handling are performed.

[0021] The fault location and fault handling include:

[0022] The target waveform is set as a positive polarity triangular wave. After modulation, the output waveform corresponding to the new driving pulse is acquired, and its waveform characteristics are compared with those of the positive polarity triangular wave to obtain the step characteristics of the fault.

[0023] Based on the stepped characteristics of the fault, locate the level of the fault and set the turn-on and turn-off times of the corresponding switching devices to zero;

[0024] Determine if the number of faulty step features exceeds a threshold. If so, stop power modulation. If not, remodulate the waveforms corresponding to other normal level levels and output them.

[0025] In a second aspect, the present invention also provides a power modulation system suitable for all-solid-state power supplies, for performing the power modulation method suitable for all-solid-state power supplies as described in any one of the first aspects, comprising: a control subsystem and a power subsystem;

[0026] The control subsystem is used to generate drive timing data for all switching devices based on the input target waveform modulation.

[0027] The power subsystem receives the timing data and converts it into real-time drive pulse signals for the corresponding switches via its internal FPGA, thereby controlling the switching devices in the all-solid-state power supply to work together and perform power modulation.

[0028] Optionally, the control subsystem includes a control core module, a waveform modulation module, a timing generation module, a human-machine interaction module, a communication transmission module, and a fault diagnosis module; the communication transmission module is connected to the power subsystem.

[0029] The control core module is used to issue control commands to control other modules and to receive and process feedback information;

[0030] The waveform modulation module is used to convert the target waveform into a multi-level discrete waveform using the NLM algorithm, and to divide it into several continuous sub-waveforms according to polarity.

[0031] The timing generation module is used to identify all level switching moments for each sub-waveform using an edge detection algorithm, obtain the time-electrical level correspondence, and generate the corresponding switching action timing matrix; it is also used to traverse the switching action timing matrix of the sub-waveform, extract the action sequences with the same level and polarity information, and convert the switching action timing parameters corresponding to the action sequences into FPGA-adapted clock crystal oscillator cycle counts.

[0032] The communication transmission module is used to transmit the switching action timing parameters using a dynamic data frame format;

[0033] The fault diagnosis module is used to monitor the characteristic parameters of the output waveform in real time to determine whether there is any abnormality or fault in the all-solid-state power supply.

[0034] The human-computer interaction module is used to configure the output parameters of the target waveform of the all-solid-state power supply and to display the fault detection results.

[0035] Optionally, the power subsystem includes a main circuit layer, a high-voltage side drive layer, an isolation layer, a low-voltage side drive layer, and a control circuit layer;

[0036] The control circuit layer includes a data access module and a signal generation module. The data access module is used to decode the received data frames and perform distributed storage of the timing parameters of each switching device. It also reads the stored timing parameters. The signal generation module is used to cyclically read the timing parameters from the data access module and generate corresponding drive pulse signals.

[0037] The low-voltage side driving layer is used to amplify the driving pulse through a power amplifier chip;

[0038] The isolation layer is used to achieve electrical isolation between control signals and power drive signals;

[0039] The high-voltage side driving layer is used to amplify the pulse signal power and generate a gate voltage signal that meets the driving requirements of each switching device in the main circuit layer.

[0040] The main circuit layer is used to control the orderly operation of each switching device with the gate voltage signal, so as to perform power modulation of the all-solid-state power supply according to the target waveform.

[0041] Compared with the prior art, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0042] 1. This invention provides a power modulation method suitable for all-solid-state power supplies. By dividing the target waveform into multiple sub-waveforms according to polarity, combining the time node of level transition with the number of electrical levels, switching timing parameters are generated for each sub-waveform. Then, a corresponding drive pulse signal is generated through an FPGA to achieve precise control of the switching devices in the all-solid-state power supply, completing the power modulation process. Furthermore, due to the adjustable nature of the number of electrical levels, flexible configuration and preview of waveform parameters are supported. For different complex waveforms, the sub-waveform segmentation and level level setting methods can be used to obtain switching timing parameters that conform to the waveform curve for precise control. It also has broad compatibility with various mainstream topologies such as Marx, LTD, and MMC, enabling this power modulation method to adapt to diverse application scenarios and a wide range of performance indicators, including AC and pulse modulation. This solves the problems of low switching timing control accuracy, lack of advanced modulation strategies, and difficulty in achieving complex waveform modulation and output in current all-solid-state power modulation methods. It adapts to the requirements of all-solid-state power supplies for precise power regulation and high real-time performance.

[0043] 2. This invention provides a power modulation method suitable for all-solid-state power supplies. Faced with timing data of a large number of switching devices, it realizes serial writing and parallel reading of timing parameters through distributed storage and parallel cyclic reading strategies. It can synchronously drive multiple switching actions, improve data throughput, reduce timing delay, and adapt to the high real-time requirements of all-solid-state power supplies for power regulation.

[0044] 3. This invention provides a power modulation method applicable to all-solid-state power supplies. It locates the fault level by comparing waveform step characteristics and triggers differentiated processing according to the fault scale. In the case of a single-level fault, a degraded operation mode is activated, and the output is maintained by using the remaining normal level. In the case of a multi-level fault, the system is immediately shut down for protection. This can avoid the problem of excessive shutdown for small faults, while ensuring system safety under serious faults and improving the reliability of the power supply.

[0045] 4. This invention provides a power modulation system suitable for all-solid-state power supplies. Through a layered hardware and software collaborative design architecture, it integrates partitioned computing, timing matrix, and distributed control strategies to achieve precise control of the timing of a large number of semiconductor switches. This not only effectively solves the output waveform distortion problem caused by poor synchronization of multiple switches in traditional solutions, but also supports the accurate synthesis and high-fidelity output of complex waveforms, thus providing key technical support for high-precision modulation of system-level power. Attached Figure Description

[0046] Figure 1 This is a complete power modulation output logic flowchart of a power modulation method applicable to all-solid-state power supplies, provided as an embodiment of the present invention.

[0047] Figure 2This is a schematic diagram illustrating the mapping of timing parameters to a matrix for a power modulation method applicable to all-solid-state power supplies, provided in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram illustrating the row and column correspondence and mapping logic of timing parameters in a matrix, as provided in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram illustrating the data frame format definition of a communication protocol module for a power modulation method applicable to all-solid-state power supplies, as provided in an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of a distributed storage and parallel cyclic reading mechanism for a power modulation method applicable to all-solid-state power supplies, provided in an embodiment of the present invention.

[0051] Figure 6 This is a schematic diagram of the control subsystem in a power modulation system suitable for all-solid-state power supplies, provided as an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of a five-layer hierarchical structure of a power subsystem in a power modulation system suitable for all-solid-state power supplies, provided as an embodiment of the present invention.

[0053] Figure 8 This is a schematic diagram of a compact structure of a power subsystem in a power modulation system suitable for all-solid-state power supplies, using Marx as an example, provided as an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0055] The following description, in conjunction with a preferred embodiment, illustrates the content involved in the above embodiments.

[0056] Example 1

[0057] like Figure 1 As shown, the present invention provides a power modulation method applicable to all-solid-state power supplies, comprising:

[0058] S1. The target waveform is converted into a multi-level discrete waveform using the NLM algorithm, and the multi-level discrete waveform is divided into several continuous sub-waveforms according to polarity; wherein, the number of levels is adjustable;

[0059] S2. For each sub-waveform, all level switching moments are identified using an edge detection algorithm to obtain the time-level correspondence and generate the corresponding switching action timing matrix; the switching action timing matrix is ​​converted into a cycle count based on the FPGA master clock; wherein, the row index of the switching action timing matrix corresponds to the level level, the odd-numbered columns store the turn-on time parameters of the corresponding switching device at the corresponding level level, and the even-numbered columns store the turn-off time parameters of the corresponding switching device;

[0060] S3. Generate a corresponding drive pulse signal based on the timing data to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform.

[0061] To address the aforementioned issues, this invention proposes a power modulation method and system applicable to all-solid-state power supplies. This solution achieves collaborative innovation at both the hardware topology and software algorithm levels. By constructing highly modular and digital power units and drive systems, and combining complex waveform intelligent modulation algorithms with distributed data control strategies, it effectively solves a series of technical problems such as precise synchronization of multiple switching devices, waveform quality optimization, and system fault diagnosis, providing a feasible technical path for the development of high-performance all-solid-state power supplies.

[0062] At the software algorithm level, the control subsystem generates the driving timing data for all switching devices; at the hardware topology level, the power subsystem controls the switching devices in the all-solid-state power supply to work together and perform power modulation.

[0063] The operating characteristics of all-solid-state power supplies dictate that the hardware can only output a limited number of discrete levels. Therefore, the target waveform needs to be converted into a multi-level discrete waveform with adjustable level levels using the NLM algorithm. Furthermore, the switching frequency of hardware switching devices (such as IGBTs and MOSFETs) has an upper limit, and the time interval between adjacent level transitions cannot be less than the minimum switching period, imposing rigid constraints on the discrete waveform. Therefore, these constraints must be incorporated into the discretization process of the target waveform; otherwise, excessively rapid switching may lead to hardware failure or abnormal output. After generating the multi-level discrete waveform, the level sequence of the discrete waveform needs to be verified. If the time interval between two consecutive level transitions of the same level is less than the minimum switching period, the level duration is automatically extended to meet the hardware operating requirements. The corrected multi-level waveform data serves as the basis for subsequent segmentation into multiple sub-waveforms according to polarity.

[0064] Using zero-crossing points as boundaries, the complete multi-level discrete waveform is divided into several continuous sub-waveforms with different polarities. Specifically, a zero-crossing detection algorithm is used to identify all zero-crossing points in the multi-level discrete waveform that intersect with the zero-level axis; using the zero-crossing points as dividing boundaries, the multi-level discrete waveform is divided into multiple continuous sub-waveform segments; each sub-waveform segment is located between two adjacent zero-crossing points, and its voltage value maintains a single polarity.

[0065] For each sub-waveform, extract all level switching moments. For example, the sub-waveform starts from V1=2U. o Switch to V2=3U o At time t=600ns, the third-level switch needs to operate. Using this method, the multi-level waveform is decomposed to obtain the time-level correspondence, clarifying the level number corresponding to each time interval. Based on this, a switch action matrix is ​​further generated. The rows of the matrix correspond one-to-one with the level number. Odd-numbered columns define the turn-on time of the corresponding level, and even-numbered columns define the turn-off time. For example, if the first column of the second row is 120 and the second column is 250, it means the second-level switch needs to be turned on at 120ns and turned off at 250ns. Furthermore, two consecutive odd-numbered columns and even-numbered columns in the same row form a complete "turn-on-off" action pair. The mapping method from timing parameters to the matrix is ​​as follows... Figure 2 As shown. To illustrate the method of generating the time series matrix more specifically, a bipolar waveform is used as an example. Figure 3 The diagram shows the complete process of the bipolar waveform from its original form, through feature point identification and level switching extraction, to finally being mapped into a positive polarity timing matrix and a negative polarity timing matrix. It intuitively reveals the row and column correspondence of timing parameters in the matrix and the mapping logic.

[0066] Before transmitting the switching action matrix timings corresponding to each sub-waveform, it is necessary to traverse the switching action timing matrices of the sub-waveforms and extract the action sequences (a row of the positive / negative polarity timing matrix) that have the same level and polarity information. This action sequence uniquely corresponds to the full-cycle action logic of a specific switching device in the main circuit layer. To ensure that the controller can accurately identify and execute the timing parameters, the timing parameters of all switching actions are converted into the crystal oscillator cycle number based on the FPGA master clock. These parameters are then encoded through the communication transmission module and sent to the data access module for the controller to call and execute. After obtaining this timing data, the controller (FPGA) generates corresponding drive pulse signals to control the switching devices in the all-solid-state power supply for power modulation.

[0067] Specifically, the timing parameters for each switching device are stored in a distributed manner.

[0068] The total action sequence is converted into a dynamic data frame format; wherein, the data frame adopts a hierarchical field architecture, including a switch address identifier field, an action round count field, an action time sequence field, and a frame verification field; the length of the action time sequence field contained in the data frame is related to the action round count;

[0069] Based on the total number of switching devices in the main circuit layer and the address encoding rules, the on-chip memory is divided into multiple independent storage blocks; each storage block stores the timing parameters of a switching device, which are obtained by decoding the data frame; the capacity of each storage block is configured according to the maximum number of operation cycles of the stored switching device.

[0070] Meanwhile, when the controller obtains the switching timing parameters from the on-chip memory, it includes: upon receiving a trigger signal, accessing all memory blocks of the on-chip memory in parallel through multiple independent address lines and data lines, and directly reading the timing parameters stored therein; and generating the corresponding drive pulse for the switching device in real time based on the read timing parameters.

[0071] During data storage, the received data frames are first decoded to extract the action timing parameters from the switch action matrix, and the timing information of each switch is serially written into the corresponding storage block. Upon receiving a trigger signal, a multi-port parallel read logic is initiated, simultaneously accessing all storage blocks through multiple independent address and data lines.

[0072] The data frame adopts a hierarchical field architecture, containing four core fields: switch address identifier, action round count, action time sequence, and frame verification. Figure 4As shown. The switch address identifier field occupies 1 byte (8 bits) and uses binary encoding. The high 7 bits identify the level to which the switch belongs, and the low 1 bit identifies the output polarity information of that level. This field uniquely identifies the corresponding switch device in the main circuit layer. The action round count field occupies 1 byte (8 bits) and stores the number of complete "on-off" action pairs contained in this frame of data. It directly maps to the effective data length of the action time sequence field, providing a clear index for data parsing for the data access module. The action time sequence field is a variable-length field, and its length is dynamically adjusted according to the action round count. Each "on-off" action pair corresponds to 8 bytes, with the on-time and off-time each occupying 4 bytes. The crystal oscillator cycle number is stored using a 32-bit unsigned integer. For example, when the action round count is 3, the field length is 24 bytes, storing 3 sets of timing data: "on time 1 - off time 1 - on time 2 - off time 2 - on time 3 - off time 3", thus completely defining the timing sequence of all actions of the corresponding switch within the waveform period. The frame check field occupies 1 byte (8 bits) and uses the CRC16 cyclic redundancy check algorithm to generate a check value. The receiving end compares the recalculated check value with this field to quickly detect bit errors caused by interference during data transmission, ensuring the integrity of the time-series data. The dynamic nature of the data frame is reflected in the strong binding relationship between the length of the action time sequence field and the action round count. When a switch has fewer action rounds within a cycle, the field length automatically shortens; when there are more action rounds, the field length increases linearly with the number of rounds. This avoids bandwidth idleness in scenarios with few action rounds for fixed-length frames, or fragmented transmission delays in scenarios with many action rounds, significantly improving the utilization efficiency of transmission resources. The fields and bit lengths of the data frame in this embodiment are only examples. Those skilled in the art can adaptively adjust each field and bit length according to the scale, accuracy, and bandwidth requirements of the actual system.

[0073] like Figure 5 As shown, taking the first discharge switch as an example, the system continuously reads two data points (r1 and r2) from its dedicated storage block. According to the definition of the switch timing matrix, a drive signal is sent at time point r1 to turn on the switch; a reverse drive signal is sent at time point r2 to turn off the switch. After the switch is turned off, a flag pulse is generated, which triggers the reading of the next set of data points and updates the values ​​of r1 and r2 accordingly. When the read value is empty, it indicates that the switch has completed all predetermined actions, and its cyclic data loading process terminates. This design can read the timing parameters of all switches in parallel, significantly improving data throughput and meeting the real-time requirements of simultaneous access to timing parameters for a large number of switching devices. The FPGA generates corresponding drive pulse signals based on the acquired timing parameters, controlling the switching devices in the main circuit layer to turn on / off according to the drive pulse timing sequence, so that the output is consistent with the high-voltage pulse power of the multi-level discrete waveform.

[0074] like Figure 1 As shown, optionally, after generating a corresponding drive pulse signal based on the timing data to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform, the method further includes:

[0075] The output waveform is compared with the multi-level discrete waveform to calculate the voltage deviation at each sampling point. If the deviation of all sampling points does not exceed the set threshold, the output waveform is determined to be normal and control continues according to the current output waveform. If the deviation of any sampling point exceeds the set threshold, the output waveform is determined to be faulty, and fault location and fault handling are performed.

[0076] The fault location and fault handling include:

[0077] The target waveform is set as a positive polarity triangular wave. After modulation, the output waveform corresponding to the new driving pulse is acquired, and its waveform characteristics are compared with those of the positive polarity triangular wave to obtain the step characteristics of the fault.

[0078] Based on the stepped characteristics of the fault, locate the level of the fault and set the turn-on and turn-off times of the corresponding switching devices to zero;

[0079] Determine if the number of faulty step features exceeds a threshold. If so, stop power modulation. If not, remodulate the waveforms corresponding to other normal level levels and output them.

[0080] To ensure a stable and distortion-free output waveform, fault monitoring and feedback are performed on the output waveform.

[0081] The system collects voltage waveform data from the main circuit output in real time, compares the collected actual voltage waveform with the multi-level discrete waveform, calculates the voltage deviation at each sampling point, and determines that the power supply is working normally and continues to operate with the current modulation parameters if the deviation at all sampling points does not exceed the set threshold. If the deviation at any sampling point exceeds the threshold, it determines that there is a fault and triggers the fault diagnosis process.

[0082] In fault diagnosis mode, the control power supply switches to a positive polarity triangular wave pulse output. The rising segment of this triangular wave has a progressively increasing stepped shape, with each step corresponding to a level in the main circuit layer. The actual output triangular waveform is acquired by an analog-to-digital converter and compared with the stepped characteristics of a standard triangular wave: if a level is working normally, its corresponding step will be clearly displayed; if a level is faulty, the corresponding step will be missing or distorted. By identifying abnormal steps, the faulty level can be accurately located. After locating the faulty level, the fault classification processing logic is activated. First, a fault level threshold is preset (the minimum number of levels to ensure normal power supply operation). If there are few faulty levels and the threshold is not exceeded, the on and off times of the faulty level in the original switching action matrix are first set to zero, causing the faulty level to stop outputting. Subsequently, based on the remaining normal level levels, the level value of each normal level is recalculated, and its switching action sequence is replanned accordingly. The switching action matrix is ​​updated, and by reducing the number of effective levels, the system operates at a lower level while maintaining the output waveform without distortion. If the fault level exceeds the threshold, a shutdown signal is immediately sent, stopping all switching device drive pulses. Simultaneously, fault information is fed back and displayed. This added fault monitoring and feedback mechanism enables degraded operation in fault conditions, ensuring that the system can maintain maximum normal output even when a partial unit fails, greatly improving power supply reliability.

[0083] This invention divides the target waveform into multiple sub-waveforms according to polarity, combines the time node of level transition with the number of electrical levels, and generates switching action timing parameters for each sub-waveform. Then, an FPGA generates corresponding drive pulse signals to achieve precise control of the switching devices in the all-solid-state power supply, completing the power modulation process. Due to the adjustable nature of the number of electrical levels, flexible configuration and preview of waveform parameters are supported. For different complex waveforms, the sub-waveform segmentation and level level setting methods can be used to obtain switching action timing parameters that conform to the waveform curve for precise control. This meets the requirements of all-solid-state power supplies for precise power regulation and high real-time performance.

[0084] Example 2

[0085] like Figure 6 and 7 As shown, the present invention also provides a power modulation system suitable for all-solid-state power supplies, for performing the power modulation method suitable for all-solid-state power supplies as described in any one of Embodiment 1, comprising: a control subsystem and a power subsystem;

[0086] The control subsystem is used to generate drive timing data for all switching devices based on the input target waveform modulation.

[0087] The power subsystem receives the timing data and converts it into real-time drive pulse signals for the corresponding switches via its internal FPGA, thereby controlling the switching devices in the all-solid-state power supply to work together and perform power modulation.

[0088] By co-designing hardware and software and using a layered architecture, complex power modulation tasks are decoupled, thereby achieving flexible control and highly reliable power output.

[0089] Furthermore, such as Figure 6 As shown, optionally, the control subsystem includes a control core module, a waveform modulation module, a timing generation module, a human-machine interaction module, a communication transmission module, and a fault diagnosis module; the communication transmission module is connected to the power subsystem.

[0090] The control core module is used to issue control commands to control other modules and to receive and process feedback information;

[0091] The waveform modulation module is used to convert the target waveform into a multi-level discrete waveform using the NLM algorithm, and to divide it into several continuous sub-waveforms according to polarity.

[0092] The timing generation module is used to identify all level switching moments for each sub-waveform using an edge detection algorithm, obtain the time-electrical level correspondence, and generate the corresponding switching action timing matrix; it is also used to traverse the switching action timing matrix of the sub-waveform, extract the action sequences with the same level and polarity information, and convert the switching action timing parameters corresponding to the action sequences into FPGA-adapted clock crystal oscillator cycle counts.

[0093] The communication transmission module is used to transmit the switching action timing parameters using a dynamic data frame format;

[0094] The fault diagnosis module is used to monitor the characteristic parameters of the output waveform in real time to determine whether there is any abnormality or fault in the all-solid-state power supply.

[0095] The human-computer interaction module is used to configure the output parameters of the target waveform of the all-solid-state power supply and to display the fault detection results.

[0096] Specifically, the human-machine interface module receives the target waveform parameters and transmits them to the control core module; the control core module then calls the waveform modulation module. The multi-level waveform data is transmitted from the control core module to the timing generation module.

[0097] Specifically, the human-machine interface module provides an intuitive parameter setting interface, allowing configuration of power supply output parameters, including waveform type, voltage amplitude, operating frequency, and number of level levels. Simultaneously, the human-machine interface module incorporates parameter verification logic, pre-storing parameter thresholds permitted by the main circuit layer hardware, including the maximum withstand voltage of switching devices, maximum switching frequency, minimum operating time, and upper limit of level levels. It automatically compares the parameters to be set with these thresholds to prevent exceeding the hardware's permissible range, ensuring that the expected waveform can be output through the hardware circuit without distortion. Based on the verified parameters, the waveform modulation module's algorithm is invoked to generate and visualize the expected multi-level waveform. Simultaneously, it continuously collects and displays key operating status information of the power supply. When the fault diagnosis module detects an anomaly, it displays fault alarm information and the location of the fault.

[0098] Specifically, the timing generation module achieves precise mapping from multi-level waveforms to specific switching action time sequences. Employing a partitioned computation and timing matrix strategy, for the input multi-level target waveform, the timing generation module first automatically extracts zero-crossing points (i.e., the intersection of the waveform and the zero-level axis) from the waveform using a preset feature point recognition algorithm. Using these feature points as boundaries, the complete multi-level waveform is divided into several continuous sub-waveforms. Each sub-waveform corresponds to the operation range of the switching device in the main circuit layer with a specific output polarity, and the polarity of the switching device and the sub-waveform is strictly matched within this range. For each sub-waveform, its level transition time node is identified. After identification, a corresponding switching action timing matrix is ​​generated based on all time nodes according to positive and negative polarities. The row index of the matrix corresponds one-to-one with the level level of the multi-level waveform. The odd-numbered columns of the matrix store the turn-on time parameters of the corresponding level device, and the even-numbered columns store the turn-off time parameters of the corresponding switching device. Furthermore, two consecutive odd-numbered columns and an even-numbered column in the same row constitute a complete "turn-on-off" action pair. When the switching action matrix corresponding to each sub-waveform is sent by the communication transmission module, the timing generation module traverses the switching action matrix of all sub-waveforms and extracts the action sequence (a row of the positive / negative polarity timing matrix) that has the same level and polarity information. This total action sequence uniquely corresponds to the full-cycle action logic of a specific switching device in the main circuit layer. Subsequently, the switching action timing data corresponding to the total action sequence is converted into an FPGA-adapted clock crystal oscillator cycle count.

[0099] Specifically, the communication transmission module uses a dynamic data frame format to achieve efficient transmission of switch action timing data. The data frame adopts a hierarchical field architecture, and the dynamism of the data frame is reflected in the strong binding relationship between the length of the action time sequence field and the action round count. When a switch has fewer action rounds within a cycle, the field length is automatically shortened; when there are more action rounds, the field length increases linearly with the number of rounds. This avoids bandwidth idleness of fixed-length frames in scenarios with fewer action rounds, or fragmented transmission delay in scenarios with more action rounds, and significantly improves the utilization efficiency of transmission resources.

[0100] Specifically, the fault diagnosis module locates faults through waveform feature comparison and uses hierarchical logic to handle faults. The module compares the actual output voltage waveform fed back from the control circuit layer with a preset target waveform, calculates the voltage deviation at each sampling point, and determines that the power supply is working normally and continues to operate with the current modulation parameters if the deviation at all sampling points does not exceed a set threshold. If any sampling point deviation exceeds the threshold, a fault is detected, triggering the fault diagnosis process. A standard triangular wave is output when fault diagnosis is triggered. The triangular wave is chosen because each level corresponds to a clear step transition; for example, the nth level corresponds to an amplitude of n*U0 (U0 is the unit level reference value). The control circuit layer collects the triangular wave feedback signal output from the main circuit layer in real time, filters it, and transmits it to the fault diagnosis module. The module extracts the step transition time and the amplitude before and after the transition from the feedback waveform to form an actual step feature set. This is compared with the original standard triangular wave theoretical step feature set. If a fault occurs at a certain level, the corresponding actual step will exhibit abnormal characteristics, such as complete absence, a transition time deviation exceeding the normal range, or oscillating distortion at the step edge, thus determining the fault level. The fault diagnosis module has built-in fault classification processing logic. First, it presets a fault level threshold (the minimum level to ensure normal power supply operation). When there are few fault levels and the threshold is not exceeded, the control core module triggers a downgrade operation mode, stops the fault level output, and calls the waveform modulation module and timing generation module to re-modulate and calculate the timing based on the remaining normal levels. When the fault level exceeds the threshold, a shutdown signal is immediately sent to the control circuit layer to stop all switching device drive pulses. At the same time, fault information is sent to the human-machine interaction module to prompt the specific fault level information, which facilitates subsequent maintenance.

[0101] At the hardware level, the power subsystem adopts a five-layer hierarchical design, including a control circuit layer, a low-voltage side drive layer, an isolation layer, a high-voltage side drive layer, and a main circuit layer, such as... Figure 7 As shown. The functions of each layer are as follows:

[0102] The control circuit layer serves as the core of the power supply system's control. It includes a data access module and a signal generation module. The data access module decodes the received data frames and performs distributed storage of the timing parameters of each switching device's operation obtained from the decoding. It also reads the stored timing parameters. The signal generation module cyclically reads the timing parameters from the data access module and generates corresponding drive pulse signals.

[0103] The data access module adopts a distributed control strategy and storage architecture design, such as Figure 5 As shown, a block-based strategy is adopted for the on-chip memory. Based on the total number of switching devices in the main circuit layer and the address encoding rules, the memory is divided into multiple independent storage blocks, each uniquely corresponding to one switching device. The capacity of each storage block is configured according to the maximum number of operation rounds of the switching device, and a fixed mapping is formed between the block address and the level address and polarity information of the switching device, ensuring that the timing data of a single switching device is only written to its dedicated block, avoiding storage conflicts. The module adopts a serial storage and parallel cyclic reading mechanism. Upon receiving a trigger command, it starts multi-port parallel reading logic, simultaneously accessing all storage blocks through multiple independent address lines and data lines, synchronously reading the timing parameters of the current address unit of each block according to a preset cycle. This mechanism overcomes the single-port access bottleneck of centralized storage, and the data throughput increases linearly with the number of switching devices, meeting the real-time requirements of simultaneous access to timing parameters by a large number of switching devices.

[0104] By integrating the FPGA to receive and decode command data from the communication transmission module and storing it in the data access module, the signal generation module cyclically reads timing parameters from the data access module and generates nanosecond-precision switching drive pulses based on an internal high-frequency clock, which are then output to the low-voltage side drive layer. The control circuit layer also integrates an analog-to-digital converter for real-time acquisition of the output voltage waveform of the main circuit layer, achieving closed-loop feedback.

[0105] The low-voltage side drive layer, isolation layer, and high-voltage side drive layer work together to block interference from the high-voltage side to the low-voltage control system. Among various isolation schemes, this embodiment prefers a magnetic isolation scheme to achieve better signal integrity and anti-interference capability. For the magnetic isolation drive method adopted in this embodiment, the low-voltage side drive layer receives the low-voltage drive pulses generated by the control circuit layer and uses a dedicated drive chip to amplify the signal to provide sufficient drive capability, ensuring that the drive pulses have extremely short rise / fall times, low distortion, and strong drive capability, meeting the nanosecond-level high-speed switching requirements of high-voltage switching devices. The isolation layer consists of a high-performance magnetic core and a high-voltage line passing through the magnetic core, transmitting energy and signals through magnetic field coupling, achieving stable and reliable electrical isolation between the low-voltage control side and the high-voltage power side. The high-voltage side drive layer receives the signal output from the secondary winding of the magnetic core, amplifies it through a drive amplifier circuit, and generates a gate drive voltage that meets the requirements of the high-voltage switching devices.

[0106] The main circuit layer, as the power output unit, can adopt mainstream topologies such as Marx, LTD, and MMC. At the hardware integration level, the main circuit layer needs to integrate a large number of energy storage capacitors and high-reliability power switching devices. The energy storage capacitors, as the core energy storage carrier, must possess high withstand voltage, high energy density, and long cycle life to meet the energy requirements of a single pulse output or support the energy supply for continuous AC / DC output. The power switching devices must have nanosecond-level fast switching capability, high current withstand limit, and low conduction loss. When a power output command is received, the power switching devices coordinate their actions according to preset timing control logic to achieve precise power modulation, ultimately enabling the main circuit layer to generate a multi-level high-voltage waveform that meets the requirements.

[0107] It should be understood that although this embodiment describes and prefers a magnetic isolation scheme, other isolation technologies such as optical isolation (e.g., using optocouplers to achieve electro-optical-electrical conversion) are also applicable to this hardware framework. To further illustrate the hierarchical design concept of the power subsystem, such as... Figure 8 As shown, a compact structure diagram is given using the Marx circuit topology as an example.

[0108] This invention employs a layered hardware and software collaborative design architecture, integrating partitioned computing, timing matrices, and distributed control strategies to achieve precise control over the timing of a large number of semiconductor switches. This not only effectively solves the output waveform distortion problem caused by poor synchronization of multiple switches in traditional solutions, but also supports the accurate synthesis and high-fidelity output of complex waveforms, thus providing crucial technical support for high-precision modulation of system-level power.

[0109] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power modulation method applicable to all-solid-state power supplies, characterized in that, include: The NLM algorithm is used to convert the target waveform into a multi-level discrete waveform, and the multi-level discrete waveform is divided into several continuous sub-waveforms according to polarity; wherein, the number of levels is adjustable; For each sub-waveform, all level switching moments are identified using an edge detection algorithm to obtain the time-level correspondence and generate the corresponding switching action timing matrix. The switching action timing matrix is ​​then converted into a cycle count based on the FPGA master clock. The row index of the switching action timing matrix corresponds to the level level, the odd-numbered columns store the turn-on time parameters of the corresponding switching devices at the corresponding level level, and the even-numbered columns store the turn-off time parameters of the corresponding switching devices. Based on the timing data of the switching action timing matrix, a corresponding drive pulse signal is generated to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform.

2. The method as described in claim 1, characterized in that, The step of dividing the multi-level discrete waveform into several continuous sub-waveforms according to polarity includes: A zero-crossing detection algorithm is used to identify all zero-crossing points in the multi-level discrete waveform that intersect with the zero-level axis. Using the zero-crossing point as the dividing boundary, the multi-level discrete waveform is divided into multiple continuous sub-waveform segments; each sub-waveform segment is located between two adjacent zero-crossing points, and its voltage value maintains a single polarity.

3. The method as described in claim 1, characterized in that, Also includes: The timing parameters of each switching device are stored in a distributed manner.

4. The method as described in claim 3, characterized in that, The timing parameters of each switching device are distributed and stored, including: The timing parameters of the actions corresponding to each switching device are converted into a dynamic data frame format; wherein, the data frame adopts a hierarchical field architecture, including a switch address identifier field, an action round count field, an action time sequence field, and a frame check field; the length of the action time sequence field contained in the data frame is related to the action round count. Based on the total number of switching devices in the main circuit layer and the address encoding rules, the on-chip memory is divided into multiple independent storage blocks; each storage block stores the timing parameters of a switching device, which are obtained by decoding the data frame; the capacity of each storage block is configured according to the maximum number of operation cycles of the stored switching device.

5. The method as described in claim 4, characterized in that, Upon receiving a trigger signal, all memory blocks in the on-chip memory are accessed in parallel via multiple independent address lines and data lines to directly read the timing parameters stored therein; Based on the read timing parameters, drive pulses for the corresponding switching devices are generated in real time.

6. The method as described in claim 1, characterized in that, After generating a corresponding drive pulse signal based on the timing data to control the switching devices in the all-solid-state power supply, perform power modulation, and output the target waveform, the method further includes: The output waveform corresponding to the drive pulse is compared with the multi-level discrete waveform to calculate the voltage deviation of each sampling point. If the deviation of all sampling points does not exceed the set threshold, the output waveform is determined to be normal and control continues according to the current output waveform. If the deviation of any sampling point exceeds the set threshold, the output waveform is determined to be faulty and fault location and fault handling are performed. The fault location and fault handling include: The target waveform is set as a positive polarity triangular wave. After modulation, the output waveform corresponding to the new driving pulse is acquired, and its waveform characteristics are compared with those of the positive polarity triangular wave to obtain the step characteristics of the fault. Based on the stepped characteristics of the fault, locate the level of the fault and set the turn-on and turn-off times of the corresponding switching devices to zero; Determine if the number of faulty step features exceeds a threshold. If so, stop power modulation. If not, remodulate the waveforms corresponding to other normal level levels and output them.

7. A power modulation system suitable for all-solid-state power supplies, characterized in that, The method for performing the power modulation method applicable to all-solid-state power supplies as described in any one of claims 1-6 includes: a control subsystem and a power subsystem; The control subsystem is used to generate drive timing data for all switching devices based on the input target waveform modulation. The power subsystem receives the timing data and converts it into real-time drive pulse signals for the corresponding switches via its internal FPGA, thereby controlling the switching devices in the all-solid-state power supply to work together and perform power modulation.

8. The system as described in claim 7, characterized in that, The control subsystem includes a control core module, a waveform modulation module, a timing generation module, a human-machine interaction module, a communication transmission module, and a fault diagnosis module; the communication transmission module is connected to the power subsystem. The control core module is used to issue control commands to control other modules and to receive and process feedback information; The waveform modulation module is used to convert the target waveform into a multi-level discrete waveform using the NLM algorithm, and to divide it into several continuous sub-waveforms according to polarity. The timing generation module is used to identify all level switching moments for each sub-waveform using an edge detection algorithm, obtain the time-electrical level correspondence, and generate the corresponding switching action timing matrix; it is also used to traverse the switching action timing matrix of the sub-waveform, extract the action sequences with the same level and polarity information, and convert the switching action timing parameters corresponding to the action sequences into FPGA-adapted clock crystal oscillator cycle counts. The communication transmission module is used to transmit the switching action timing parameters using a dynamic data frame format; The fault diagnosis module is used to monitor the characteristic parameters of the output waveform in real time to determine whether there is any abnormality or fault in the all-solid-state power supply. The human-computer interaction module is used to configure the output parameters of the target waveform of the all-solid-state power supply and to display the fault detection results.

9. The system as described in claim 7, characterized in that, The power subsystem includes a main circuit layer, a high-voltage side drive layer, an isolation layer, a low-voltage side drive layer, and a control circuit layer. The control circuit layer includes a data access module and a signal generation module. The data access module is used to decode the received data frames and to distribute and store the timing parameters of each switching device. The signal generation module is used to cyclically read the timing parameters from the data access module and generate corresponding drive pulse signals. The low-voltage side driving layer is used to amplify the driving pulse through a power amplifier chip; The isolation layer is used to achieve electrical isolation between control signals and power drive signals; The high-voltage side driving layer is used to amplify the pulse signal power and generate a gate voltage signal that meets the driving requirements of each switching device in the main circuit layer. The main circuit layer is used to control the orderly operation of each switching device with the gate voltage signal, so as to perform power modulation of the all-solid-state power supply according to the target waveform.

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