Arm server high-temperature heat power consumption processing method and device

Abstract

The invention discloses an arm server high-temperature thermal power consumption processing method and device, and the method comprises the steps: 1, monitoring the temperature of each processing unit in a server CPU in real time, carrying out the statistics of the number of times of high-power-consumption events triggered by the processing unit in unit time so as to obtain the number of high-power-consumption instructions, and executing a step 2 when the processing unit is close to a high-temperature state; 2, judging an interval in which the number of the high-power-consumption instructions is located, and pausing all instruction distribution in the processing unit for an execution intermittent period when the number of the high-power-consumption instructions is within an interval which does not exceed a preset range, and when the number of the high-power-consumption instructions is within an interval exceeding a preset range, inhibiting the high-power-consumption instructions in the processing unit at a preset inhibition degree greater than 0. Compared with the prior art, the method has the advantages that the temperature rise of PE close to high temperature in the CPU is quickly inhibited from the micro-framework level, high-temperature protection is performed from the interior of the processor, data loss is prevented, and local PE temperature rise in the CPU is quickly inhibited.

Description

Technical Field

[0001] This invention relates to the field of Arm servers, and more particularly to a method and apparatus for handling high-temperature heat dissipation in Arm servers. Background Technology

[0002] In ARM servers, overall thermal design is crucial for performance. Traditional methods for transitioning the internal temperature from room temperature to high temperatures include various approaches, such as directly turning on the fans or increasing their speed, and liquid cooling, which are more physical methods. Some software systems implement dynamic frequency and voltage regulation. As the temperature continues to rise to its extreme limit, the software will shut down the system. However, this temperature management method has the following problems: 1. The handling of the temperature transition from high to extreme temperatures relies heavily on physical and software methods, limiting the controllable dimensions. 2. The temperature rise from high to extreme temperatures is generally rapid, and poor control can lead to data loss. 3. There is a lack of protection against localized high temperatures within the processor.

[0003] Therefore, there is an urgent need for a temperature control method that can solve the above problems. Summary of the Invention

[0004] The purpose of this invention is to provide a method and apparatus for handling high-temperature thermal power consumption in ARM servers, which can quickly suppress the temperature rise of the processing unit in the CPU at the microarchitecture level, provide high-temperature protection from inside the processor, prevent data loss, and quickly suppress CPU temperature rise.

[0005] To achieve the above objectives, the present invention provides a method for handling high-temperature thermal power consumption in an ARM server, comprising: Step 1, real-time monitoring of the temperature of each processing unit in the server CPU, counting the number of high-power events triggered by the processing unit per unit time to obtain the number of high-power instructions, and executing Step 2 when the processing unit approaches a high-temperature state; Step 2, determining the range in which the number of high-power instructions is located, and when the number of high-power instructions is within a range not exceeding a preset range, pausing the distribution of all instructions in the processing unit for one execution interval cycle, and when the number of high-power instructions is within a range exceeding the preset range, suppressing the high-power instructions in the processing unit with a preset suppression level greater than 0.

[0006] Preferably, before step 1, a correspondence is established between the suppression level of high-power instructions and N levels of power buffer levels, where N is greater than or equal to 2, and the suppression levels of the N power buffer levels increase sequentially from smallest to largest. In step 2, when the processing unit approaches a high-temperature state, the power buffer level corresponding to the current number of high-power instructions is obtained according to the correspondence and executed. The power buffer level corresponding to the range where the number of high-power instructions exceeds a preset range has a suppression level greater than 0. This invention configures the corresponding power buffer level for the processing unit based on the number of high-power instructions executed, thereby maintaining the ARM server in a stable environment and keeping the overall power consumption curve of the ARM server at a stable level, without fluctuating wildly.

[0007] Specifically, the interval where the number of high-power instructions does not exceed a preset range corresponds to the power buffer level of level 0, and the suppression degree of the power buffer level of level 0 for high-power instructions is 0; in step 2, when the processing unit is close to a high temperature state, the power buffer level corresponding to the current number of high-power instructions is obtained according to the correspondence and executed. When the power buffer level is the power buffer level of level 0, the distribution of all instructions of the processing unit is paused for one execution interval cycle.

[0008] Specifically, before step 1, high-power instructions are set to multiple levels, and the correspondence between the number of high-power instructions of multiple levels running per unit time and N power buffer levels is set.

[0009] More specifically, before step 1, the high-power instructions are categorized into j levels based on type or power consumption, from smallest to largest, where j is greater than or equal to 2. Each level of high-power instructions corresponds to a preset number. The interval where the high-power instructions of level i exceed the corresponding preset number but the high-power instructions of levels i+1 to j do not exceed the corresponding preset number corresponds to the power buffer level of level i, where i = 1, 2, ..., j. The suppression degree of the power buffer levels from level 1 to level j increases sequentially from smallest to largest. This scheme sets a corresponding high-power instruction suppression program based on the power consumption or type of the high-power instructions, thereby adjusting the power suppression degree of the processing unit according to the actual situation, further increasing the power stability of the ARM server.

[0010] Preferably, before step 1, M suppression levels are assigned to the user according to their performance requirements or the configuration they purchased, where M is greater than or equal to 2. In step 2, the power buffer level corresponding to the number of high-power instructions is adjusted based on the user's suppression level to serve as the final power buffer level. This balances the relationship between user needs and the current number of instructions, ensuring the stability of the ARM server's power consumption curve while maximizing user satisfaction.

[0011] Preferably, the execution interval is 10-100 nanoseconds.

[0012] More preferably, in step 2, before pausing the distribution of all instructions of the current processing unit for one execution interval cycle, the execution interval cycle is adjusted according to the temperature of the processing unit; the higher the temperature of the processing unit, the longer the execution interval cycle, and the execution interval cycle is 10-100 nanoseconds.

[0013] Preferably, in step 1, the temperature of the server processing unit is monitored in real time. When the temperature of the processing unit approaches a high temperature, the number of high-power events triggered by the processing unit per unit time is counted to obtain the number of high-power instructions before step 2 is executed.

[0014] Preferably, step 2 is followed by step 3, which determines whether the temperature of the processing unit is high. If so, the frequency and / or supply voltage of the processing unit are reduced to suppress the temperature rise; otherwise, the process ends to suppress the temperature rise at the program decision level.

[0015] The present invention also provides a high-temperature thermal power consumption processing device for an ARM server, including an auxiliary counter, a temperature sensor, a memory, a processor, and one or more operation instructions stored in the memory. The auxiliary counter monitors the number of high-power instructions per unit time in real time, the temperature sensor monitors the temperature of each processing unit in the server CPU in real time, and the processor executes the operation instructions to implement the high-temperature thermal power consumption processing method for an ARM server as described above.

[0016] Compared with existing technologies, on the one hand, this invention rapidly suppresses the temperature rise of processing units in the CPU at the microarchitecture level, providing high-temperature protection from within the processor to prevent data loss. On the other hand, when the temperature of processing units in the CPU rises, this invention effectively suppresses the power consumption of processing units in the CPU from within the server by suppressing high-power instructions or suppressing intermittent cycles of all instructions, achieving temperature equalization from within the server. This allows for rapid suppression of temperature rise even when the number of CPU processing units increases. Attached Figure Description

[0017] Figure 1 This is a flowchart of the high-temperature thermal power consumption handling method for ARM servers in Embodiment 1 of the present invention.

[0018] Figure 2 This is a flowchart of the high-temperature thermal power consumption handling method for ARM servers in Embodiment 2 of the present invention.

[0019] Figure 3 This is a structural diagram of the high-temperature thermal power consumption processing device for ARM servers of the present invention. Detailed Implementation

[0020] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0021] Example 1: refer to Figure 1 The present invention discloses a method for handling high-temperature thermal power consumption of ARM server, including steps S1 to S6.

[0022] S1 monitors the current temperature of each processing unit in the server's CPU in real time. A processing unit (PE) is a specific core within the CPU. A CPU (AP, Application Processor) contains several processing units (PEs). The processing unit will be referred to as PE for short.

[0023] S2, determine if the temperature of PE is close to a high temperature. If so, proceed to step S3; otherwise, return.

[0024] Specifically, the comparison between PE and a preset temperature value determines that the temperature of PE is close to a high temperature when the temperature of PE is greater than or equal to the first preset temperature value.

[0025] S3, count the number of high-power events triggered by the processing unit per unit time to obtain the number of high-power instructions.

[0026] This unit of time is a duration determined based on the main frequency. For example, a 3GHz CPU corresponds to a unit of time of 10ms. Specifically, the number of high-power instructions is obtained by reading the count from the auxiliary counter in the current AMU (Automatic Management Unit).

[0027] Specifically, when the temperature of the PE approaches a high temperature, the MPMM feature is enabled, and the gear counter starts to trigger counting for high power consumption. At the end of a unit time, the difference is calculated to obtain the number of high power consumption instructions remembered by the gear counter within that unit time.

[0028] High-power instructions include memory read / write, vector operations (NEON / SVE), floating-point operations, encryption / decryption, and memory system transactions.

[0029] The Maximum Power Mitigation Mechanism (MPMM) is used to limit the execution of high-power instructions. Enabling MPMM will set an appropriate power buffer level for the CPU's Processing Execution Environment (PE) at the microarchitecture level, suppressing all instructions that exceed the current power buffer level. This will suppress high-power instructions running on PEs that are close to high temperatures in the CPU, thus extending the execution time of such instructions.

[0030] S4. Determine whether the number of high-power instructions exceeds the preset range. If yes, proceed to step S5; otherwise, proceed to step S6.

[0031] S5, suppresses high-power instructions in the processing unit, such as common memory access, vector operations (NEON / SVE), floating-point operations, etc., with a preset suppression level greater than 0, thereby affecting PE activity.

[0032] The suppression level refers to the percentage reduction in the issue rate of high-power instructions, specifically by delaying the execution time of these instructions. This percentage is a reduction ratio, indicating the extent to which the issue rate of high-power instructions and memory system transactions is reduced when the maximum power mitigation mechanism is implemented. For example, reducing the number of these high-power instructions issued within an execution cycle by one percentage point.

[0033] The preset suppression level can be a fixed value or a set of values ​​determined based on the range of high-power instructions. If the preset suppression level is a set of values ​​determined based on the range of high-power instructions, then the corresponding suppression level is determined based on the number of high-power instructions, and then the high-power instructions in the processing unit are suppressed based on the determined suppression level.

[0034] Specifically, in step S4, the range of high-power command counts is determined. A range where the number of high-power commands exceeds a preset range is defined as the first range, and a range where the number of high-power commands does not exceed the preset range is defined as one or more ranges. Then, it is determined whether the range containing the high-power command count is the first range. If not, step S5 is executed; otherwise, step S6 is executed. Alternatively, in step S4, the range of high-power command counts is determined, and a range where the number of high-power commands exceeds a preset range is defined as the first range. A power buffer level corresponding to the range of high-power command counts is obtained. Then, it is determined whether this power buffer level corresponds to the first range. If not, step S5 is executed (using a power buffer level corresponding to a range of high-power command counts to suppress high-power commands in the processing unit); if so, step S6 is executed. Each power buffer level corresponds to a preset suppression level.

[0035] S6 pauses the distribution of all instructions in the PE for one execution interval cycle.

[0036] Specifically, disabling the MPMM feature pauses all instruction dispatches for the PE for one execution interval cycle.

[0037] Specifically, the PE is intermittently enabled to pause the execution of all instructions distributed by the PE, which is currently operating at near-high temperatures, during intermittent periods. This limits instruction distribution and further affects the data throughput on the bus, achieving a frequency reduction effect. The execution intermittent period is 10-100 nanoseconds.

[0038] In step S6, an execution interval period (approximately 10-100 nanoseconds) is set based on the current PE temperature. Then, all instruction dispatching on the current PE is restricted, pausing it for one execution interval period. During this period, all instruction dispatching on the current PE is suspended. The higher the PE temperature, the longer the execution interval period. The relationship between PE temperature and execution interval period can be either stepwise or linear. This execution interval period is the DISPBLK (dispatch block, microarchitecture-level instruction dispatch restriction) execution interval period.

[0039] Alternatively, the ARM server high-temperature thermal power consumption handling method further includes step S7, which determines whether the temperature of the PE is high. If so, the frequency of the PE is reduced and / or the power supply voltage is reduced to suppress the temperature rise of the PE; otherwise, the process ends.

[0040] Specifically, after a delay of a certain time after step S5, step S7 is executed. Step S7 is executed after step S6. In step S7, it is determined whether the temperature of PE is greater than or equal to the second preset temperature, which is greater than the first preset temperature. If so, it is determined that the temperature is at a high temperature; otherwise, it is determined that the temperature is not at a high temperature.

[0041] Preferably, in step S2, when the PE is close to a high temperature state, the frequency of PE temperature monitoring is increased.

[0042] Example 2: S1 monitors the current temperature of each processing element (PE) in the server's CPU in real time.

[0043] S2, determine if the temperature of PE is close to a high temperature. If so, proceed to step S3; otherwise, return.

[0044] Specifically, the comparison between PE and a preset temperature value determines that the temperature of PE is close to a high temperature when the temperature of PE is greater than or equal to the first preset temperature value.

[0045] S3, count the number of high-power events triggered by the processing unit per unit time to obtain the number of high-power instructions.

[0046] Before step S1, a correspondence is established between the number of high-power commands and N power buffer levels. Each of the N power buffer levels corresponds to the degree of suppression of a high-power command, and the degree of suppression of the N power buffer levels increases sequentially from small to large, with N being greater than or equal to 2.

[0047] Among them, high-power instructions are set to multiple levels. The specific correspondence is: the number of high-power instructions of multiple levels running per unit time and the correspondence of N power buffer levels.

[0048] In this embodiment, the high-power instructions are divided into j levels according to their type or power consumption from smallest to largest, where j is greater than or equal to 2. Each level of high-power instructions corresponds to a preset number. The j auxiliary counters (level counters) in the AMU count the high-power instructions of level j respectively.

[0049] Specifically, when the PE temperature approaches a high temperature, the MPMM feature is enabled. J auxiliary counters begin triggering and counting events for high-power instructions of level j. At the end of a unit time, a difference calculation is performed to obtain the number of high-power instructions of level j recorded by the j level counters within that unit time. The system reads this number of high-power instructions and compares it with the preset number corresponding to high-power instructions of level j. If the number of any high-power instruction exceeds the corresponding preset number, the count corresponding to that level counter is marked, for example, as 1. The interval where the high-power instructions of level i exceed the corresponding preset number but the high-power instructions of levels i+1 to j do not exceed the corresponding preset number corresponds to the power buffer level of level i, i=1,2…j. The suppression degree of the power buffer levels from level 1 to level j increases sequentially from smallest to largest. The interval where the number of all j high-power instructions does not exceed the corresponding preset number (i.e., the interval where the number of high-power instructions does not exceed the preset range) corresponds to the 0th level of power buffer. The 0th level of power buffer has a suppression degree of 0 for high-power instructions. N=j+1.

[0050] Referring to Table 1 below, using j=3 as an example, the correspondence between the number of high-power instructions and the N-level power buffer level is illustrated, or in other words, the correspondence between the range of high-power instructions and the N-level power buffer level. In this embodiment, N=4.

[0051]

[0052] Table 1 - MPMM Performance Index In this system, the high-power command count obtained by the level counter technology is recorded as 1 when it exceeds the corresponding preset number and as 0 when it does not exceed the corresponding preset number. X can be either 0 or 1, thus setting 4 intervals for the number of high-power commands to correspond to 4 power buffer levels from the 0th to the 3rd: the 0th level power buffer level, the 1st level power buffer level, the 2nd level power buffer level, and the 3rd level power buffer level.

[0053] The power buffer levels are categorized into N levels based on their suppression severity: Level 0 (no suppression), Level 1 (low suppression), Level 2 (medium suppression), and Level 3 (high suppression). Level 1 (low suppression) specifically suppresses 20% of high-power commands attenuated; Level 2 (medium suppression) specifically suppresses 50% of currently running high-power commands attenuated; and Level 3 (high suppression) specifically suppresses 70% of currently running high-power commands attenuated. However, the specific suppression percentage for each power buffer level is not limited to the values ​​described above.

[0054] S4a: Based on the correspondence between the number of high-power commands and N power buffer levels (see the MPMM performance index table in Table 1 above), set the power buffer level corresponding to the current number of high-power commands and execute it. Specifically, set the power buffer level corresponding to the current number of high-power commands according to the MPMM performance index table in Table 1 and execute it.

[0055] Preferably, before step S2, M suppression levels are assigned to the user according to the user's performance requirements or the configuration purchased by the user, where M is greater than or equal to 2. In step S4a, based on the correspondence between the number of high-power commands and N power buffer levels, the power buffer level corresponding to the current number of high-power commands is obtained, and the power buffer level corresponding to the number of high-power commands is adjusted according to the user's suppression level to serve as the final power buffer level and executed.

[0056] For example, M=3, with suppression levels of high, medium, and low. If the current user (the user using this PE) has a suppression level of low, then the power buffer level corresponding to the number of high-power commands is increased by one level, which is used as the final power buffer level. If the user's suppression level is medium, then the power buffer level corresponding to the number of high-power commands is used as the final power buffer level. If the user's suppression level is high, then the power buffer level corresponding to the number of high-power commands is decreased by one level, which is used as the final power buffer level.

[0057] Currently, unlike this, M can also be equal to 2. In this case, the suppression level can be high, medium, or medium and low. Also unlike this, the suppression level M can be 3, 4, 5, etc., in which case the power buffer level is increased or decreased by a preset amount depending on the suppression level.

[0058] The specific implementation of this power buffer level is as follows: based on the suppression level corresponding to the set power buffer level, high-power instructions in the CPU are suppressed, such as common memory access, vector operations (NEON / SVE), floating-point operations, etc., thereby affecting CPU activity.

[0059] S5a, determine whether the power buffer level is level 0. If yes, proceed to step S6; otherwise, proceed to step S7.

[0060] You can either execute step S7 directly or wait and then execute step S7.

[0061] S6 pauses all instruction dispatching for the PE for one execution interval cycle. Specifically, disabling the MPMM feature pauses all instruction dispatching for the PE for one execution interval cycle.

[0062] Specifically, the PE is intermittently enabled to pause the execution of all instructions distributed by the PE, which is currently operating at near-high temperatures, during intermittent periods. This limits instruction distribution and further affects the data throughput on the bus, achieving a frequency reduction effect. The execution intermittent period is 10-100 nanoseconds.

[0063] In step S6, the execution interval period is adjusted according to the current PE temperature (each execution interval period is approximately 10-100 nanoseconds), and then all instruction distribution on the current PE is restricted, causing it to pause for one execution interval period. During this execution interval period, all instruction distribution on the current PE is suspended. The higher the PE temperature, the longer the execution interval period. The relationship between PE temperature and execution interval period can be either a stepwise or linear relationship. This execution interval period is the DISPBLK (dispatch block, microarchitecture-level instruction distribution restriction) execution interval period.

[0064] Alternatively, the high-temperature thermal power consumption handling method for ARM servers may further include step S7, which determines whether the temperature of the PE is high. If so, step S8 is executed: the frequency of the PE is reduced and / or the power supply voltage is reduced to suppress the temperature rise of the PE. Otherwise, the process ends.

[0065] Specifically, after a delay of a certain time after step S5a, step S7 is executed. Step S7 is executed after step S6. In step S7, it is determined whether the temperature of PE is greater than or equal to the second preset temperature, which is greater than the first preset temperature. If so, it is determined that the temperature is at a high temperature; otherwise, it is determined that the temperature is not at a high temperature.

[0066] Preferably, in step S2, when the PE is close to a high temperature state, the frequency of PE temperature monitoring is increased.

[0067] refer to Figure 3 The present invention also discloses a high-temperature thermal power consumption processing device for an ARM server, including an auxiliary counter 50, a temperature sensor 40, a memory 10, a processor 20, and one or more operation instructions 30 stored in the memory 10. The auxiliary counter monitors the number of high-power instructions per unit time in real time, the temperature sensor monitors the temperature of each PE in the CPU in real time, and the processor 20 executes the operation instructions 30 to implement the high-temperature thermal power consumption processing method for an ARM server as described above.

[0068] Compared with existing technologies, on the one hand, this invention rapidly suppresses the temperature rise of near-high-temperature PEs in the CPU at the microarchitecture level, providing high-temperature protection from within the processor to prevent data loss. On the other hand, this invention can specifically suppress high-power instructions from near-high-temperature PEs in the CPU from within the server, achieving temperature equalization from within the server, so that even when the number of PEs in the CPU increases, temperature rise can still be rapidly suppressed.

[0069] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A method for handling high-temperature thermal power consumption in an ARM server, characterized in that: The method comprises the following steps: Step 1, real-time monitoring the temperature of each processing unit in the server CPU, counting the number of high-power consumption events triggered by the processing unit in a unit time to obtain the number of high-power consumption instructions, and executing step 2 when the processing unit approaches a high-temperature state; Step 2, judging the interval in which the number of high-power consumption instructions is located, pausing the distribution of all instructions in the processing unit for an execution interval when the number of high-power consumption instructions is in an interval not exceeding a preset range, and inhibiting the high-power consumption instructions in the processing unit by a preset inhibition degree greater than 0 when the number of high-power consumption instructions is in an interval exceeding the preset range. 2.The arm server high temperature thermal power consumption processing method of claim 1, wherein: Before step 1, a corresponding relationship between the number of high-power consumption instructions and N power buffer gears is set, the N power buffer gears correspond to an inhibition degree of a high-power consumption instruction respectively, and the inhibition degrees of the N power buffer gears increase from small to large in turn, and N is greater than or equal to 2; In step 2, when the processing unit approaches a high-temperature state, the power buffer gear corresponding to the current number of high-power consumption instructions is obtained according to the corresponding relationship and executed, and the inhibition degree of the high-power consumption instruction in the power buffer gear corresponding to the interval in which the number of high-power consumption instructions exceeds the preset range is greater than 0. 3.The arm server high temperature thermal power consumption processing method of claim 2, wherein: The interval in which the number of high-power consumption instructions does not exceed the preset range corresponds to the 0th power buffer gear, and the inhibition degree of the high-power consumption instruction in the 0th power buffer gear is 0; In step 2, when the processing unit approaches a high-temperature state, the power buffer gear corresponding to the current number of high-power consumption instructions is obtained according to the corresponding relationship and executed, and all instructions in the current processing unit are paused for an execution interval when the power buffer gear is the 0th power buffer gear. 4.The arm server high temperature thermal power consumption processing method of claim 2, wherein: Before step 1, the high-power consumption instructions are set to multiple levels, and a corresponding relationship between the number of high-power consumption instructions of multiple levels running in a unit time and N power buffer gears is set. 5.The arm server high temperature thermal power consumption processing method of claim 4, wherein: Before step 1, the high-power consumption instructions are divided into j levels according to the type or power consumption from small to large, j is greater than or equal to 2, and each level of high-power consumption instructions corresponds to a preset number; The interval in which the high-power consumption instructions of the ith level exceed the corresponding preset number and the high-power consumption instructions of the (i+1)th level to the jth level do not exceed the corresponding preset number corresponds to the ith power buffer gear, i=1, 2…j, and the inhibition degrees of the power buffer gears of the first level to the jth level increase from small to large in turn. 6.The arm server high temperature thermal power consumption processing method of claim 5, wherein: Before step 1, M inhibition levels corresponding to the user's performance requirement or the configuration purchased by the user are also allocated to the user, M is greater than or equal to 2, and before the step 2 of obtaining the power buffer gear corresponding to the current number of high-power consumption instructions according to the corresponding relationship and executing, the power buffer gear is also adjusted according to the inhibition level corresponding to the user as the finally set power buffer gear.

7. The arm server high temperature thermal power handling method of claim 1, wherein: In step 1, the temperature of the server processing unit is monitored in real time, and step 2 is executed after the number of high-power consumption instructions is obtained by counting the number of high-power consumption events triggered by the processing unit in a unit time when the temperature of the processing unit approaches a high-temperature state. 8.The arm server high temperature thermal power consumption processing method of claim 1, wherein: In step 2, before pausing the execution of all instructions of the current processing unit for an execution pause period, the execution pause period is adjusted according to the temperature of the processing unit; the higher the temperature of the processing unit, the longer the execution pause period, and the execution pause period is 10-100 nanoseconds.

9. The arm server high temperature thermal power handling method of claim 1, wherein: Step 2 is followed by step 3, which determines whether the temperature of the processing unit is high; if so, the frequency and / or supply voltage of the processing unit are reduced to suppress the temperature rise; if not, the process ends.

10. An arm server high temperature thermal power handling apparatus, comprising: The auxiliary counter, temperature sensor, memory, processor, and one or more operation instructions stored in the memory are included, the auxiliary counter monitors the number of high-power consumption instructions per unit of time in real time, the temperature sensor monitors the temperature of each processing unit in the server CPU in real time, and the processor executes the operation instructions to implement the arm server high-temperature thermal power consumption processing method of any one of claims 1-9.

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