Preparation method of shallow trench isolation structure
By selectively depositing silicon nitride hard masks and silicon oxide dielectric layers, and utilizing the difference in adsorption activation energy to form a silicon oxide filling layer, the problems of voids and seams in shallow trench isolation structures are solved, thereby improving product yield.
Patent Information
- Application Number
- CN202411180985.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-03-06
AI Technical Summary
Existing technologies often produce holes and seams when fabricating shallow trench isolation structures with high aspect ratios, leading to isolation failure and even short circuits in devices.
By selectively depositing silicon nitride hard masks and silicon oxide dielectric layers, and utilizing the difference in adsorption activation energy between the precursors, a silicon oxide filling layer is formed to fill the pores. By combining selective deposition and etching processes, the removal of silicon nitride hard masks is ensured.
It effectively fills the pores in the silicon oxide dielectric layer, solves the isolation failure problem, and improves product yield.
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Figure CN121620181A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a method for preparing a shallow trench isolation structure. Background Technology
[0002] With the development of semiconductor technology, the feature size of integrated circuit devices is getting smaller and smaller. In order to fabricate high-density and high-performance semiconductor devices, and to ensure that different components operate independently without interfering with each other, the fabrication of isolation structures is crucial.
[0003] Currently, shallow trench isolation (STI) structures have excellent isolation performance and have gradually become one of the mainstream isolation structures for active regions of semiconductor devices.
[0004] Current shallow trench isolation fabrication typically employs silicon nitride as a hard mask to etch trenches onto the substrate, followed by the formation of silicon oxide to fill the trenches as the dielectric material. However, as semiconductor device dimensions shrink, trench aspect ratios increase. For nodes below 40nm, even with high aspect ratio processes (HARP) for trench filling, it is difficult to avoid the formation of voids and / or seams. Furthermore, in subsequent processes, such as planarization of the silicon oxide dielectric layer and removal of the silicon nitride hard mask, the voids and / or seams are easily magnified. Consequently, during the subsequent fabrication of conductive materials, such as polysilicon deposition, the voids and / or seams may also be filled with conductive material, leading to isolation failure of the shallow trench isolation structure and even short circuits in the device.
[0005] Therefore, it is necessary to provide a method for preparing a shallow trench isolation structure. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a shallow trench isolation structure, which solves the problem of holes and / or seams in the shallow trench isolation structure in the prior art.
[0007] To achieve the above and other related objectives, the present invention provides a method for preparing a shallow trench isolation structure, comprising the following steps:
[0008] Provide semiconductor substrates;
[0009] A patterned silicon nitride hard mask is formed on the surface of the semiconductor substrate, and the surface of the silicon nitride hard mask has amino groups.
[0010] Based on the silicon nitride hard mask, trenches are formed in the semiconductor substrate;
[0011] A silicon oxide dielectric layer is formed on the silicon nitride hard mask to fill the trench. The silicon oxide dielectric layer has pores and hydroxyl groups on its surface.
[0012] Remove part of the silicon oxide dielectric layer to expose the silicon nitride hard mask and the pores;
[0013] A precursor is provided and selectively deposited to form a silicon oxide filling layer on the silicon oxide dielectric layer to fill the pores, wherein the adsorption activation energy of the precursor on the silicon oxide dielectric layer is less than the adsorption activation energy on the silicon nitride hard mask.
[0014] Remove the silicon nitride hard mask.
[0015] Optionally, the precursor comprises diisopropylamine silane.
[0016] Optionally, the selective deposition temperature range includes below 100°C, and the reaction gas includes ozone.
[0017] Optionally, the depth of the pores to be filled is less than 4 nm.
[0018] Optionally, when the depth of the pores to be filled is greater than 4 nm, the method further includes the step of removing the silicon oxide filling layer on the silicon nitride hard mask by etching.
[0019] Optionally, after forming the silicon oxide dielectric layer filling the trench on the silicon nitride hard mask, the process includes a first annealing step, and between removing a portion of the silicon oxide dielectric layer and performing the selective atomic layer deposition, a second annealing step is also included.
[0020] Optionally, the selective deposition method includes selective atomic layer deposition; the method for forming the silicon oxide dielectric layer includes a high aspect ratio process.
[0021] Optionally, a pad oxide layer is also formed between the semiconductor substrate and the silicon nitride hard mask.
[0022] Optionally, before forming the silicon oxide dielectric layer, the method further includes the step of forming a trench oxide layer covering the bottom and sidewalls of the trench in the trench.
[0023] Optionally, the semiconductor substrate includes a single-crystal semiconductor substrate or a semiconductor compound substrate.
[0024] As described above, the method for preparing the shallow trench isolation structure of the present invention achieves selective deposition on the silicon nitride hard mask and the silicon oxide dielectric layer based on the difference in adsorption activation energy of the precursor on the silicon nitride hard mask and the silicon oxide dielectric layer, so as to form a silicon oxide filling layer that can fill the pores in the silicon oxide dielectric layer.
[0025] The method for preparing the shallow trench isolation structure of the present invention can effectively fill the pores in the silicon oxide dielectric layer, solve the isolation failure problem of the shallow trench isolation structure, and improve the product yield. Attached Figure Description
[0026] Figure 1 The diagram shows the fabrication process flow of the shallow trench isolation structure in an embodiment of the present invention.
[0027] Figure 2 The diagram shown is a schematic representation of the structure of a semiconductor substrate in an embodiment of the present invention.
[0028] Figure 3 The diagram shown is a schematic representation of the structure after forming a silicon nitride hard mask in an embodiment of the present invention.
[0029] Figure 4 The diagram shown is a schematic representation of the structure after the patterned photoresist is formed in an embodiment of the present invention.
[0030] Figure 5 The diagram shown is a schematic representation of the structure after the formation of the trench oxide layer in an embodiment of the present invention.
[0031] Figure 6 The diagram shown is a schematic representation of the structure after the formation of the silicon oxide dielectric layer in an embodiment of the present invention.
[0032] Figure 7 The diagram shows the structure after removing part of the silicon oxide dielectric layer to expose the silicon nitride hard mask and pores in an embodiment of the present invention.
[0033] Figure 8 The diagram shown is a schematic representation of the structure after the formation of the silicon oxide filling layer in an embodiment of the present invention.
[0034] Figure 9 The diagram shown is a schematic representation of the structure after removing the silicon nitride hard mask in an embodiment of the present invention.
[0035] Figure 10 The diagram shows a comparison between the adsorption activation energy of the precursor on the silicon oxide dielectric layer and the adsorption activation energy on the silicon nitride hard mask in an embodiment of the present invention.
[0036] Explanation of reference numerals in the attached figures
[0037] 100 Semiconductor Substrate
[0038] 200 Pad Oxide Layer
[0039] 300 Silicon Nitride Hard Mask
[0040] 400 photoresist
[0041] 500 trench
[0042] 600 trench oxide layer
[0043] 700 silicon oxide dielectric layer
[0044] 800 pores
[0045] 900 silica filler layer Detailed Implementation
[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0047] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0048] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0050] See Figure 1This embodiment provides a method for preparing a shallow trench isolation structure, including the following steps:
[0051] S1: Provides a semiconductor substrate;
[0052] S2: A patterned silicon nitride hard mask is formed on the surface of the semiconductor substrate, and the surface of the silicon nitride hard mask has amino groups;
[0053] S3: Based on the silicon nitride hard mask, a trench is formed in the semiconductor substrate;
[0054] S4: A silicon oxide dielectric layer filling the trench is formed on the silicon nitride hard mask, the silicon oxide dielectric layer having pores and the surface of the silicon oxide dielectric layer having hydroxyl groups;
[0055] S5: Remove part of the silicon oxide dielectric layer to expose the silicon nitride hard mask and the pores;
[0056] S6: Provide a precursor and selectively deposit it to form a silicon oxide filling layer on the silicon oxide dielectric layer to fill the pores, wherein the adsorption activation energy of the precursor on the silicon oxide dielectric layer is less than the adsorption activation energy on the silicon nitride hard mask.
[0057] S7: Remove the silicon nitride hard mask.
[0058] The method for fabricating the shallow trench isolation structure described in this embodiment is based on the difference in adsorption activation energy of the precursor on the silicon nitride hard mask and the silicon oxide dielectric layer, thereby achieving selective deposition on the silicon nitride hard mask and the silicon oxide dielectric layer to form the silicon oxide filling layer that can fill the pores in the silicon oxide dielectric layer.
[0059] The method for preparing the shallow trench isolation structure described in this embodiment can effectively fill the pores in the silicon oxide dielectric layer, solve the isolation failure problem of the shallow trench isolation structure, and improve the product yield.
[0060] The following is in conjunction with the instruction manual. Figures 2 to 10 The preparation of the shallow trench isolation structure is further described below.
[0061] First, refer to Figure 1 and Figure 2 Step S1 is performed to provide a semiconductor substrate 100.
[0062] Specifically, the semiconductor substrate 100 may include a semiconductor single crystal substrate or a semiconductor compound substrate. If necessary, the semiconductor substrate 100 may include a silicon substrate, a germanium substrate, a carbon substrate, etc. Of course, if necessary, the semiconductor substrate 100 may also be a semiconductor compound substrate such as a gallium nitride substrate or a gallium oxide substrate.
[0063] Next, refer to Figures 1-5 Steps S2 and S3 are performed to form a patterned silicon nitride hard mask 300 on the surface of the semiconductor substrate 100, and the surface of the silicon nitride hard mask 300 has amino groups. Based on the silicon nitride hard mask 300, trenches 500 are formed in the semiconductor substrate 100.
[0064] For details, please refer to Figure 3 In this embodiment, a pad oxide layer 200 is preferably formed between the semiconductor substrate 100 and the silicon nitride hard mask 300. The pad oxide layer 200 serves as an adhesive layer between the semiconductor substrate 100 and the silicon nitride hard mask 300, and also as an etching stop layer for the silicon nitride hard mask 300. The pad oxide layer 200 can be prepared by a thermal oxidation process, such as a silicon oxide layer prepared by thermal oxidation, but the type and preparation method of the pad oxide layer 200 are not limited to these.
[0065] The silicon nitride hard mask 300 can be prepared by methods such as chemical vapor deposition, and as is well known to those skilled in the art, the surface of the silicon nitride hard mask 300 formed in the final product has amino groups (-NH2).
[0066] Next, refer to Figure 4 After the silicon nitride hard mask 300 is formed, patterned photoresist 400 with openings can be formed on the silicon nitride hard mask 300 through coating, exposure, and development processes. The specific type of photoresist 400 is not limited here.
[0067] Since the openings in the photoresist 400 expose the silicon nitride hard mask 300, see reference. Figure 5 The silicon nitride hard mask 300 and the pad oxide layer 200 can be etched based on the photoresist 400 to expose the semiconductor substrate 100, and then a trench 500 can be formed in the semiconductor substrate 100 by etching.
[0068] Then, the photoresist 400 is removed.
[0069] Furthermore, after removing the photoresist 400, a cleaning step such as using hydrofluoric acid (HF) can be performed to remove the native oxides on the surface of the semiconductor substrate 100.
[0070] See Figure 5In this embodiment, a trench oxide layer 600 is preferably formed in the trench 500, covering the bottom and sidewalls of the trench 500, so as to reduce the etching damage on the surface of the trench 500 and smooth the corners of the trench 500, thereby improving the isolation effect of the shallow trench isolation structure subsequently prepared.
[0071] The trench oxide layer 600 is preferably made of silicon oxide to ensure good contact with the subsequently prepared silicon oxide dielectric layer. The trench oxide layer 600 can be prepared using methods such as thermal oxidation, chemical vapor deposition, or high aspect ratio process (HARP).
[0072] Next, refer to Figure 1 and Figure 6 In step S4, a silicon oxide dielectric layer 700 is formed on the silicon nitride hard mask 300 to fill the trench 500. The silicon oxide dielectric layer 700 has pores 800 and the surface of the silicon oxide dielectric layer 700 has hydroxyl groups (-OH).
[0073] Specifically, the preferred method for preparing the silicon oxide dielectric layer 700 is a high aspect ratio process (HARP) to minimize the content of the pores 800 in the silicon oxide dielectric layer 700. As is well known to those skilled in the art, the surface of the final silicon oxide dielectric layer 700 formed during the preparation of the silicon oxide dielectric layer 700 has hydroxyl groups (-OH).
[0074] The pore 800 includes voids and / or seams.
[0075] After the silicon oxide dielectric layer 700 is formed, a first annealing process step is preferably performed to form the silicon oxide dielectric layer 700 with a stable crystal structure, thereby densifying the silicon oxide dielectric layer 700. The temperature of the first annealing is preferably 1050°C, but is not limited to this.
[0076] Next, refer to Figure 1 and Figure 7 Step S5 is executed to remove part of the silicon oxide dielectric layer 700, exposing the silicon nitride hard mask 300 and the pores 800.
[0077] Specifically, the method for removing part of the silicon oxide dielectric layer 700 may be chemical mechanical polishing (CMP), but is not limited to this.
[0078] Furthermore, after removing part of the silicon oxide dielectric layer 700, a second annealing process is preferably performed to further densify the remaining silicon oxide dielectric layer 700 and release the mechanical stress caused by CMP. The temperature of the second annealing is lower than the temperature of the first annealing. In this embodiment, the temperature of the second annealing is selected as 950°C, but it is not limited to this.
[0079] Next, refer to Figure 1 and Figure 8 Step S6 is performed to provide a precursor and selectively deposit it to form a silicon oxide filling layer 900 that fills the pores 800 on the silicon oxide dielectric layer 700, wherein the adsorption activation energy of the precursor on the silicon oxide dielectric layer 700 is less than the adsorption activation energy on the silicon nitride hard mask 300.
[0080] Specifically, in this embodiment, the precursor is diisopropylamine silane (DIPAS), also known as N,N-diisopropylsilaneamine or diisopropylaminosilane, with the chemical formula C6H. 17 NSi is an organosilicon compound. (See also...) Figure 10 It is known that, regardless of physical adsorption or chemical adsorption, the adsorption activation energy of the precursor DIPAS for -OH groups is less than that for -NH2 groups. Therefore, the adsorption activation energy of the precursor DIPAS on the silicon oxide dielectric layer 700 is less than that on the silicon nitride hard mask 300. Thus, the precursor DIPAS will be selectively deposited on the silicon oxide dielectric layer 700 and the silicon nitride hard mask 300. Then, by controlling the selective deposition temperature to below 100°C, such as 100°C, 90°C, 80°C, etc., and by providing a reactive gas such as ozone (O3), the silicon oxide filling layer 900 that can fill the pores 800 can be formed on the surface of the silicon oxide dielectric layer 700.
[0081] The type of precursor is not limited to this; selective deposition on the surfaces of the silicon oxide dielectric layer 700 and the silicon nitride hard mask 300 can be achieved. Specifically, the type of precursor and the deposition process can be selected as needed.
[0082] When the depth of the pores 800 to be filled is less than 4 nm, due to the selective deposition of the precursor DIPAS on the silicon oxide dielectric layer 700 and the silicon nitride hard mask 300, the silicon oxide filling layer 900 is almost only located on the silicon oxide dielectric layer 700, and almost no silicon oxide filling layer 900 is formed on the silicon nitride hard mask 300. Therefore, the removal process of the silicon nitride hard mask 300 can be directly performed subsequently.
[0083] When the depth of the pores 800 to be filled is greater than 4 nm, such as 8 nm or 10 nm, as the deposition process proceeds, some of the precursor DIPAS will also be adsorbed on the silicon nitride hard mask 300, thereby forming a silicon oxide filling layer 900 on the silicon nitride hard mask 300 that is thinner than the silicon oxide dielectric layer 700. Therefore, in order to reduce the difficulty of the subsequent removal process of the silicon nitride hard mask 300, it is preferable to use a process step that combines selective deposition and etching to remove the silicon oxide filling layer 900 located on the silicon nitride hard mask 300. In each deposition process, due to the difference in adsorption activation energy, the thickness of the silicon oxide filling layer 900 formed on the silicon oxide dielectric layer 700 is much greater than the thickness of the silicon oxide filling layer 900 formed on the silicon nitride hard mask 300. Thus, by cyclically performing deposition and etching steps, the silicon oxide filling layer 900 formed on the silicon nitride hard mask 300 can be removed relatively easily, and finally a thicker silicon oxide filling layer 900 on the silicon nitride hard mask 300 that fills the pores 800 is prepared.
[0084] The method of etching away the silicon oxide filling layer 900 located on the silicon nitride hard mask 300 can be achieved by cleaning with hydrofluoric acid (HF) for convenient removal, but the removal method is not limited to this.
[0085] Next, refer to Figure 1 and Figure 9 Step S7 is executed to remove the silicon nitride hard mask 300.
[0086] Specifically, the silicon nitride hard mask 300 can be removed by methods such as hot phosphoric acid cleaning. Furthermore, if the pad oxide layer 200 is silicon oxide, it can be removed by methods such as hydrofluoric acid (HF). The method for removing the silicon nitride hard mask 300 can be selected according to specific needs and is not limited here. This completes the fabrication of the shallow trench isolation structure.
[0087] In summary, the method for preparing the shallow trench isolation structure of the present invention achieves selective deposition on the silicon nitride hard mask and the silicon oxide dielectric layer based on the difference in adsorption activation energy of the precursor on the silicon nitride hard mask and the silicon oxide dielectric layer, so as to form the silicon oxide filling layer that can fill the pores in the silicon oxide dielectric layer.
[0088] The method for preparing the shallow trench isolation structure of the present invention can effectively fill the pores in the silicon oxide dielectric layer, solve the isolation failure problem of the shallow trench isolation structure, and improve the product yield.
[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method of forming a shallow trench isolation structure, comprising: The method comprises the following steps: providing a semiconductor substrate; forming a patterned silicon nitride hard mask on a surface of the semiconductor substrate, and a surface of the silicon nitride hard mask has amino groups; forming a trench in the semiconductor substrate based on the silicon nitride hard mask; forming a silicon oxide dielectric layer filling the trench on the silicon nitride hard mask, the silicon oxide dielectric layer has pores, and a surface of the silicon oxide dielectric layer has hydroxyl groups; removing part of the silicon oxide dielectric layer to expose the silicon nitride hard mask and the pores; providing a precursor and performing selective deposition to form a silicon oxide filling layer filling the pores on the silicon oxide dielectric layer, wherein an adsorption activation energy of the precursor on the silicon oxide dielectric layer is less than an adsorption activation energy of the precursor on the silicon nitride hard mask; removing the silicon nitride hard mask.
2. The method of claim 1, wherein: The precursor comprises diisopropylamine silane.
3. The method of claim 2, wherein: The temperature range of the selective deposition comprises below 100°C, and the reaction gas comprises ozone.
4. The method of claim 1, wherein: The depth of the pores to be filled ranges from below 4 nm.
5. The method of claim 1, wherein: When the depth of the pores to be filled is greater than 4 nm, the method further comprises a step of removing the silicon oxide filling layer on the silicon nitride hard mask by etching.
6. The method of claim 1, wherein: After forming the silicon oxide dielectric layer filling the trench on the silicon nitride hard mask, the method comprises a step of performing first annealing, and between removing part of the silicon oxide dielectric layer and performing the selective atomic layer deposition, the method further comprises a step of performing second annealing.
7. The method of claim 1, wherein: The method of the selective deposition comprises selective atomic layer deposition, and the method of forming the silicon oxide dielectric layer comprises high aspect ratio process.
8. The method of claim 1, wherein: A pad oxide layer is further formed between the semiconductor substrate and the silicon nitride hard mask.
9. The method of claim 1, wherein: Before forming the silicon oxide dielectric layer, the method further comprises a step of forming a trench oxide layer covering a bottom and sidewalls of the trench in the trench.
10. The method of claim 1, wherein: The semiconductor substrate comprises a semiconductor single crystal substrate or a semiconductor compound substrate.