Integrated circuit chip, preparation method of integrated circuit chip and electronic device

Abstract

The invention discloses an integrated circuit chip, a preparation method of the integrated circuit chip and an electronic device. The integrated circuit chip comprises a substrate layer, a first functional layer, a second functional layer and a chip voltage port, the substrate layer, the first functional layer and the second functional layer are at least partially stacked, the first functional layer is arranged above the substrate layer, and the second functional layer is arranged on the side, away from the substrate layer, of the first functional layer; the chip voltage port is arranged on the substrate layer to receive a first voltage for the integrated circuit chip; the first functional layer comprises a first voltage conversion module. According to the integrated circuit chip, high-efficiency voltage conversion can be completed nearby in the integrated circuit chip, the problems of loss, noise and resource occupation caused by long-path power supply are solved, and the performance potential of three-dimensional integration is released.

Description

Technical Field

[0001] The embodiments of this disclosure relate to an integrated circuit chip, a method for fabricating an integrated circuit chip, and an electronic device. Background Technology

[0002] 3D stacking technology breaks through the performance, power consumption, and area bottlenecks of 2D integrated circuits, improving integration density and bandwidth, but it poses a severe challenge to the power supply architecture. Traditional board-level distributed power supply solutions require step-down via a board-level DC-DC module before power supply through pins. As the number of stacked layers increases, the long power supply path causes problems such as voltage drop, heat loss, and power supply noise. It also occupies board area and chip input / output interface resources, increasing cost and complexity. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an integrated circuit chip, comprising: a substrate layer, a first functional layer, a second functional layer, and a chip voltage port, wherein the substrate layer, the first functional layer, and the second functional layer are at least partially stacked, the first functional layer is disposed above the substrate layer, and the second functional layer is disposed on a side of the first functional layer away from the substrate layer; the chip voltage port is disposed on the substrate layer to receive a first voltage for the integrated circuit chip; the first functional layer includes a first voltage conversion module configured to be electrically connected to the chip voltage port, receiving the first voltage provided by the chip voltage port, and converting the first voltage into a first operating voltage as the operating voltage of the first functional layer; the second functional layer includes a second voltage conversion module configured to be electrically connected to the chip voltage port, receiving the first voltage provided by the chip voltage port, and converting the first voltage into a second operating voltage as the operating voltage of the second functional layer.

[0004] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the integrated circuit chip further includes a chip voltage conversion module, wherein the chip voltage conversion module is connected to the chip voltage port and configured to provide the first voltage through the chip voltage port.

[0005] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the chip voltage conversion module is disposed on the side of the substrate layer opposite to the first functional layer.

[0006] For example, in an integrated circuit chip provided in an embodiment of this disclosure, at least one of the first voltage conversion module and the second voltage conversion module includes a switched capacitor voltage conversion module and a linear regulator. The switched capacitor voltage conversion module is configured to receive the first voltage provided by the chip voltage port and perform a step-down conversion on the first voltage to generate a corresponding intermediate voltage. The linear regulator is configured to regulate the corresponding intermediate voltage to output a corresponding operating voltage.

[0007] For example, in an integrated circuit chip provided in one embodiment of this disclosure, the switched capacitor voltage conversion module includes a plurality of switched capacitor voltage conversion units arranged in an array. The plurality of switched capacitor voltage conversion units are evenly spaced apart to form a trace area for laying interlayer vertical interconnect channels between adjacent switched capacitor conversion units.

[0008] For example, in an integrated circuit chip provided in one embodiment of this disclosure, the switched capacitor voltage conversion module is stacked with the linear regulator and is disposed on the side of the switched capacitor conversion module away from the substrate.

[0009] For example, in an embodiment of the integrated circuit chip provided in this disclosure, each of the plurality of switched-capacitor conversion units includes a transistor and a parallel plate capacitor.

[0010] For example, in an integrated circuit chip provided in one embodiment of this disclosure, the linear regulator includes a low-dropout linear regulator, wherein the switched capacitor voltage conversion module is further configured to perform an integer multiple step-down conversion on the first voltage to output the corresponding intermediate voltage; and the low-dropout linear regulator is configured to perform a fractional-proportional linear adjustment on the corresponding intermediate voltage to output the corresponding operating voltage.

[0011] For example, in an integrated circuit chip provided in an embodiment of this disclosure, a first interconnect layer is disposed between the first functional layer and the substrate layer, and a second interconnect layer is disposed between the second functional layer and the first functional layer; the chip voltage port is configured to be electrically connected to the first voltage conversion module through a first interconnect channel in the first interconnect layer, and electrically connected to the second voltage conversion module through the first interconnect channel in the first interconnect layer and the second interconnect channel in the second interconnect layer.

[0012] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the integrated circuit chip is a monolithic three-dimensional integrated chip, the first functional layer and the second functional layer are semiconductor circuit layers directly integrated using semiconductor technology, the first interconnect layer and the second interconnect layer are insulating layers directly integrated using semiconductor technology; the first interlayer interconnect channel and the second interlayer interconnect channel include interlayer vias.

[0013] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the first voltage conversion module is integrated in the first functional layer on the side facing away from the substrate layer through a semiconductor process; the second voltage conversion module is integrated in the second functional layer on the side facing away from the substrate layer through a semiconductor process.

[0014] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the integrated circuit chip is a three-dimensional packaged chip, the first functional layer is a first sub-integrated circuit chip and the second functional layer is a second sub-integrated circuit chip, the first interconnect layer and the second interconnect layer are chip bonding layers; the first interconnect channel includes a chip bonding structure and the second interconnect channel includes a chip bonding structure.

[0015] For example, in an embodiment of the integrated circuit chip provided in this disclosure, the first voltage conversion module is disposed on the side of the first sub-integrated circuit chip facing away from the substrate layer; the second voltage conversion module is disposed on the side of the second sub-integrated circuit chip facing away from the substrate layer; the first voltage conversion module in the first sub-integrated circuit chip is electrically connected to the functional circuit portion of the first sub-integrated circuit chip through a through-silicon via; the second voltage conversion module in the second sub-integrated circuit chip is electrically connected to the functional circuit portion of the second sub-integrated circuit chip through a through-silicon via.

[0016] At least one embodiment of this disclosure provides a method for fabricating an integrated circuit chip, comprising: providing a first functional layer on a substrate, wherein a chip voltage port is disposed on the substrate to receive a first voltage for the integrated circuit chip; providing a second functional layer on a side of the first functional layer away from the substrate; wherein the first functional layer includes a first voltage conversion module, and the second functional layer includes a second voltage conversion module, wherein the first voltage conversion module is configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a first operating voltage as the operating voltage of the first functional layer; the second voltage conversion module is configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a second operating voltage as the operating voltage of the second functional layer.

[0017] At least one embodiment of this disclosure provides an electronic device, including an integrated circuit chip provided in any embodiment of this disclosure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1 A schematic block diagram of an integrated circuit chip is shown.

[0020] Figure 2 A schematic block diagram of an integrated circuit chip provided in at least one embodiment of the present disclosure is shown;

[0021] Figure 3 A schematic block diagram of another integrated circuit chip provided in at least one embodiment of the present disclosure is shown;

[0022] Figure 4 A schematic block diagram of yet another integrated circuit chip provided in at least one embodiment of the present disclosure is shown;

[0023] Figure 5 This diagram illustrates an application architecture schematic of an integrated circuit chip provided in at least one embodiment of the present disclosure;

[0024] Figure 6 This diagram illustrates a schematic block diagram of an application architecture for another integrated circuit chip provided in at least one embodiment of the present disclosure;

[0025] Figure 7 The illustration shows an application diagram of a method for fabricating an integrated circuit chip according to at least one embodiment of the present disclosure; and

[0026] Figure 8 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0029] With the continuous miniaturization of semiconductor process nodes and the increasing demands for system performance, 3D stacking technology has become a key technological path to overcome the performance, power consumption, and area bottlenecks of traditional 2D integrated circuits. 3D stacking significantly improves system integration and bandwidth by vertically stacking multiple chips or functional layers. However, while 3D integration brings performance advantages, it also poses more severe challenges to its power supply architecture. In traditional 2D chips and early 3D stacking systems, the power supply architecture typically employs a board-level distributed power management scheme. For example, higher input voltages (e.g., 12V or 48V) are first stepped down by multiple discrete DC-DC converter modules located on the printed circuit board to generate different voltage levels required for each voltage domain of the chip (e.g., 5V, 3.3V, 1.8V, 1.2V, etc.), and then distributed to the chip's internal circuitry through their respective power pins. To optimize dynamic power consumption, linear regulators or switching regulators may be further integrated within the chip for local voltage regulation.

[0030] However, as the number of layers in a three-dimensional stacked chip increases and the power consumption of each layer rises, the current density increases dramatically, and the shortcomings of this architecture become increasingly apparent:

[0031] For example, if the power supply path from the board-level converter output to the stacked upper circuit is too long, the IR voltage drop and Joule heat loss caused by its parasitic resistance will be significantly worsened, which will seriously affect the power supply voltage quality of the upper circuit and the system energy efficiency.

[0032] For example, equipping each voltage domain with an independent board-level conversion module and chip pins occupies valuable board area and chip I / O resources, increasing system cost and complexity;

[0033] For example, parasitic inductance in long paths can easily cause severe power supply noise and ground bounce when the load current changes rapidly, threatening the integrity of circuit signals.

[0034] Figure 1 A schematic block diagram of an integrated circuit chip is shown.

[0035] like Figure 1 As shown, the substrate layer is located at the bottom of the chip, carrying the input pins connected to the PCB and serving as the "entry point" for external voltage to enter the chip. There are at least three layers (functional layers 1, 2, and 3), stacked together; each functional layer integrates logic circuits, PMOS / NMOS devices, etc., and needs to receive power from its corresponding voltage domain. Through-silicon vias (TSVs) in the interlayer interconnect layers are used to enable voltage transfer between the substrate layer and each functional layer.

[0036] This integrated circuit chip adopts a board-level multi-voltage conversion and three-dimensional chip stacking architecture. It uses a unified high voltage (48V) as the external input, and multiple independent board-level DC-DC conversion modules are deployed on the PCB to convert the 48V to the operating voltages required by different functional layers of the chip (e.g., 18V, 3.3V, 5V). Each module corresponds to a voltage domain. The connection between the board level and the chip relies on bump structures (e.g., ...). Figure 1 The “R_Bump” and “L_Bump” shown are the parasitic resistance and parasitic inductance of the bump, which are one of the sources of power loss and power supply noise.

[0037] The inventors of this disclosure have noted that multiple DC-DC modules need to be deployed at the board level, occupying a large amount of PCB area; the chip needs to reserve independent input pins for each voltage domain, squeezing I / O resources; as the number of stacked layers increases, the power supply path of the upper functional layer becomes longer, and parasitic resistance / inductance leads to increased IR drop and power loss; different voltage domains need to be routed independently, further squeezing the internal interconnection resources of the chip.

[0038] To address these challenges, one approach is to increase the board-level input voltage (e.g., from 12V to 48V), thereby reducing the input current while transmitting the same power, thus mitigating path losses and IR drop. Another example is a rear-side power supply network, which significantly shortens the power supply distance by placing the power supply network on the back of the chip and directly supplying power to the transistors via through-silicon vias.

[0039] While these technologies have alleviated the problem to some extent, the fundamental contradiction remains unresolved for multi-layer 3D stacked structures, especially monolithic 3D integration processes: regardless of the input voltage, low voltage and high current must still be provided to the circuits on the upper layers of the stack, and the current still needs to pass through the long interconnect paths of all the lower-layer chips. Path loss and voltage drop problems accumulate with the number of layers. At the same time, if board-level conversion continues to be used to generate all voltage domains, the area and pin occupancy problems will increase in tandem with the number of voltage domains.

[0040] In particular, in monolithic 3D integration technology, multiple functional layers are directly integrated onto the same substrate through back-end processes, with interlayer interconnects at the nanometer scale, making the power supply architecture design a completely new challenge. However, existing research has mostly focused on computing and storage architectures, while exploration of efficient and compact power supply architectures remains a gap.

[0041] Therefore, there is an urgent need for an innovative on-chip power supply architecture that is deeply adapted to the three-dimensional stacked structure, which can complete efficient voltage conversion locally within the integrated circuit chip, fundamentally solving the problems of power loss, noise and resource occupation caused by long-path power supply, and releasing the performance potential of three-dimensional integration.

[0042] In view of the above, embodiments of this disclosure provide an integrated circuit chip, which includes: a substrate layer, a first functional layer, a second functional layer, and a chip voltage port, wherein the substrate layer, the first functional layer, and the second functional layer are at least partially stacked, the first functional layer is disposed above the substrate layer, and the second functional layer is disposed on the side of the first functional layer away from the substrate layer; the chip voltage port is disposed on the substrate layer to receive a first voltage for the integrated circuit chip; the first functional layer includes a first voltage conversion module, which is configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a first operating voltage as the operating voltage of the first functional layer; the second functional layer includes a second voltage conversion module, which is configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a second operating voltage as the operating voltage of the second functional layer. The integrated circuit chip in this embodiment can significantly reduce IR drop and Joule loss caused by long-distance power supply, and effectively suppress power supply noise and ground bounce due to reduced transmission current, thereby comprehensively improving power integrity. At the same time, it can make it possible to provide only a single voltage externally, which greatly saves the area occupied by the board-level DC-DC conversion module and the number of dedicated power supply pins on the chip, improving system integration and resource utilization efficiency. In addition, in other embodiments, the voltage of each functional layer can be set and adjusted independently, which facilitates dynamic voltage adjustment and system expansion. Moreover, this architecture is compatible with 3D packaging and monolithic 3D integration processes, providing an efficient and compact on-chip solution for power supply of multi-layer stacked chips.

[0043] Furthermore, embodiments of this disclosure also provide a method for fabricating the aforementioned integrated circuit chip and an electronic device.

[0044] Figure 2 A schematic block diagram of an integrated circuit chip provided in at least one embodiment of the present disclosure is shown.

[0045] like Figure 2As shown, in some embodiments of this disclosure, the integrated circuit chip 1000 includes a substrate 100, a first functional layer 110, a second functional layer 120, and a chip voltage port 130 (not shown). The substrate 100, the first functional layer 110, and the second functional layer 120 are at least partially stacked, with the first functional layer 110 disposed above the substrate 100 and the second functional layer 120 disposed on the side of the first functional layer 110 away from the substrate 100. The chip voltage port 130 is disposed on the substrate 100 to receive a first voltage for the integrated circuit chip 1000. The first functional layer 110 includes a first voltage conversion module 111 (not shown), and the second functional layer 120 includes a second voltage conversion module 121 (not shown).

[0046] The first voltage conversion module 111 is configured to be electrically connected to the chip voltage port 130, receive the first voltage provided by the chip voltage port 130, and convert the first voltage into a first operating voltage as the operating voltage of the first functional layer 110.

[0047] The second voltage conversion module 121 is configured to be electrically connected to the chip voltage port 130, receive the first voltage provided by the chip voltage port 130, and convert the first voltage into a second operating voltage as the operating voltage of the second functional layer 120.

[0048] For example, the substrate 100, serving as the mechanical support and electrical foundation for the entire chip stack, may include a silicon substrate carrying silicon-based CMOS circuitry, or a passive silicon interposer or part of a packaging substrate, etc., and the embodiments disclosed herein are not limited thereto. In this embodiment, a chip voltage port 130 is integrated on the substrate 100.

[0049] For example, the first functional layer 110 is disposed above the substrate layer 100. Here, "above" refers to the positional relationship along the direction perpendicular to the substrate surface (i.e., the stacking direction), as shown in the figure.

[0050] For example, the first functional layer 110 and the substrate layer 100 can be integrated through direct semiconductor processes (such as in monolithic 3D integration), or they can be stacked in 3D packaging through bonding processes such as microbumps and hybrid bonding. The embodiments disclosed herein do not limit this.

[0051] For example, the second functional layer 120 is disposed on the side of the first functional layer 110 away from the substrate layer 100, that is, above the first functional layer 110. The substrate layer 100, the first functional layer 110 and the second functional layer 120 are stacked sequentially in a manner that is at least partially stacked to form a vertically integrated structure.

[0052] Here, "at least partially stacked" means that the layers have overlapping areas in the vertical projection to achieve compact three-dimensional integration, but the area and shape of each layer do not have to be exactly the same.

[0053] For example, the chip voltage port 130 is disposed on or integrated therein on the substrate layer 100.

[0054] For example, chip voltage port 130 is the electrical interface between integrated circuit chip 1000 and an external power supply network (such as a printed circuit board), used to receive a higher first voltage (e.g., 12V or 48V) from the outside. This first voltage serves as the uniform input voltage for the entire internal power supply network of the chip.

[0055] For example, a first voltage conversion module 111 may be integrated within the first functional layer 110. For example, the first functional layer 110 itself may include semiconductor circuits that perform specific functions, such as arithmetic calculation units, logic calculation units or control units, storage operation units, cache memories, input / output circuits, etc., for example, to implement central processing units (CPUs), graphics processing units (GPUs), signal processors (ISPs), etc.

[0056] For example, a second voltage conversion module 121 is integrated within the second functional layer 120. Similarly, the second functional layer 120 may include functional circuits that are the same as or different from those in the first functional layer 110, such as high-bandwidth memory (HBM), neural network accelerators, radio frequency modules, etc., and the embodiments of this disclosure are not limited thereto.

[0057] For example, the external first voltage received by the chip voltage port 130 can be provided to the first functional layer 110 and the second functional layer 120 through a vertical interconnect structure that runs through each layer.

[0058] For example, one power supply path can start from the chip voltage port 130, pass through the vertical interconnect structure to reach the first voltage conversion module 111. Another power supply path continues upward through the first functional layer 110 (or its interconnect area), and passes through the vertical interconnect structure to reach the second voltage conversion module 121.

[0059] For example, the first voltage conversion module 111 can receive a first voltage (e.g., 12V) from the chip voltage port 130 and efficiently convert it into a first operating voltage (e.g., 1.8V) required by the functional circuitry of that layer. The converted first operating voltage is then distributed to the functional circuitry of that layer through a local power supply network within the first functional layer 110.

[0060] For example, the second voltage conversion module 121 can receive the same first voltage (12V) from the chip voltage port 130 and independently convert it into a second operating voltage (e.g., 0.9V) required by the functional circuitry of the second functional layer 120. The second operating voltage can be distributed to the functional circuitry of the second functional layer 120 through the power supply network inside the second functional layer 120.

[0061] For example, the operating voltages (first operating voltage and second operating voltage) of the first functional layer 110 and the second functional layer 120 can be the same or different, depending on the performance and power consumption optimization requirements of their respective functional circuits. The embodiments of this disclosure do not impose such limitations. The voltage conversion modules of each layer can be independently configured to output their corresponding operating voltages.

[0062] For example, for stacking methods, Figure 1 The diagram shows two functional layers, but this architecture can naturally be extended to a stack of three or more layers. For the Nth layer (N>1, a positive integer), its voltage conversion module can also be directly or indirectly connected to the chip voltage port 130, receive the first voltage, and perform the conversion locally (at the Nth layer).

[0063] For example, the first voltage conversion module 111 and the second voltage conversion module 121 can adopt the same circuit topology, or they can adopt different designs according to the current requirements, efficiency targets and area constraints of their respective layers.

[0064] For example, vertical interconnect structures used to transmit the first voltage need to have low resistance to reduce path losses. For example, in 3D packaging, vertical interconnect structures involve through-silicon vias (TSVs) and bonding points; for example, in monolithic 3D integration, vertical interconnect structures involve interlayer vias (ILVs) formed by back-end processes.

[0065] In at least one embodiment of this disclosure, the integrated circuit chip 1000 can significantly reduce IR drop and Joule loss caused by long-distance power supply, and effectively suppress power supply noise and ground bounce due to reduced transmission current, thereby comprehensively improving power integrity. At the same time, it can make it possible to provide only a single voltage externally, which greatly saves the area occupied by the board-level DC-DC conversion module and the number of dedicated power supply pins on the chip, and improves the system integration and resource utilization efficiency. In addition, the voltage of each functional layer can be set and adjusted independently, which facilitates dynamic voltage regulation and system expansion. Moreover, the architecture is compatible with three-dimensional packaging and monolithic three-dimensional integration processes, providing an efficient and compact on-chip solution for power supply of multi-layer stacked chips.

[0066] In some embodiments of this disclosure, the integrated circuit chip 1000 may further include a chip voltage conversion module 140, which is electrically connected to a chip voltage port 130, thereby supplying power to the chip through the chip voltage port 130.

[0067] The chip voltage conversion module 140 can be configured to provide a first voltage through the chip voltage port 130.

[0068] For example, the output of the chip voltage conversion module 140 is electrically connected to the chip voltage port 130, and its input is used to receive an input power supply voltage from outside the integrated circuit chip 1000 that is different from the first voltage.

[0069] For example, the chip voltage conversion module 140 can be configured to convert the received input supply voltage (e.g., buck conversion) to generate a first voltage, and provide this first voltage to the internal power supply network of the chip through the chip voltage port 130. In other words, the chip voltage port 130 can serve as the output port of the chip voltage conversion module 140, used to introduce the first voltage generated by the module 140 into the subsequent stacked power supply architecture.

[0070] For example, the chip voltage conversion module 140 can be a standalone, packaged power management integrated circuit mounted on a packaging substrate or printed circuit board that carries the integrated circuit chip 1000.

[0071] For example, the output of the chip voltage conversion module 140 can be connected to the chip voltage port 130 via traces on the substrate.

[0072] For example, the chip voltage conversion module 140 can be directly integrated into or on the surface of the substrate 100 using semiconductor processes. In this case, the substrate 100 can be a silicon substrate containing active devices, and the chip voltage conversion module 140 can be fabricated together with its logic or analog circuitry. For example, the chip voltage port 130 can be considered as an output pad or bump of the module 140 on the substrate surface.

[0073] For example, if the substrate 100 is a passive silicon interposer or a glass interposer, the chip voltage conversion module 140 can also be integrated on this interposer to achieve tighter power integration.

[0074] For example, the chip voltage conversion module 140 can be implemented using a high-efficiency switching-mode power supply circuit, such as a synchronous buck converter. Internally, it may include power switches (such as MOSFETs), a controller, drive circuitry, and necessary passive components (such as inductors and capacitors).

[0075] For example, the design goal of the chip voltage conversion module 140 may be to convert a higher external input supply voltage (e.g., 48V, suitable for scenarios such as data centers) into a lower first voltage (e.g., 12V) suitable for medium- to long-distance vertical transmission within the chip with high conversion efficiency. For example, in the embodiments of this disclosure, choosing 12V instead of a lower voltage as the first voltage may be to obtain a current one order of magnitude smaller than the core voltage of about 1V when transmitting the same power within the chip, thereby significantly reducing transmission path loss.

[0076] In at least one embodiment of this disclosure, by integrating a chip voltage conversion module 140, the integrated circuit chip 1000 can be directly connected to an industry-standard, relatively high DC voltage (such as a 48V or 12V bus voltage) without requiring the system motherboard to provide precise multi-channel low voltages. This simplifies system-level power supply design and bill of materials. The voltage conversion module 140 can convert high voltage to a corresponding relay voltage (e.g., a first voltage), thus optimizing the overall energy transfer chain from the external power supply to the various functional layers within the chip. The high voltage input reduces board-level transmission losses, while the optimized first voltage balances the losses of vertical transmission within the chip with the efficiency of subsequent on-chip conversion. For example, the chip voltage conversion module 140 can serve as the "front end" of the entire integrated circuit chip 1000 power supply system and can also integrate more complex control functions, such as soft start, overcurrent protection, overvoltage protection, and enable control, improving the reliability and controllability of the integrated circuit chip 1000.

[0077] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, the chip voltage conversion module 140 may be disposed on the side of the substrate layer 100 opposite to the first functional layer 110.

[0078] For example, the chip voltage conversion module 140 can be integrated on the back side of the substrate 100 (i.e., the side away from the stacking direction of all functional layers). The first functional layer 110 is located on the front side of the substrate 100. This configuration forms a "back-to-back" or "chip back-integrated power supply" layout.

[0079] For example, the chip voltage conversion module 140 can be implemented on the back side of the substrate layer 100 in a variety of ways:

[0080] For example, wafer-level back-side process: after the front-side circuit of the substrate layer 100 is manufactured, the wafer can be thinned, and then the circuit elements (such as transistors, capacitors, interconnects) of the chip voltage conversion module 140 can be directly fabricated on the back side using semiconductor processes such as photolithography, etching, and deposition.

[0081] For example, chip stacking or bonding: the chip voltage conversion module 140 can be first fabricated on another independent thin chip or silicon wafer, and then flip-chip and bonded to the back side of the substrate 100 using interconnect technologies such as hybrid bonding, oxide-oxide direct bonding, or microbumps. The electrical connection between the module 140 and the substrate 100 is achieved through interconnect structures (such as copper pillars, through-silicon vias, TSVs) at the bonding interface;

[0082] For example, in package integration: the chip voltage conversion module 140 can also be a discrete component or chip, embedded in the package substrate or mounted in the package structure on the back of the substrate 100, and connected to the contact points on the back of the substrate 100 through the internal wiring and vias of the package.

[0083] For example, the chip voltage port 130 can be disposed on the back side of the substrate 100 and directly connected to the output of the chip voltage conversion module 140. Alternatively, the chip voltage port 130 can still be disposed on the front side, while the output of the module 140 is connected to the front port through a through-silicon via (TSV) penetrating the substrate 100.

[0084] For example, the first voltage generated by the chip voltage conversion module 140 can be transmitted to the front side of the substrate 100 through the vertical interconnect structure that penetrates the substrate 100, and then provided to the upper first functional layer 110 and second functional layer 120 via the interconnect on the front side or the vertical interconnect that continues upward.

[0085] In at least one embodiment of this disclosure, the chip voltage conversion module 140 is integrated on the back side of the substrate. The heat generated by the voltage conversion module can be dissipated directly through the back side of the substrate or more effectively conducted to an external heat sink, avoiding heat accumulation inside the functional layer stack. This helps to reduce the overall chip junction temperature and improve reliability. It achieves good electrical isolation, spatially separating the power conversion circuit that may generate large switching noise from the noise-sensitive core functional layer circuit, and using the substrate as a natural shield, effectively reducing the interference of power supply noise on the signal integrity above. Furthermore, it saves valuable front-side stacking space, without occupying the area on the front side of the substrate used for functional circuits or vertical interconnects, making the three-dimensional stack layout more compact and facilitating more flexible power supply network routing. It also improves manufacturing and integration flexibility.

[0086] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, at least one of the first voltage conversion module 111 and the second voltage conversion module 121 includes a switched capacitor voltage conversion module and a linear regulator.

[0087] Here, "at least one" includes either or both of the first voltage conversion module 111 and the second voltage conversion module 121 employing this structure. Each functional layer can also independently choose whether to adopt this cascaded architecture based on its own voltage accuracy, efficiency targets, and area constraints.

[0088] The switched capacitor voltage conversion module can be configured to receive a first voltage provided by the chip voltage port 130, and perform a step-down conversion on the first voltage to generate a corresponding intermediate voltage.

[0089] A linear regulator can be configured to regulate the corresponding intermediate voltage to output the corresponding operating voltage.

[0090] For example, the input of the switched capacitor voltage conversion module is electrically connected to the chip voltage port 130 (or the vertical power supply network extending from it) to receive a first voltage (e.g., 12V).

[0091] For example, the switched-capacitor voltage conversion module is configured to perform a high-efficiency integer-multiple step-down conversion on the first voltage to generate an intermediate voltage. For example, when the first voltage is 12V and the corresponding functional layer's operating voltage is 1.8V, the switched-capacitor voltage conversion module can use a 4:1 conversion ratio to convert 12V into an intermediate voltage of approximately 3V.

[0092] For example, the input of the linear regulator can be connected to the output of the switched capacitor voltage conversion module 210 to receive the intermediate voltage.

[0093] For example, a linear regulator can be configured to precisely regulate and stabilize the intermediate voltage, outputting a stable, low-noise operating voltage (e.g., 1.8V).

[0094] For example, a linear regulator may include a low-dropout linear regulator to accommodate a small input-output voltage difference while maintaining high efficiency.

[0095] For example, classic switched-capacitor architectures such as Dickson charge pumps, series-parallel switched-capacitor networks, or flying-through capacitor multilevel topologies can be used. By controlling the switching sequence, the capacitor is reconfigured in different phase periods to achieve proportional voltage scaling.

[0096] For example, MOSFET transistors can be used as switching elements, and for back-end process integration, low-temperature process compatible devices such as indium gallium zinc oxide transistors or carbon nanotube transistors can be used.

[0097] For example, capacitor elements can be metal-insulator-metal capacitors, metal-oxide-metal capacitors, or deep trench capacitors.

[0098] For example, the conversion ratio of a switched capacitor converter can be fixed (e.g., 2:1, 3:1, 4:1) or multiple ratios can be selected through a programmable switching network to adapt to different intermediate voltage requirements.

[0099] For example, the circuit of a linear regulator may include an error amplifier, a voltage reference source, a feedback resistor network, and a regulating transistor.

[0100] For example, the regulating transistor can be a MOSFET, which operates, for example, in the linear region.

[0101] For example, a feedback network can compare a portion of the output voltage with a reference voltage, and an error amplifier can drive a regulating transistor to adjust its on-resistance, thereby stabilizing the output voltage at a set value.

[0102] For example, for functional layers where the operating voltage is a simple fraction of the first voltage (such as 1 / 2 or 1 / 3), a switched-capacitor converter is sufficient; for layers requiring more precise or adjustable voltages, cascaded linear regulators can be added.

[0103] For example, the output voltage of a linear regulator can be dynamically adjusted through a programmable feedback network, thereby supporting dynamic voltage regulation of this functional layer.

[0104] In at least one embodiment of this disclosure, a high-efficiency integer-multiple voltage reduction is achieved through a switched-capacitor converter, followed by voltage regulation and ripple suppression through a linear regulator, enabling high conversion efficiency without the need for inductors. For example, both the switched capacitor and the linear regulator can be manufactured using low-temperature processes, making them highly compatible with 3D integration processes and providing independent, efficient, low-loss, and compact power solutions for each functional layer.

[0105] Figure 3 A schematic block diagram of another integrated circuit chip provided in at least one embodiment of the present disclosure is shown.

[0106] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, the switched capacitor voltage conversion module includes a plurality of switched capacitor voltage conversion units arranged in an array. The plurality of switched capacitor voltage conversion units are evenly spaced to form a trace area between adjacent switched capacitor conversion units for routing interlayer vertical interconnect channels.

[0107] like Figure 3 As shown, for example, multiple switched capacitor voltage conversion units can be arranged in a regular grid or staggered pattern on a two-dimensional plane (e.g., the interconnection layer plane of the functional layer).

[0108] For example, each switched capacitor voltage conversion unit is a basic and fully functional switched capacitor voltage converter sub-circuit, capable of independently or in conjunction with other units to complete a portion of the voltage conversion function.

[0109] For example, these multiple switched-capacitor voltage conversion units are not closely adjacent in the array, but rather maintain a generally uniform spacing between them. This regular spacing creates a wiring area between the units.

[0110] For example, each switched-capacitor voltage conversion unit may include all the switching transistors (such as MOSFETs) and capacitors required to achieve a specific conversion ratio (such as 2:1).

[0111] For example, multiple switched capacitor voltage conversion units can be connected in parallel with input and output nodes or connected according to a specific phase relationship to form a complete multiphase switched capacitor converter with greater power handling capability.

[0112] For example, the routing area can be specifically reserved or designed for laying interlayer vertical interconnect channels. These interlayer vertical interconnect channels can be through silicon vias, interlayer vias, or other vertical conductive structures used to connect adjacent functional layers, etc., and the embodiments disclosed herein are not limited thereto.

[0113] For example, routing areas provide physical space and wiring paths for the vertical crossing of a large number of signal lines, clock lines, data buses, and control lines.

[0114] For example, the array density and cell spacing can be optimized based on the interconnection requirements of specific functional layers. For instance, in areas with extremely dense vertical interconnections, the cell spacing can be appropriately increased to provide wider routing channels; conversely, in areas with relatively low interconnection requirements, the spacing can be slightly reduced to improve area utilization.

[0115] For example, the array of switched-capacitor voltage converters can be designed in conjunction with the layout of the linear regulator circuit above it (if present). For example, the components of the linear regulator can be partially covered above or interspersed with the converter array to further optimize the use of three-dimensional space.

[0116] In at least one embodiment of this disclosure, by decomposing the switched-capacitor voltage conversion module into multiple uniformly spaced, array-distributed units, the spatial competition between power conversion and high-density vertical interconnects in a three-dimensional stacked chip is resolved. The reserved routing area provides a regular vertical channel for more inter-layer signal interconnects, ensuring that the large area of ​​the switched-capacitor voltage conversion module does not obstruct or limit the overall three-dimensional interconnect capability of the chip, thereby maintaining high-bandwidth inter-layer communication.

[0117] Figure 4A schematic block diagram of another integrated circuit chip provided in at least one embodiment of the present disclosure is shown.

[0118] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, a switched capacitor voltage conversion module and a linear regulator are stacked and disposed on the side of the switched capacitor conversion module away from the substrate.

[0119] like Figure 4 As shown, for example, the switched capacitor voltage conversion module is located on the lower layer closer to the substrate 100.

[0120] For example, a linear regulator can be stacked on top of a switched capacitor voltage conversion module.

[0121] For example, the switched capacitor voltage conversion module can be directly or through an intermediate interconnect layer connected to the power supply network from the chip voltage port 130 to receive the first voltage.

[0122] For example, the input of a linear regulator can be electrically connected to the output (providing an intermediate voltage) of a switched-capacitor voltage converter module via a vertical interlayer interconnect (such as an array of vias above the switched-capacitor voltage converter module). The output of the linear regulator then delivers the final operating voltage (such as 1.8V) to the functional circuitry of this functional layer via its upper or lateral interconnect structure.

[0123] For example, this stacked structure of a switched-capacitor voltage converter module and a linear regulator can be implemented by fully utilizing three-dimensional integrated back-end interconnect layers. The switching transistors and capacitors required for the switched-capacitor voltage converter module can be integrated in a few relatively low metal interconnect layers.

[0124] For example, the circuitry of a linear regulator (such as error amplifiers, regulating transistors, feedback resistors, etc.) can be integrated into a higher interconnect layer above the switched capacitor voltage conversion module.

[0125] For example, the vertical interconnect required for the stacked configuration of switched capacitor voltage conversion modules and linear regulators can be achieved through a dense array of vias to enable low-impedance connections and good current delivery capabilities.

[0126] In at least one embodiment of this disclosure, by vertically stacking and integrating the switched capacitor voltage conversion module with the linear regulator, the power conversion function is extremely compressed in three dimensions, greatly improving the area utilization of the chip layout and freeing up more planar space for core functional circuits. At the same time, this compact vertical stacking shortens the interconnection distance between cascaded circuits, reduces parasitic effects, and helps to improve conversion efficiency and transient response performance. In addition, this structure provides a physical basis for hierarchical management of power supply noise and optimization of vertical heat dissipation paths. Through reasonable interlayer isolation and interconnection design, high-performance and high-reliability on-chip voltage conversion can be achieved in a limited space.

[0127] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, each of the plurality of switched capacitor conversion units includes a transistor and a parallel plate capacitor.

[0128] For example, transistors can be used as the main switching element in a switched-capacitor conversion unit to control the charge transport path.

[0129] For example, a switched-capacitor conversion unit (such as a 2:1 conversion stage) may include multiple transistors (e.g., four MOSFETs) connected in a specific topology. For instance, these transistors can be periodically turned on and off under the drive of a control signal (clock signal), reconfiguring the capacitor connections to achieve voltage scaling.

[0130] For example, "parallel plate capacitor" specifically refers to its physical structure, which consists of two parallel conductive plates (plate electrodes) sandwiching an insulating dielectric layer in between.

[0131] For example, a parallel-plate capacitor can be used as an energy storage and charge transfer element in a switched-capacitor conversion unit. For example, in the topology described above, the parallel-plate capacitor can be used as a "flying capacitor." For example, in one phase of the clock, the parallel-plate capacitor can be charged to a certain voltage; in another phase, the connection of the parallel-plate capacitor can be switched, transferring its stored charge to the output or another capacitor, thereby achieving voltage multiplication or division.

[0132] For example, in the implementation of transistors, in monolithic 3D integration or back-end integration embodiments, these transistors can be back-end process compatible transistors. These transistors can be fabricated in the interconnect layer using low-temperature (e.g., below 400°C) processes after standard CMOS front-end processes are completed, without damaging the underlying silicon-based devices.

[0133] For example, transistors may include metal-oxide-semiconductor transistors (based on non-silicon channel materials, such as indium gallium zinc oxide), carbon nanotube thin-film transistors, oxide semiconductor transistors, etc., and the embodiments disclosed herein are not limited thereto. These transistors have moderate mobility, extremely low off-state leakage current, and good low-temperature process compatibility.

[0134] For example, parallel-plate capacitors can also be implemented using a structure compatible with downstream interconnect processes. For example, metal-insulator-metal capacitors.

[0135] For example, the fabrication of parallel-plate capacitors can be synchronized with the interconnection process. Two adjacent metal layers (e.g., the Mth and M+1th metal layers) can be used as the upper and lower plates, respectively, with a reserved area for the interlayer dielectric or a specially deposited high-dielectric-constant insulating material serving as the capacitor dielectric. Here, M is a positive integer.

[0136] For example, the capacitance of a parallel plate capacitor can be controlled by adjusting the area of ​​the plates (layout design) and the characteristics of the dielectric (material and thickness) to meet the energy storage and ripple requirements of different conversion units.

[0137] For example, transistors and parallel-plate capacitors can be connected via metal wiring in the same interconnect layer or adjacent interconnect layers according to a transformation topology.

[0138] In some embodiments of this disclosure, the use of back-end process compatible transistors enables the entire power conversion module to be well integrated with advanced 3D integration (e.g., monolithic 3D integration) processes without modifying the underlying silicon-based circuitry; while MIM parallel-plate capacitors implemented using standard interconnect processes can provide a high-density, high-reliability energy storage solution.

[0139] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, the linear regulator includes a low-dropout linear regulator.

[0140] The switched capacitor voltage conversion module can be further configured to perform an integer multiple step-down conversion on the first voltage to output the corresponding intermediate voltage.

[0141] Low dropout linear regulators can be configured to linearly regulate the corresponding intermediate voltage by a fractional proportion to output the corresponding operating voltage.

[0142] For example, a low dropout linear regulator (LDO) is a linear regulator that can still operate normally while maintaining voltage regulation even when the input and output voltages are very close (i.e., low dropout). This allows it to operate in a more efficient region in a cascaded architecture.

[0143] For example, a switched-capacitor voltage converter module can be configured to perform an integer multiple of buck conversion. For example, the conversion ratio n:1 (where n is an integer greater than 1) of the switched-capacitor voltage converter module can be a fixed or optional integer ratio.

[0144] For example, if the first voltage V_first is 12V and the target operating voltage V_target is 1.2V, the switched capacitor module can be configured to perform a 10:1 conversion, converting 12V to an intermediate voltage V_int of approximately 1.2V.

[0145] For example, a low-dropout linear regulator can be configured to perform fractional-proportional linear regulation. For instance, the low-dropout linear regulator can receive an intermediate voltage V_int from the preceding stage and precisely and continuously regulate it to the final desired operating voltage V_target. This regulation process can, for example, be a non-integer proportional relationship.

[0146] For example, V_int from 3V can be adjusted to V_target from 1.8V with a scaling factor of 0.6. Since the input-output voltage difference (V_int - V_target) has been significantly reduced by the preceding stage, the LDO operates in a small voltage drop state, minimizing the power consumption of its internal regulating transistor (proportional to the voltage drop and load current), thereby maintaining the overall high efficiency of the cascaded system.

[0147] For example, the integer conversion ratio can be determined by the specific topology of the switched capacitor network. For instance, a Dickson charge pump or a series-parallel switch array can achieve conversion ratios of 2:1, 3:1, 4:1, etc.

[0148] For example, more complex topologies can be constructed by adding switches and capacitors, or a programmable switch network can be used to allow a single module to switch between multiple predetermined integer conversion ratios to adapt to different operating modes or the needs of different functional layers.

[0149] In at least one embodiment of this disclosure, the functional division of labor between the switched capacitor voltage conversion module for integer multiple step-down and the low dropout linear regulator for fractional-proportional linear adjustment makes the overall conversion efficiency better than that of a single type of voltage converter. In addition, the fractional-proportional adjustment capability of the LDO provides each functional layer with flexible and precise voltage setting and dynamic adjustment means, further enhancing the adaptability of the power supply architecture and the level of energy efficiency management.

[0150] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, a first interconnect layer 150 is disposed between the first functional layer 110 and the substrate layer 100, and a second interconnect layer 160 is disposed between the second functional layer 120 and the first functional layer 110.

[0151] The chip voltage port 130 can be configured to be electrically connected to the first voltage conversion module 111 via the first interconnect channel 151 in the first interconnect layer 150, and to be electrically connected to the second voltage conversion module 121 via the first interconnect channel 151 in the first interconnect layer 150 and the second interconnect channel 161 in the second interconnect layer 160.

[0152] For example, a first interconnect layer 150 is disposed between the substrate layer 100 and the first functional layer 110. A second interconnect layer 160 is disposed between the first functional layer 110 and the second functional layer 120. These interconnect layers can provide mechanical support and bonding between layers in a three-dimensional stacked structure, and can also carry vertical and horizontal wiring to realize electrical interconnection.

[0153] For example, the interconnect layer may include an insulating medium (such as silicon dioxide or a polymer) and interconnect channels formed by conductive materials embedded therein.

[0154] For example, the path to the first functional layer 110: chip voltage port 130, is electrically connected to the first voltage conversion module 111 through the first interconnect channel 151 in the first interconnect layer 150. The first interconnect channel 151 includes at least one conductive path extending vertically upward (or laterally and then vertically) from the chip voltage port 130 and passing through the first interconnect layer 150 to the input terminal of the first voltage conversion module 111.

[0155] For example, the path to the second functional layer 120: the chip voltage port 130, is electrically connected to the second voltage conversion module 121 through the first interconnect channel 151 in the first interconnect layer 150 and the second interconnect channel 161 in the second interconnect layer 160. That is, the power supply path needs to pass through two interconnect layers in sequence.

[0156] For example, the first interconnect channel 151 can traverse the first interconnect layer 150. This path needs to extend upwards, penetrating the first functional layer 110 itself or its edge / specific reserved area (not shown in the figure, for example, through vias or specific wiring channels within the first functional layer). Subsequently, the second interconnect channel 161 in the second interconnect layer 160 can traverse the second interconnect layer to reach the input terminal of the second voltage conversion module 121.

[0157] For example, the first interconnect channel 151 and the second interconnect channel 161 can be electrically continuous, together forming a vertical power supply channel from the substrate layer to the corresponding functional layer.

[0158] For example, the first interconnect channel 151 and the second interconnect channel 161 can be specifically embodied in various three-dimensional interconnect technologies, such as through-silicon vias (when they pass through a silicon substrate or chip body), microbumps (for inter-chip bonding interconnects), copper-copper interconnect pillars at hybrid bonding interfaces, or interlayer vias in monolithic three-dimensional integration, etc. The embodiments disclosed herein do not limit this.

[0159] For example, the first interconnect channel 151 and the second interconnect channel 161 may include metals (such as copper or tungsten).

[0160] For example, the first interconnect channel 151 and the second interconnect channel 161 may be composed of multiple parallel conductive structures (such as a TSV array or a set of dense bumps) to reduce resistance.

[0161] In some embodiments of the present disclosure, the integrated circuit chip 1000 is a monolithic three-dimensional integrated chip. The first functional layer 110 and the second functional layer 120 are semiconductor circuit layers directly integrated using semiconductor technology. The first interconnect layer 150 and the second interconnect layer 160 are insulating layers directly integrated using semiconductor technology. The first interlayer interconnect channel and the second interlayer interconnect channel include interlayer vias (ILVs).

[0162] For example, integrated circuit chip 1000 is a monolithic three-dimensional integrated chip. Each functional layer can be directly and layer-by-layer constructed on a single wafer substrate through a sequential semiconductor manufacturing process, rather than physically stacking and bonding pre-fabricated independent chips.

[0163] For example, both the first functional layer 110 and the second functional layer 120 are semiconductor circuit layers directly integrated using semiconductor technology. Each functional layer includes active devices (such as transistors) and passive devices, forming specific functional circuits (such as logic, memory, and analog circuits) through their internal local interconnections.

[0164] For example, these functional layers can be fabricated on top of the underlying silicon-based CMOS circuit in a later process using low-temperature processes (e.g., process temperatures below 400°C).

[0165] For example, the first interconnect layer 150 and the second interconnect layer 160 are insulating layers directly integrated using semiconductor processes. These insulating layers not only provide interlayer electrical isolation but also serve as carriers for three-dimensional vertical and horizontal wiring.

[0166] For example, the first interconnect layer 150 and the second interconnect layer 160 may include dielectric materials (such as SiO2, SiCN, low-k dielectrics), and the first interconnect layer 150 and the second interconnect layer 160 may have an interconnect network formed of metals (such as Cu, W) embedded inside them.

[0167] For example, the first and second interconnect channels used for power supply may include interlayer vias (ILVs). Interlayer vias are nanoscale vertical interconnect structures used to connect adjacent metal or functional layer circuit elements, formed by etching insulating layers and filling them with conductive material during semiconductor manufacturing processes. For example, the diameter of interlayer vias can range from nanometers to submicrometers.

[0168] For example, in the fabrication method of the integrated circuit chip 1000 as a monolithic three-dimensional integrated chip, the front-end CMOS device can be fabricated on a silicon substrate. Then, the back-end interconnect process is performed. After forming several layers of metal interconnects, the first functional layer 110 (e.g., a memory array based on IGZO transistors) is constructed. After the device fabrication of the first functional layer 110 is completed, a dielectric material for forming the first interconnect layer 150 is deposited on top of it, and metal wiring and ILVs for upward interconnection are fabricated within this layer. Next, the second functional layer 120 (e.g., a sensing circuit based on CNT transistors) is directly fabricated on top of the first interconnect layer 150, followed by the construction of the second interconnect layer 160.

[0169] For example, transistors and capacitors in a switched-capacitor voltage conversion module can be integrated into the layer containing the corresponding functional layer, or into the interconnect layer region immediately below it, using the same or similar back-end low-temperature processes as those used in the fabrication of the functional layer.

[0170] For example, the power supply path for transmitting the first voltage (such as 12V) can be composed of one or more parallel ILV arrays that run from top to bottom through the associated interconnect layers to form a low-resistance vertical current path.

[0171] For example, due to the small size and relatively large individual resistance of ILVs, a large number of ILVs can be connected in parallel to meet the resistance and current carrying requirements of the power network. These power supply ILVs can be arranged in an interleaved manner with the ILVs used for signal transmission on the layout, realizing a coordinated layout of power supply and signal networks.

[0172] For example, within the first interconnect layer 150 and the second interconnect layer 160, power supply ILVs, signal ILVs, horizontal power grids, horizontal signal lines, decoupling capacitors, etc., can be co-designed and integrated.

[0173] In at least one embodiment of this disclosure, on-chip voltage conversion is achieved by using devices that are fully compatible with back-end processes, and a vertical power supply network is constructed using process-native, high-density interlayer vias. This not only solves the problem of board-level power supply being infeasible due to nanoscale interconnects in M3D, but also significantly reduces the current transmitted in the dense ILV network through local (corresponding functional layer) conversion, thereby reducing losses and voltage drops caused by ILV resistance, while also mitigating noise caused by current variations on the parasitic inductance of the ILV.

[0174] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, a first voltage conversion module 111 is integrated in the first functional layer 110 on the side facing away from the substrate layer 100 by a semiconductor process, and a second voltage conversion module 121 is integrated in the second functional layer 120 on the side facing away from the substrate layer 100 by a semiconductor process.

[0175] For example, the first voltage conversion module 111 can be integrated into the first functional layer 110 on the side facing away from the substrate layer 100 using semiconductor technology.

[0176] Here, "the side facing away from the substrate" refers to the surface or adjacent area of ​​the first functional layer 110 that is furthest from its interface with the substrate 100. The first functional layer 110 (as a separate sub-chip) may include a front side facing the substrate 100 (this side can be the active side of the device, such as the core circuitry including transistors) and a back side opposite it. For example, the first voltage conversion module 111 may be integrated into the back side of the first functional layer 110 or in an interconnect layer very close to the back side.

[0177] For example, the second voltage conversion module 121 can be integrated into the second functional layer 120 on the side facing away from the substrate layer 100 using semiconductor processes. For example, the second voltage conversion module 121 can be integrated into the back side of the second functional layer 120 or in an interconnect layer adjacent to its back side.

[0178] For example, the manufacturing of the voltage conversion module can be completed within the wafer-level process flow of the functional layer chip. For example, the manufacturing of the front-side functional circuits and some interconnects of the chip can be completed first; then the wafer can be thinned; then, on the back side of the thinned wafer, semiconductor processes such as photolithography, etching, and thin film deposition can be used to fabricate the TSV (if used), the back interconnect layer, and integrate the voltage conversion module circuit consisting of back-end compatible transistors and MIM capacitors.

[0179] For example, the input / output terminals of the voltage conversion module can be connected to the TSV that runs through the chip via the back interconnect layer, thereby achieving electrical connection with the external (upper or lower) power supply network and the internal front functional circuitry.

[0180] For example, when multiple functional layer chips are stacked in a face-to-back (F2B) configuration, the front of one chip corresponds to the back of another. For instance, the input terminal (receiving a first voltage) of a voltage conversion module located on the back of an upper-layer chip can be directly connected to the power supply network provided on the front of the lower-layer chip via bonding points.

[0181] In at least one embodiment of this disclosure, by integrating the voltage conversion modules of each layer onto the back of the corresponding functional layer chip, the final power supply path between the core circuit of each layer and its dedicated power supply is greatly shortened (only separated by chip thickness and TSV), effectively minimizing the IR voltage drop and parasitic inductance of this path, and providing a clean and fast-responding power supply for the functional circuit; the power conversion circuit that may generate heat and switching noise is naturally isolated from the dense signal circuit (located on the front of the chip) that is extremely sensitive to heat and noise in space by the silicon substrate, which plays the role of heat diffusion and electromagnetic shielding, significantly improving the thermal management and signal integrity of the system.

[0182] In some embodiments of the present disclosure, the integrated circuit chip 1000 is a three-dimensional packaged chip, the first functional layer 110 is a first sub-integrated circuit chip and the second functional layer 120 is a second sub-integrated circuit chip, the first interconnect layer 150 and the second interconnect layer 160 are chip bonding layers; the first interconnect channel includes a chip bonding structure and the second interconnect channel includes a chip bonding structure.

[0183] For example, integrated circuit chip 1000 is a three-dimensional packaged chip that can be formed by vertically stacking and interconnecting multiple pre-manufactured, independent sub-integrated circuit chips (also known as "chips" or "chips") through packaging technology.

[0184] For example, the first functional layer 110 can be specifically a first sub-integrated circuit chip, and the second functional layer 120 can be specifically a second sub-integrated circuit chip. The first voltage conversion module is disposed on the side of the first sub-integrated circuit chip facing away from the substrate layer; the second voltage conversion module is disposed on the side of the second sub-integrated circuit chip facing away from the substrate layer.

[0185] For example, in a 3D packaged chip, the first interconnect layer 150 and the second interconnect layer 160 are not insulating films deposited in a monolithic integration process, but rather chip bonding layers that enable mechanical and electrical interconnections between chips. The bonding layers are located between two adjacent sub-chips and include a medium (such as a polymer or oxide) for bonding the chips and conductive structures for achieving electrical connections.

[0186] For example, the first and second interconnect channels used for power supply and signal transmission can be specifically embodied in the chip bonding structure.

[0187] For example, a chip bonding structure can be a microstructure formed on the surface of a sub-chip for alignment and bonding with corresponding structures on adjacent sub-chips, thereby achieving electrical connection.

[0188] For example, chip bonding structures may include micro-bumps.

[0189] For example, microbumps can include solder (such as a tin-silver-copper alloy) or copper pillars and solder caps, and can be connected to corresponding bumps on the upper and lower chips through thermoforming or reflow soldering processes. Microbumps can have a certain protrusion height to accommodate unevenness on the chip surface and alleviate thermal stress.

[0190] For example, chip bonding structures can include hybrid bonding.

[0191] For example, hybrid bonding can achieve both copper-to-copper direct connections and dielectric-to-dielectric direct connections by simultaneously bonding copper pads on the chip surface to an insulating dielectric (such as SiO2). Hybrid bonding can achieve higher interconnect density and smaller pitch, without the need for bumps, resulting in lower interconnect height.

[0192] For example, the three-dimensional packaging stacking method can include face-to-back, face-to-face, or back-to-back. Taking face-to-back as an example, the front side (active side) of the first sub-integrated circuit chip faces the substrate, and its back side is bonded to the substrate layer 100 through the first interconnect layer 150 (bonding layer). The front side of the second sub-integrated circuit chip (120) is bonded to the back side of the first sub-chip through the second interconnect layer 160 (bonding layer).

[0193] For example, each sub-integrated circuit chip may integrate the switched capacitor voltage conversion module located on its back side, as provided in the aforementioned embodiments.

[0194] For example, chip bonding structures (microbumps or hybrid bonded copper connections) are arrayed at the bonding interface, a portion of which can be used to transmit the first voltage, forming a vertical power supply channel; another portion can be used to transmit signals, clocks, etc., and the embodiments disclosed herein do not limit this.

[0195] For example, starting from the chip voltage port 130 on the substrate 100, a first voltage can be transmitted to the first sub-integrated circuit chip through the bonding structure (first interconnect channel) in the first interconnect layer 150. This voltage can directly reach the input terminal of the first voltage conversion module 111 integrated on the back of the first sub-chip, or it can be further transmitted through structures such as TSVs inside the first sub-chip. For example, the first voltage can continue upwards, reaching a specific location on its front or back side through a TSV (if any) penetrating the first sub-integrated circuit chip, and then be transmitted to the second sub-integrated circuit chip through the bonding structure (second interconnect channel) in the second interconnect layer 160, and then reach the second voltage conversion module 121 on its back side.

[0196] In at least one embodiment of this disclosure, by utilizing the chip bonding structure inherent in three-dimensional packaging as an interlayer vertical interconnect channel, the advantages of three-dimensional packaging in heterogeneous integration and design flexibility can be fully utilized; at the same time, combined with the layout of voltage conversion modules integrated on the back of each sub-integrated circuit chip, the power delivery path and thermal noise isolation are further optimized.

[0197] In some embodiments of the integrated circuit chip 1000 provided in this disclosure, a first voltage conversion module 111 is disposed on the side of the first sub-integrated circuit chip facing away from the substrate layer 100; a second voltage conversion module 121 is disposed on the side of the second sub-integrated circuit chip facing away from the substrate layer 100; the first voltage conversion module 111 in the first sub-integrated circuit chip is electrically connected to the functional circuit portion of the first sub-integrated circuit chip through a through-silicon via; the second voltage conversion module 121 in the second sub-integrated circuit chip is electrically connected to the functional circuit portion of the second sub-integrated circuit chip through a through-silicon via.

[0198] For example, in the architecture of a three-dimensional packaged chip, in the first sub-integrated circuit chip (i.e., the first functional layer 110), the integrated first voltage conversion module 111 (e.g., it may be located on the back of the chip) is electrically connected to the functional circuit portion 113 inside the first sub-integrated circuit chip through a through-silicon via.

[0199] For example, in the second sub-integrated circuit chip (i.e., the second functional layer 120), the integrated second voltage conversion module 121 (e.g., may be located on the back of the chip) is electrically connected to the functional circuit portion inside the second sub-integrated circuit chip through a through-silicon via.

[0200] For example, the functional circuitry can be the core computing or storage unit of each sub-integrated circuit chip, such as logic circuits, computing cores (e.g., CPU, GPU, NPU), cache, memory arrays (e.g., SRAM, eDRAM), input / output interface circuits, or analog / RF circuits, etc., and the embodiments disclosed herein are not limited thereto. For example, these functional circuits can be fabricated on the front side (i.e., the active side) of the sub-integrated circuit chip.

[0201] For example, a through-silicon via (TSV) can be a vertical conductive channel that penetrates the silicon substrate or part of the silicon body of each sub-integrated circuit chip. It can be fabricated, for example, during the manufacturing process of each sub-integrated circuit chip using processes such as deep hole etching, insulating / barrier layer deposition, and copper filling.

[0202] For example, a voltage conversion module located on the back of a sub-integrated circuit chip can efficiently and with low loss deliver its generated operating voltage (such as 1.8V, 0.9V) from the back of the sub-integrated circuit chip to the functional circuit section on the front via a TSV, directly powering the latter.

[0203] For example, a TSV can also be used to transfer a first voltage (such as 12V) from the front bonding interface of a sub-integrated circuit chip to the input terminal of a voltage conversion module on the back, thereby enabling power input. That is, a single sub-integrated circuit chip can include multiple TSVs, which are used to transmit the input high voltage and the output operating voltage, respectively.

[0204] For example, a uniform first voltage (e.g., 12V) provided externally can enter the integrated circuit chip through the chip voltage port 130 on the substrate. This first voltage can enter the first sub-integrated circuit chip through the bonding structure of the first interconnect layer 150, and reach the first voltage conversion module 111 on its back side via the internal interconnects (e.g., including TSVs) of the first sub-integrated circuit chip. The first voltage conversion module 111 can convert 12V into a first operating voltage (e.g., 1.2V) required by the first sub-integrated circuit chip, and the converted 1.2V can be directly delivered to the functional circuit section on the front side through a through-silicon via. For example, the first voltage of 12V can continue to be transmitted through the interconnects of the first sub-integrated circuit chip and the bonding structure of the second interconnect layer 160 above it to the second voltage conversion module 121 on the back side of the second sub-integrated circuit chip. The second voltage conversion module 121 can convert it into a second operating voltage (e.g., 0.9V) required by the second sub-integrated circuit chip, and the converted 0.9V can be delivered to the functional circuit section on the front side of the second sub-integrated circuit chip through a through-silicon via.

[0205] In at least one embodiment of this disclosure, by using through-silicon vias as a vertical path between the back-side voltage conversion module and the front-side functional circuit of the connecting integrated circuit chip, an extremely short, efficient, and low-noise final power supply link is constructed inside the three-dimensional packaged chip; overcoming the technical problems of loss and delay in the horizontal long-distance transmission of operating voltage inside the chip.

[0206] Figure 5 A schematic block diagram illustrating the application architecture of an integrated circuit chip provided in at least one embodiment of this disclosure is shown.

[0207] like Figure 5 As shown, the integrated circuit chip is a three-dimensional stacked integrated circuit chip power supply architecture.

[0208] For example, deploying only one board-level DC-DC conversion module converts the externally input 48V to 12V and transmits it to the chip through bumps ("R_Bump, L_Bump" in the figure are the parasitic resistance and inductance of the bumps). Compared with the multi-module design, this greatly reduces the PCB area occupied and also reduces the cost and complexity of the board-level power module.

[0209] For example, functional layers (1 / 2 / 3): Each functional layer integrates a BEOL (back-end process compatible) on-chip voltage conversion module, which directly converts the 12V input from the board to its own operating voltage.

[0210] Functional layer 1: 12V→5V;

[0211] Functional layer 2: 12V→18V;

[0212] Functional layer 3: 12V → 3.3V;

[0213] For example, for interlayer interconnects, 12V high voltage can be transmitted through through silicon vias (TSVs) (the current is only 1 / 5 to 1 / 18 of that of the low voltage at the same power), which greatly reduces the parasitic loss (IR drop) of the power supply path across layers.

[0214] In at least one embodiment of this disclosure, the on-chip module is integrated using back-to-end (BEOL) technology, which does not damage the functional circuitry fabricated in the front end; only one DC-DC module is required at the board level, reducing chip pin occupancy (only one set of 12V input pins is required); each functional layer completes voltage conversion locally, shortening the power supply path and solving the problems of power loss and increased IR drop caused by the increase in the number of layers in traditional solutions.

[0215] Figure 6 A schematic block diagram illustrating the application architecture of another integrated circuit chip provided in at least one embodiment of this disclosure is shown.

[0216] like Figure 6 As shown, the integrated circuit chip is a monolithic 3D integrated (M3D) power supply architecture.

[0217] For example, on the board-level power supply side, only one board-level DC-DC conversion module is configured to convert the externally input 48V high voltage to 12V, and then transmit it to the integrated circuit chip through the bump structure on the bottom of the chip (including parasitic resistance R_Bump and parasitic inductance L_Bump). Compared with the multi-module solution, this design significantly reduces the PCB board area and power module cost, while only requiring one set of 12V input pins, which significantly reduces the crowding of chip I / O resources.

[0218] For example, the chip is based on a monolithic 3D integration process. The core logic circuits of each functional layer are fabricated using semiconductor front-end processes (such as CMOS processes) to carry core functions such as computing and storage. The on-chip voltage conversion module is integrated into the layer where the logic circuit is located using back-end processes (BEOL). Its process temperature does not exceed 400°C, which can avoid damage to the logic devices fabricated in the front end. The function of this module is to convert the 12V high voltage input from the board level into the working voltage required by the logic circuit of the corresponding layer.

[0219] For example, in terms of interlayer interconnection, a structure is adopted that combines back TSV (through silicon via) and chip bonding points: the back TSV serves as a conductive channel that vertically penetrates each functional layer, enabling the rapid transmission of 12V high voltage between layers; the chip bonding points serve as electrical connection units between layers in monolithic 3D integration, ensuring stable conduction of 12V between layers.

[0220] In at least one embodiment of this disclosure, the above interconnection structure effectively shortens the cross-layer power supply path. Combined with the low current characteristics of 12V high-voltage transmission, it significantly reduces the parasitic loss and IR drop problems caused by the increase in the number of layers in traditional solutions. At the same time, it adapts to the process characteristics of monolithic 3D integrated front-end construction logic, back-end interconnection and auxiliary modules, and achieves the unity of functional integration and process compatibility.

[0221] Figure 7 A schematic diagram of a method for fabricating an integrated circuit chip according to at least one embodiment of the present disclosure is shown.

[0222] In some embodiments of this disclosure, a method for fabricating an integrated circuit chip is also provided. For example... Figure 7 As shown, the method for fabricating this integrated circuit chip includes steps S210 to S230. This method for fabricating the integrated circuit chip can be applied, for example, to the fabrication of the integrated circuit chip provided in any embodiment of this disclosure.

[0223] Step S210: Provide a first functional layer on the substrate.

[0224] Step S230: Provide a second functional layer on the side of the first functional layer away from the substrate layer.

[0225] For example, a chip voltage port is disposed on a substrate layer to receive a first voltage for the integrated circuit chip; for example, a first functional layer includes a first voltage conversion module, and a second functional layer includes a second voltage conversion module. The first voltage conversion module can be configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a first operating voltage as the operating voltage of the first functional layer; the second voltage conversion module can be configured to be electrically connected to the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a second operating voltage as the operating voltage of the second functional layer.

[0226] In some embodiments of this disclosure, the method for fabricating the integrated circuit chip further includes step S200 after step S210.

[0227] Step S200: Provide a chip voltage conversion module.

[0228] For example, a chip voltage conversion module is connected to a chip voltage port and configured to provide a first voltage through the chip voltage port.

[0229] For example, the chip voltage conversion module is located on the side of the substrate layer opposite to the first functional layer.

[0230] In some embodiments of this disclosure, step S210 may further include step S211: providing a first voltage conversion module.

[0231] In some embodiments of this disclosure, step S220 may further include step S221: providing a second voltage conversion module.

[0232] For example, the specific operation method, function or beneficial effect of the above-mentioned integrated circuit chip fabrication method can be found in the description of the integrated circuit chip embodiment provided in any embodiment of this disclosure, and will not be repeated here.

[0233] Figure 8 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0234] like Figure 8 As shown, the electronic device 300 includes an integrated circuit chip 400.

[0235] For example, the integrated circuit chip 400 can be any of the integrated circuit chips provided in the above embodiments. For example, the electronic device 300 may further include other devices, such as a central processing unit (CPU), a data bus, memory, etc. The electronic device 300 can be a signal processing device, a computing device, etc., and for example, it can be used as a controller, terminal equipment, or server equipment.

[0236] In addition to the illustrative descriptions above, the following points also need to be noted in this disclosure:

[0237] (1) The accompanying drawings of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0238] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0239] (3) It should be understood that in the embodiments of this disclosure, the order of the above steps does not mean the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0240] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An integrated circuit chip comprising: a substrate layer, a first functional layer, a second functional layer, and a chip voltage port, wherein the substrate layer, the first functional layer, and the second functional layer are at least partially stacked, the first functional layer is disposed above the substrate layer, and the second functional layer is disposed on a side of the first functional layer away from the substrate layer; the chip voltage port is disposed on the substrate layer to receive a first voltage for the integrated circuit chip; the first functional layer includes a first voltage conversion module configured to electrically connect with the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a first operating voltage as an operating voltage of the first functional layer; the second functional layer includes a second voltage conversion module configured to electrically connect with the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a second operating voltage as an operating voltage of the second functional layer.

2. The integrated circuit chip of claim 1, further comprising a chip voltage conversion module, wherein the chip voltage conversion module is connected with the chip voltage port and configured to provide the first voltage through the chip voltage port.

3. The integrated circuit chip of claim 1, wherein, the chip voltage conversion module is disposed on a side of the substrate layer opposite to the first functional layer.

4. The integrated circuit chip of claim 1, wherein, at least one of the first voltage conversion module and the second voltage conversion module includes a switched-capacitor voltage conversion module and a linear voltage regulator, wherein the switched-capacitor voltage conversion module is configured to receive the first voltage provided by the chip voltage port, and step-down convert the first voltage to generate a corresponding intermediate voltage; the linear voltage regulator is configured to adjust the corresponding intermediate voltage to output a corresponding operating voltage.

5. The integrated circuit chip of claim 4, wherein, the switched-capacitor voltage conversion module includes a plurality of switched-capacitor voltage conversion units arranged in an array, the plurality of switched-capacitor voltage conversion units are uniformly distributed among each other to form a wiring area for laying an interlayer vertical interconnection channel between adjacent switched-capacitor conversion units.

6. The integrated circuit chip of claim 4, wherein, the switched-capacitor voltage conversion module and the linear voltage regulator are stacked and disposed on a side of the switched-capacitor conversion module away from the substrate.

7. The integrated circuit chip of claim 4, wherein, the linear voltage regulator includes a low-dropout linear voltage regulator, wherein the switched-capacitor voltage conversion module is further configured to step-down convert the first voltage by an integer multiple to output the corresponding intermediate voltage; and the low-dropout linear voltage regulator is configured to linearly adjust the corresponding intermediate voltage by a decimal ratio to output the corresponding operating voltage.

8. The integrated circuit chip of any of claims 1-7, wherein, a first interconnection layer is disposed between the first functional layer and the substrate layer, and a second interconnection layer is disposed between the second functional layer and the first functional layer; The chip voltage port is configured to be electrically connected with the first voltage conversion module through the first interconnection channel in the first interconnection layer, and to be electrically connected with the second voltage conversion module through the first interconnection channel in the first interconnection layer and the second interconnection channel in the second interconnection layer.

9. The integrated circuit chip of claim 8, wherein, The integrated circuit chip is a monolithic three-dimensional integrated chip, the first functional layer and the second functional layer are semiconductor circuit layers integrated directly by a semiconductor process, and the first interconnection layer and the second interconnection layer are insulating layers integrated directly by a semiconductor process. The first interlayer interconnection channel and the second interlayer interconnection channel include interlayer vias.

10. The integrated circuit chip of claim 9, wherein, The first voltage conversion module is integrated in the first functional layer by a semiconductor process and faces away from the substrate layer. The second voltage conversion module is integrated in the second functional layer by a semiconductor process and faces away from the substrate layer.

11. The integrated circuit chip of claim 8, wherein, The integrated circuit chip is a three-dimensional packaged chip, the first functional layer is a first sub integrated circuit chip, and the second functional layer is a second sub integrated circuit chip, and the first interconnection layer and the second interconnection layer are chip bonding layers. The first interconnection channel includes a chip bonding structure, and the second interconnection channel includes a chip bonding structure.

12. The integrated circuit chip of claim 11, wherein, The first voltage conversion module is arranged on a side of the first sub integrated circuit chip facing away from the substrate layer. The second voltage conversion module is arranged on a side of the second sub integrated circuit chip facing away from the substrate layer. The first voltage conversion module in the first sub integrated circuit chip is electrically connected with a functional circuit part in the first sub integrated circuit chip through a through silicon via. The second voltage conversion module in the second sub integrated circuit chip is electrically connected with a functional circuit part in the second sub integrated circuit chip through a through silicon via.

13. A method for manufacturing an integrated circuit chip, comprising: providing a first functional layer on a substrate layer, wherein a chip voltage port is arranged on the substrate layer to receive a first voltage for the integrated circuit chip; providing a second functional layer on a side of the first functional layer away from the substrate layer, wherein the first functional layer includes a first voltage conversion module, and the second functional layer includes a second voltage conversion module, wherein the first voltage conversion module is configured to be electrically connected with the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a first working voltage as a working voltage of the first functional layer; the second voltage conversion module is configured to be electrically connected with the chip voltage port, receive the first voltage provided by the chip voltage port, and convert the first voltage into a second working voltage as a working voltage of the second functional layer.

14. An electronic device comprising the integrated circuit chip of any one of claims 1-12.

Images