Chip packaging structure, manufacturing method thereof and electronic equipment

Abstract

The invention provides a chip packaging structure, a manufacturing method thereof and electronic equipment. The chip packaging structure comprises a substrate; a groove is formed in one side of the base plate; the first chip is arranged in the groove; at least one second chip; the second chip is electrically connected with the first chip through the conductive structure; a first heat dissipation channel is formed between the first chip and the second chip; the packaging layer is arranged on one side, far away from the substrate, of the second chip; the packaging layer wraps the side part of the second chip and a part of the substrate; the packaging layer is provided with a through hole; the through hole is communicated with the first heat dissipation channel to form a heat dissipation channel. A first heat dissipation channel is arranged between a first chip and a second chip, at least two through holes are formed in a packaging layer, and the first heat dissipation channel and the through holes are communicated to form a heat dissipation channel, so that heat dissipation can be directly performed on the first chip and the second chip by using a cooling medium in the heat dissipation channel; and the heat dissipation efficiency of the chip packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a chip packaging structure, its manufacturing method, and an electronic device. Background Technology

[0002] With the development of electronic technology, consumers have increasingly higher demands for electronic products, and these products are integrating more and more functions. To meet the requirements of high integration and miniaturization, chips are packaged to form chip package structures.

[0003] However, the performance of current chip packaging structures needs to be improved. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a chip packaging structure, a method for manufacturing the same, and an electronic device, which is beneficial to improving the performance of the chip packaging structure.

[0005] To achieve the above objectives, one embodiment of this application provides a chip packaging structure, comprising: a substrate; a groove formed on one side of the substrate; a first chip disposed in the groove; at least one second chip; the second chip being electrically connected to the first chip via a conductive structure; a first heat dissipation channel being formed between the first chip and the second chip; an encapsulation layer disposed on the side of the second chip away from the substrate; the encapsulation layer covering the side portion of the second chip and a portion of the substrate; the encapsulation layer having at least two through holes; the through holes communicating with the first heat dissipation channel to form a heat dissipation channel.

[0006] In some implementations, at least a portion of the front of the first chip is exposed in the first heat dissipation channel.

[0007] In some implementations, at least a portion of the front of the second chip is exposed in the first heat dissipation channel.

[0008] In some embodiments, the orthographic projection of the side of the first chip on the substrate at least partially overlaps with the orthographic projection of the heat dissipation channel on the substrate.

[0009] In some embodiments, the orthographic projection of the side of the first chip on the substrate is within the orthographic projection of the heat dissipation channel on the substrate.

[0010] In some embodiments, the chip packaging structure further includes a connection layer; the connection layer is disposed between the first chip and the substrate; the connection layer is used to connect the first chip and the substrate.

[0011] In some embodiments, the width of the via in the first direction is greater than or equal to the height of the first heat dissipation channel in the second direction; the second direction is the stacking direction of the chip package structure; the first direction intersects the second direction.

[0012] In some embodiments, the height of the first heat dissipation channel in the second direction ranges from 20μm to 500μm; the second direction is the stacking direction of the chip packaging structure.

[0013] In some embodiments, the encapsulation layer includes a first encapsulation layer; the orthographic projection of the first encapsulation layer on the substrate overlaps with the orthographic projection of the second chip on the substrate; the thickness of the first encapsulation layer in a second direction ranges from 20 μm to 300 μm; the second direction is the stacking direction of the chip encapsulation structure.

[0014] One embodiment of this application provides a method for fabricating a chip package structure. The method is applied to fabricating any of the chip package structures described above, comprising: providing the substrate; forming a groove on one side of the substrate; placing a first chip in the groove; forming a conductive structure on the side of the first chip away from the substrate; forming at least one second chip on the side of the conductive structure away from the substrate; forming a first heat dissipation channel between the second chip and the first chip; forming an encapsulation layer on the side of the second chip away from the substrate; the encapsulation layer covering the side portion of the second chip and a portion of the substrate; forming at least two through holes in the encapsulation layer; the through holes communicating with the first heat dissipation channel to form the heat dissipation channel.

[0015] One embodiment of this application provides an electronic device, which includes any of the chip packaging structures described above.

[0016] One embodiment of this application provides a chip packaging structure that, compared with the prior art, has the following advantages: by constructing a connected heat dissipation channel in the chip gap and the packaging layer, heat dissipation can be directly achieved using a cooling medium, thereby improving heat dissipation efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0019] Figure 2 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0020] Figure 3 This is a flowchart illustrating a method for fabricating a chip packaging structure according to one embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure of a substrate provided for one embodiment of this application.

[0022] Figure 5 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0023] Figure 6 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0024] Figure 7 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0025] Figure 8 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0026] Figure 9 This is a schematic diagram of a chip packaging structure provided for one embodiment of this application.

[0027] Marker explanation: 100. Chip packaging structure; 110. Substrate; 111. Groove; 112. Conductive pillar; 113. First pad; 114. Second pad; 115. Metal wiring; 116. Solder ball; 117. First via; 120. First chip; 121. Second via; 122. Second chip; 130. Conductive structure; 131. First heat dissipation channel; 140. Encapsulation layer; 141. Through hole; 142. First encapsulation layer; 150. Heat dissipation channel; 160. Connecting layer; 170. Dielectric layer. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0029] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0030] The features and implementation methods of various aspects of this application will now be described in detail. Furthermore, the features, structures, or characteristics described in this application may be combined in any suitable manner in one or more implementations.

[0031] Currently, in the semiconductor technology field, chip packaging structures are crucial for protecting chips and enhancing their electrothermal performance. Common chip packaging structures typically include a substrate, a chip mounted on one side of the substrate, and a packaging layer located on the side of the chip away from the substrate and encapsulating its sides. However, existing chip packaging structures of this type generally suffer from insufficient heat dissipation capabilities.

[0032] Please see Figure 1 and Figure 4 To address the aforementioned problems, one embodiment of this application provides a chip packaging structure 100, comprising: a substrate 110; a groove 111 is provided on one side of the substrate 110; a first chip 120 is disposed in the groove 111; at least one second chip 122; the second chip 122 is electrically connected to the first chip 120 through a conductive structure 130; a first heat dissipation channel 131 is formed between the first chip 120 and the second chip 122; an encapsulation layer 140 is disposed on the side of the second chip 122 away from the substrate 110; the encapsulation layer 140 covers the side portion of the second chip 122 and a portion of the substrate 110; the encapsulation layer 140 is provided with at least two through holes 141; the through holes 141 communicate with the first heat dissipation channel 131 to form a heat dissipation channel 150.

[0033] In this embodiment, the chip packaging structure 100 may include a substrate 110, a first chip 120, at least one second chip 122, and a packaging layer 140. A groove 111 is provided on one side of the substrate 110, and the first chip 120 is disposed in the groove 111. The first chip 120 and the second chip 122 are electrically connected through a conductive structure 130.

[0034] In this embodiment, the substrate 110 serves as the support carrier for the entire package and is typically made of an insulating material. For example, the substrate 110 can be an organic resin substrate 110, a ceramic substrate 110, or a silicon substrate 110. A groove 111 is provided on one side of the substrate 110. The function of the groove 111 is to provide a positioning and mounting space for accommodating subsequent chips, which helps to improve the integration and structural stability of the package, while also reducing the overall thickness of the chip package structure 100.

[0035] In this embodiment, the chip package structure 100 may include a first chip 120, which is disposed within the recess 111 with its back side facing the substrate 110. The back side is the side opposite to the front side of the chip. The front side of the chip refers to the main functional surface formed by photolithography, etching, deposition, and other processes during chip manufacturing, which contains active areas, transistors, interconnects, and functional pads. The back side refers to the substrate material surface opposite to the front side, which typically does not have the aforementioned fine circuit structures formed therein. The back side is usually thinned, polished, and metallized. This embedded arrangement allows the first chip 120 to achieve a tight physical bond with the substrate 110. Specifically, the first chip 120 can be fixed within the recess 111 by a connecting layer 160, which can be an adhesive or a chip bonding film. Its function is to achieve a mechanical connection and possible thermal conductivity between the first chip 120 and the substrate 110.

[0036] In this embodiment, the chip package structure 100 may further include at least one second chip 122, which is at least one secondary chip stacked on top of the first chip 120, and together with the first chip 120, constitutes a vertically integrated multifunctional chipset. The second chip 122 also has a front side with integrated active circuitry and functional pads, and a back side as a substrate body.

[0037] In this embodiment, the second chip 122 can be soldered using a flip-chip method. Specifically, the second chip 122 can face the first chip 120, and the front side of the second chip 122 is electrically connected to the first chip 120 through a conductive structure 130. For example, the first chip 120 is provided with a first pad 113, and the second chip 122 is provided with a second pad 114. The two ends of the conductive structure 130 are electrically connected to the two pads respectively, so that the first chip 120 and the second chip 122 are electrically connected. By providing the conductive structure 130 between the first chip 120 and the second chip 122, and maintaining a certain gap between the first chip 120 and the second chip 122, a first heat dissipation channel 131 is formed between the first chip 120 and the second chip 122. This first heat dissipation channel 131 is a cavity or gap located between chip stacking layers, and its function is to provide a path for the flow of cooling medium so as to remove the heat generated during chip operation in a timely manner.

[0038] In this embodiment, the conductive structure 130 is an interconnecting medium formed between the first chip 120 and the second chip 122 to achieve electrical connection between the two. While providing a path for electrical signal transmission and power supply, the conductive structure 130 itself has a specific geometric height in the stacking direction of the chip package structure 100. This physical characteristic defines and maintains a preset gap space between the first chip 120 and the second chip 122, which constitutes an important part of the first heat dissipation channel 131.

[0039] Specifically, the conductive structure 130 may include at least one of a first solder ball, a copper pillar, or a composite bump with a metal core. The conductive structure 130 can be metallurgically bonded to the first pad 113 on the first chip 120 and the second pad 114 on the front side of the second chip 122 via a reflow soldering process, thereby establishing a robust electrical and mechanical connection.

[0040] In this embodiment, the conductive structure 130 ensures reliable transmission of signals and power between chips. Its inherent height creates vertical space in the chip stack, providing a structural basis for the formation of the first heat dissipation channel 131. When at least part of the conductive structure 130 is located in the first heat dissipation channel 131, the cooling medium flowing through it can simultaneously provide auxiliary heat dissipation for the conductive structure 130 itself.

[0041] In this embodiment, the chip packaging structure 100 further includes an encapsulation layer 140. The material of the encapsulation layer 140 may include at least one controlled-flow material selected from polyimide, benzoxazine, or modified epoxy resin. The encapsulation layer 140 is disposed on the side of the second chip 122 away from the substrate 110, and the encapsulation layer 140 covers the side portion of the second chip 122. The encapsulation layer 140 may also cover a portion of the substrate 110. The encapsulation layer 140 provides physical protection, mechanical support, and environmental protection for the first chip 120 and the second chip 122 inside the chip packaging structure 100. Specifically, the encapsulation layer 140 can be formed by a thermal pressing process and covers the side portion of the second chip 122 and a portion of the front surface of the first chip 120, thereby securely encapsulating the chip stack structure together.

[0042] In this embodiment, the encapsulation layer 140 is provided with at least two through holes 141. These through holes 141 are connected to the first heat dissipation channel 131, together forming a complete heat dissipation channel 150. Specifically, the two through holes 141 can be respectively disposed at both ends of the encapsulation layer 140, increasing the area for cooling medium flow and improving the heat dissipation effect of the chip encapsulation structure 100. The heat dissipation channel 150 can penetrate the encapsulation layer 140 and extend into the space between the first chip 120 and the second chip 122, allowing external cooling medium to enter the first heat dissipation channel 131 through one through hole 141 and flow out of the first heat dissipation channel 131 through the other through hole 141, directly and efficiently cooling the first chip 120 and the second chip 122.

[0043] In this embodiment, by constructing a connected first heat dissipation channel 131 inside the chip package structure 100 and opening a through-hole 141 on the package layer 140, a heat dissipation channel 150 is formed that runs directly from the outside of the chip package structure 100 to the heat sources of the first chip 120 and the second chip 122. This solves the problem of excessively high chip junction temperature and limited performance caused by poor heat dissipation path and excessive thermal resistance in the existing chip package structure 100, and improves the heat dissipation capacity of the package to a certain extent, allowing the chip to operate stably at higher power, thereby improving the reliability and performance of the chip package structure 100.

[0044] In some embodiments, the cooling medium can be a gaseous cooling medium. For example, the gaseous cooling medium can be air or an inert gas. The cooling medium can also be a liquid cooling medium. For example, the liquid cooling medium can be water, fluorinated liquid, or heat transfer oil. The flow of the cooling medium can be driven by natural convection or by an external forced drive device. Specifically, for example, the forced drive device can be an external air-cooling device. When the external air-cooling device is connected to the heat dissipation channel 150, the cooling medium is forcibly blown into or drawn into the heat dissipation channel 150. The forced drive device can be an external liquid-cooling device. When the heat dissipation channel 150 is connected to an external liquid-cooling device, the cooling medium is pumped into the heat dissipation channel 150. By allowing the cooling medium to directly enter the interior of the chip packaging structure 100 and directly contact the chip surface, the heat exchange efficiency is enhanced to a certain extent, thereby achieving active heat dissipation of the chip packaging structure 100.

[0045] In some embodiments, the chip package structure 100 may further include a conductive post 112 that penetrates the substrate 110 and embeds the first chip 120, and is electrically connected to the first pad 113 for electrically connecting the first chip 120 to the metal wiring 115 and / or solder balls 116 on the other side of the substrate 110.

[0046] In some embodiments, the side of the substrate 110 away from the first chip 120 may also be provided with metal wiring 115 and solder balls 116. The metal wiring 115 is used to electrically connect the conductive post 112 and the solder balls 116.

[0047] In some embodiments, a dielectric layer 170 is provided on the side of the substrate 110 away from the first chip 120. The dielectric layer covers a portion of the solder balls 116. The side of the solder balls 116 away from the substrate 110 is not covered by the dielectric layer 170. This portion is used for electrical connection with other external structures. The dielectric layer 170 is electrically isolated between the metal wiring 115 and / or the solder balls 116.

[0048] In some implementations, at least a portion of the front of the first chip 120 is exposed in the first heat dissipation channel 131.

[0049] In this embodiment, at least a portion of the front surface of the first chip 120 is configured to be directly exposed within the cavity defined by the first heat dissipation channel 131. The front surface of the first chip 120 is the core heat-generating area during chip operation. By directly facing and contacting the cooling medium flowing through the first heat dissipation channel 131 with the heat-generating surface of the first chip 120, the cooling medium (whether it is a forced convection gas or liquid) can directly and forcibly convect heat transfer with the heat source without intermediate medium obstruction, thereby achieving the shortest and lowest thermal resistance heat transfer path from the chip junction region to the cooling medium at the physical level. This enhances the heat exchange efficiency and heat dissipation rate of the first chip 120 to a certain extent, ensuring that the core heat of the first chip 120 is quickly and efficiently dissipated, thereby effectively reducing the operating junction temperature of the first chip 120 and improving the power load capacity and long-term operational reliability of the entire chip package structure 100.

[0050] In some implementations, at least a portion of the front of the second chip 122 is exposed in the first heat dissipation channel 131.

[0051] In this embodiment, at least a portion of the front surface of the second chip 122 is exposed in the first heat dissipation channel 131, and the front surface of the first chip 120 corresponds to the front surface of the second chip 122, which can improve heat dissipation efficiency and reduce the thickness of the chip package structure 100. At least a portion of the front surface of the second chip 122 is also configured to be directly exposed inside the cavity defined by the first heat dissipation channel 131. This structural feature, in conjunction with the exposed area of ​​the front surface of the first chip 120, enables synchronous heat dissipation of multiple chips in the chip package structure 100.

[0052] Specifically, the front side of the second chip 122, as its main functional surface integrating active devices and interconnects, also generates significant heat during operation. By making its front side directly face the first heat dissipation channel 131, the cooling medium flowing through this channel can directly cool both the first chip 120 and the second chip 122, the two main heat sources, simultaneously. The front sides of the first chip 120 and the second chip 122 are spatially opposite each other. This front-to-front arrangement of the first chip 120 and the second chip 122 has the following effects: In terms of heat dissipation, it allows the two chips' main heat-generating surfaces to share and be exposed to the same heat dissipation channel 150, increasing the effective heat dissipation area, optimizing the cooling medium flow field, and thus improving overall heat dissipation efficiency. In addition, this structure avoids the additional intermediary or adhesive layers required for back-to-back or front-to-back stacking of the first chip 120 and the second chip 122, helping to reduce the overall thickness of the entire chip package structure 100 in the vertical direction.

[0053] This chip packaging structure 100 not only achieves coordinated heat dissipation for multiple chips and effectively controls the overall temperature of stacked chips, but also simultaneously optimizes the vertical dimensions of the packaging structure, providing a compact and efficient thermal management solution for high-density, high-performance chip stacking packaging.

[0054] In some embodiments, the orthographic projection of the side of the first chip 120 on the substrate 110 at least partially overlaps with the orthographic projection of the heat dissipation channel 150 on the substrate 110.

[0055] In this embodiment, the side of the first chip 120 is the side boundary of the first chip 120 parallel to the stacking direction of the chip package structure 100. The vertical projection outline of the side of the first chip 120 on the surface of the substrate 110 at least partially overlaps with the vertical projection area of ​​the heat dissipation channel 150 in the package layer 140 on the surface of the substrate 110. That is, when viewed from a direction perpendicular to the plane of the substrate 110, the side projection of the first chip 120 and the projection area of ​​the heat dissipation channel 150 partially overlap, rather than being completely separated.

[0056] This structural relationship ensures that the heat dissipation channel 150 can cover part of the front edge of the first chip 120. This overlapping layout provides a channel for the cooling medium to flow into and out of the heat dissipation space at part of the edge of the first chip 120.

[0057] In some embodiments, the orthographic projection of the side of the first chip 120 on the substrate 110 lies within the orthographic projection of the heat dissipation channel 150 on the substrate 110.

[0058] In this embodiment, when viewed from a direction perpendicular to the plane of the substrate 110, the orthographic projection of the side of the first chip 120 onto the substrate 110 is completely covered by the heat dissipation channel 150. The side of the first chip 120 can be its lateral boundary parallel to the stacking direction of the chip package structure 100. The first chip 120 is completely contained within the boundary range of the orthographic projection of the heat dissipation channel 150 onto the substrate 110, thereby increasing the contact area between the first chip 120 and the cooling medium, and thus improving the heat dissipation effect of the chip package structure 100.

[0059] In some embodiments, the chip package structure 100 further includes a connection layer 160; the connection layer 160 is disposed between the first chip 120 and the substrate 110; the connection layer 160 is used to connect the first chip 120 and the substrate 110.

[0060] In this embodiment, the chip packaging structure 100 may further include a connection layer 160. This connection layer 160 is disposed between the first chip 120 and the substrate 110, achieving a stable and reliable mechanical connection and physical fixation between the first chip 120 and the substrate 110. Specifically, the connection layer 160 may refer to an adhesive dielectric layer 170 between the chip and the substrate 110. For example, the connection layer 160 may be a chip adhesive made of polymer materials such as epoxy resin, polyimide, or silicone gel, or it may be an anisotropic conductive film or a non-conductive film. Through its own adhesive properties, the connection layer 160 firmly bonds the back side of the first chip 120 to the groove 111 on the substrate 110 or to the surface of the substrate 110.

[0061] In this embodiment, the interconnect layer 160 provides the necessary mechanical strength to ensure that the first chip 120 is stably positioned on the substrate 110 during subsequent chip stacking, molding process, and device service life, preventing displacement or detachment, thereby improving the mechanical reliability of the entire package structure. The interconnect layer 160 also effectively improves the heat conduction path from the first chip 120 to the substrate 110. The heat generated by the first chip 120 during operation can be partially transferred downwards to the substrate 110 and dissipated through the interconnect layer 160, forming another important auxiliary heat dissipation path besides the heat dissipation channel 150, enhancing the overall thermal management capability.

[0062] In some embodiments, the width of the via 141 in the first direction (X) is greater than or equal to the height of the first heat dissipation channel 131 in the second direction (Y); the second direction is the stacking direction of the chip package structure 100; the first direction intersects the second direction.

[0063] In this embodiment, the width of the via 141 in the first direction is set to be greater than or equal to the height of the first heat dissipation channel 131 in the second direction; wherein, the second direction is the stacking direction of the chip package structure 100, that is, the thickness direction of the chip stack, and the first direction intersects the second direction, which is usually a horizontal direction parallel to the surface of the substrate 110. This dimensional relationship can, to a certain extent, ensure that the inlet area of ​​the via 141 is sufficient to support sufficient cooling medium flow into the relatively narrow inter-chip gap, preventing the inlet from becoming a heat dissipation bottleneck.

[0064] In some embodiments, the height of the first heat dissipation channel 131 in the second direction ranges from 20μm to 500μm; the second direction is the stacking direction of the chip packaging structure 100.

[0065] In this embodiment, the height of the first heat dissipation channel 131 in the second direction can be greater than or equal to 20 μm and less than or equal to 500 μm. Within the above range, the first heat dissipation channel 131 can ensure effective flow of the cooling medium and avoid increasing the thickness of the entire chip package structure 100.

[0066] Specifically, for example, the height of the first heat dissipation channel 131 can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, 210μm, 220μm, 230μm, 240μm, 250μm, 260μm, 270μm, 280μm, 290μm, 300μm, 310μm, 320μm, 330μm, 340μm, 350μm, 360μm, 370μm , 380μm, 390μm, 400μm, 410μm, 420μm, 430μm, 440μm, 450μm, 460μm, 470μm, 480μm, 490 or 500μm.

[0067] When the height of the first heat dissipation channel 131 in the second direction is less than 20 μm, the flow resistance is too high, and the cooling medium cannot flow effectively. When the height of the first heat dissipation channel 131 in the second direction is greater than 500 μm, it will unnecessarily increase the thickness of the entire package structure, which goes against the trend of miniaturization.

[0068] Please see Figure 2 In some embodiments, the encapsulation layer 140 includes a first encapsulation layer 142; the orthographic projection of the first encapsulation layer 142 on the substrate 110 overlaps with the orthographic projection of the second chip 122 on the substrate 110; the thickness of the first encapsulation layer 142 in a second direction ranges from 20 μm to 300 μm; the second direction is the stacking direction of the chip encapsulation structure 100.

[0069] In this embodiment, the encapsulation layer 140 may further include a first encapsulation layer 142. The orthographic projection of the first encapsulation layer 142 on the substrate 110 overlaps with the orthographic projection of the second chip 122 on the substrate 110, meaning that it is mainly used to cover and protect the second chip 122. The thickness of the first encapsulation layer 142 in the second direction of the stacking direction of the chip package structure 100 is greater than or equal to 20 μm and less than or equal to 300 μm. This thickness range can minimize the overall thickness of the chip package structure 100 while ensuring sufficient protection for the second chip 122.

[0070] Specifically, for example, the thickness of the first encapsulation layer 142 in the second direction can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, 210μm, 220μm, 230μm, 240μm, 250μm, 260μm, 270μm, 280μm, 290μm, or 300μm, etc.

[0071] When the thickness of the first encapsulation layer 142 in the second direction is less than 20 μm, the thickness of the first encapsulation layer 142 is too thin, resulting in the first encapsulation layer 142 being unable to provide sufficient protection for the second chip 122. When the thickness of the first encapsulation layer 142 in the second direction is greater than 300 μm, the thickness of the first encapsulation layer 142 is too thick, thereby increasing the overall thickness of the chip encapsulation structure 100.

[0072] Please see Figure 3 One embodiment of this application provides a method for manufacturing a chip package structure 100. This method is applicable to manufacturing any of the aforementioned chip package structures 100 and includes the following steps: Step S110: Provide substrate 110.

[0073] In this embodiment, a substrate 110 is provided to provide a basis for fabricating the chip package structure 100. Specifically, the substrate 110 can be a rigid substrate 110, a flexible substrate 110, or a rigid-flexible composite substrate 110.

[0074] Please see Figure 4 Step S120: A groove 111 is provided on one side of the substrate 110.

[0075] In this embodiment, a groove 111 can be formed on one side of the substrate 110 by means of etching, laser ablation or mechanical processing to provide a position for the first chip 120.

[0076] Please see Figure 5In some embodiments, after forming a groove 111 on one side of the substrate 110, a first through-hole 117 can also be formed on the substrate 110. The first through-hole 117 can be a hole penetrating the substrate 110, and it can also communicate with the groove 111. Specifically, the substrate 110 can be a glass substrate, and the method for forming the first through-hole 117 on the glass substrate can include a composite process combining laser induction and wet etching, a pure laser drilling process, a sandblasting process, or a mechanical drilling process. Specifically, the composite process combining laser induction and wet etching first uses a laser to modify the glass substrate at a preset position to form an induction trajectory, and then selectively etches the induction trajectory with a wet etching solution to form a first through-hole 117 with a high aspect ratio. Alternatively, a high-energy laser beam can be directly used to ablate the glass substrate to form the first through-hole 117 through a laser drilling process. The first through-hole 117 can also be formed by sandblasting using abrasive with a predetermined particle size, or by mechanical drilling using a precision mechanical drill bit. By fabricating the first through-hole 117 on the glass substrate, a structural basis is provided for subsequent vertical interconnects.

[0077] S130: The first chip 120 is set in the groove 111.

[0078] In this embodiment, the first chip 120 is disposed in the groove 111, thereby fixing the first chip 120. Specifically, the back side of the first chip 120 faces the substrate 110. Specifically, for example, the first chip 120 can be disposed in the groove 111 using the interconnect layer 160.

[0079] Please see Figure 6 In some embodiments, after the first chip 120 is disposed in the groove 111, a second through-hole 121 can be disposed on the first chip 120, the second through-hole 121 communicating with the first through-hole 117. A first pad 113 is disposed on the back side of the first chip 120 corresponding to the position of the second through-hole 121. A conductive post 112 can be formed in the second through-hole 121 by metal filling, the conductive post 112 electrically connecting the metal wiring 115 located on both sides of the substrate 110.

[0080] Please see Figure 7 S140: A conductive structure 130 is provided on the side of the first chip 120 away from the substrate 110.

[0081] In this embodiment, a conductive structure 130 can be formed on the side of the first chip 120 away from the substrate 110 using a reflow soldering process. Specifically, a first pad 113 is provided on the front side of the first chip 120 away from the substrate 110, and the conductive structure 130 is electrically connected to the first chip 120 through the first pad 113. The conductive structure 130 has a certain height in the second direction, so that after the second chip 122 is formed on the side of the conductive structure 130 away from the substrate 110, there is a gap between the first chip 120 and the second chip 122.

[0082] S150: At least one second chip 122 is disposed on the side of the conductive structure 130 away from the substrate 110; a first heat dissipation channel 131 is formed between the second chip 122 and the first chip 120.

[0083] In this embodiment, at least one second chip 122 is disposed on the side of the first chip 120 away from the substrate 110, and the process parameters of the conductive structure 130 are controlled such that a first heat dissipation channel 131 with a predetermined height is formed between the second chip 122 and the first chip 120. Specifically, a second pad 114 is disposed on the side of the second chip 122 facing the substrate 110, the conductive structure 130 is electrically connected to the first pad 113 and the second pad 114, and the gap between the first chip 120 and the second chip 122 is the first heat dissipation channel 131.

[0084] S160: An encapsulation layer 140 is provided on the side of the second chip 122 away from the substrate 110; the encapsulation layer 140 covers the side of the second chip 122 and part of the substrate 110.

[0085] In this embodiment, an encapsulation layer 140 is provided on the side of the second chip 122 away from the substrate 110. The encapsulation layer 140 can wrap the side of the second chip 122 and part of the substrate 110 to protect the second chip 122.

[0086] Please see Figure 8 S170: At least two through holes 141 are provided in the encapsulation layer 140; the through holes 141 are connected to the first heat dissipation channel 131 to form a heat dissipation channel 150.

[0087] In this embodiment, at least two through holes 141 can be formed on the packaging layer 140 by processes such as laser drilling, plasma etching or photolithography, and the through holes 141 are precisely aligned and connected with the first heat dissipation channel 131, thereby finally forming the heat dissipation channel 150.

[0088] A through hole 141 can be provided on the encapsulation layer 140 at a certain distance from the side of the second chip 122. The portion of the encapsulation layer 140 remaining on the side of the second chip 122 can protect the side of the second chip 122.

[0089] Because the encapsulation layer 140 is made of a controlled-flow material, which exhibits controlled flow characteristics in its uncured state, these materials are designed to exhibit limited viscous flow under specific temperature and pressure conditions to fill the sides and gaps of the second chip 122.

[0090] When fabricating the encapsulation layer 140, a certain distance is set between the encapsulation layer 140 on the side of the second chip 122 and the first chip 120, so that the first heat dissipation channel 131 extends and thus communicates with the through hole 141.

[0091] In some embodiments, the chip package structure 100 may include at least two second chips 122, with a certain distance between adjacent second chips 122. Since the package layer 140 is made of a poor-flowing packaging material, during the fabrication of the package layer 140, a certain distance is maintained between the portion of the package layer 140 between the adjacent second chips 122 and the first chip 120, so that the first heat dissipation channel 131 extends to the corresponding position between the adjacent second chips 122.

[0092] Please see Figure 9 and Figure 1 In some embodiments, after the via 141 is formed in the encapsulation layer 140, a metal wiring 115 is formed on the side of the substrate 110 away from the first chip 120. This metal wiring 115 is used for electrically connecting the conductive pillars 112. A dielectric layer 170 may also be formed on the side of the metal wiring 115 away from the substrate 110. The dielectric layer 170 may be located between wiring layers of the substrate 110, cover the surface of the rewiring layer, or exist as part of the interconnect layer 160. Its function is to prevent short circuits, provide the required dielectric strength, and maintain a stable signal transmission environment through its material properties.

[0093] Specifically, dielectric layer 170 can be composed of various inorganic or organic dielectric materials. For example, inorganic dielectric materials may include silicon dioxide, silicon nitride, or composite layers thereof, formed by chemical vapor deposition. Organic dielectric materials may include polyimide, benzocyclobutene, or polybenzoxazole, formed by spin coating, spraying, or lamination processes. These materials are selected for their low dielectric constant (to reduce parasitic capacitance), good thermal stability, and coefficient of thermal expansion that matches that of the silicon chip and metal wiring 115.

[0094] Solder balls 116 are disposed in dielectric layer 170. The solder balls 116 penetrate dielectric layer 170 and are electrically connected to metal wiring 115. Part of the solder balls 116 are exposed on the side of dielectric layer 170 away from substrate 110 for electrical connection with external structure.

[0095] One embodiment of this application provides an electronic device, which includes any of the above-described chip package structures 100.

[0096] In this embodiment, the electronic device may include any of the aforementioned chip package structures 100. The electronic device may be a smartphone, tablet computer, laptop computer, high-performance server, or display driver module, etc. Its advantage lies in that, due to the integration of the highly efficient heat dissipation chip package structure 100, the core chip in the electronic device can operate at a lower temperature, thereby improving the device's computing performance, image processing capabilities, display effect, and overall lifespan and reliability. Specifically, the chip package structure 100 can be electrically connected to other structures of the electronic device via solder balls 116.

[0097] The various embodiments described in this application emphasize the parts that differ from other embodiments, and these embodiments can be explained by comparison with each other. Any combination of the various embodiments in this specification is covered by the disclosure of this specification based on general technical knowledge and is applicable to those skilled in the art.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above are only some embodiments described in this specification and are not intended to limit this specification. Any modifications or equivalent substitutions made within the spirit and principles of this specification should be included within the scope of this specification.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a substrate; a groove is arranged on one side of the substrate; a first chip arranged in the groove; at least one second chip; the second chip is electrically connected with the first chip through a conductive structure; a first heat dissipation channel is formed between the first chip and the second chip; a packaging layer arranged on a side of the second chip away from the substrate; the packaging layer wraps a side of the second chip and part of the substrate; the packaging layer is provided with at least two through holes; the through holes are in communication with the first heat dissipation channel to form a heat dissipation channel.

2. The chip package structure of claim 1, wherein, At least part of a front surface of the first chip is exposed in the first heat dissipation channel.

3. The chip package structure of claim 1, wherein, At least part of a front surface of the second chip is exposed in the first heat dissipation channel.

4. The chip package structure of claim 1, wherein, A normal projection of a side edge of the first chip on the substrate at least partially overlaps a normal projection of the heat dissipation channel on the substrate; Preferably, the normal projection of the side edge of the first chip on the substrate is within the normal projection of the heat dissipation channel on the substrate.

5. The chip package structure of claim 1, wherein, The chip package structure further comprises a connecting layer; the connecting layer is arranged between the first chip and the substrate; the connecting layer is used to connect the first chip and the substrate.

6. The chip package structure of claim 1, wherein, A width of the through hole in a first direction is greater than or equal to a height of the first heat dissipation channel in a second direction; the second direction is a stacking direction of the chip package structure; the first direction intersects the second direction.

7. The chip package structure of claim 1, wherein, The height of the first heat dissipation channel in the second direction is in a range of 20 μm to 500 μm; the second direction is a stacking direction of the chip package structure.

8. The chip package structure of claim 1, wherein, The packaging layer comprises a first packaging layer; a normal projection of the first packaging layer on the substrate overlaps a normal projection of the second chip on the substrate; a thickness of the first packaging layer in a second direction is in a range of 20 μm to 300 μm; the second direction is a stacking direction of the chip package structure.

9. A method for fabricating a chip package structure, the method comprising: The manufacturing method is used to manufacture the chip package structure in any one of claims 1 to 8, and comprises: providing the substrate; arranging the groove on one side of the substrate; arranging the first chip in the groove; arranging the conductive structure on a side of the first chip away from the substrate; arranging at least one second chip on a side of the conductive structure away from the substrate; the second chip and the first chip form the first heat dissipation channel; arranging the packaging layer on a side of the second chip away from the substrate; the packaging layer wraps a side of the second chip and part of the substrate; arranging at least two through holes in the packaging layer; the through holes are in communication with the first heat dissipation channel to form the heat dissipation channel.

10. An electronic device, in particular, the electronic device comprises the chip package structure in any one of claims 1 to 8.

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