High-stacking chip packaging structure and method for accurate alignment of vertical leads

Abstract

The invention relates to the technical field of semiconductor processing, in particular to a high-stacking chip packaging structure and method for accurate alignment of vertical leads, and the structure comprises packaging modules, packaging interconnection layers and salient points, a plurality of packaging modules are vertically stacked, and the packaging interconnection layers are arranged between every two vertically adjacent packaging modules. The chip of the packaging module located on the upper layer deviates inwards by 100-200 microns compared with the chip of the packaging module located on the lower layer, a packaging interconnection layer is arranged on the surface of the packaging module located on the end portion, and a plurality of protruding points are arranged on the surface of the packaging interconnection layer. Compared with the prior art, the vertical leads are exposed out of the flat circular end faces through the plastic package grinding process, and in combination with the specific offset stacking design of the upper-layer chip, accurate and reliable alignment and bonding of the vertical leads among the multiple layers of modules are achieved, the stability and precision of vertical interconnection are remarkably improved, and the reliability of the vertical interconnection is improved. And parasitic inductance and resistance caused by overlong leads are greatly reduced, so that the overall electrical performance and reliability of the high-stacking chip packaging structure are guaranteed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically to a high-stack chip packaging structure and method with precise vertical lead alignment. Background Technology

[0002] As chip stacking height increases, traditional wire bonding technology faces many challenges. For example, excessively long horizontal wires lead to unstable bonding curvature, and excessively long loops introduce huge parasitic inductance and resistance, which seriously affect the reliability and performance of memory.

[0003] To overcome the limitations of traditional wire bonding, vertical interconnect technology has emerged. Vertical wire bonding is attractive due to its simple process and low cost; however, this method faces a significant technical hurdle: due to the rigidity of the wire itself and limitations of the implantation process, its perpendicularity is difficult to guarantee, and the end-face morphology is uncontrollable. This results in the inability to achieve precise and reliable alignment and bonding between upper and lower interconnect units in multilayer interconnect processes.

[0004] Therefore, it is necessary to design a high-stack chip packaging structure and method with precise vertical lead alignment to achieve accurate and reliable alignment and bonding of vertical leads between multi-layer modules, thereby effectively overcoming the shortcomings of traditional wire bonding and early vertical interconnect technologies. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-stack chip packaging structure and method with precise vertical lead alignment, so as to achieve accurate and reliable alignment and bonding of vertical leads between multi-layer modules, thereby effectively overcoming the defects of traditional wire bonding and early vertical interconnect technologies.

[0006] To achieve the above objectives, the present invention provides a high-stacked chip packaging structure with precise vertical lead alignment, comprising packaging modules, packaging interconnect layers, and bumps. Several packaging modules are vertically stacked. In two adjacent packaging modules, the chip in the upper packaging module is offset inward by 100~200μm compared to the chip in the lower packaging module. The packaging module at the end has a packaging interconnect layer on its surface, and the surface of the packaging interconnect layer has several bumps.

[0007] The packaging module includes a chip, vertical leads, leads, and epoxy resin. Several chips are stacked in a staggered manner in the vertical direction and interconnected by leads. Vertical leads are provided on the side of the chips. The chips, vertical leads, leads, and are encapsulated in epoxy resin, and the end faces of the vertical leads are exposed outside the epoxy resin.

[0008] When package modules are stacked vertically, the end faces of the vertical leads of two adjacent package modules are in contact, and the end face of the vertical lead of the package module at the end is in contact with the package interconnect layer, thereby realizing the interconnection between package modules and the interconnection between package modules and the package interconnect layer.

[0009] The aforementioned packaging interconnect layer is a substrate or a redistribution layer.

[0010] The diameter of the vertical lead is 12~50μm, and the height of the vertical lead is higher than the total stacking height of the chip.

[0011] The aforementioned leads are electrically connected between chips using wire bonding technology.

[0012] The vertical leads are located between the two sets of chip stacks or on the outside of the chip stacks.

[0013] The vertical lead is located beside the lead or above the bottommost chip.

[0014] A packaging method for a high-stacked chip packaging structure with precise vertical lead alignment includes the following steps: Step 1, mounting chips of the packaging module on a substrate according to the design layout; Step 2, using wire bonding technology to complete the electrical interconnection between several chips within the packaging module; Step 3, forming a vertical lead array next to the chip leads using a wire bonding machine with a half-cutting blade; Step 4, encapsulating with epoxy resin and polishing until the circular end faces of the vertical leads are exposed, forming the packaging module; Step 5, mounting the chip of the next packaging module onto the packaging module, with the chip mounting position of the next packaging module offset inward by 100° relative to the chip position of the current packaging module. 200μm; Step 6, using wire bonding technology, complete the electrical interconnection between several chips in the next packaging module, and the wires of the bottommost chip are bonded to the vertical lead end faces on both sides of the packaging module; Step 7, on the side of the chip leads of the next packaging module, a vertical lead array is formed using a wire bonding machine with a half-cutting blade, and the vertical leads of the next packaging module are directly bonded to the exposed vertical lead end faces of the packaging module; Step 8, use epoxy resin for molding and polishing until the circular end faces of the vertical leads are exposed to form the next packaging module; Step 9, repeat steps 5 to 8 to serially produce subsequent packaging modules; Step 10, make bumps on the bottom of the substrate.

[0015] A packaging method for a high-stacked chip packaging structure with precise vertical lead alignment includes the following steps: Step 1, on a glass substrate, using photopolymerizable adhesive as bonding glue, the chips of the packaging module are mounted according to the design layout; Step 2, using wire bonding technology to complete the electrical interconnection between several chips within the packaging module; Step 3, using a wire bonding machine with a half-cutting blade to form a vertical lead array next to the chip leads; Step 4, using epoxy resin for molding and polishing until the circular end faces of the vertical leads are exposed to form the packaging module; Step 5, mounting the chips of the next packaging module onto the packaging module, with the chip mounting position of the next packaging module offset inward by 100~200μm relative to the chip position of the current packaging module; Step 6, using wire bonding... The process involves: Step 7, completing the electrical interconnection between several chips within the next packaging module, with the wire bonded to the vertical lead end faces on both sides of the packaging module; Step 8, forming a vertical lead array next to the chip leads of the next packaging module using a wire bonding machine with a half-cutting blade, and directly bonding the vertical leads of the next packaging module to the exposed vertical lead end faces of the packaging module; Step 9, encapsulating with epoxy resin and polishing until the circular end faces of the vertical leads are exposed to form the next packaging module; Step 10, repeating steps 5-8 to sequentially fabricate subsequent packaging modules; Step 11, after the packaging modules are stacked, removing the bottom glass substrate by laser separation; Step 12, fabricating a redistribution layer on the packaging modules located at the ends, and then fabricating bumps.

[0016] A packaging method for a high-stacked chip packaging structure with precise vertical lead alignment includes the following steps: Step 1, on a glass substrate, using photopolymerizable adhesive as a bonding agent, the chips of the packaging module are mounted according to the design layout; Step 2, using wire bonding technology to complete the electrical interconnection between several chips within the packaging module; Step 3, on the bottom-layer chip, using a wire bonding machine with a half-cutting blade to form vertical leads; Step 4, using epoxy resin for molding and polishing until the circular end face of the vertical leads is exposed, forming the packaging module; Step 5, mounting the chips of the next packaging module onto the packaging module, with the chip mounting position of the next packaging module offset inward by 100° relative to the chip position of the current packaging module. ~200μm; Step 6, using wire bonding technology, complete the electrical interconnection between several chips in the next packaging module. On the chips of the next packaging module, a vertical lead is formed using a wire bonding machine with a half-cutting blade. The vertical lead of the next packaging module is directly bonded to the exposed vertical lead end face of the packaging module; Step 7, use epoxy resin for molding and polishing until the circular end face of the vertical lead is exposed to form the next packaging module; Step 8, repeat steps 5 to 7 to serially produce subsequent packaging modules; Step 9, after the packaging modules are stacked, a redistribution layer is made on the exposed lead end face of the packaging module, and then bumps are made; Step 10, the bottom glass substrate is removed by laser dissociation.

[0017] Compared with existing technologies, this invention exposes the vertical leads with a flat, circular end face through a plastic encapsulation grinding process. Combined with a specific offset stacking design of the upper-layer chip, it achieves precise and reliable alignment and bonding of vertical leads between multi-layer modules. This not only significantly improves the stability and accuracy of vertical interconnects, but also greatly reduces parasitic inductance and resistance caused by excessive lead length, thereby ensuring the overall electrical performance and reliability of the high-stack chip packaging structure. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0019] Figure 2 This is a schematic diagram of the encapsulation method according to Embodiment 1 of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0021] Figure 4 This is a schematic diagram of the encapsulation method according to Embodiment 2 of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0023] Figure 6 This is a schematic diagram of the encapsulation method according to Embodiment 3 of the present invention.

[0024] Figure 7 This is a schematic diagram of the structure of Embodiment 4 of the present invention.

[0025] Figure 8 This is a structural schematic diagram of Embodiment 5 of the present invention. Detailed Implementation

[0026] The present invention will now be further described with reference to the accompanying drawings. Example 1

[0027] See Figure 1 This invention is a high-stacked chip packaging structure with precise vertical lead alignment, including packaging modules, packaging interconnect layers, and bumps. Several packaging modules 3 are vertically stacked. In two adjacent packaging modules 3, the chip 31 of the upper packaging module 3 is offset inward by 100~200μm compared to the chip 31 of the lower packaging module 3. The packaging module 3 at the end has a packaging interconnect layer on its surface, and the surface of the packaging interconnect layer has several bumps 4.

[0028] The packaging module 3 includes a chip 31, vertical leads 32, leads 33, and epoxy resin 34. Several chips 31 are stacked in a staggered manner in the vertical direction and interconnected by leads 33. Vertical leads 32 are provided on the side of the chips 31. The chips 31, vertical leads 32, and leads 33 are encapsulated in epoxy resin 34, and the end face of the vertical leads 32 is exposed outside the epoxy resin 34.

[0029] The vertical lead 32 has a diameter of 12~50μm and its height is higher than the total stacking height of the chip 31.

[0030] Lead 33 uses wire bonding technology to achieve electrical connection between chips 31.

[0031] The inward offset of chip 31 is mainly to make room for the subsequent fabrication of vertical leads 32, so that the leads 33 of chip 31 of upper packaging module 3 can be bonded to the exposed end face of vertical leads 32 of lower packaging module 3, while the vertical leads of upper packaging module 3 are directly bonded to the exposed end face of vertical leads 32 of lower packaging module 3, thereby constructing a continuous and reliable vertical conductive path.

[0032] When the packaging modules 3 are stacked vertically, the end faces of the vertical leads 32 of two adjacent packaging modules 3 are in contact, and the end face of the vertical lead 32 of the packaging module 3 located at the end is in contact with the packaging interconnect layer, thereby realizing the interconnection between the packaging modules 3 and the interconnection between the packaging module 3 and the packaging interconnect layer.

[0033] In this embodiment, the packaging interconnect layer is substrate 1, the vertical lead 32 is located between the stacked structures of the two sets of chips 31, and the vertical lead 32 is located next to the lead 33.

[0034] See Figure 2 The packaging method of this embodiment includes the following steps: Step 1, on the substrate, the chips of the packaging module are mounted according to the design layout; Step 2, wire bonding process is used to complete the electrical interconnection between several chips in the packaging module; Step 3, a vertical lead array is formed next to the chip leads using a wire bonding machine with a half-cutting blade; Step 4, epoxy resin is used for molding and polishing until the circular end face of the vertical leads is exposed to form the packaging module; Step 5, the chip of the next packaging module is mounted on the packaging module, and the chip mounting position of the next packaging module is offset inward by 100~200μm relative to the chip position of the packaging module; 6. Using wire bonding technology, complete the electrical interconnection between several chips in the next packaging module, and the wires of the bottommost chip are bonded to the vertical lead end faces on both sides of the packaging module; Step 7. On the side of the chip leads of the next packaging module, a vertical lead array is formed using a wire bonding machine with a half-cutting blade, and the vertical leads of the next packaging module are directly bonded to the exposed vertical lead end faces of the packaging module; Step 8. Use epoxy resin for molding and polishing until the circular end faces of the vertical leads are exposed to form the next packaging module; Step 9. Repeat steps 5 to 8 to serially produce subsequent packaging modules; Step 10. Create bumps on the bottom of the substrate. Example 2

[0035] See Figure 3 In this embodiment, the package interconnect layer is the redistribution layer 2, the vertical lead 32 is located between the stacked structures of the two sets of chips 31, and the vertical lead 32 is located next to the lead 33.

[0036] See Figure 4The packaging method of this embodiment includes the following steps: Step 1, on a glass substrate, photopolymer adhesive is used as the bonding adhesive, and the chips of the packaging module are mounted according to the design layout; Step 2, wire bonding process is used to complete the electrical interconnection between several chips in the packaging module; Step 3, a vertical lead array is formed next to the chip leads using a wire bonding machine with a half-cutting blade; Step 4, epoxy resin is used for molding and polishing until the circular end face of the vertical leads is exposed to form the packaging module; Step 5, the chip of the next packaging module is mounted on the packaging module, and the chip mounting position of the next packaging module is offset inward by 100~200μm relative to the chip position of the packaging module; Step 6, wire bonding process is used to complete the next packaging module. The electrical interconnection between several chips within the packaging module is performed, with the wires of the bottommost chip bonded to the vertical lead end faces on both sides of the packaging module; Step 7: A vertical lead array is formed next to the chip leads of the next packaging module using a wire bonding machine with a half-cutting blade, and the vertical leads of the next packaging module are directly bonded to the exposed vertical lead end faces of the packaging module; Step 8: Epoxy resin is used for encapsulation, and the surface is ground and polished until the circular end faces of the vertical leads are exposed, forming the next packaging module; Step 9: Steps 5-8 are repeated to sequentially produce subsequent packaging modules; Step 10: After the packaging modules are stacked, the bottom glass substrate is removed by laser separation; Step 11: After a redistribution layer is made on the packaging module located at the end, bumps are then made. Example 3

[0037] See Figure 5 In this embodiment, the packaging interconnect layer is the redistribution layer 2, the vertical lead 32 is located between the stacked structures of the two sets of chips 31, and the vertical lead 32 is located above the bottommost chip 31.

[0038] See Figure 6The packaging method of this embodiment includes the following steps: Step 1, on a glass substrate, photopolymer adhesive is used as the bonding adhesive, and the chips of the packaging module are mounted according to the design layout; Step 2, wire bonding process is used to complete the electrical interconnection between several chips in the packaging module; Step 3, on the bottommost chip, a half-cut wire bonding machine is used to form vertical leads; Step 4, epoxy resin is used for molding and polishing until the circular end face of the vertical leads is exposed to form the packaging module; Step 5, the chips of the next packaging module are mounted on the packaging module, and the chip mounting position of the next packaging module is offset inward by 100~200μm relative to the chip position of the packaging module; Step 6: Using wire bonding technology, complete the electrical interconnection between several chips in the next packaging module. On the chips of the next packaging module, use a wire bonding machine with a half-cutting blade to form vertical leads. The vertical leads of the next packaging module are directly bonded to the exposed vertical lead end face of the packaging module. Step 7: Use epoxy resin for molding and polishing until the circular end face of the vertical lead is exposed to form the next packaging module. Step 8: Repeat steps 5 to 7 to serially produce subsequent packaging modules. Step 9: After the packaging modules are stacked, make a redistribution layer on the exposed lead end face of the packaging module, and then make bumps. Step 10: Remove the bottom glass substrate by laser dissociation. Example 4

[0039] See Figure 7 In this embodiment, the package interconnect layer is the redistribution layer 2, the vertical lead 32 is located outside the stacked structure of chip 31, and the vertical lead 32 is located next to the lead 33. Example 5

[0040] See Figure 8 In this embodiment, the packaging interconnect layer is the redistribution layer 2, and the vertical lead 32 is located outside the stacked structure of the chip 31, above the bottommost chip 31.

[0041] This invention uses a molding and grinding process to expose a flat, circular end face of the vertical leads. Combined with a specific offset stacking design of the upper-layer chip, it achieves precise and reliable alignment and bonding of the vertical leads between multi-layer modules. This not only significantly improves the stability and accuracy of vertical interconnects, but also greatly reduces parasitic inductance and resistance caused by excessively long leads, thereby ensuring the overall electrical performance and reliability of the high-stack chip package structure.

Claims

1. A high stack chip package structure with vertical wire precision alignment, comprising a package module, a package interconnection layer, a bump, characterized in that: The plurality of packaging modules (3) are vertically stacked, in two adjacent packaging modules (3) from top to bottom, the chip (31) of the packaging module (3) on the upper layer is offset inward by 100-200 mu m than the chip (31) of the packaging module (3) on the lower layer, the surface of the packaging module (3) at the end is provided with a packaging interconnection layer, the surface of the packaging interconnection layer is provided with a plurality of bumps (4), The packaging module (3) comprises a chip (31), a vertical lead (32), a lead (33), and an epoxy resin (34), a plurality of chips (31) are stacked in the vertical direction and are interconnected by leads (33), the side of the chip (31) is provided with a vertical lead (32), the chip (31), the vertical lead (32), the lead (33), and the epoxy resin (34) are molded, and the end face of the vertical lead (32) is exposed outside the epoxy resin (34), When the packaging modules (3) are vertically stacked, the end faces of the vertical leads (32) of two adjacent packaging modules (3) from top to bottom are in contact, the end face of the vertical lead (32) of the packaging module (3) at the end is in contact with the packaging interconnection layer, and the interconnection between the packaging modules (3) and the interconnection between the packaging module (3) and the packaging interconnection layer are realized.

2. The high stack chip package structure of claim 1, wherein: The packaging interconnection layer is a substrate (1) or a redistribution layer (2).

3. The high stack chip package structure of claim 1, wherein: The diameter of the vertical lead (32) is 12-50 mu m, and the height of the vertical lead (32) is higher than the total stacking height of the chip (31).

4. The high stack chip package structure of claim 1, wherein: The lead (33) realizes the electrical connection between the chips (31) by a wire bonding process.

5. The high stack chip package structure of claim 1, wherein: The vertical lead (32) is located between two groups of chip (31) stacking structures or above the chip (31) stacking structure.

6. The high stack chip package structure of claim 1, wherein: The vertical lead (32) is located beside the lead (33) or above the lowermost chip (31). The vertical lead (32) is located beside the lead (33) or above the lowermost chip (31).

7. A packaging method of a high stack chip package structure with vertical lead precision alignment as claimed in any one of claims 1-6, wherein: The method comprises the following steps: step 1, chip mounting of a packaging module is performed on a substrate according to a design layout; step 2, electrical interconnection between a plurality of chips in the packaging module is completed by adopting a wire bonding process; step 3, a vertical wire array is formed on the side of the chip wire by adopting a wire bonder with a half-cutting wedge; step 4, plastic packaging is performed by adopting epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming the packaging module; step 5, the chip mounting position of a next packaging module is offset inward by 100-200 μm relative to the chip mounting position of the packaging module; step 6, electrical interconnection between a plurality of chips in the next packaging module is completed by adopting the wire bonding process, and the wire of the lowermost chip is bonded to the vertical wire end surface on the two sides of the packaging module; step 7, a vertical wire array is formed on the side of the chip wire of the next packaging module by adopting the wire bonder with the half-cutting wedge, and the vertical wire of the next packaging module is directly bonded to the exposed vertical wire end surface of the packaging module; step 8, plastic packaging is performed by adopting the epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming the next packaging module; step 9, steps 5-8 are repeated, and subsequent packaging modules are sequentially manufactured; and step 10, a bump is manufactured at the bottom of the substrate.

8. A packaging method of a high stack chip package structure with vertical lead precision alignment as claimed in any one of claims 1-6, characterized in that: The method comprises the following steps: step 1, chip mounting of a packaging module is performed on a glass carrier according to a design layout by adopting photolysis glue as bonding glue; step 2, electrical interconnection between a plurality of chips in the packaging module is completed by adopting a wire bonding process; step 3, a vertical wire array is formed on the side of the chip wire by adopting a wire bonder with a half-cutting wedge; step 4, plastic packaging is performed by adopting epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming the packaging module; step 5, the chip mounting position of a next packaging module is offset inward by 100-200 μm relative to the chip mounting position of the packaging module; step 6, electrical interconnection between a plurality of chips in the next packaging module is completed by adopting the wire bonding process, and the wire of the lowermost chip is bonded to the vertical wire end surface on the two sides of the packaging module; step 7, a vertical wire array is formed on the side of the chip wire of the next packaging module by adopting the wire bonder with the half-cutting wedge, and the vertical wire of the next packaging module is directly bonded to the exposed vertical wire end surface of the packaging module; step 8, plastic packaging is performed by adopting the epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming the next packaging module; step 9, steps 5-8 are repeated, and subsequent packaging modules are sequentially manufactured; step 10, after the packaging module stacking is completed, the glass carrier at the bottom is removed by laser dissociation; and step 11, a redistribution layer is manufactured on the packaging module at the end, and then a bump is manufactured.

9. A packaging method of a high stack chip package structure with vertical lead precision alignment as claimed in any one of claims 1-6, characterized in that: The method comprises the following steps: step 1, chip mounting of a packaging module is performed on a glass substrate according to a design layout by using photodegradable glue as a bonding glue; step 2, electrical interconnection between a plurality of chips in the packaging module is completed by using a wire bonding process; step 3, vertical wires are formed on the lowermost chip by using a wire bonder with a half-cutting wedge; step 4, plastic packaging is performed by using epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming a packaging module; step 5, a chip of a next packaging module is mounted on the packaging module, and the mounting position of the chip of the next packaging module is offset inward by 100-200 μm relative to the position of the chip of the packaging module; step 6, electrical interconnection between a plurality of chips in the next packaging module is completed by using a wire bonding process, vertical wires are formed on the chip of the next packaging module by using a wire bonder with a half-cutting wedge, and the vertical wires of the next packaging module are directly bonded on the exposed end surface of the vertical wire of the packaging module; step 7, plastic packaging is performed by using epoxy resin, and grinding and polishing are performed until the round end surface of the vertical wire is exposed, thereby forming the next packaging module; step 8, steps 5-7 are repeated, and subsequent packaging modules are sequentially manufactured; step 9, after the packaging modules are stacked, a redistribution layer is manufactured on the exposed wire end surface of the packaging modules, and then, bumps are manufactured; and step 10, the bottom glass substrate is removed by laser dissociation.

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