Current acquisition circuit, load control circuit, linear electromagnetic valve and vehicle

Abstract

The invention discloses a current acquisition circuit, a load control circuit, a linear electromagnetic valve and a vehicle. The current acquisition circuit comprises a first current mirror image circuit, a first transistor and a second current mirror image circuit. The first transistor is connected between the driving transistor and the ground electrode, and the first transistor is configured to be turned off when the driving transistor is turned on. The second current mirroring circuit is configured to replicate a current flowing through the first transistor as a second mirrored current. When the first transistor is turned off, the current acquisition circuit determines a current acquisition value according to the first mirror current, and when the first transistor is turned on, the current acquisition circuit determines a current acquisition value according to the second mirror current. The electronic components of the current acquisition circuit are all integrated in the chip, and a sampling resistor does not need to be additionally arranged outside the chip, so that the area of a circuit board and the system cost are saved.

Description

Technical Field

[0001] This application relates to the field of current acquisition technology, and more specifically, to a current acquisition circuit, a load control circuit, a linear solenoid valve, and a vehicle. Background Technology

[0002] In related technologies, a sampling resistor can be connected in series in the load circuit, and the current flowing through the load can be detected by detecting the voltage of the sampling resistor. This requires setting a high-precision sampling resistor to ensure the accuracy of current detection.

[0003] However, due to limitations in existing manufacturing processes, it is difficult to integrate high-precision sampling resistors into the current sampling chip. Setting the sampling resistor outside the current sampling chip would occupy additional circuit board area and increase system cost. Summary of the Invention

[0004] This application provides a current acquisition circuit, a load control circuit, a linear solenoid valve, and a vehicle.

[0005] The current acquisition circuit provided in this application is used to acquire the current flowing through a load. The voltage source of the load is grounded through a driving transistor and the load. The current acquisition circuit may include a first current mirror circuit, a first transistor, and a second current mirror circuit. The first current mirror circuit is configured to replicate the current flowing through the driving transistor as a first mirror current. The first transistor is connected between the driving transistor and ground, and the first transistor is configured to be turned off when the driving transistor is turned on. The second current mirror circuit is configured to replicate the current flowing through the first transistor as a second mirror current. When the first transistor is turned off, the current acquisition circuit is configured to determine the current acquisition value based on the first mirror current; when the first transistor is turned on, the current acquisition circuit is configured to determine the current acquisition value based on the second mirror current.

[0006] The current acquisition circuit of this application can determine the load current when the driving transistor is turned on based on the current flowing through the driving transistor, and determine the load current when the driving transistor is turned off based on the current flowing through the first transistor. This replaces the scheme of detecting the current flowing through the load by detecting the voltage of the sampling resistor, and eliminates the need for a high-precision sampling resistor. All electronic components of the current acquisition circuit can be integrated inside the chip, eliminating the need for an external sampling resistor, thus saving circuit board area and system cost.

[0007] In some embodiments, the driving transistor is configured to turn on or off according to a driving signal provided by the driving circuit. The current acquisition circuit may further include a first control circuit. The first control circuit is connected between the driving circuit and the control electrode of the first transistor and is configured to control the first transistor to turn off when the driving circuit provides a driving signal, so that the first transistor is turned off when the driving transistor is turned on.

[0008] In some implementations, the driving transistor is configured to turn off when the driving circuit stops providing a driving signal, and the first control circuit is configured to control the first transistor to turn on when the driving circuit stops providing a driving signal.

[0009] In some embodiments, the first current mirror circuit includes a first mirror transistor, the control terminal of the first mirror transistor is connected to the control terminal of the driving transistor, the first terminal of the first mirror transistor and the first terminal of the driving transistor are connected to the voltage source of the load, and the first mirror circuit is determined based on the current flowing through the first mirror transistor.

[0010] In some embodiments, the first current mirror circuit includes a first clamping circuit connected to the second terminal of the first mirror transistor. The first clamping circuit is configured to clamp the voltage at the second terminal of the first mirror transistor so that the voltage at the second terminal of the first mirror transistor is consistent with the voltage at the second terminal of the driving transistor.

[0011] In some embodiments, the first clamping circuit includes a first operational amplifier and a second transistor. The first operational amplifier includes a first input terminal and a second input terminal. The first input terminal is connected to the second terminal of the driving transistor, and the second input terminal is connected to the second terminal of the first mirror transistor and the second terminal of the second transistor. The output terminal of the first operational amplifier is connected to the control terminal of the second transistor.

[0012] In some embodiments, the second current mirror circuit includes at least one stage of second mirror transistors. The control terminal of the first stage of the second mirror transistor is connected to the control terminal of the first transistor, and the second terminal of the first stage of the second mirror transistor is grounded. Each stage of the second mirror transistor is configured to replicate the current flowing through the first transistor, or to replicate the current flowing through the previous stage of the second mirror transistor. The second mirror current is determined based on the current flowing through the at least one stage of the second mirror transistor.

[0013] In some implementations, the current flowing through the first-stage second mirror transistor is a current flowing from the ground to a negative potential, and the current flowing through the last-stage second mirror transistor is a current flowing from a positive potential to the ground.

[0014] In some embodiments, the second current mirror circuit has at least one third transistor, the first terminal of each third transistor is connected to the first terminal of the corresponding previous second mirror transistor, the control terminal of each third transistor is connected to the control terminal of the corresponding next second mirror transistor, and the second terminal of each third transistor is connected to the second terminal of the corresponding next second mirror transistor.

[0015] In some embodiments, the second current mirror circuit includes at least one second clamping circuit, each second clamping circuit being connected to the first terminal of a corresponding first-stage second mirror transistor and configured to clamp the first terminal voltage of the first-stage second mirror transistor so that the first terminal voltage of each stage of the second mirror transistor is consistent with the first terminal voltage of the first transistor or with the first terminal voltage of a corresponding first-stage third transistor.

[0016] In some embodiments, each of the second clamping circuits includes a second operational amplifier and a fourth transistor. The second operational amplifier includes a third input terminal and a fourth input terminal. The fourth input terminal is connected to the first terminal of the corresponding first-stage second mirror transistor and the second terminal of the fourth transistor. The output terminal of the second operational amplifier is connected to the control terminal of the fourth transistor. The third input terminal is connected to the first terminal of the first transistor, or the third input terminal is connected to the first terminal of the corresponding first-stage third transistor.

[0017] The load control circuit provided in this application includes the current acquisition circuit and drive circuit of the above embodiments. The drive circuit is configured to provide a drive signal to the drive transistor according to the current acquisition value determined by the current acquisition circuit, so as to drive the drive transistor to turn on or off, thereby controlling the current flowing through the load.

[0018] In some embodiments, the driving circuit includes a second control circuit and a comparator. The second control circuit is configured to determine a current control signal based on the current acquisition value. The comparator is configured to provide a pulse-width modulation signal to the driving transistor based on the current control signal and a ramp signal to drive the driving transistor to turn on or off, thereby controlling the current flowing through the load.

[0019] This application also provides a linear solenoid valve, which includes the current acquisition circuit or load control circuit described in the above embodiments.

[0020] This application also provides a vehicle that may include the current acquisition circuit of the above embodiments or a linear solenoid valve.

[0021] This application discloses a current acquisition circuit, a load control circuit, a linear solenoid valve, and a vehicle. The current acquisition circuit is used to acquire the current flowing through a load. The voltage source of the load is grounded through a driving transistor and the load. The current acquisition circuit may include a first current mirror circuit, a first transistor, and a second current mirror circuit. The first current mirror circuit is configured to replicate the current flowing through the driving transistor as a first mirror current. The first transistor is connected between the driving transistor and ground, and the first transistor is configured to be turned off when the driving transistor is turned on. The second current mirror circuit is configured to replicate the current flowing through the first transistor as a second mirror current. When the first transistor is turned off, the current acquisition circuit is configured to determine the current acquisition value based on the first mirror current; when the first transistor is turned on, the current acquisition circuit is configured to determine the current acquisition value based on the second mirror current.

[0022] The current acquisition circuit can determine the load current when the driving transistor is turned on based on the current flowing through it, and determine the load current when the driving transistor is turned off based on the current flowing through it. This replaces the scheme of detecting the current flowing through the load by detecting the voltage of the sampling resistor, eliminating the need for a high-precision sampling resistor. All electronic components of the current acquisition circuit can be integrated inside the chip, eliminating the need for an external sampling resistor, thus saving circuit board space and system cost.

[0023] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0025] Figure 1 This is a schematic diagram of the current acquisition circuit according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the current acquisition circuit and load control circuit of some embodiments of this application;

[0027] Figure 3 This is a circuit diagram of the current acquisition circuit and load control circuit in related technologies;

[0028] Figure 4 This is a circuit diagram of the current acquisition circuit and load control circuit of some embodiments of this application;

[0029] Figure 5 This is a circuit diagram of the first current mirror circuit in some embodiments of this application;

[0030] Figure 6 This is a circuit diagram of the second current mirror circuit in some embodiments of this application;

[0031] Figure 7 This is a schematic diagram of a linear solenoid valve according to an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of a vehicle according to an embodiment of this application.

[0033] Explanation of key component symbols:

[0034] Load 10, drive transistor 20, current acquisition circuit 100, first current mirror circuit 110, first mirror transistor 111, first clamping circuit 112, first operational amplifier 1121, second transistor 1122, first transistor 120, second current mirror circuit 130, second mirror transistor 131, third transistor 132, second clamping circuit 133, second operational amplifier 1331, fourth transistor 1332, first control circuit 140, digital-to-analog converter circuit 150, load control circuit 1000, drive circuit 200, second control circuit 210, comparator 220, linear solenoid valve 2000, vehicle 3000. Detailed Implementation

[0035] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are optional and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0036] In related technologies, a sampling resistor can be connected in series in the load circuit, and the current flowing through the load can be detected by detecting the voltage of the sampling resistor. This requires setting a high-precision sampling resistor to ensure the accuracy of current detection.

[0037] However, due to limitations in existing manufacturing processes, it is difficult to integrate high-precision sampling resistors into the current sampling chip. Setting the sampling resistor outside the current sampling chip would occupy additional circuit board area and increase system cost.

[0038] This application provides a current acquisition circuit (such as...) Figures 1-6 (As shown). The electronic components of the current acquisition circuit can all be integrated inside the chip, eliminating the need for additional sampling resistors outside the chip, thus saving circuit board area and system cost.

[0039] Please see Figure 1The current acquisition circuit 100 provided in this application embodiment is used to acquire the current flowing through the load 10. The voltage source of the load 10 is grounded through the driving transistor 20 and the load 10. The current acquisition circuit 100 may include a first current mirror circuit 110, a first transistor 120 and a second current mirror circuit 130.

[0040] The first current mirror circuit 110 is configured to replicate the current flowing through the driving transistor 20 as a first mirror current. The first transistor 120 is connected between the driving transistor 20 and ground, and is configured to be turned off when the driving transistor 20 is turned on. The second current mirror circuit 130 is configured to replicate the current flowing through the first transistor 120 as a second mirror current. When the first transistor 120 is turned off, the current acquisition circuit 100 is configured to determine the current acquisition value based on the first mirror current; when the first transistor 120 is turned on, the current acquisition circuit 100 is configured to determine the current acquisition value based on the second mirror current.

[0041] Specifically, with Figure 2 For example, the equivalent resistance of load 10 can be set as a resistive element RL, and the equivalent inductance of load 10 can be set as an inductor element L-load. The voltage source of load 10 can provide the supply voltage of load 10 to the VBAT terminal. The driving transistor 20 can be set as transistor NH,1. The VL terminal can be set as the first connection terminal of load 10, and the GND terminal can be grounded and set as the second connection terminal of load 10. Load 10 can be connected between the VL terminal and the GND terminal. The VBAT terminal can be connected to the first terminal of transistor NH,1, and the second terminal of transistor NH,1 can be connected to the VL terminal. The VL terminal can be grounded through the inductor element L-load and the resistive element RL.

[0042] When transistor NH,1 is turned on, the VBAT terminal can supply the power supply voltage to the VL terminal. The VL terminal is connected to a positive voltage, and the current flowing through the load 10 can be set as current I-1. Current I-1 flows from the VBAT terminal through transistor NH,1, inductor L-load, and resistor RL to the GND terminal. The first current mirror circuit 110 can replicate the current I-1 flowing through transistor NH,1 to obtain the current IH.

[0043] The first transistor 120 can be configured as transistor NL,1. The first terminal of transistor NL,1 can be connected to the second terminal of transistor NH,1, and the second terminal of transistor NL,1 can be connected to the GND terminal. When transistor NH,1 is turned on, transistor NL,1 is in the off state to prevent transistors NH,1 and NL,1 from being turned on simultaneously, and to prevent overcurrent in transistors NH,1 and NL,1 caused by shorting the VBAT terminal and the GND terminal.

[0044] When transistor NH,1 is off, transistor NL,1 can be on, and NL,1 can be set as the freewheeling transistor of load 10. Due to the inductive characteristics of load 10, when transistor NH,1 is off, inductor L-load can discharge, forming a freewheeling loop of inductor L-load - resistor RL-GND terminal - transistor NL,1 - inductor L-load. At this time, a negative voltage is applied to the VL terminal, and the current flowing through load 10 can be set as current I-2. Current I-2 flows from inductor L-load through resistor RL-GND terminal and transistor NL,1 to inductor L-load. The second current mirror circuit 130 can replicate the current I-2 flowing through transistor NL,1 to obtain current IL.

[0045] In related technologies, a sampling resistor can be connected in series in the load circuit, and the current flowing through the load can be detected by detecting the voltage across the sampling resistor.

[0046] by Figure 3 For example, the sampling resistor can be set as a resistor element Rs. The operational amplifier can be connected across the resistor element Rs to obtain the voltage across the resistor element Rs. Based on the voltage across the resistor element Rs and the resistance of the resistor element Rs, the current flowing through the resistor element Rs is determined, and then the current flowing through the load 10 is determined.

[0047] To ensure the accuracy of current detection flowing through load 10, the resistor Rs needs to be a high-precision (milliohm level) sampling resistor with a very low temperature coefficient. Due to limitations in current manufacturing processes, it is difficult to integrate a high-precision sampling resistor into the current sampling chip. Placing the sampling resistor outside the current sampling chip would occupy additional board space, increasing system cost.

[0048] It is understood that the current acquisition circuit 100 in this embodiment can determine the load 10 current when the driving transistor 20 is turned on based on the current flowing through the driving transistor 20, and determine the load 10 current when the driving transistor 20 is turned off based on the current flowing through the first transistor 120. This replaces the scheme of detecting the current flowing through the load 10 by detecting the voltage of the sampling resistor, and eliminates the need for a high-precision sampling resistor. All electronic components of the current acquisition circuit 100 can be integrated inside the chip, eliminating the need for an external sampling resistor, thus saving circuit board area and system cost.

[0049] by Figure 3 For example, in related technologies, an additional freewheeling diode is required as a freewheeling element for inductive loads.

[0050] The freewheeling diode can be set as diode element D-2. The cathode of diode element D-2 can be connected to the VL terminal, and the anode of diode element D2 can be connected to the ground.

[0051] The VBAT terminal can be connected to the load 10 and the VL terminal through the transistor QL. When the transistor QL is turned on, the VBAT terminal can provide the supply voltage to the load 10, and the current flowing through the load 10 is the current I-1.

[0052] When transistor QL switches from on to off, due to the inductive characteristics of load 10, inductor L-load can be discharged through diode D2. At this time, diode D-2 is forward-biased and forms a freewheeling loop of inductor L-load - resistor RL-GND terminal - diode D2 - inductor L-load. The current flowing through load 10 at this time is current I-2.

[0053] Current I-2 flows from the anode to the cathode of diode element D-2, that is, current I-2 flows from the ground electrode to the VL terminal. At this time, the voltage at the VL terminal is negative. When the conduction voltage of diode element D-2 is 0.7V, the voltage at the VL terminal is -0.7V.

[0054] The operational amplifier can be connected across the resistor element Rs to obtain the voltage across the resistor element Rs, and determine the current flowing through the resistor element Rs, i.e. the current flowing through the diode D-2, based on the voltage across the resistor element Rs and the resistance of the resistor element Rs, and then determine the current flowing through the load 10.

[0055] The forward voltage of the freewheeling diode is relatively constant, around 0.7V, and remains essentially unchanged. When the freewheeling diode is conducting, the power consumed by it is related to the current Ia flowing through the diode and the forward voltage Ua, and the power consumed by the freewheeling diode Pa = Ua * Ia.

[0056] When the driving transistor 20 is turned on, the power consumed by the driving transistor 20 is related to the current Ib flowing through the driving transistor 20 and the on-resistance Rb. The power consumed by the driving transistor 20 is Pb = Ib. 2 *Rb.

[0057] For the freewheeling diode, since the forward voltage Ua is constant, the power Pa consumed by the freewheeling diode is basically determined by the current Ia flowing through the diode. For the driving transistor 20, the power Pb consumed by the driving transistor 20 is determined by the current Ib flowing through the driving transistor and the on-resistance Rb. The on-resistance of the driving transistor 20 can be reduced by properly setting its size and structure, thereby reducing the power consumed by the driving transistor 20.

[0058] For example, the driving transistor 20 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). By increasing the area of ​​the MOSFET, its on-resistance Rb can be reduced, so that the driving transistor 20 consumes less power in the freewheeling phase than the freewheeling diode consumes power in the freewheeling phase.

[0059] It is understood that the current acquisition circuit 100 in this embodiment can be configured to use a driving transistor 20 as a freewheeling device instead of a freewheeling diode. Compared to using a freewheeling diode as a freewheeling device, the current acquisition circuit 100 in this embodiment generates less heat.

[0060] Reference Figure 2 This application also provides a load control circuit 1000, which may include the current sampling circuit and drive circuit 200 of this application. The load control circuit 1000 may include all the technical effects of the current acquisition circuit 100 of this application, which will not be described in detail again.

[0061] Specifically, the drive circuit 200 is configured to provide a drive signal to the drive transistor 20 based on the current acquisition value determined by the current acquisition circuit 100, so as to drive the drive transistor 20 to turn on or off, thereby controlling the current flowing through the load 10.

[0062] The drive signal provided by the drive circuit 200 can control the drive transistor 20 to turn on or off. When the drive transistor 20 is turned on, the current flowing through the load 10 increases; when the drive transistor 20 is turned off, the current flowing through the load 10 decreases. The drive circuit 200 can provide a drive signal to the drive transistor 20 based on the current sampling value to drive the drive transistor 20 to turn on or off, thereby controlling the current flowing through the load 10.

[0063] The drive signal provided by the drive circuit 200 can be a PWM (Pulse Modulation) signal. Within one PWM cycle, the longer the drive transistor 20 is turned on, the greater the current flowing through the load 10. The longer the drive transistor 20 is turned off, the smaller the current flowing through the load 10.

[0064] The current sampling circuit obtains the current at a certain moment each time it samples. Within one PWM cycle, the current sampling circuit can sample multiple times to obtain the current at different moments, and calculate the average current value within one PWM cycle based on the current sampling values ​​obtained from multiple samplings. Based on the average current value, the current flowing through the load I0 within one PWM cycle is determined.

[0065] In some embodiments, the current acquisition circuit 100 may further include a first control circuit 140. The first control circuit 140 is connected between the drive circuit 200 and the control electrode of the first transistor 120, and is configured to control the first transistor 120 to turn off when the drive circuit 200 provides a drive signal, so that the first transistor 120 is turned off when the drive transistor 20 is turned on.

[0066] Specifically, with Figure 2 For example, the drive signal provided by the drive circuit 200 can be set as signal H-gate, and the control signal provided by the first control circuit 140 can be set as signal L-gate. The first control circuit 140 can control the transistor NL,1 to turn on or off according to the drive signal provided by the drive circuit 200. Specifically, when the drive circuit 200 provides the drive signal, the transistor NL,1 can be in an on or off state, and the first control circuit 140 controls the transistor NL,1 to turn off. For example, the drive signal provided by the drive circuit 200 can be a PWM (Pulse Modulation) signal. Within one PWM cycle, when the PWM signal drives the transistor NL,1 to turn on or off, the transistor NL,1 turns off.

[0067] In some embodiments, the driving transistor 20 is configured to turn off when the driving circuit 200 stops providing a driving signal, and the first control circuit 140 is configured to control the first transistor 120 to turn on when the driving circuit 200 stops providing a driving signal.

[0068] Specifically, when the drive circuit 200 stops providing the drive signal, it can be determined that the transistor NH,1 is in the off state, and the first control circuit 140 controls the transistor NL,1 to turn on, so that the control transistor NL,1 acts as the freewheeling transistor of the load 10.

[0069] The drive signal provided by the drive circuit 200 can be a PWM (Pulse Modulation) signal. In PWM control, the dead time can be set as the transition phase of the PWM cycle. The first control circuit 140 can be set as a dead time control circuit. During the transition phase of the PWM cycle, the first control circuit 140 can provide the corresponding L-gate according to the acquired signal H-gate to control the transistor NL,1 to turn on, so that the control transistor NL,1 acts as the freewheeling transistor of the load 10.

[0070] Reference Figure 2 In some embodiments, the current acquisition circuit 100 may further include a digital-to-analog converter circuit 150, which can convert the analog quantity of the current acquisition value into a digital quantity to quantize the current IL and the current IH, so that the drive circuit 200 can determine the drive signal based on the current acquisition value.

[0071] Reference Figure 2 In some embodiments, the drive circuit 200 may include a second control circuit 210 and a comparator 220. The second control circuit 210 is configured to determine a current control signal based on the current acquisition value. The comparator 220 is configured to provide a pulse width modulation signal to the drive transistor 20 based on the current control signal and a ramp signal, thereby driving the drive transistor 20 to turn on or off, and thus controlling the current flowing through the load 10.

[0072] Specifically, the second control circuit 210 may include a corresponding logic gate circuit, which can process the digital value of the current acquisition according to the set operation logic and provide the corresponding current control signal to the comparator.

[0073] A ramp signal is a voltage signal that increases or decreases linearly with time; the voltage of the ramp signal changes linearly with time. The current control signal can be set as a voltage signal. Comparator 220 can compare the voltage of the current control signal with the voltage of the ramp signal and output a drive signal based on the comparison result.

[0074] Reference Figure 4The first mirror circuit is connected between the driving transistor 20 and the digital-to-analog converter circuit 150, and is configured to replicate the current flowing through the driving transistor 20 as a first mirror current to be provided to the digital-to-analog converter circuit 150. The second mirror circuit can be connected between the first transistor 120 and the digital-to-analog converter circuit 150, and is configured to replicate the current flowing through the first transistor 120 as a second mirror current to be provided to the digital-to-analog converter circuit 150.

[0075] In some embodiments, the first current mirror circuit 110 includes a first mirror transistor 111, the control electrode of the first mirror transistor 111 is connected to the control electrode of the driving transistor 20, the first electrode of the first mirror transistor 111 and the first electrode of the driving transistor 20 are connected to the voltage source of the load 10, and the first mirror circuit is determined based on the current flowing through the first mirror transistor 111.

[0076] Specifically, with Figure 5 For example, the first mirror transistor 111 can be set as transistor NH,2. The first terminal of transistor NH,2 can be connected to the VBAT terminal, and the control terminal of transistor NH,2 can be connected to the control terminal of transistor NH,1. Transistor NH,2 can be set as a mirror transistor of transistor NH,1. W1 / L1 can be set as the width-to-length ratio of the channel of transistor NH,1, and W2 / L2 can be set as the width-to-length ratio of the channel of transistor NH,2. The ratio of W2 / L2 to W1 / L1 can be set as K1:1. The current flowing through transistor NH,2 can be set as K1*(I-1). The current flowing through transistor NH,2 can be set as IH, i.e., IH = K1*(I-1). K1 can be set arbitrarily according to actual needs.

[0077] In some embodiments, the first current mirror circuit 110 includes a first clamping circuit 112 connected to the second terminal of the first mirror transistor 111. The first clamping circuit 112 is configured to clamp the voltage of the second terminal of the first mirror transistor 111 so that the voltage of the second terminal of the first mirror transistor 111 is consistent with the voltage of the second terminal of the driving transistor 20.

[0078] Specifically, with Figure 5 For example, both transistors NH,1 and NH,2 can be set as NMOS transistors. When the voltage difference between the source and drain of transistor NH,1 and the voltage difference between the source and drain of transistor NH,2 are not the same, the current flowing through transistor NH,2 will deviate from K1*(I-1).

[0079] The drain voltage of transistor NH,1 can be set to voltage VP,1. The first clamping circuit 112 can be used to clamp the drain voltage of transistor NH,2, so that the drain voltage of transistor NH,1 is consistent with the drain voltage of transistor NH,2, ensuring that the voltage difference between the source and drain of transistor NH,1 is consistent with the voltage difference between the source and drain of transistor NH,2, thereby determining that the current flowing through transistor NH,2 is K1*(I-1).

[0080] In some embodiments, the first clamping circuit 112 includes a first operational amplifier 1121 and a second transistor 1122. The first operational amplifier 1121 includes a first input terminal and a second input terminal. The first input terminal is connected to the second terminal of the driving transistor 20, and the second input terminal is connected to the second terminal of the first mirror transistor 111 and the second terminal of the second transistor 1122. The output terminal of the first operational amplifier 1121 is connected to the control terminal of the second transistor 1122.

[0081] Specifically, with Figure 5 For example, the first operational amplifier 1121 can be set as operational amplifier OP1, and the second transistor 1122 can be set as transistor PH,1. The first input terminal can be set as the positive input terminal of operational amplifier OP1, and the second input terminal can be set as the negative input terminal of operational amplifier OP1. The positive input terminal of operational amplifier OP1 is connected to the VL terminal, and the negative input terminal of operational amplifier OP1 is connected to the second terminal of transistor PH,1 and the second terminal of transistor NH,2.

[0082] When transistor NH,1 is turned on, its drain is connected to the VL terminal, and the voltage applied to the VL terminal is the drain voltage of transistor NH,1. Operational amplifier OP1 can clamp the drain voltage of transistor NH,2 through negative feedback. The reference voltage can be provided by the VL terminal. When the drain voltage of NH,2 is less than the reference voltage provided by the VL terminal, operational amplifier OP1 can output a corresponding voltage to the control terminal of transistor PH,1, making the voltage at the second terminal of transistor PH,1 consistent with the reference voltage. That is, the drain voltage of transistor NH,2 becomes consistent with the reference voltage provided by the VL terminal, thus clamping the drain voltage of transistor NH,2 to match the drain voltage of transistor NH,1.

[0083] In some embodiments, the second current mirror circuit 130 includes at least one second mirror transistor 131. The control electrode of the first-stage second mirror transistor 131 is connected to the control electrode of the first transistor 120, and the second electrode of the first-stage second mirror transistor 131 is grounded. Each stage of the second mirror transistor 131 is configured to replicate the current flowing through the first transistor 120, or to replicate the current flowing through the previous stage of the second mirror transistor 131. The second mirror current is determined based on the current flowing through the at least one stage of the second mirror transistor 131.

[0084] Specifically, with Figure 6 For example, the second mirror transistor 131 can be set to any one of transistors NL,2, NL,4, and PH,3. W3 / L3 can be set to the width-to-length ratio of the NL,1 channel, W4 / L4 can be set to the width-to-length ratio of the NL,2 channel, W5 / L5 can be set to the width-to-length ratio of the NL,4 channel, and W6 / L6 can be set to the width-to-length ratio of the PH,3 channel. W4 / L4:W3 / L3 can be set to K2:1, W5 / L5:W4 / L4 can be set to K3:1, and W6 / L6:W5 / L5 can be set to K4:1.

[0085] In this configuration, transistor NL,2 can be configured as the second mirror transistor 131 in the first stage. The control electrode of transistor NL,2 can be connected to the control electrode of transistor NL,1. The second electrode of transistor NL,2 can be connected to the GND terminal. The current flowing through transistor NL,2 can be set as I-2,a, and the current flowing through transistor NL,2 can be set as K2*(I-2), where I-2,a = K2*(I-2). K2 can be arbitrarily set according to actual needs.

[0086] Transistor NL,4 can be configured as the second-stage second mirror transistor 131. The current flowing through transistor NL,4 can be set as I-2,b, where I-2,b = K3 * (I-2,a). K3 can be arbitrarily set according to actual needs. Transistor NH,3 can be configured as the third-stage second mirror transistor 131. The current flowing through transistor NH,3 can be set as I-2,c, where I-2,c = K4 * (I-2,b). K4 can be arbitrarily set according to actual needs.

[0087] The current IL can be the same as the current flowing through transistor PH,3, that is, IL=I-2,c=K4*K3*K2*(I-2).

[0088] The second current mirror circuit 130 can also be configured with corresponding fourth-stage mirror transistors, fifth-stage mirror transistors, and sixth-stage mirror transistors. The circuit structure and implementation of the fourth-stage second mirror transistor 131, the fifth-stage second mirror transistor 131, and the sixth-stage second mirror transistor 131 can be referred to the first-stage second mirror transistor 131, the second-stage second mirror transistor 131, and the third-stage second mirror transistor 131, and will not be described in detail here.

[0089] In some implementations, the current flowing through the first-stage second mirror transistor 131 is the current flowing from the ground to a negative potential, and the current flowing through the last-stage second mirror transistor 131 is the current flowing from the positive potential to the ground.

[0090] Specifically, with Figure 6 For example, the current acquisition circuit 100 may also include a positive voltage generation circuit and a negative voltage generation circuit. The positive voltage generation circuit can provide a positive potential voltage through the VDD terminal. The negative voltage generation circuit can provide a negative potential voltage through the Vneg terminal. The voltage provided by the VDD terminal can be 3.3V or 5V, and the voltage provided by the Vneg terminal can be -3.3V or -5V. The current I-2,a flowing through transistor NL,2 is the current flowing from the GND terminal to the Vneg terminal. The current I-2,b flowing through transistor NL,4 is the current flowing from the VDD terminal to the Vneg terminal, and the current I-2,c flowing through transistor PH,3 is the current flowing from the VDD terminal to the GND terminal.

[0091] The multi-stage second mirror transistor 131 can be used in conjunction to change the direction of current flow, so that the replicated current flows from the positive potential to the ground, so that the digital-to-analog converter circuit 150 can quantize the current acquisition value.

[0092] In some embodiments, the second current mirror circuit 130 has at least one third transistor 132, the first terminal of each third transistor 132 is connected to the first terminal of the corresponding previous second mirror transistor 131, the control terminal of each third transistor 132 is connected to the control terminal of the corresponding next second mirror transistor 131, and the second terminal of each third transistor 132 is connected to the second terminal of the corresponding next second mirror transistor 131.

[0093] Specifically, with Figure 6 For example, the third transistor 132 can be either transistor NL,3 or transistor PH,2. Specifically, the first terminal of transistor NL,3 can be connected to the first terminal of transistor NL,2, and the control terminal of transistor NL,3 can be connected to the control terminal of transistor NL,4 at the first terminal of transistor NL,3. The second terminal of transistor NL,3 can be connected to the second terminal of transistor NL,4 at the Vneg terminal. Similarly, the first terminal of transistor PH,2 can be connected to the first terminal of transistor NL,4, and the control terminal of transistor PH,2 can be connected to the control terminal of transistor PH,3 at the first terminal of transistor PH,2. The second terminal of transistor PH,2 can be connected to the second terminal of transistor PH,3 at the VDD terminal.

[0094] The third transistor 132 in each stage can be connected in series with the second mirror transistor 131 in the previous stage. The second mirror transistor 131 in the next stage can replicate the current flowing through the corresponding third transistor 132 in the first stage, and thus replicate the current flowing through the second mirror transistor 131 in the previous stage. The current flowing through transistor NL,3 is the same as the current flowing through transistor NL,2, and the current flowing through transistor NL,4 is the same as the current flowing through transistor NH,2.

[0095] In some embodiments, the second current mirror circuit 130 includes at least one second clamping circuit 133, each second clamping circuit 133 being connected to the first terminal of a corresponding first-stage second mirror transistor 131 and configured to clamp the first terminal voltage of the first-stage second mirror transistor 131 so that the first terminal voltage of each stage second mirror transistor 131 is consistent with the first terminal voltage of the first transistor 120 or with the first terminal voltage of the corresponding first-stage third transistor 132.

[0096] Specifically, with Figure 6 For example, the second clamping circuit 133 can clamp the drain voltage of transistor NL,2 so that the drain voltage of transistor NL,2 is consistent with the drain voltage of transistor NL,1, ensuring that the voltage difference between the source and drain of transistor NL,1 is consistent with the voltage difference between the source and drain of transistor NL,2, thereby determining that the current flowing through transistor NL,2 is K2*(I-2).

[0097] The second clamping circuit 133 can also clamp the drain voltage of transistor NL,4, so that the drain voltage of transistor NL,4 is consistent with the drain voltage of transistor NL,3, that is, the drain voltage of transistor NL,4 is consistent with the drain voltage of transistor NL,2, ensuring that the voltage difference between the source and drain of transistor NL,4 is consistent with the voltage difference between the source and drain of transistor NL,2, thereby determining that the current flowing through transistor NL,4 is K3*(I-2,a).

[0098] The second clamping circuit 133 can also clamp the drain voltage of transistor NH,3, so that the drain voltage of transistor NH,3 is consistent with the drain voltage of transistor NH,2, that is, the drain voltage of transistor NH,3 is consistent with the drain voltage of transistor NL,4, ensuring that the voltage difference between the source and drain of transistor NL,4 is consistent with the voltage difference between the source and drain of transistor NH,3, thereby determining that the current flowing through transistor NH,3 is K4*(I-2,b).

[0099] In some embodiments, each of the second clamping circuits 133 includes a second operational amplifier 1331 and a fourth transistor 1332. The second operational amplifier 1331 includes a third input terminal and a fourth input terminal. The fourth input terminal is connected to the first terminal of the corresponding first-stage second mirror transistor 131 and the second terminal of the fourth transistor 1332. The output terminal of the second operational amplifier 1331 is connected to the control terminal of the fourth transistor 1332. The third input terminal is connected to the first terminal of the first transistor 120, or the third input terminal is connected to the first terminal of the corresponding first-stage third transistor 132.

[0100] Specifically, with Figure 6 For example, the second operational amplifier 1331 can be set as operational amplifier OP2, and the fourth transistor 1332 can be set as transistor PH,6. The third input terminal can be set as the positive input terminal of operational amplifier OP2, and the fourth input terminal can be set as the negative input terminal of operational amplifier OP2. The positive input terminal of operational amplifier OP2 is connected to the VL terminal, and the negative input terminal of operational amplifier OP2 is connected to the second terminal of transistor PL,2 and the second terminal of transistor NL,3.

[0101] When transistor NL,1 is turned on, its drain is connected to the VL terminal, and the voltage applied to the VL terminal is the drain voltage of transistor NL,1. Operational amplifier OP2 can clamp the drain voltage of transistor NL,2 through negative feedback. When the drain voltage of NL,2 is less than the reference voltage provided by the VL terminal, op-amp OP2 can output a corresponding voltage to the control terminal of transistor PH,6, making the voltage at the second terminal of transistor PH,6 consistent with the reference voltage; that is, the drain voltage of transistor NL,2 is consistent with the drain voltage of transistor NL,1.

[0102] The second operational amplifier 1331 can also be configured as operational amplifier OP3, and the fourth transistor 1332 can be configured as transistor PH,5. The third input terminal can be configured as the positive input terminal of operational amplifier OP3, and the fourth input terminal can be configured as the negative input terminal of operational amplifier OP3. The positive input terminal of operational amplifier OP3 is connected to the drain of transistor PL,3, and the negative input terminal of operational amplifier OP3 is connected to the second terminals of transistor PL,4 and transistor PH,5.

[0103] Operational amplifier OP3 can clamp the drain voltage of transistor NL,4 through negative feedback. When the drain voltage of transistor NL,4 is less than the drain voltage of transistor PL,3, op-amp OP3 can output the corresponding voltage to the control electrode of transistor PH,5, so that the drain voltage of transistor NL,4 is consistent with the drain voltage of transistor PL,3.

[0104] The second operational amplifier 1331 can also be configured as operational amplifier OP4, and the fourth transistor 1332 can be configured as transistor PH,4. The third input terminal can be configured as the positive input terminal of operational amplifier OP4, and the fourth input terminal can be configured as the negative input terminal of operational amplifier OP4. The positive input terminal of operational amplifier OP4 is connected to the drain of transistor PH,2, and the negative input terminal of operational amplifier OP4 is connected to the second terminals of transistors PH,3 and PH,4.

[0105] Operational amplifier OP4 can clamp the drain voltage of transistor PH,3 through negative feedback. When the drain voltage of transistor PH,3 is less than the drain voltage of transistor PH,2, op-amp OP4 can output the corresponding voltage to the control electrode of transistor PH,4, so that the drain voltage of transistor PH,3 is consistent with the drain voltage of transistor PH,2.

[0106] Reference Figure 7 This application also provides a linear solenoid valve 2000, which includes the current acquisition circuit 100 or the load control circuit 1000 described in the above embodiments. The linear solenoid valve 2000 can include all the technical effects of the current acquisition circuit 100 of the embodiments of this application, which will not be repeated here.

[0107] Specifically, the linear solenoid valve 2000 may include a linear solenoid valve, the degree of opening and closing of which is proportional to the current flowing through the load 10. The load control circuit 1000 provided in this application embodiment can control the current flowing through the load 10 to control the degree of opening and closing of the linear solenoid valve.

[0108] Reference Figure 8 This application also provides a vehicle 3000, which may include the current acquisition circuit 100 of the above embodiments or the linear solenoid valve 2000. All the technical effects of the current acquisition circuit 100 of the embodiments of this application can be included in the vehicle 3000, and will not be repeated here.

[0109] In the description of this specification, the references to terms such as "some embodiments," "in one example," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0110] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0111] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are optional and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A current harvesting circuit for harvesting current flowing through a load, characterized by, The current collection circuit comprises: a first current mirror circuit configured to copy a current flowing through the driving transistor as a first mirror current; a first transistor connected between the driving transistor and a ground, the first transistor being configured to be turned off when the driving transistor is turned on; a second current mirror circuit configured to copy a current flowing through the first transistor as a second mirror current; when the first transistor is turned off, the current collection circuit is configured to determine a current collection value according to the first mirror current, and when the first transistor is turned on, the current collection circuit is configured to determine a current collection value according to the second mirror current.

2. The current harvesting circuit of claim 1, wherein, The driving transistor is configured to be turned on or turned off according to a driving signal provided by a driving circuit, and the current collection circuit comprises: a first control circuit connected between the driving circuit and a control electrode of the first transistor, and configured to control the first transistor to be turned off when the driving circuit provides the driving signal, so that the first transistor is turned off when the driving transistor is turned on.

3. The current harvesting circuit of claim 2, wherein, The driving transistor is configured to be turned off when the driving circuit stops providing the driving signal, and the first control circuit is configured to control the first transistor to be turned on when the driving circuit stops providing the driving signal.

4. The current harvesting circuit of claim 1, wherein, The first current mirror circuit comprises a first mirror transistor, a control electrode of the first mirror transistor is connected to a control electrode of the driving transistor, a first electrode of the first mirror transistor and a first electrode of the driving transistor are connected to a voltage source of the load, and the first mirror current is determined according to a current flowing through the first mirror transistor.

5. The current harvesting circuit of claim 4, wherein, The first current mirror circuit comprises a first clamping circuit connected to a second electrode of the first mirror transistor, and the first clamping circuit is configured to clamp a voltage of the second electrode of the first mirror transistor, so that the voltage of the second electrode of the first mirror transistor is consistent with a voltage of a second electrode of the driving transistor.

6. The current harvesting circuit of claim 5, wherein, The first clamping circuit comprises a first operational amplifier and a second transistor, the first operational amplifier comprises a first input terminal and a second input terminal, the first input terminal is connected to the second electrode of the driving transistor, the second input terminal is connected to the second electrode of the first mirror transistor and a second electrode of the second transistor, and an output terminal of the first operational amplifier is connected to a control electrode of the second transistor.

7. The current harvesting circuit of claim 1, wherein, The second current mirror circuit comprises at least one second mirror transistor, a control electrode of the first second mirror transistor is connected to a control electrode of the first transistor, and a second electrode of the first second mirror transistor is grounded; Each second mirror transistor is configured to copy a current flowing through the first transistor, or is configured to copy a current flowing through a previous second mirror transistor, and the second mirror current is determined according to a current flowing through at least one second mirror transistor.

8. The current harvesting circuit of claim 7, wherein, The current flowing through the first-stage second mirror transistor is a current flowing from the ground to a negative potential, and the current flowing through the last-stage second mirror transistor is a current flowing from a positive potential to the ground.

9. The current harvesting circuit of claim 7, wherein, The second current mirror circuit comprises at least one second clamping circuit, each second clamping circuit being connected to the first electrode of a corresponding second mirror transistor and configured to clamp the voltage of the first electrode of the corresponding second mirror transistor, so that the voltage of the first electrode of each second mirror transistor is consistent with the voltage of the first electrode of the first transistor, or consistent with the voltage of the first electrode of the corresponding third transistor.

10. The current harvesting circuit of claim 9, wherein, Each second clamping circuit comprises a second operational amplifier and a fourth transistor, the second operational amplifier comprising a third input terminal and a fourth input terminal, the fourth input terminal being connected to the first electrode of the corresponding second mirror transistor and the second electrode of the fourth transistor, and the output terminal of the second operational amplifier being connected to the control electrode of the fourth transistor.

11. The current harvesting circuit of claim 10, wherein, The third input terminal is connected to the first electrode of the first transistor, or the third input terminal is connected to the first electrode of the corresponding third transistor. The current acquisition circuit comprises:

12. A load control circuit, characterized by The current acquisition circuit according to any one of claims 1-10; The driving circuit is configured to provide a driving signal for the driving transistor according to the current acquisition value determined by the current acquisition circuit, so as to drive the driving transistor to be turned on or turned off, thereby controlling the current flowing through the load. The driving circuit comprises:

13. The load control circuit of claim 12, wherein, The second control circuit is configured to determine a current control signal according to the current acquisition value; The comparator is configured to provide a pulse width modulation signal for the driving transistor according to the current control signal and a ramp signal, so as to drive the driving transistor to be turned on or turned off, thereby controlling the current flowing through the load. The linear electromagnetic valve comprises the current acquisition circuit according to any one of claims 1-11, or the load control circuit according to claim 12 or 13.

14. A linear solenoid valve characterized by comprising: The vehicle comprises the current acquisition circuit according to any one of claims 1-11, or the linear electromagnetic valve according to claim 14.

15. A vehicle characterized by comprising: ​

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