Light detector with integrated grating coupler

Abstract

The invention relates to a light detector with an integrated grating coupler. The present disclosure relates to a structure for a photonic chip including a photodetector and a grating coupler and a method of forming such a structure. The structure includes a photodetector including a semiconductor layer, and a grating coupler adjacent to the semiconductor layer of the photodetector. The structure also includes a waveguide core including a portion laterally spaced from the grating coupler.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to photonic chips, and more particularly to structures for photonic chips including photodetectors and grating couplers and methods of forming such structures. BACKGROUND

[0002] Photonic chips can be used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips include photonic integrated circuits composed of optical components such as modulators, polarizers, and optical couplers that are used to manipulate light received from a light source, such as a fiber or a laser. Photodetectors can be employed in photonic integrated circuits to convert light that can be modulated into an optical signal into an electrical signal.

[0003] There is a need for improved structures for photonic chips including photodetectors and grating couplers and methods of forming such structures. SUMMARY

[0004] In an embodiment of the invention, a structure for a photonic chip is provided. The structure includes a photodetector including a semiconductor layer and a grating coupler adjacent to the semiconductor layer of the photodetector. The structure further includes a waveguide core including a portion laterally spaced apart from the grating coupler.

[0005] In an embodiment of the invention, a method of forming a structure for a photonic chip is provided. The method includes forming a photodetector including a semiconductor layer, forming a grating coupler adjacent to the semiconductor layer of the photodetector, and forming a waveguide core including a portion laterally spaced apart from the grating coupler. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the present invention. In the drawings, like reference numerals indicate the same features in the various views.

[0007] Figure 1 is a top view of a structure in accordance with an embodiment of the invention, in an initial manufacturing stage of a processing method.

[0008] Figure 2 is a cross-sectional view taken generally along line 2-2 in Figure 1

[0009] Figure 2A is a cross-sectional view taken generally along line 2A-2A in Figure 1

[0010] Figure 2B is a cross-sectional view taken generally along​​Figure 1 The cross-sectional view taken from line 2B-2B in the diagram.

[0011] Figure 3 , 3A 3B is Figure 1 , 2 Cross-sectional view of the structure in the manufacturing stage of the processing methods after 2A and 2B.

[0012] Figure 4 This is a top view of the structure according to an alternative embodiment of the present invention.

[0013] Figure 5 This is a schematic top view of the structure according to an alternative embodiment of the present invention. Detailed Implementation

[0014] refer to Figure 1 , 2 According to embodiments of the present invention, structure 10 includes a waveguide core 12 and a photodetector 14 located on and above a dielectric layer 16 and a semiconductor substrate 18. The dielectric layer 16 is disposed on the semiconductor substrate 18. In embodiments, the dielectric layer 16 may be made of a dielectric material such as silicon dioxide, and the semiconductor substrate 18 may be made of a semiconductor material such as single-crystal silicon. In embodiments, the dielectric layer 16 may be a buried oxide layer on a silicon-on-insulator substrate, and the dielectric layer 16 may provide a low-refractive-index cladding.

[0015] Structure 10 includes a pad 24 having a side edge 30, a side edge 31 opposite to the side edge 30, a side edge 32 opposite to the side edge 32, and a side edge 33 opposite to the side edge 32. The side edges 30, 31, 32, and 33 may surround the outer periphery of the pad 24, and the side edges 30, 31, 32, and 33 may extend from the top surface of the pad 24 to the top surface of the dielectric layer 16.

[0016] The photodetector 14 includes a semiconductor layer 26 providing a light-absorbing layer disposed on a pad 24 and having an inwardly spaced distance from the outer periphery of the pad 24. The semiconductor layer 26 may have a periphery surrounded by a sidewall 34, a sidewall 35 opposite to the sidewall 34, a sidewall 36, and a sidewall 37 opposite to the sidewall 36. The sidewall 34 is positioned adjacent to a side edge 30 of the pad 24, the sidewall 35 is spaced apart from a side edge 31 of the pad 24, the sidewall 36 is positioned adjacent to a side edge 32 of the pad 24, and the sidewall 37 is positioned adjacent to a side edge 33 of the pad 24. The semiconductor layer 26 extends along a longitudinal axis 22 from the sidewall 34 to the sidewall 35. A portion of the pad 24 is laterally positioned between the sidewall 36 of the semiconductor layer 26 and the side edge 32 of the pad 24. Another portion of the pad 24 is laterally positioned between the sidewall 37 of the semiconductor layer 26 and the side edge 33 of the pad 24.

[0017] The waveguide core 12 includes a portion disposed laterally adjacent to the side edge 33 of the spacer 24. The spacer 24 can include a grating coupler 40 configured to receive light laterally coupled from the laterally adjacent portion of the waveguide core 12 and transmit the light to the photodetector 14. The grating coupler 40 is located on and above the dielectric layer 16 and the semiconductor substrate 18, and can be located in the same horizontal plane as the waveguide core 12. The grating coupler 40 is located between the sidewall 35 of the semiconductor layer 26 and the side edge 31 of the spacer 24.

[0018] The grating coupler 40 includes segments 42 and trenches 44 positioned in groups adjacent to the semiconductor layer 26. The trenches 44, which have a width dimension Wl, can represent perforations in the spacer 24 that fully penetrate the spacer 24 to the dielectric layer 16. The segments 42 and the trenches 44 can be arranged such that one of the trenches 44 is laterally located between each pair of adjacent segments 42. In embodiments, the length dimension L of the segments 42 and the trenches 44 can increase with distance from the semiconductor layer 26, such that the narrowest segments 42 and the narrowest trenches 44 are closest to the sidewall 35 of the semiconductor layer 26. The segments 42 can be aligned along a longitudinal axis 43. In embodiments, the longitudinal axis 43 can be aligned parallel to the longitudinal axis 22 of the semiconductor layer 26.

[0019] The segments 42 of the grating coupler 40 can be sized and positioned with a grating pitch that is small enough to define a subwavelength Bragg grating. For example, the period of the segments 42 can be less than half the wavelength of light propagating in the waveguide core 12. In embodiments, the grating pitch and duty cycle with which the segments 42 are sized and positioned can be uniform. In alternative embodiments, the grating pitch and duty cycle of the segments 42 can be aperiodic (i.e., non-uniform).

[0020] In embodiments, the waveguide core 12 and the spacer 24 can be composed of a material having a refractive index greater than that of silicon dioxide. In embodiments, the waveguide core 12 and the spacer 24 can be composed of a semiconductor material. In embodiments, the waveguide core 12 and the spacer 24 can be composed of single crystalline silicon. The waveguide core 12 and the spacer 24 of the photodetector 14 can be formed by patterning a layer composed of the material thereof using photolithography and etching processes. The trenches 44 can be formed when the spacer 24 is patterned to define the side edges 30, 31, 32, 33. In embodiments, the waveguide core 12 and the spacer 24 of the photodetector 14 can be formed by patterning a semiconductor material, such as single crystalline silicon, of a device layer of a silicon-on-insulator substrate.

[0021] The semiconductor layer 26 is composed of a light-absorbing material capable of performing photoelectric conversion by converting photon energy of light into an electrical signal. In an embodiment, the semiconductor layer 26 can be composed of an intrinsic semiconductor material. In an embodiment, the semiconductor layer 26 can be composed of intrinsic germanium. In an embodiment, the semiconductor layer 26 can be composed of intrinsic silicon-germanium. In an alternative embodiment, the semiconductor layer 26 can be composed of a different type of semiconductor material, such as a III-V compound semiconductor material or intrinsic silicon.

[0022] The photodetector 14 can include a doped region 46 formed between the side edge 32 of the pad 24 and the sidewall 36 of the semiconductor layer 26. The photodetector 14 can include a doped region 48 formed between the side edge 33 of the pad 24 and the sidewall 37 of the semiconductor layer 26. The doped region 46 can be different in conductivity type from the doped region 48. The semiconductor layer 26 is laterally positioned on the pad 24 between the doped region 46 and the doped region 48. The doped regions 46, 48 can extend completely through the entire thickness of the pad 24 to the underlying dielectric layer 16. In an embodiment, the doped region 46 can define an anode of the photodetector 14, and the doped region 48 can define a cathode of the photodetector 14. In an alternative embodiment, the doped region 46 can define a cathode of the photodetector 14, and the doped region 48 can define an anode of the photodetector 14.

[0023] The doped region 46 can be formed by, for example, ion implantation using an implantation mask having an opening that defines an implantation area of the pad 24. The implantation mask can include a photoresist layer applied by a spin-on process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an opening over the area of the pad 24 to be implanted. Implantation conditions such as ion species, dose, and kinetic energy can be selected to adjust the electrical and physical properties of the doped region 46. The implantation mask can be stripped after the doped region 46 is formed. In an embodiment, the semiconductor material of the doped region 46 can include a p-type dopant, such as boron, that provides p-type conductivity. In an alternative embodiment, the semiconductor material of the doped region 46 can include an n-type dopant, such as phosphorus or arsenic, that provides n-type conductivity. In an alternative embodiment, a portion of the semiconductor layer 26 immediately adjacent to the doped region 46 can also be implanted due to overlap of the opening in the implantation mask with the portion of the semiconductor layer 26.

[0024] Doped region 48 can be formed by ion implantation, for example, using an implantation mask having openings that define the implanted regions of pad 24. The implantation mask can include a photoresist layer applied by a spin-on process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define openings over the regions of pad 24 to be implanted. Implantation conditions such as ion species, dose, and kinetic energy can be selected to adjust the electrical and physical properties of doped region 48. The implantation mask can be stripped after doped region 48 is formed. In an embodiment, if doped region 46 includes a p-type dopant, the semiconductor material of doped region 48 can include an n-type dopant, such as phosphorus or arsenic, that provides n-type conductivity. In an alternative embodiment, if doped region 46 includes an n-type dopant, the semiconductor material of doped region 48 can include a p-type dopant, such as boron, that provides p-type conductivity. In an alternative embodiment, portions of semiconductor layer 26 immediately adjacent to doped region 48 can also be implanted due to overlap of the openings in the implantation mask with portions of semiconductor layer 26.

[0025] A portion of pad 24 beneath semiconductor layer 26 can be composed of intrinsic semiconductor material, such as intrinsic silicon, that is not doped by the ion implantation that forms doped region 46 and the ion implantation that forms doped region 48. The intrinsic semiconductor material of doped region 46, semiconductor layer 26, and the portion of pad 24 beneath semiconductor layer 26, and doped region 48 can define a lateral p-i-n diode that contributes to the functionality of photodetector 14.

[0026] A heavily doped region 47 can be formed in a portion of doped region 46 adjacent to side edge 32 of pad 24 by masked ion implantation, and a heavily doped region 49 can be formed in a portion of doped region 48 adjacent to side edge 33 of pad 24 by masked ion implantation. Heavily doped region 47 can have the same conductivity type as doped region 46, but a higher dopant concentration. Heavily doped region 49 can have the same conductivity type as doped region 48, but a higher dopant concentration.

[0027] In an alternative embodiment, photodetector 14 can have a vertical arrangement instead of a lateral arrangement. Specifically, in a vertical arrangement, doped region 46 and heavily doped region 47 can be arranged in pad 24 on one or both sides of semiconductor layer 28, and doped region 48 and heavily doped region 49 can be arranged in an upper portion of semiconductor layer 28. In an alternative embodiment, photodetector 14 can be configured as an avalanche photodetector that includes an intrinsic semiconductor region in pad 24 that defines a multiplication region and an additional doped region in pad 24 that defines a charge control region.

[0028] Reference is made to Figure 3 , 3A , 3B, where like reference numerals refer to like elements in Figure 1 ,2 The same features as in 2A and 2B allow for the formation of a dielectric layer 50 over the waveguide core 12, photodetector 14, and grating coupler 40 during subsequent manufacturing stages. The dielectric layer 50 can be made of a dielectric material such as silicon dioxide, which is deposited and then planarized after deposition. The dielectric material constituting the dielectric layer 50 can have a lower refractive index than the materials constituting the waveguide core 12 and the pad 24. One or more conformal dielectric layers (not shown) can be formed over the photodetector 14 prior to the formation of the dielectric layer 50.

[0029] The dielectric material of the dielectric layer 50 can be located in the trenches 44 between the segments 42, such that the metamaterial structure can be defined as a region of the pad 24 in which the material constituting the segments 42 has a higher refractive index than the dielectric material of the dielectric layer 50. The metamaterial structure can be considered as a homogeneous material having an effective refractive index between the refractive index of the material constituting the segments 42 and the refractive index of the dielectric material constituting the dielectric layer 50.

[0030] Contact 52 can be formed that completely penetrates the dielectric layer 50 to land on the heavily doped region 47. Contact 54 can be formed that completely penetrates the dielectric layer 50 to land on the heavily doped region 49. The heavily doped region 47 electrically couples contact 52 to doped region 46. The heavily doped region 49 electrically couples contact 54 to doped region 48. Contacts 52 and 54 can be made of a metal such as tungsten. Doped regions 46 and 48 can be biased by contacts 52 and 54, which can be coupled to interconnect 56, which is formed as a metallization in an interlayer dielectric layer (not shown) formed above the dielectric layer 50.

[0031] In use, light, such as laser light, propagates in waveguide core 12 to the vicinity of grating coupler 40 and is laterally coupled from waveguide core 12 to grating coupler 40. In an embodiment, light received by photodetector 14 from waveguide cores 12, 13 can be modulated into an optical signal. Grating coupler 40 reflects the light in a direction opposite to the propagation direction in waveguide core 12 to semiconductor layer 26 of photodetector 14. Semiconductor layer 26 absorbs photons of the light and converts the absorbed photons into charge carriers through photoelectric conversion. Biasing of doped regions 46, 48 causes charge carriers to be collected and output from photodetector 14 to provide a measurable photocurrent over time.

[0032] Structure 10 can rely on subwavelength reverse coupling of light from waveguide core 12 to photodetector 14 via grating coupler 40. This reverse coupling of light to grating coupler 40 can be characterized by high wavelength selectivity and high coupling efficiency. Grating coupler 40 can be configured to reflect light within a selected wavelength band and have a peak optical power selectable by the configuration of segments 42 and trenches 44. The grating coupler 40 of structure 10 is a passive photonic component, requiring neither power supply nor a large footprint to provide wavelength selectivity when supplying light to photodetector 14. In the latter respect, structure 10 differs from Mach-Zehnder interferometer lattices with significantly larger footprints suitable for wavelength division multiplexing.

[0033] refer to Figure 4 According to an alternative embodiment, the grating coupler 58 may be formed having segments 60 and ribs 62 overlapping the segments 60. The grating coupler 58 is configured to receive light laterally coupled from the waveguide core 12 and guide that light to the photodetector 14. The grating coupler 58 is positioned adjacent to the sidewalls 35 of the semiconductor layer 26 and the side edges 31 of the pad 24. Adjacent pairs of segments 60 are separated by gaps having a width dimension W2, the gaps being bridged by the ribs 62. The segments 60 may be arranged such that one of the gaps is laterally positioned between each pair of adjacent segments 60. In an embodiment, the width dimension W2 of the segments 60 may be constant, and the width dimension of the ribs 62 may vary within the length of the grating coupler 58. The segments 60 may be aligned along a longitudinal axis 61, and the longitudinal axis 61 may be aligned parallel to the longitudinal axis 22 of the semiconductor layer 26.

[0034] The segments 60 of the grating coupler 58 can be sized and positioned with a sufficiently small grating pitch to define a subwavelength grating. For example, the period of segment 60 can be less than half the wavelength of the light propagating in waveguide core 12. In one embodiment, the grating pitch and duty cycle of segment 60 can be uniform. In an alternative embodiment, the grating pitch and duty cycle of segment 60 can be non-periodic (i.e., non-uniform).

[0035] The gaps between segments 60 can be filled with the dielectric material of the subsequently deposited dielectric layer 50, allowing the metamaterial structure to be defined by the grating coupler 58, wherein the material constituting segments 60 has a higher refractive index than the dielectric material of dielectric layer 50. The metamaterial structure can be considered as a homogeneous material having an effective refractive index between the refractive index of the material constituting segments 60 and the refractive index of the dielectric material constituting dielectric layer 50.

[0036] refer to Figure 5According to an alternative embodiment, the wavelength division multiplexing (WDM) receiver 66 can be configured as a multichannel device comprising instances of multiple structures 10, each including a grating coupler 58 and a photodetector 14. A waveguide core 12 is routed in the layout of the WDM receiver 66 to have corresponding portions adjacent to different instances of the grating couplers 58. The WDM receiver 66 can receive multiplexed light 70 propagating in the waveguide core 12, the multiplexed light 70 comprising multiple optical signals of different wavelengths, such as multiple different wavelengths within the near-infrared portion of the electromagnetic spectrum. Each grating coupler 58 can be configured, for example, by selecting a grating pitch and duty cycle that determines the size and location of the segment 42, to laterally couple optical power of a specific wavelength among the different wavelengths of the multiplexed light 70. In this way, instances of the grating couplers 58 and the photodetector 14 can allow optical power characterized by each of the different wavelengths to be separated into different channels of the multichannel device.

[0037] In an alternative embodiment, in addition to the photodetector 14, the wavelength division multiplexing receiver 66 may also include a plurality of devices having grating couplers 40 ( Figure 1 ) is an example of structure 10.

[0038] Compared to other types of wavelength division multiplexing (WDM) receivers, such as those relying on Mach-Zehnder interferometer lattices, the reliance on instances of grating coupler 58 allows the WDM receiver 66 to have a compact footprint. Grating coupler 58 provides a passive photonic component for achieving wavelength selectivity. Each instance of grating coupler 58 and photodetector 14 integrates optical detection and wavelength filtering into an integrated photonic component.

[0039] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of intermediate or final products. The final product can be any product that includes integrated circuit chips, such as a computer product with a central processing unit or a smartphone.

[0040] References to terms modified by approximate language such as “approximately,” “about,” or “substantially” are not limited to the specified exact values ​​or conditions. In embodiments, approximate language may indicate a range of + / -10% of the value or condition.

[0041] The use of terms such as “vertical” and “horizontal” in this document is by way of example rather than limitation, in order to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to directions in the frame of reference perpendicular to the horizontal plane just defined. The term “lateral” refers to a direction within the horizontal plane in the frame of reference.

[0042] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly connected” or “directly coupled” to or with another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or with another feature. A feature that is “on” or “in contact” with another feature can be directly on or in direct contact with that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly” on or in direct contact with another feature. If at least one intermediate feature exists, a feature can be “indirectly” on or indirectly in contact with another feature. If a feature extends over and covers a portion of another feature, the different features can “overlap.”

[0043] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photonic chip, the structure comprising: a first photodetector comprising a first semiconductor layer; a first grating coupler adjacent to the first semiconductor layer of the first photodetector; and a waveguide core comprising a first portion laterally spaced apart from the first grating coupler.

2. The structure of claim 1, further comprising: a spacer, wherein the first semiconductor layer is on the spacer, the spacer comprises a first side edge, the first semiconductor layer comprises a sidewall, and the first grating coupler is in the spacer between the first side edge of the spacer and the sidewall of the first semiconductor layer. the spacer comprises a second side edge, and the first portion of the waveguide core is positioned adjacent to the second side edge of the spacer.

3. The structure of claim 2, wherein, the first portion of the waveguide core is laterally spaced apart from the second side edge of the spacer by a gap.

4. The structure of claim 3, wherein, the first grating coupler comprises a plurality of trenches in the spacer and a plurality of segments between the plurality of trenches, and each trench is disposed between an adjacent pair of the plurality of segments.

5. The structure of claim 2, wherein, the plurality of segments are sized and positioned to define a subwavelength grating, and the plurality of trenches are filled with a dielectric material.

6. The structure of claim 5, wherein, the spacer comprises a first doped region of a first conductivity type, a second doped region of a second conductivity type different from the first conductivity type, and the first semiconductor layer is laterally positioned between the first doped region and the second doped region.

7. The structure of claim 2, wherein, 8. The structure of claim 1, further comprising: a spacer, wherein the first semiconductor layer is on the spacer, the spacer comprises a first side edge, the first semiconductor layer comprises a sidewall adjacent to the first side edge of the spacer, and the first grating coupler comprises a plurality of segments positioned adjacent to the first side edge of the spacer. the first side edge of the spacer is between the plurality of segments and the sidewall of the first semiconductor layer.

9. The structure of claim 8, wherein, the first portion of the waveguide core is positioned laterally adjacent to the plurality of segments of the first grating coupler.

10. The structure of claim 8, wherein, the first portion of the waveguide core is laterally spaced apart from the plurality of segments of the first grating coupler by a gap.

11. The structure of claim 10, wherein, the first grating coupler comprises a plurality of gaps between the plurality of segments, each gap is disposed between an adjacent pair of the plurality of segments, the plurality of segments are sized and positioned to define a subwavelength grating, and the plurality of gaps are filled with a dielectric material.

12. The structure of claim 8, wherein, the spacer comprises a first doped region of a first conductivity type, a second doped region of a second conductivity type different from the first conductivity type, and the first semiconductor layer is laterally positioned between the first doped region and the second doped region.

13. The structure of claim 8, wherein, 14. The structure of claim 1, further comprising: a second photodetector comprising a second semiconductor layer; and a second grating coupler adjacent to the second semiconductor layer of the second photodetector, wherein the waveguide core comprises a second portion laterally spaced apart from the second grating coupler. ​ ​ 15. The structure of claim 14, wherein, The first grating coupler is configured to laterally couple light in a first wavelength band to the first semiconductor layer, the second grating coupler is configured to laterally couple light in a second wavelength band to the second semiconductor layer, and the first wavelength band is different than the second wavelength band.

16. The structure of claim 1, wherein, The first semiconductor layer includes germanium.

17. The structure of claim 1, wherein, The first semiconductor layer includes a first longitudinal axis, the first grating coupler includes a second longitudinal axis and a plurality of segments aligned along the second longitudinal axis, and the second longitudinal axis is parallel to the first longitudinal axis.

18. The structure of claim 1, wherein, The first grating coupler is configured to provide counter-coupling of light from the first portion of the waveguide core to the first semiconductor layer of the first photodetector.

19. The structure of claim 1, further comprising: a semiconductor substrate; and a dielectric layer disposed on the semiconductor substrate, wherein the waveguide core, the first photodetector, and the first grating coupler are on the dielectric layer.

20. A method of forming a structure for a photonic chip, the method comprising: forming a photodetector including a semiconductor layer; forming a grating coupler adjacent to the semiconductor layer of the photodetector; and forming a waveguide core including a portion laterally spaced apart from the grating coupler.

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