Multi-transmission instruction scheduling method and multi-transmission instruction scheduling device

Abstract

The invention relates to a multi-transmission instruction scheduling device and a multi-transmission instruction scheduling method. The device comprises a thread beam scheduling module used for receiving a plurality of thread beams, executing a bubble instruction on the plurality of thread beams to eliminate plate conflict of a single instruction and extracting a plurality of instructions conforming to a scheduling strategy from the plurality of thread beams according to the preset scheduling strategy; the conflict detection module is used for detecting plate conflicts among the plurality of instructions and selecting M instructions without the plate conflicts among the plurality of instructions from the plurality of instructions, and M is equal to 3; and the instruction distribution module is used for distributing the M instructions selected by the conflict detection module. According to the invention, the hardware overhead can be reduced and the utilization rate of instruction generation can be improved.

Description

Technical Field

[0001] This invention relates to processor technology, specifically to a multi-issue instruction scheduling method, a multi-issue instruction scheduling device, and a processor. Background Technology

[0002] Multiple-issue instruction scheduling is mainly used in the fields of computer architecture and processor design. This technology allows the processor to execute multiple instructions simultaneously within a single clock cycle, thereby significantly improving the processor's execution efficiency.

[0003] Several schemes exist for multi-issue instruction scheduling in existing technologies, but each has its shortcomings. In superscalar processors, a reservation and reordering mechanism is used to achieve multi-issue instructions, eliminating data hazards caused by consecutive instructions. After decoding, an instruction is allocated to a reservation, and the status of the registers corresponding to the instruction's operands is checked. Only after the previous instruction is written to the register can the current instruction be issued to the downstream execution unit. However, this approach has two problems: First, each instruction is placed in a reservation, and when the reservation is full, no new instructions can be issued. Second, for performance reasons, a reservation needs to be allocated for each type of computation, thus increasing the physical area required.

[0004] Another approach in streaming processors employs a scoreboard and operand collector to avoid register hazards and block conflicts in order to schedule thread bundles and issue instructions. The scoreboard records the current readiness status of all registers; an instruction can only be issued when all registers corresponding to its operands are ready. Each instruction is allocated a collector unit upon entering the register read phase. An arbitrator among multiple collector units prevents block conflicts between operands, allowing multiple instructions to overlap in reading source operands and improving throughput. However, in the worst-case scenario, if the operands of multiple instructions happen to be located in the same block, completing all operand reads requires a significant delay, making reverse blocking instruction issuance a bottleneck. Summary of the Invention

[0005] In order to solve the problems in the prior art, the present invention aims to provide a multi-issue instruction scheduling method and a multi-issue instruction scheduling device that can reduce hardware overhead and improve instruction generation utilization.

[0006] A multi-launch command scheduling apparatus according to one aspect of the present invention includes:

[0007] The thread bundle scheduling module is used to receive multiple thread bundles, execute bubble instructions for the multiple thread bundles to eliminate block conflicts of a single instruction, and extract multiple instructions that conform to the scheduling strategy from the multiple thread bundles according to the preset scheduling strategy.

[0008] A conflict detection module is used to detect plate conflicts between the multiple instructions and select M instructions from the multiple instructions that do not have plate conflicts, where M is a natural number; and

[0009] The instruction distribution module is used to distribute the M instructions selected by the conflict detection module.

[0010] Optionally, M = 3.

[0011] Optionally, in the thread bundle scheduling module, executing bubble instructions for the multiple thread bundles to eliminate block conflicts of individual instructions includes:

[0012] For the plurality of thread bundles, execute the bubble instruction of the thread bundle itself; and

[0013] Execute bubble instructions inserted by the compiler.

[0014] Optionally, the conflict detection module divides the register group accessed by the instruction into register blocks using a low-order address interleaving pattern, detects whether there are block conflicts between the multiple instructions and selects 3 instructions that do not have block conflicts.

[0015] Optionally, the register block is divided into a vector register group and a scalar register group.

[0016] Optionally, detecting whether there is a block conflict between the multiple instructions in the register blocks includes:

[0017] Each register block uses a dual-port memory;

[0018] If there is only one read and write operation per register block in a cycle, then no block conflict is detected. If two or more instructions in a cycle read or write the same register block simultaneously in the fetch or write-back pipeline, then a block conflict is detected.

[0019] Optionally, the preset scheduling strategy includes: an old-priority strategy and a round-robin strategy.

[0020] The multi-issue command scheduling method of this invention includes:

[0021] The thread bundle scheduling step involves receiving multiple thread bundles, executing thread bundle execution bubble instructions for the multiple thread bundles to eliminate block conflicts of individual instructions, and extracting multiple instructions that conform to the scheduling strategy from the multiple thread bundles according to the pre-set scheduling strategy.

[0022] The conflict detection step involves detecting board conflicts among the multiple instructions and selecting M instructions from the multiple instructions that do not have board conflicts, where M is a natural number; and

[0023] The instruction distribution step distributes the M instructions selected in the conflict detection step.

[0024] Optionally, M = 3.

[0025] Optionally, the thread beam scheduling step includes:

[0026] For the plurality of thread bundles, execute the bubble instruction of the thread bundle itself; and

[0027] Execute bubble instructions inserted by the compiler.

[0028] Optionally, the collision detection step includes:

[0029] For register groups accessed by instructions, register blocks are divided using a low-order address interleaving pattern;

[0030] Detecting whether there are plate conflicts between the multiple instructions in the register plate; and

[0031] Select 3 instructions that do not have plate conflicts.

[0032] Optionally, the register block includes a vector register group and a scalar register.

[0033] Optionally, detecting plate conflicts between register plates for the multiple instructions includes:

[0034] Each register block uses a dual-port memory;

[0035] If there is only one read and write operation per register block in a cycle, then no block conflict is detected. If two or more instructions in a cycle read or write the same register block simultaneously in the fetch or write-back pipeline, then a block conflict is detected.

[0036] A computer-readable medium of the present invention stores a computer program thereon, which, when executed by a processor, implements the aforementioned multiple-issue instruction scheduling method.

[0037] A computer device according to one aspect of the present invention includes a storage module, a processor, and a computer program stored on the storage module and executable on the processor, wherein the processor implements the described multi-issue instruction scheduling method when executing the computer program.

[0038] A computer program product according to one aspect of the present invention includes a computer program that, when executed by a processor, implements the above-described multiple issue instruction scheduling method.

[0039] A processor according to one aspect of the present invention is characterized in that it includes the above-described multi-issue command scheduling device.

[0040] According to the present invention, by dividing the registers into blocks using a low-order address interleaving pattern, block conflicts can be efficiently avoided. Simultaneously, by introducing a hardware-software collaborative approach, the compiler performs instruction sorting and bubble insertion, eliminating data dependencies between instructions and significantly reducing the design complexity of the scheduling unit. The multi-issue instruction scheduling device and method of the present invention can issue up to three instructions per instruction cycle, thereby fully leveraging the parallel capabilities of downstream execution units' multiple pipelines and improving the throughput and utilization of the entire system. Attached Figure Description

[0041] The described and other objects and advantages of this application will become more fully clear from the following detailed description taken in conjunction with the accompanying drawings, wherein the same or similar elements are denoted by the same reference numerals.

[0042] Figure 1 This is a schematic diagram illustrating the structure of a multi-launch command scheduling device according to an embodiment of the present invention.

[0043] Figure 2 The example provided is a sequence of multithreaded beam instructions.

[0044] Figure 3 The example provided illustrates the read / write process for each module.

[0045] Figure 4 This is a flowchart illustrating a multi-issue command scheduling method according to an embodiment of the present invention. Detailed Implementation

[0046] The following are some embodiments of the present invention, intended to provide a basic understanding of the invention. They are not intended to identify key or decisive elements of the invention or to limit the scope of protection sought.

[0047] For purposes of brevity and illustrativeness, the principles of the invention are described herein primarily with reference to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equivalently applicable to all types of multi-issue command scheduling methods and apparatuses, and that these same principles can be implemented therein, and that any such variations do not depart from the true spirit and scope of this patent application.

[0048] Furthermore, reference is made in the following description to the accompanying drawings, which illustrate specific exemplary embodiments. Electrical, mechanical, logical, and structural modifications may be made to these embodiments without departing from the spirit and scope of the invention. Moreover, while features of the invention are disclosed in conjunction with only one of several embodiments, this feature may be combined with one or more other features of other embodiments if desired and / or advantageous for any given or identifiable function. Therefore, the following description should not be considered limiting in any sense, and the scope of the invention is defined by the appended claims and their equivalents.

[0049] Terms such as “possessing” and “comprising” indicate that, in addition to having units (modules) and steps that are directly and explicitly stated in the specification and claims, the technical solution of the present invention does not exclude the presence of other units (modules) and steps that are not directly or explicitly stated.

[0050] Before describing the multi-send command scheduling apparatus and method of the present invention, the relevant technical terms will be explained first.

[0051] (1) GPGPU architecture

[0052] The GPGPU (General-Purpose Graphics Processing Unit) architecture is an architecture that applies graphics processing units (GPUs) to the field of general computing. It utilizes the massive parallel processing capabilities of GPUs to transfer computational tasks that should have been executed on the central processing unit (CPU) to the GPU.

[0053] (2) SIMD backend execution unit

[0054] The SIMD (Single Instruction, Multiple Data) back-end execution unit is a component of the processor that is responsible for executing SIMD instructions to achieve parallel processing of multiple data items.

[0055] (3) Data Adventure

[0056] A data hazard is a situation in computer architecture where an instruction begins execution before the data it needs to read is ready (i.e., the result of the previous instruction has not been written to the destination register or memory). This situation leads to an execution error because the instruction uses incorrect data. Data hazards are generally classified into three types: Read-After-Write (WAR), Write-After-Read (RAW), and Write-After-Write (WAW).

[0057] (4) WAR (Read and write)

[0058] WAR (Warranty Instructions) refers to an instruction that attempts to read an operand, which is then written to by another instruction. Simply put, it means reading a value, and then that value is modified by another instruction.

[0059] (5) RAW (Write and Read)

[0060] WAR indicates that an instruction attempts to read a value that was previously written by another instruction. In other words, an instruction reads the result of a previous instruction's write operation.

[0061] (6) WAW (Write after writing)

[0062] WAW occurs when two instructions attempt to write to the same operand or register. This happens when multiple functional units are present. Although instructions are executed sequentially, some instructions (such as multiplication) have a longer execution order than others (such as addition), causing later instructions to complete and write data earlier than earlier instructions.

[0063] (7) Bubble Command

[0064] In the field of computer science, particularly in processor architecture and instruction execution flow, bubble instructions are instructions in which the processor does not produce any actual results or operations during the instruction cycle, but instead halts the subsequent operations of the pipeline. They are mainly used to create gaps or delays in the instruction flow to ensure that data dependencies and risky conditions are properly handled.

[0065] (8) Older-first strategy

[0066] The old-first strategy typically refers to prioritizing the scheduling of threads that have been waiting for a long time or have already executed part of their instructions, in order to ensure that they can complete as quickly as possible.

[0067] (9) Thread bundle (i.e., warp)

[0068] A warp is the basic unit for GPU task scheduling. A warp contains 32 threads, meaning that GPU scheduling is based on units of 32 threads.

[0069] (10) Source Operand

[0070] The source operand refers to the data being operated on, that is, the operand that provides the original data or value in the instruction.

[0071] (11) Destination Operand: The destination operand is where the result of instruction execution is stored. After the source operand is calculated or processed, the value is usually stored in the location specified by the destination operand.

[0072] (12) Block conflict is a conflict that occurs when multiple operands access the same memory or register block during vector or matrix operations.

[0073] The technical concept of the multi-transmission command scheduling device and multi-transmission command scheduling method of the present invention is as follows:

[0074] To address data hazards and block conflicts in operands during instruction multi-issue, this invention employs a hardware-software co-operational solution. Specifically, to resolve data hazards in instruction operands, the compiler first reorders instructions and inserts bubble instructions into the program flow to eliminate data hazards within thread bundles. Then, the register set itself is segmented according to thread bundles to eliminate data hazards between thread bundles.

[0075] To resolve operand conflicts, the compiler first ensures that operand conflicts within a single instruction are avoided. The register set is divided into blocks using a low-order address interleaving pattern. Thread bundles select instructions from multiple thread bundles and send them to the scheduling stage through a configured scheduling strategy. Block conflicts between these instructions are determined and eliminated. Finally, three non-conflicting instructions are selected and sent to the execution unit through three issue ports.

[0076] Next, a multi-launch command scheduling apparatus according to an embodiment of the present invention will be described.

[0077] Figure 1 This is a schematic diagram illustrating the structure of a multi-launch command scheduling device according to an embodiment of the present invention.

[0078] like Figure 1 As shown, a multi-launch command scheduling device 100 according to an embodiment of the present invention includes: a thread bundle scheduling module 110, a conflict detection module 120, and a command distribution module 130.

[0079] The multi-issue instruction scheduling device 100 of the present invention receives a thread bundle from the thread bundle fetch module 200 and performs multi-issue instruction scheduling on the thread bundle, and then sends the instruction to the back-end execution computing unit 300 through the transmit port 1 to the transmit port 3.

[0080] Specifically, firstly, the thread bundle scheduling module 110 receives thread bundles 0 to 5 of instruction sequence 0 to instruction sequence 5 from the thread bundle fetch module 200. The compiler reorders the instructions and inserts bubble instructions into the program flow (i.e., thread bundles 0 to 5 of instruction sequence 0 to instruction sequence 5). The thread bundle scheduling module 110 first executes the bubble instructions of the thread bundle itself, and then executes the bubble instructions inserted by the compiler. This ensures that there are no data hazards such as WAR (read-after-write), RAW (write-after-read), and WAW (write-after-write) between the operands used by the preceding and following instructions within a single thread bundle.

[0081] Next, the thread bundle scheduling module 110 uses a pre-defined scheduling strategy, such as the old priority strategy and the round-robin strategy, to extract multiple instructions that can participate in the scheduling from multiple thread bundles and send them to the conflict detection module 120.

[0082] Since the compiler has already avoided block conflicts for individual instructions, the main function of the conflict detection module 120 is to avoid block conflicts between multiple issued instructions. The inventors' research revealed that in the computer field, block conflicts between instructions are usually related to the processor's register set design and instruction scheduling strategy. When a processor attempts to execute multiple instructions in parallel, block conflicts may occur if these instructions attempt to access the same block (i.e., memory region) in the same register set simultaneously. Such block conflicts can lead to data inconsistency, calculation errors, or performance degradation because the processor needs to wait for one instruction to complete its read / write operation before executing another.

[0083] To avoid board conflicts between multiple instructions, based on the above research findings on board conflicts, the conflict detection module 120 is configured to perform the following actions:

[0084] First, the register sets accessed by the instruction are divided into vector register sets and scalar register sets based on the operand types. Each register set is further divided into N blocks (N is a natural number) based on the low-order bits of the address interleaving mapping. For example, in Figure 1 The example shows register blocks 0 through 5, each of which uses a dual-port memory and can support one read and one write operation per clock cycle.

[0085] Next, operand parsing is performed on the multiple instructions involved in scheduling, and conflict determination is performed on the source operand 0, source operand 1, source operand 2 and destination operand. Furthermore, the vector register group and scalar register group are determined separately.

[0086] Here, the specific determination method is as follows: Since each block uses a dual-port memory, only one read and write operation is allowed per cycle. If two instructions read or write to the same block at the same time in the fetch / write pipeline, it is determined to be a conflict. The conflicting instruction is marked (for example, marked as ready). This instruction will not be scheduled and issued in the current instruction cycle. Instead, other non-conflicting instructions from other threads will be scheduled. The instruction marked as ready can continue to participate in scheduling in subsequent instruction cycles.

[0087] In this way, for instructions with multiple thread bundles, the conflict detection module 120 can select three instructions that do not conflict with each other and send them to the back-end execution calculation unit 300 for operand reading and writing back, which can make full use of the read and write bandwidth of the register group.

[0088] In addition, for Figure 1 The backend execution computing unit 300 in the process will be briefly explained.

[0089] The back-end execution computing unit 300 parses the received instructions, retrieves the source operands, and then sends them to three pipelines for writing back. The first pipeline is a vector-floating-point pipeline (specifically for instructions with floating-point data type), the second pipeline is a vector-mixed pipeline (specifically for instructions with mixed floating-point and fixed-point data type), and the third pipeline is a scalar pipeline (specifically for instructions with scalar data type).

[0090] on the other hand, Figure 1 The operation "Source operand address / read enable" means sending the address to be read and the control signal for reading the data to the register block. "Original operand data return" means that the register bank selects the corresponding register data based on the address and control signal and returns it to the execution unit. "Destination operand write back, destination operand address / write enable" means that after the execution unit completes an instruction and obtains the final data as the write-back result, it needs to send the register address, write-back control signal and write-back data together to the register block to realize the data write-back to the register block.

[0091] Figure 2 The example provided is a sequence of multithreaded beam instructions. Figure 2 In the instruction set, ADD represents addition, SUB represents subtraction, and SSADD represents scalar signed addition (where the first S represents scalar, the second S represents signed, and ADD represents addition). V1 to V7 represent vector registers 1 to 7, with the numbers indicating their positions and V representing vectors. S0 to S1 represent scalar registers, with the numbers indicating their positions and S representing scalars.

[0092] exist Figure 2 In the example of inst1 (i.e. instruction 1), ADD V1, V1, V4 represent that this instruction is an ADD addition operation, which is a 2-operand instruction. The first V1 represents vector register 1 as the destination register, the second V1 represents vector register 1 as the source operand 0, and the third V4 represents vector register 4 as the source operand 1. The overall meaning is V1 = V1 + V4.

[0093] For the `inst1` of three warps, determining if these three instructions conflict involves checking whether their destination register, source operand 0, and source operand 1 are on the same block. For example... Figure 2In this code, V1 and V6 are not in the same section as S2, V1 and V3 are not in the same section as S0, and V4 and V2 are not in the same section as S1. Therefore, these three instructions do not conflict with each other. (Note: V0 / V4 / V8 are in one section, V1 / V5 / V9 are in one section, V2 / V6 / V10 are in one section, V3 / V7 / V11 are in one section, S0 / S4 / S8 are in one section, S1 / S5 / S9 are in one section, S2 / S6 / S10 are in one section, and S3 / S7 / S11 are in one section.)

[0094] To obtain the source operand, a block needs to be read; to obtain the destination register, a block needs to be written back. As long as there are no two access requests or two write-back requests operating on the same block in the same clock cycle, block conflicts are avoided.

[0095] Figure 3 The example illustrates the read / write process for each register block.

[0096] Figure 3 The left side represents the read / write flow of the Cycle (instruction cycle) of the vector register Banks 0-3. Figure 3 The right side represents the read / write flow of the Cycle (instruction cycle) of scalar register Banks 0-3. Here, W stands for warp, V for vector register, and S for scalar register.

[0097] Cycle0 first reads the source operand 0 from the inst-1 instructions of the three thread bundles, i.e., W1:V1, W2:V3, W5:S0. Cycle1 reads the source operand 1 from the inst-1 instructions of the three thread bundles, i.e., W1:V4, W2:V2, W5:S1. Cycle2 writes back the destination registers from the inst-1 instructions of the three thread bundles, i.e., W1:V1, W2:V6, W3:S2. (Note: W2 will issue inst-2 two clock cycles after inst-1. Therefore, Cycle2 will simultaneously perform the operation of reading the source operand 0 from inst-2.)

[0098] In the second cycle of vector register block 1, V1 of W1 is the destination register, which is a write-back operation to the register block. V5 of W2 is the source operand 0 of the second instruction, inst-2, which is a read operation accessing the register block. As explained above, the register block is a dual-port block, allowing one read operation and one write operation in the same clock cycle. Therefore, although vector register block 1 has two operations in the second cycle, they are a read and a write-back, respectively, and thus do not conflict. However, if two read operations or two write operations occur in the same cycle, a block conflict occurs. Thus, according to the multi-launch command scheduling device of the present invention, the commands that have finally eliminated plate conflicts are sent to the command distribution module 130. The command distribution module 130 sends the commands to the back-end execution computing unit 300 through launch ports 1 to 3 respectively. Since there are three pipelines in the back-end execution computing unit 300 (namely, vector-floating-point pipeline, vector-hybrid pipeline, and scalar-computation pipeline), the task of the command distribution module 130 is to select the corresponding launch port for launch from the multiple commands that have eliminated data hazards and plate conflicts from the upstream, according to the execution type of the command, so as to realize the parallel execution of multiple pipelines.

[0099] The multi-issue command scheduling apparatus of the present invention has been described above. Next, the multi-issue command scheduling method will be described.

[0100] Figure 4 This is a flowchart illustrating a multi-issue command scheduling method according to an embodiment of the present invention.

[0101] A multi-issue command scheduling method according to an embodiment of the present invention includes:

[0102] Thread bundle scheduling step S100: Receive multiple thread bundles and execute thread bundle execution bubble instructions for the multiple thread bundles to eliminate block conflicts of individual instructions and extract multiple instructions from the multiple thread bundles using a pre-set scheduling strategy.

[0103] Conflict detection step S200: Detect block conflicts between the multiple instructions and select M instructions from the multiple instructions that do not have block conflicts, where M is a natural number; and

[0104] Instruction distribution step S300: Distribute the M instructions selected in the conflict detection step.

[0105] Where M = 3.

[0106] The thread beam scheduling step S100 includes:

[0107] For the plurality of thread bundles, execute the bubble instruction of the thread bundle itself; and

[0108] Execute bubble instructions inserted by the compiler.

[0109] The collision detection step S200 includes:

[0110] For register groups accessed by instructions, register blocks are divided using a low-order address interleaving pattern;

[0111] Detecting plate conflicts between register plates for the multiple instructions; and

[0112] Choose 3 non-conflicting instructions.

[0113] The register module includes a vector register group and a scalar register.

[0114] The detection of block conflicts between register blocks for the multiple instructions includes:

[0115] Each register block uses dual-port memory and only one read and write operation is allowed per cycle. If two instructions read or write to the same register block simultaneously in the fetch or write-back pipeline, it is detected that the two instructions conflict.

[0116] The instruction distribution step S300 includes: receiving multiple instructions that exclude data hazards and plate conflicts, and selecting the corresponding transmission port from these multiple instructions according to the execution type of the instructions for transmission.

[0117] In summary, the multi-issue instruction scheduling device and method of the present invention can effectively solve the data hazards and block conflicts encountered in the process of multi-instruction parallel issuance, increase the issuance efficiency of instructions, improve the bandwidth of the overall stream processor, and have the advantages of simple implementation, low hardware overhead, and high resource utilization.

[0118] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art can conceive of other feasible variations or substitutions based on the technical scope disclosed in this application, and such variations or substitutions are all covered within the scope of protection of this application. Where there is no conflict, the embodiments and features described in the embodiments of this application can also be combined with each other. The scope of protection of this application is determined by the claims.

Claims

1. A multiple issue instruction scheduling apparatus, characterized by, comprising: a thread bundle scheduling module, configured to receive a plurality of thread bundles, execute bubble instructions on the plurality of thread bundles to eliminate the bank conflict of a single instruction, and extract a plurality of instructions from the plurality of thread bundles according to a preset scheduling strategy; a conflict detection module, configured to detect the bank conflict among the plurality of instructions and select M instructions without bank conflict from the plurality of instructions, where M is a natural number; and an instruction distribution module, configured to distribute the M instructions selected by the conflict detection module.

2. The multi-issue instruction scheduling apparatus of claim 1, wherein the M = 3.

3. The multi-issue instruction scheduling apparatus of claim 1, wherein in the thread bundle scheduling module, the execution of the bubble instructions on the plurality of thread bundles to eliminate the bank conflict of a single instruction comprises: the execution of the bubble instructions of the thread bundle itself on the plurality of thread bundles; and the execution of the bubble instructions inserted by a compiler.

4. The multi-issue instruction scheduling apparatus of claim 1, wherein the conflict detection module divides the register bank accessed by the instructions into register banks in an address low bit interleaving mode, detects whether there is a bank conflict among the plurality of instructions in the register banks, and selects 3 instructions without bank conflict.

5. The multi-issue instruction scheduling apparatus of claim 3, wherein the register banks are divided into vector register banks and scalar register banks.

6. The multi-issue instruction scheduling apparatus of claim 4, wherein the detection of whether there is a bank conflict among the plurality of instructions in the register banks comprises: each register bank uses a dual-port memory; for each register bank, there is only one read and write operation in one cycle, and if there are more than two instructions reading or writing the same register bank in the instruction fetch or write back pipeline in one cycle, it is detected that there is a bank conflict.

7. The multi-issue instruction scheduling apparatus of claim 1, wherein the preset scheduling strategy comprises an age-first strategy and a round-robin strategy. comprising: a thread bundle scheduling step, configured to receive a plurality of thread bundles, execute bubble instructions on the plurality of thread bundles to eliminate the bank conflict of a single instruction, and extract a plurality of instructions from the plurality of thread bundles according to a preset scheduling strategy; a conflict detection step, configured to detect the bank conflict among the plurality of instructions and select M instructions without bank conflict from the plurality of instructions, where M is a natural number; and an instruction distribution step, configured to distribute the M instructions selected by the conflict detection step. The computer program is executed by a processor to implement the multi-issue instruction scheduling method of claim 8.

8. A method of scheduling multiple transmit instructions, the method comprising:

10. A computer device, comprising a storage module, a processor, and a computer program stored in the storage module and executable on the processor, wherein the processor executes the computer program to implement the multi-issue instruction scheduling method of claim 8. ​ ​ ​ ​ 9. A computer readable medium having stored thereon a computer program, characterized in that, ​ ​ ​

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