Multi-heterogeneous main body system optimization method and system oriented to real-time processing scene

Abstract

The invention discloses a multi-heterogeneous main body system optimization method and system oriented to a real-time processing scene, and the method comprises the steps: a CPU employs a bare core BMP mode for parallel division of labor, the CPU comprises a plurality of large cores and a plurality of small cores, a control task and a protection task are operated on the large cores, a master station command is received, and a background task is operated on the small cores; the FPGA writes back and reads data between a DDR (Double Data Rate) memory of the CPU and an internal cache of the FPGA according to a set time slot or period, and data preprocessing carried out in the data writing back and reading process is migrated from the CPU to an FPGA layer to be executed; three-buffer independent access and atomic state switching are combined, and data interaction among multiple cores is carried out; the compiler automatically inserts a prefetch instruction in a loop expansion and pipeline scheduling stage; and the compiler performs linear address arrangement on the data members in a physical address space. The instruction execution efficiency and the data access efficiency are improved.

Description

Technical Field

[0001] This invention belongs to the field of multi-heterogeneous entity system optimization technology, and more specifically, relates to a method and system for optimizing multi-heterogeneous entity systems for real-time processing scenarios. Background Technology

[0002] With the continuous expansion of new energy power generation and the increasing demand for cross-regional energy interconnection, new power systems are rapidly developing towards high-proportion renewable energy integration and high power electronics. Large-scale DC transmission technology, as a core means of achieving efficient energy allocation, plays a crucial role in this process. Against this backdrop, DC protection and control equipment, serving as the "first line of defense" for the safe and stable operation of DC transmission systems, faces increasingly stringent performance challenges, specifically in terms of significantly higher requirements for real-time performance, parallel computing capabilities, data consistency, and development efficiency. On the one hand, DC system faults develop rapidly and transient processes are complex, requiring protection algorithms to complete fault identification and decision-making within a 10μs timescale. On the other hand, diverse protection strategies and the need for real-time processing of multi-source data place higher demands on equipment computing resource scheduling, data sharing mechanisms, and development adaptability.

[0003] However, current DC protection and control equipment solutions based on processors and RTOS have significant shortcomings in terms of parallel computing capabilities, data sharing efficiency, FPGA-CPU processor collaborative performance, and development efficiency. They can no longer meet the requirements of high performance, high reliability, and high flexibility for equipment in the development of new power systems and large-scale DC transmission. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method and system for optimizing multi-heterogeneous systems for real-time processing scenarios.

[0005] The present invention adopts the following technical solution.

[0006] The first aspect of this invention proposes an optimization method for a multi-heterogeneous agent system for real-time processing scenarios, wherein the multi-heterogeneous agent system consists of an FPGA and a CPU, specifically: The CPU employs a bare-core BMP mode for parallel division of labor. The CPU includes multiple large cores and multiple small cores. Control tasks, protection tasks, and receiving commands from the master station are run on the large cores, while background tasks are run on the small cores. An FPGA active data synchronization mechanism is constructed to facilitate data interaction between the FPGA and the CPU. According to the FPGA active data synchronization mechanism, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. The data preprocessing performed during the data write-back and read-back process is migrated from the CPU to the FPGA layer for execution. Combine triple-buffered independent access with atomic state switching to enable data interaction between multiple cores; The compilation process is optimized by automatically inserting prefetch instructions during loop unrolling and pipelining stages; and the compiler arranges data members in a linear address space.

[0007] Preferably, the operation control task, protection task, and receiving master station commands on the large core specifically include: The first major core deploys the interruption of the first interruption cycle, and runs the first real-time level control tasks and / or protection tasks on the first major core. The first real-time level control tasks and / or protection tasks run during the interruption of the first interruption cycle. The first real-time level control tasks include inner loop control and outer loop control in the power system. The first real-time level protection tasks are instantaneous protection without delay. The instantaneous protection without delay includes DC overvoltage protection and DC undervoltage overcurrent protection. The second core deploys interrupts for the second interrupt cycle and the third interrupt cycle; it runs control tasks and / or protection tasks of the second real-time level on the second core. The control tasks and / or protection tasks of the second real-time level run during the interrupt of the second interrupt cycle. The control tasks of the second real-time level include soft three-out-of-two criteria and sequential control. The protection tasks of the second real-time level include DC line differential protection, starting circuit thermal overload protection and neutral point resistor thermal overload protection. Furthermore, the system receives commands from the master station on the second core and runs protection tasks of the third real-time level on the second core. The system receives commands from the master station and runs protection tasks of the third real-time level during the interruption of the third interrupt cycle. The third real-time level protection includes AC overvoltage protection, AC overcurrent protection and AC frequency protection. The first interruption period is equal to the control period of the protection device in the power system, and the first interruption period is shorter than the second interruption period, while the second interruption period is shorter than the third interruption period.

[0008] Preferably, the step of performing waveform data processing and interacting with I / O peripherals on the small core specifically includes: The first small core is deployed during the second interrupt cycle interrupt and main loop. The first small core performs waveform data processing and transmission, responds to and executes I / O operations corresponding to control tasks and / or protection tasks in the second large core, and runs during the second interrupt cycle interrupt. The I / O operations include I / O peripherals and network data corresponding to input / output. Furthermore, the first small core performs message and SOE transmission and collects and monitors the device's operating status, running in the main loop; the device's operating status includes temperature and voltage; The second small core deploys the interrupt and main loop of the second interrupt cycle. The second small core acts as a monitoring core, monitoring the running status of the two large cores and the first small core.

[0009] Preferably, in the bare-core BMP mode, when the background task does not use floating-point registers, the interrupt handler only saves the general-purpose registers X0 to X30 and the CPACR_EL1, ELR_EL1 and SPSR_EL1 registers during the context switch, and does not save the floating-point registers; the floating-point registers are also not restored when returning from the interrupt.

[0010] Preferably, when the FPGA receives data, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. Specifically, the FPGA periodically collects power system signals and receives data from other devices at a first fixed period and preprocesses the power system signals. The preprocessing includes zero drift calibration according to the zero drift coefficient issued by the CPU and mapping from physical channels to logical channels according to the mapping relationship between physical channels and logical channels issued by the CPU. The FPGA initiates a direct memory access (DMA) operation via the PCIe bus. At the first predetermined moment within each first fixed cycle, the data acquired and preprocessed in the previous first fixed cycle and the data received from other devices are written into the first and second main caches in the DDR memory, respectively. The first and second main caches adopt a circular queue structure. Within each first fixed cycle, the CPU polls, reads, and uses the data in the first and second main caches.

[0011] Preferably, when the CPU sends data, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period, specifically: At the second predetermined moment of each second fixed cycle, the CPU writes the control data to be sent into a preset third buffer in DDR memory. This third buffer is an alternating buffer, employing A / B alternating buffering. At the third predetermined moment of each second fixed cycle, the FPGA initiates a direct memory access (DMA) operation via the PCIe bus, reads data from the third set of buffers preset in the DDR memory, and sends the read data to external devices, including power system signals and other devices. Both the first fixed period and the second fixed period are equal to the control period of the protection device in the power system. The first predetermined time, the second predetermined time and the third predetermined time are set sequentially and staggered within the corresponding fixed period.

[0012] Preferably, both the first and second main caches have reserved locations. The FPGA does not write data to the reserved locations. When the CPU polls and reads and uses data in the first and second main caches, the first and second large cores read the data in the first and second main caches and then perform calculations. The intermediate data generated during the calculations is written to the reserved location of the main cache corresponding to the data read. When the first small core reads data from the first group of main cache and the second group of main cache, it reads directly without copying the data; The data structures of the first main cache, the second main cache, and the third buffer are all byte-aligned according to the capacity of the CPU cache line.

[0013] Preferably, the combination of independent access to the triple buffer and atomic state switching for data interaction between multiple cores specifically includes: Three shared buffers are constructed for intra-core communication. The core that writes data to the corresponding buffer is the producer core, and the core that reads data from the corresponding buffer is the consumer core. The buffer where data is written by the producer core is the producer buffer, the buffer where data is currently being read by the consumer core is the consumer buffer, and the currently unread / unwritten idle buffer is the spare buffer. Construct a global state pointer, which is an atomic variable containing three index fields and a version number. Each index field indicates the buffer number currently used as a production buffer, consumption buffer, and standby buffer, respectively, and the version number indicates the number of times the global state pointer has been updated. When the producer core writes data to the current production buffer, after writing a frame of cross-sectional data, it inserts a write memory barrier instruction, updates the global state pointer through atomic comparison and exchange, switches the spare buffer to the new production buffer, switches the producer buffer to the new spare buffer, and inserts a full memory barrier instruction. When reading data, the consumer core reads the global state pointer atomically, inserts a read memory barrier instruction, and checks whether there is new data in the spare buffer identified in the global state pointer by incrementing the version number of the global state pointer. If there is new data, it updates the global state pointer by atomic comparison and swap, switches the spare buffer to the new consumer buffer, switches the consumer buffer to the new spare buffer, and reads the data in the currently bound consumer buffer.

[0014] Preferably, the optimization of the compilation process involves the compiler automatically inserting prefetch instructions during the loop unrolling and pipelining stages; and the compiler linearly arranging data members in the physical address space, specifically: The compiler arranges all data members in the program that have been accessed consecutively more than a set threshold, and all data members that have been repeatedly accessed more than a set threshold in loops or hot paths, adjacent to each other in the physical address space; and obtains all data members that have data flow or control dependencies, and arranges these data members adjacent to each other in the physical address space; the data members are fields inside structures or objects; The compiler automatically inserts prefetch instructions during the loop unrolling and pipelining stages. If it detects that the access address in the loop iteration shows a linear growth and the step size of the loop iteration is a fixed value, it is assumed that the elements of the array or structure array are accessed sequentially. In this case, the compiler prefetches the subsequent elements of the array or structure array through prefetch instructions. The operation values ​​of the corresponding array or structure array are converted into NEON vector instructions. The operation values ​​are operation instructions for arithmetic operations, data movement, or conditional judgments on each element of the array or structure array. Batch parallel processing is performed on the subsequent consecutive elements in the array or structure array through a single NEON vector instruction.

[0015] The second aspect of this invention proposes an optimization system for multi-heterogeneous systems in real-time processing scenarios based on the optimization method described in the first aspect of this invention, comprising: a parallel optimization module, an FPGA-CPU data interaction optimization module, an inter-core data interaction optimization module, and a compiler optimization module, specifically: Parallel optimization module: used for CPU parallel division of labor using bare core BMP mode. The CPU includes multiple large cores and multiple small cores. Control tasks, protection tasks and receiving master station commands are run on the large cores, while background tasks are run on the small cores. FPGA and CPU data interaction optimization module: used to build an FPGA active data synchronization mechanism for data interaction between FPGA and CPU. According to the FPGA active data synchronization mechanism, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. The data preprocessing performed during the data write-back and read-back process is migrated from the CPU to the FPGA layer for execution. Inter-core data interaction optimization module: used to combine triple-buffered independent access with atomic state switching to enable data interaction between multiple cores; The compiler optimization module is used to optimize the compilation process. The compiler automatically inserts prefetch instructions during loop unrolling and pipelining stages, and arranges data members in a linear address space.

[0016] The beneficial effects of this invention are as follows: Compared with existing technologies, different CPU cores handle different power system tasks. Large cores focus on control and / or protection tasks, while small cores isolate waveform recording tasks, avoiding task interference and ensuring the response speed and reliability of critical real-time tasks. Furthermore, small cores independently handle waveform data transfer and network transmission, improving the overall system throughput and efficiency. An FPGA-based active data synchronization mechanism is constructed to avoid frequent outbound reads by the CPU. Combining independent access via triple buffers with atomic state switching enables data interaction between multiple cores, avoiding lock contention between cores, improving the concurrency and determinism of data interaction, reducing waiting time, and ensuring high efficiency in multi-core collaborative work. The compilation process is optimized by improving the instruction cache hit rate and real-time task response speed through instruction prefetching. Data members are linearly arranged in the physical address space, and the reserved memory for each core is reallocated in real time, reducing redundant memory operations. The optimized compilation process improves instruction execution efficiency and data access efficiency. Attached Figure Description

[0017] Figure 1 This is a flowchart of the present invention; Figure 2 This is a schematic diagram of the structure of the multi-heterogeneous host system of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0019] like Figure 1 As shown, Embodiment 1 of the present invention proposes an optimization method for a multi-heterogeneous entity system for real-time processing scenarios. The multi-heterogeneous entity system consists of an FPGA and a CPU, specifically as follows: The CPU employs a bare-core BMP (Browser-Macro) parallel division of labor. The CPU includes multiple large cores and multiple small cores. The large cores run tasks such as receiving master station commands, protection tasks, and control tasks, while the small cores run background tasks. It should be noted that the composition of a multi-heterogeneous main body system is as follows: Figure 2 As shown, this embodiment uses a domestically produced multi-core processor and a domestically produced FPGA as the hardware foundation. The domestically produced multi-core processor is the Phytium E2000Q processor, which integrates two large cores (FTC664) and two small cores (FTC310), with a maximum clock speed of 1.8GHz; the FPGA chip is a 400K high-capacity domestically produced FPGA.

[0020] An FPGA active data synchronization mechanism is constructed to facilitate data interaction between the FPGA and the CPU. According to the FPGA active data synchronization mechanism, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. The data preprocessing performed during the data write-back and read-back process is migrated from the CPU to the FPGA layer for execution. Combine triple-buffered independent access with atomic state switching to enable data interaction between multiple cores; The compilation process of the CPU is optimized by automatically inserting prefetch instructions during the loop unrolling and pipelining stages; the compiler also arranges data members linearly in the physical address space and reallocates the reserved memory of each core in real time.

[0021] In this preferred embodiment, the operation control task, protection task, and receiving master station commands on the large core specifically include: The first major core deploys the interruption of the first interruption cycle, and runs the first real-time level control tasks and / or protection tasks on the first major core. The first real-time level control tasks and / or protection tasks run during the interruption of the first interruption cycle. The first real-time level control tasks include inner loop control and outer loop control in the power system. The first real-time level protection tasks are instantaneous protection without delay. The instantaneous protection without delay includes DC overvoltage protection and DC undervoltage overcurrent protection. The second core deploys interrupts during the second and third interrupt cycles; the first core runs control and / or protection tasks of the second real-time level, which are executed during the interrupts of the second interrupt cycle. The control tasks of the second real-time level include soft three-out-of-two criteria and sequential control, and the protection tasks of the second real-time level include DC line differential protection, start-up circuit thermal overload protection and neutral point resistor thermal overload protection. Furthermore, the system receives commands from the master station on the second core and runs protection tasks of the third real-time level on the second core. The system receives commands from the master station and runs protection tasks of the third real-time level during the interruption of the third interruption cycle. The third real-time level protection includes AC overvoltage protection, AC overcurrent protection and AC frequency protection. The first interruption cycle is equal to the control cycle of the control and protection device in the power system, and the first interruption cycle is less than the second interruption cycle, and the second interruption cycle is less than the third interruption cycle. Specifically, the control cycle of the protection device in the power system is 10μs, the first interrupt cycle is set to 10μs, the second interrupt cycle is 100μs, and the third interrupt cycle is 1ms.

[0022] In this preferred embodiment, the step of performing waveform data processing and interacting with I / O peripherals on the small core specifically involves: The first small core is deployed during the second interrupt cycle interrupt and main loop. The first small core performs waveform data processing and transmission, responds to and executes I / O operations corresponding to control tasks and / or protection tasks in the second large core, and runs during the second interrupt cycle interrupt. The I / O operations include I / O peripherals and network data corresponding to input / output. Furthermore, the first small core performs message and SOE transmission and collects and monitors the device's operating status, running in the main loop; the device's operating status includes temperature and voltage; The second small core deploys the interrupt and main loop of the second interrupt cycle. The second small core acts as a monitoring core, monitoring the running status of the two large cores and the first small core, and issuing alarm information when an abnormality is detected in the running core. In this embodiment, preferably, in the bare-core BMP mode, when the background task does not use floating-point registers, the interrupt handler only saves the general-purpose registers X0 to X30 and the CPACR_EL1, ELR_EL1 and SPSR_EL1 registers during the context switch, and does not save the floating-point registers; the floating-point registers are also not restored when returning from the interrupt, thereby minimizing the time for register saving and restoring during the context switch and improving interrupt response speed and execution efficiency.

[0023] In this preferred embodiment, when the FPGA receives data, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. Specifically, the FPGA periodically collects power system signals and receives data from other devices at a first fixed period and preprocesses the power system signals. The preprocessing includes zero drift calibration according to the zero drift scale coefficient issued by the CPU and mapping from physical channels to logical channels according to the mapping relationship between physical channels and logical channels issued by the CPU. The FPGA initiates a direct memory access (DMA) operation via the PCIe bus. At the first predetermined moment within each first fixed cycle, the data acquired and preprocessed in the previous first fixed cycle and the data received from other devices are written into the first and second main caches in the DDR memory, respectively. The first and second main caches adopt a circular queue structure. Within each first fixed cycle, the CPU polls, reads, and uses the data in the first and second main caches.

[0024] When the CPU sends data, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. Specifically: The CPU writes the control data to be sent into the third set of buffers preset in the DDR memory at the second predetermined time of each second fixed cycle. The third set of buffers is an alternating buffer, which adopts A / B alternating buffering. It should be noted that the A / B alternating buffer is as follows: in a second fixed cycle, at the second reserved predetermined time, the CPU writes data to buffer A in the third group of buffers, and the FPGA reads data from buffer A in the third group of buffers at the third predetermined time. In the next second fixed cycle, at the second preset time, the CPU writes data to buffer B in the third group of buffers, and the FPGA reads data from buffer B in the third group of buffers at the third predetermined time. The buffers are swapped every second fixed cycle.

[0025] At the third predetermined moment of each second fixed cycle, the FPGA initiates a direct memory access (DMA) operation via the PCIe bus, reads data from a preset third buffer in the DDR memory, and sends the read data to external devices, including power system signals and other devices.

[0026] Both the first fixed period and the second fixed period are equal to the control period of the protection device in the power system. The first predetermined time, the second predetermined time and the third predetermined time are set sequentially and staggered within the corresponding fixed period.

[0027] It should be noted that the FPGA directly writes data to the corresponding buffer through DMA that supports the ACE protocol. The ACE protocol automatically maintains the data consistency between the CPU cache and DDR memory at the hardware level.

[0028] In this preferred embodiment, both the first group of main caches and the second group of main caches have reserved locations. The FPGA does not write data to the reserved locations. When the CPU polls and reads and uses the data in the first group of main caches and the second group of main caches, the first core and the second core read the data in the first group of main caches and the second group of main caches and then perform calculations. The intermediate data generated during the calculations is written to the reserved location of the main cache corresponding to the data it reads. When the first small core reads data from the first group of main cache and the second group of main cache, it reads directly without copying the data; The data structures of the first main cache, the second main cache, and the third buffer are all byte-aligned according to the capacity of the CPU cache line.

[0029] In this preferred embodiment, the combination of triple-buffered independent access and atomic state switching for data interaction between multiple cores specifically includes: Three shared buffers are constructed for intra-core communication. The core that writes data to the corresponding buffer is the producer core, and the core that reads data from the corresponding buffer is the consumer core. The buffer where data is written by the producer core is the producer buffer, the buffer where data is currently being read by the consumer core is the consumer buffer, and the currently unread / unwritten idle buffer is the spare buffer. Construct a global state pointer, which is an atomic variable containing three index fields and a version number. Each index field indicates the buffer number currently used as a production buffer, consumption buffer, and standby buffer, respectively, and the version number indicates the number of times the global state pointer has been updated. When the producer core writes data to the current production buffer, after writing a frame of cross-sectional data, it inserts a write memory barrier instruction, updates the global state pointer through atomic comparison and exchange, switches the spare buffer to the new production buffer, switches the producer buffer to the new spare buffer, and inserts a full memory barrier instruction. When reading data, the consumer core reads the global state pointer atomically, inserts a read memory barrier instruction, and checks whether there is new data in the spare buffer identified in the global state pointer by incrementing the version number of the global state pointer. If there is new data, it updates the global state pointer by atomic comparison and swap, switches the spare buffer to the new consumer buffer, switches the consumer buffer to the new spare buffer, and reads the data in the currently bound consumer buffer.

[0030] It should be noted that the starting addresses of the production buffer, backup buffer, and consumption buffer all satisfy cacheline alignment.

[0031] In this preferred embodiment, the compiler arranges all data members that have been accessed consecutively more than a set threshold number of times within the program, as well as all data members that have been repeatedly accessed more than a set threshold number of times in loops or hot paths, adjacent to each other in the physical address space; and obtains all data members that have data flow or control dependencies, and arranges these data members adjacent to each other in the physical address space; the data members are fields inside structures or objects; The compiler automatically inserts prefetch instructions during the loop unrolling and pipelining stages. If it detects that the access address in the loop iteration shows a linear growth and the step size of the loop iteration is a fixed value, it is assumed that the elements of the array or structure array are accessed sequentially. In this case, the compiler prefetches the subsequent elements of the array or structure array through prefetch instructions. The operation values ​​of the corresponding array or structure array are converted into NEON vector instructions. The operation values ​​are operation instructions for arithmetic operations, data movement, or conditional judgments on each element of the array or structure array. Batch parallel processing is performed on the subsequent consecutive elements in the array or structure array through a single NEON vector instruction.

[0032] Embodiment 2 of the present invention proposes an optimization system for multi-heterogeneous systems in real-time processing scenarios based on the optimization method described in Embodiment 1 of the present invention, including: a parallel optimization module, an FPGA-CPU data interaction optimization module, an inter-core data interaction optimization module, and a compiler optimization module, specifically: Parallel optimization module: used for CPU parallel division of labor using bare core BMP mode. The CPU includes multiple large cores and multiple small cores. Control tasks, protection tasks and receiving master station commands are run on the large cores, while background tasks are run on the small cores. FPGA and CPU data interaction optimization module: used to build an FPGA active data synchronization mechanism for data interaction between FPGA and CPU. According to the FPGA active data synchronization mechanism, the FPGA performs data write-back and read-back between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period. The data preprocessing performed during the data write-back and read-back process is migrated from the CPU to the FPGA layer for execution. Inter-core data interaction optimization module: used to combine triple-buffered independent access with atomic state switching to enable data interaction between multiple cores; The compiler optimization module is used to optimize the compilation process. The compiler automatically inserts prefetch instructions during loop unrolling and pipelining stages, and arranges data members in a linear address space.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A multi-heterogeneous agent system optimization method for real-time processing scenarios, the multi-heterogeneous agent system being composed of an FPGA and a CPU, characterized in that: the CPU includes parallel division of labor in a bare core BMP mode, and the CPU includes a plurality of large cores and a plurality of small cores, control tasks, protection tasks and receiving master station commands are run on the large cores, and background tasks are run on the small cores; an FPGA active data synchronization mechanism is constructed for data interaction between the FPGA and the CPU, according to the FPGA active data synchronization mechanism, the FPGA performs data write-back and reading between the CPU's DDR memory and the FPGA's internal cache according to a set time slot or period, and the preprocessing of data performed in the data write-back and reading process is migrated from the CPU to the FPGA layer for execution; three-buffer independent access is combined with atomic state switching for data interaction between the plurality of cores; the compilation process is optimized, the compiler automatically inserts a prefetch instruction in the loop expansion and pipeline scheduling stage, and the compiler linearly arranges data members in the physical address space. 2.The multi-heterogeneous agent system optimization method for real-time processing scenarios according to claim 1, characterized in that: the control tasks, protection tasks and receiving master station commands run on the large cores are specifically: a first large core is deployed with an interrupt of a first interrupt period, a control task and / or a protection task of a first real-time level are run on the first large core, the control task and / or the protection task of the first real-time level are run in the interrupt of the first interrupt period, the control task of the first real-time level includes inner loop control and outer loop control in a power system, and the protection task of the first real-time level is a non-delayed quick-acting protection, the non-delayed quick-acting protection includes direct current overvoltage protection and direct current low-voltage overcurrent protection; a second large core is deployed with an interrupt of a second interrupt period and an interrupt of a third interrupt period, a control task and / or a protection task of a second real-time level are run on the second large core, the control task and / or the protection task of the second real-time level are run in the interrupt of the second interrupt period, the control task of the second real-time level includes soft two-out-of-three criterion and sequential control, and the protection task of the second real-time level includes direct current line differential protection, starting circuit thermal overload protection and neutral point resistance thermal overload protection; and a third real-time level protection task is run on the second large core, the third real-time level protection task is run in the interrupt of the third interrupt period, the third real-time level protection includes alternating current overvoltage protection, alternating current overcurrent protection and alternating current frequency protection; the first interrupt period is equal to a control period of a control and protection device in the power system, and the first interrupt period is less than the second interrupt period, and the second interrupt period is less than the third interrupt period. 3.The multi-heterogeneous agent system optimization method for real-time processing scenarios according to claim 2, characterized in that: the recording wave data operation and I / O peripheral interaction run on the small cores are specifically: The first small core is arranged with the interrupt of the second interrupt period and the main loop, and the first small core is arranged to process and transmit the recording data, respond and execute the I / O operation corresponding to the control task and / or protection task of the second large core, run in the interrupt of the second interrupt period, and the I / O operation includes the I / O operation corresponding to the I / O peripheral and network data of the input and output; The first small core is arranged to send the message and SOE and collect and monitor the device running state, and run in the main loop; the device running state includes temperature and voltage; The second small core is arranged with the interrupt of the second interrupt period and the main loop, and the second small core is arranged as a monitoring core to monitor the running state of the two large cores and the first small core.

4. The multi-heterogeneous subject system optimization method for a real-time processing scene according to claim 1, characterized in that: In the bare core BMP mode, when the background task does not use the floating point register, the interrupt processing program only saves the general registers X0-X30 and the CPACR_EL1, ELR_EL1 and SPSR_EL1 registers in the context switching process, and does not save the floating point register; and the floating point register is also not restored when the interrupt is returned.

5. The multi-heterogeneous subject system optimization method for a real-time processing scene according to claim 3, characterized in that: When the FPGA receives data, the FPGA performs data write back and read between the DDR memory of the CPU and the internal cache of the FPGA according to the set time slot or period, and specifically: The FPGA collects power system signals and receives data from other devices at a first fixed period, and pre-processes the power system signals, the pre-processing including zero drift calibration according to the zero drift scale coefficient issued by the CPU and mapping of physical channels to logical channels according to the mapping relationship between the physical channels and the logical channels issued by the CPU; The FPGA starts a direct memory access (DMA) operation through a PCIe bus, and at a first predetermined time in each first fixed period, writes the data collected and pre-processed in the previous first fixed period and the data received from other devices into a first group of main cache areas and a second group of main cache areas in the DDR memory, respectively; The first group of main cache areas and the second group of main cache areas adopt a circular queue structure; The CPU polls and uses the data in the first group of main cache areas and the second group of main cache areas in each first fixed period.

6. The multi-heterogeneous subject system optimization method for a real-time processing scene according to claim 5, characterized in that: When the CPU sends data, the FPGA performs data write back and read between the DDR memory of the CPU and the internal cache of the FPGA according to the set time slot or period, and specifically: The CPU writes the control data to be sent into a third group of buffer areas in the DDR memory at a second predetermined time in each second fixed period, and the third group of buffer areas are alternating buffer areas, and adopt A / B alternating buffer, The FPGA initiates a direct memory access (DMA) operation at a third predetermined time in each second fixed period, reads data from a third set of preset buffer regions in the DDR memory, and sends the read data to an external device including a power system signal and other devices; The first fixed period and the second fixed period are equal to a control period of a control and protection device in the power system, and the first predetermined time, the second predetermined time, and the third predetermined time are sequentially staggered in the corresponding fixed period.

7. The multi-heterogeneous principal system optimization method for real-time processing scenarios according to claim 6, characterized in that: The first set of main cache regions and the second set of main cache regions each have a reserved position, and the FPGA does not write data to the reserved position; when the CPU polls and reads and uses data in the first set of main cache regions and the second set of main cache regions, the first large core and the second large core read data in the first set of main cache regions and the second set of main cache regions and then perform operations, and intermediate data generated in the operations is written to the reserved position of the main cache region corresponding to the read data; When the first small core reads data from the first set of main cache regions and the second set of main cache regions, it directly reads without data copying; The data structures of the first set of main cache regions, the second set of main cache regions, and the third set of buffer regions are byte-aligned according to the capacity of a CPU cache line.

8. The multi-heterogeneous principal system optimization method for real-time processing scenarios according to claim 7, characterized in that: The three-buffer independent access is combined with atomic state switching for data interaction between multiple cores, specifically: Three shared buffer regions for intra-core communication are constructed, a core that writes data into a corresponding buffer region is a producer core, and a core that reads data from a corresponding buffer region is a consumer core; a buffer region that is written by a producer core is a production buffer region, a buffer region that is currently read by a consumer core is a consumption buffer region, and an idle buffer region that is not currently read and written is a standby buffer region; A global state pointer is constructed, the global state pointer is an atomic variable, includes three index fields and a version number, each index field respectively indicates a buffer region number currently serving as a production buffer region, a consumption buffer region, and a standby buffer region, and the version number indicates the number of global state pointer updates; When a producer core writes data in a current production buffer region, a write memory barrier instruction is inserted after writing sectional data of a frame, the global state pointer is updated through atomic compare-and-swap, the standby buffer region is switched to a new production buffer region, the production buffer region is switched to a new standby buffer region, and a full memory barrier instruction is inserted; When a consumer core reads data, the global state pointer is read through atomic reading, a read memory barrier instruction is inserted, whether new data exists in the standby buffer region indicated by the global state pointer is checked through an increment of the version number of the global state pointer, if new data exists, the global state pointer is updated through atomic compare-and-swap, the standby buffer region is switched to a new consumption buffer region, the consumption buffer region is switched to a new standby buffer region, and data in the currently bound consumption buffer region is read.

9. The multi-heterogeneous principal system optimization method for real-time processing scenarios according to claim 8, characterized in that: the compiler automatically inserts prefetch instructions in the loop unrolling and pipelining stages; and the compiler linearly arranges data members in the physical address space, specifically: the compiler arranges all data members accessed continuously more than a set number of times in the program and all data members repeatedly accessed more than a set number of times in the loop or hot path in the physical address space adjacently; and the compiler arranges all data members with data flow or control dependencies in the physical address space adjacently; the data members are fields in structures or objects; the compiler automatically inserts prefetch instructions in the loop unrolling and pipelining stages; if it is identified that the access addresses in the loop iteration present linear growth and the step of the loop iteration is a fixed value, it is considered that the elements of the array or the array of structures are accessed in order, and the subsequent elements of the array or the array of structures are prefetched through the prefetch instructions; the operation values on the array or the array of structures are converted into NEON vector instructions, the operation values are operation instructions for arithmetic operations, data movements, or conditional judgments on each element of the array or the array of structures, and the subsequent continuous elements in the array or the array of structures are executed in batch parallel processing through a single NEON vector instruction.

10. A multi-heterogeneous agent system optimization system for real-time processing scenarios based on the optimization method of any of claims 1-9, comprising: The parallel optimization module, the data interaction optimization module of the FPGA and the CPU, the inter-core data interaction optimization module, and the compiler optimization module are characterized in that: the parallel optimization module: the CPU includes parallel division of labor in the BMP mode of bare cores, the CPU includes a plurality of large cores and a plurality of small cores, control tasks, protection tasks, and reception of master station commands are run on the large cores, and background tasks are run on the small cores; the data interaction optimization module of the FPGA and the CPU: the FPGA initiatively constructs a data synchronization mechanism to perform data interaction between the FPGA and the CPU, according to the FPGA initiatively constructs a data synchronization mechanism, the FPGA performs data write-back and read between the DDR memory of the CPU and the internal cache of the FPGA according to a set time slot or period, and the preprocessing of data in the data write-back and read process is migrated from the CPU to the FPGA layer for execution; the inter-core data interaction optimization module: three-buffer independent access and atomic state switching are combined to perform data interaction between a plurality of cores; the compiler optimization module: the compiler automatically inserts prefetch instructions in the loop unrolling and pipelining stages; and the compiler linearly arranges data members in the physical address space.

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