Hybrid built-in system test switch circuitry for embedded memory testing

Abstract

The invention relates to a hybrid built-in system test switch circuit arrangement for embedded memory testing. Various embodiments relate to an exemplary system-on-chip integrated circuit configured to perform built-in self-test operations on an embedded memory. An example system-on-chip integrated circuit includes a dynamic BIST switching circuitry and an embedded memory. The dynamic BIST switching circuitry is configured to generate a dynamic BIST output based on the test state. The embedded memory is configured to receive the dynamic BIST output. The embedded memory includes fixed BIST switching circuitry configured to generate a fixed BIST output based on the test state. Wherein the fixed BIST switching circuitry is inside the embedded memory and the dynamic BIST switching circuitry is outside the embedded memory.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 688,009, filed August 28, 2024, the entire contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure generally relate to built-in self-test (BIST) switching circuitry apparatus for embedded memories on a system-on-a-chip integrated circuit (SoC), and more particularly, to hybrid implementation of BIST switching circuitry apparatus on a SoC. BACKGROUND

[0004] System-on-a-chip integrated circuits (SoCs) generally utilize testing procedures to ensure proper operation of components of the electrical system. Memories are one type of electrical component that require testing procedures to ensure proper operation. Built-in self-test (BIST) can be utilized to test functionality of embedded memories on a SoC device. BIST can utilize predefined test patterns to test functionality of the embedded memories. For example, BIST can write a pattern of ones and zeros to an embedded memory block. Depending on the readout of the memory after the test pattern is written, the SoC can determine the operational status of the embedded memory.

[0005] Applicants have identified a number of technical challenges and difficulties associated with performing BIST operations on embedded memories. Through exerted efforts, ingenious designs, and innovations, Applicants have solved problems associated with performing BIST operations by developing solutions embodied in the present disclosure, which are described in detail below. SUMMARY

[0006] Various embodiments are directed to an exemplary system-on-a-chip integrated circuit (SoC) configured to perform built-in self-test (BIST) operations on an embedded memory. The exemplary system-on-a-chip integrated circuit can include a dynamic BIST switching circuitry apparatus and an embedded memory. The dynamic BIST switching circuitry apparatus is configured to generate a dynamic BIST output based on a test state. The embedded memory is configured to receive the dynamic BIST output. The embedded memory includes a fixed BIST switching circuitry apparatus configured to generate a fixed BIST output based on the test state. Wherein the fixed BIST switching circuitry apparatus is internal to the embedded memory and the dynamic BIST switching circuitry apparatus is external to the embedded memory.

[0007] In some embodiments, the dynamic BIST output is a timing critical memory signal.

[0008] In some embodiments, one or more pipeline registers are added to the dynamic BIST output between the dynamic BIST switching circuitry and the embedded memory.

[0009] In some embodiments, the dynamic setup time of a dynamic BIST switching circuit is reduced compared to the fixed setup time of a fixed BIST switching circuit.

[0010] In some embodiments, the fixed BIST output is not a timing-critical memory signal.

[0011] In some embodiments, one or more dynamic BIST transistors, including a dynamic BIST switching circuit device, are low-voltage threshold (LVT) transistors.

[0012] In some embodiments, one or more fixed BIST transistors, including a fixed BIST switching circuit arrangement, are high voltage threshold (HVT) transistors.

[0013] In some embodiments, the dynamic BIST switching circuitry includes a multiplexer (mux).

[0014] In some embodiments, the embedded memory is static random access memory (SRAM).

[0015] A second example system-on-chip integrated circuit is also provided. In some embodiments, the system-on-chip integrated circuit includes a dynamic BIST switching circuit device and an embedded memory. The BIST switching circuit device is configured to generate one or more memory control signals based on a test state. The embedded memory is configured to receive the one or more memory control signals from the dynamic BIST switching circuit device. The embedded memory includes a fixed BIST switching device configured to generate one or more data transmission signals based on the test state. The fixed BIST switching circuit device is located within the embedded memory, and the dynamic BIST switching circuit device is located outside the embedded memory.

[0016] In some embodiments, one or more memory control signals are timing-critical memory signals.

[0017] In some embodiments, one or more memory control signals include at least an address signal, a chip select signal, or a write enable signal.

[0018] In some embodiments, one or more data transmission signals include at least a data signal or a mask signal.

[0019] In some embodiments, one or more data transmission signals are based on test data signals.

[0020] In some embodiments, the test data signal includes bits defining the number of data clusters for a repeated test data pattern, and wherein the repeated test data pattern is applied to input / output (IO) blocks for each data cluster number.

[0021] In some embodiments, the number of data clusters is 2, 4, 8, or 16.

[0022] A third example system-on-chip integrated circuit (SoC) is also provided. In some embodiments, the SoC includes a dynamic BIST switching circuit device and an embedded memory. The dynamic BIST switching circuit device is configured to generate one or more data transmission signals based on a test state. The embedded memory is configured to receive the one or more data transmission signals from the dynamic BIST switching circuit device. The embedded memory further includes a fixed BIST switching circuit device configured to generate one or more memory control signals based on the test state. The fixed BIST switching circuit device is located within the embedded memory, and the dynamic BIST switching circuit device is located outside the embedded memory.

[0023] In some embodiments, the one or more data transmission signals are timing-critical memory signals.

[0024] In some embodiments, one or more data transmission signals include at least a data signal or a mask signal.

[0025] In some embodiments, one or more memory control signals include at least an address signal, a chip select signal, or a write enable signal. Attached Figure Description

[0026] Referring now to the accompanying drawings. Components shown in the drawings may or may not be present in some embodiments described herein. According to exemplary embodiments of this disclosure, some embodiments may include fewer (or more) components than those shown in the figures.

[0027] Figure 1A - Figure 1B A comparison is shown between an example embedded memory that includes a BIST switching circuit device located within the embedded memory and an example embedded memory without embedded memory.

[0028] Figure 2 A block diagram of an example SoC according to an example embodiment of this disclosure is shown.

[0029] Figure 3An example embodiment of a hybrid BIST switching circuit device including a dynamic BIST switching circuit device and a fixed BIST switching circuit device is shown according to an example embodiment of the present disclosure.

[0030] Figure 4 An example embodiment of a hybrid BIST switching circuit device including a dynamic BIST switching circuit device and a fixed BIST switching circuit device is shown according to an example embodiment of the present disclosure.

[0031] Figure 5 An example embedded memory including a hybrid BIST switching circuit device utilizing a data cluster is shown according to an example embodiment of the present disclosure.

[0032] Figure 6 An example block diagram of an example SoC including a hybrid BIST switching circuit device utilizing pipelined registers, according to an example embodiment of the present disclosure, is shown.

[0033] Figure 7 An example block diagram of the computing component of a controller according to an example embodiment of the present disclosure is depicted. Detailed Implementation

[0034] Exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the invention disclosed herein. In fact, embodiments of this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The same reference numerals throughout denote the same elements.

[0035] Various example embodiments address technical problems associated with performing BIST operations on embedded memory of a SoC. As those skilled in the art to which this disclosure pertains will understand, there are a variety of example scenarios in which users may expect to perform BIST operations on embedded memory of a SoC.

[0036] For example, SoCs typically utilize testing processes to ensure the correct operation of various electrical components within the SoC. Memory is one such electrical component that may require testing to ensure proper operation. BIST can be used to test the functionality of embedded memory on an SoC. BIST can test the functionality of embedded memory using predefined test patterns. For example, BIST can write 1s and 0s to a block of embedded memory. Depending on the memory reads after writing the test pattern, the SoC can determine the operational state of the embedded memory.

[0037] like Figure 1A - Figure 1BAs shown, BIST execution may require switching circuit devices 102a, 102b (e.g., multiple 2×1 multiplexers) to switch between standard operating memory signals and BIST memory signals. Typically, two different BIST implementations are used, such as... Figure 1A As shown, the BIST switching circuit device 102a is implemented outside the embedded memory 100a, and as... Figure 1B As shown, the BIST switching circuit device 102b is implemented in the embedded memory 100b.

[0038] Each implementation of the BIST switching circuit devices 102a and 102b can offer advantages and disadvantages. For example, as Figure 1A As shown, the BIST switching circuitry 102a is located external to the embedded memory 100a. Placing the BIST switching circuitry 102a external to the embedded memory 100a provides greater flexibility in the design and operation of the BIST switching circuitry 102a. For example, SoC design engineers can design and implement the BIST switching circuitry 102a in coordination with the SoC. In some embodiments, the embedded memory 100a may include timing-critical memory signals. For example, one or more memory control signals may limit the clock speed of the SoC. SoC design engineers may choose to optimize the BIST switching circuitry 102a to reduce setup and / or hold times associated with timing-critical memory signals, thereby improving the overall performance of the embedded memory 100a and / or the SoC.

[0039] In addition to increasing the flexibility of optimizing memory interface signals, positioning the BIST switching circuit device 102a outside the embedded memory 100a reduces routing congestion at the embedded memories 100a and 100b. Figure 1A As shown, only the output of the BIST switching circuit device 102a is routed to the embedded memory 100a. In contrast, as... Figure 1B As shown, for each memory signal used during BIST, the standard operating signal and the test signal are routed to the embedded memory 100b. By positioning the BIST switching circuit device 102a outside the embedded memory 100a, routing congestion and complexity at and around the embedded memory 100a are reduced.

[0040] However, as Figure 1A As shown, there are also disadvantages to positioning the BIST switching circuit device 102a outside the embedded memory 100a. For example, placing the BIST switching circuit device 102a outside the embedded memory 100a can occupy more space. Figure 1AAs shown, the additional space (Y) outside the embedded memory 100a for accommodating the BIST switch circuit device 102a is greater than the additional space (ΔX) required by the embedded memory 100b to position the BIST switch circuit device 102b within the embedded memory 100b.

[0041] Furthermore, the timing associated with the SoC, including the embedded memory 100a with BIST and the associated BIST switching circuitry 102a, may be affected by the configuration of the BIST switching circuitry 102a. Therefore, optimizing the BIST switching circuitry 102a late in the design process may affect the overall timing of the SoC, necessitating modifications to the overall SoC design. Conversely, when the BIST switching circuitry 102b is packaged within the embedded memory 100b, the timing characteristics of the embedded memory 100b (including the BIST switching circuitry 102b) are established during the fabrication of the embedded memory 100b.

[0042] like Figure 1B As shown, and as Figure 1A The BIST switching circuit device 102b is located within the embedded memory 100b, which utilizes less space (ΔX) compared to locating the BIST switching circuit device 102a outside the embedded memory 100a (X). However, locating the BIST switching circuit device 102b within the embedded memory 100b may require additional memory signal routing to the embedded memory 100b. For example, with the BIST switching circuit device 102b located within the embedded memory 100b, for each memory signal used during BIST operation, both the standard operating signal and the BIST signal are routed to the embedded memory 100b. Routing additional signals to the embedded memory 100b may result in additional congestion and complexity in routing within and around the embedded memory 100b.

[0043] The various example embodiments described herein provide hybrid BIST switching circuitry devices for embedded memory on a SoC. The hybrid BIST switching circuitry device includes a dynamic BIST switching circuitry device that includes switching circuitry for one or more timing-critical memory signals of the embedded memory. The dynamic BIST switching circuitry device is implemented at the SoC level outside the embedded memory. The hybrid BIST switching circuitry device further includes a fixed BIST switching circuitry device that includes switching circuitry for one or more low latency memory signals, which are typically not timing-critical memory signals of the embedded memory. The fixed BIST switching circuitry device is implemented within the embedded memory. The hybrid BIST switching circuitry device enables optimization of the BIST switching circuitry device based on area and timing constraints.

[0044] Furthermore, in some embodiments, data clustering techniques can be utilized to further reduce the complexity and congestion associated with signal routing at or near the embedded memory. For example, in some embodiments, repeated test data patterns can be written to the embedded memory during BIST operation. The test data patterns enable the transmission of test data signals and / or test mask signals with reduced bit widths. The test data patterns established by the reduced-size test data signals can be repeated on consecutive I / O blocks of the embedded memory.

[0045] As a result of the exemplary embodiments described herein, and in some examples, the efficiency of embedded memory can be significantly improved. For example, timing-critical signals of the embedded memory BIST can be optimized based on the parameters and constraints of the SoC. Furthermore, due to the BIST switching circuitry, the area used by the BIST switching circuitry and the routing complexity in and around the embedded memory can be reduced.

[0046] Now for reference Figure 2 A sample SoC200 is provided. Figure 2 As shown, the example SoC 200 includes embedded memory 206, which includes embedded memory core circuitry 210 and fixed BIST switch circuitry 208. Fixed BIST switch circuitry 208 is configured to provide a fixed BIST output 213 to embedded memory core circuitry 210. The example SoC 200 also includes a dynamic BIST switch circuitry 204 external to embedded memory 206. Dynamic BIST switch circuitry 204 is configured to generate a dynamic BIST output 217 containing one or more memory signals and to transmit the dynamic BIST output 217 to embedded memory 206. Figure 2The SoC 200 further describes that it includes a controller 202 configured to generate a BIST memory signal 212 and an operation memory signal 214 for a fixed BIST switch circuit device 208; a time-critical BIST memory signal 216 and a time-critical operation memory signal 218 for a dynamic BIST switch circuit device 204; and a test state 215 signal.

[0047] like Figure 2 As shown, SoC 200 includes any combination of hardware, software, and / or firmware, which includes one or more integrated circuits and integrates most or all of the components of a computer or other electronic system. For example, SoC 200 may include a central processing unit (CPU), a microprocessor, or another controller (e.g., controller 202). SoC 200 may also include one or more memory controllers configured to interface with embedded memory (e.g., embedded memory 206), external memory, flash memory, memory cache, etc. SoC 200 may also include various processing circuitry, such as radio, modem, input / output circuitry, graphics processing unit, etc. In some embodiments, the listed components may be implemented on a single substrate or microchip.

[0048] like Figure 2 As further illustrated, the example SoC 200 includes embedded memory 206. Embedded memory 206 includes any hardware exemplified on the SoC 200 substrate and includes associated software and / or firmware configured to store information. Embedded memory 206 may include non-volatile and / or volatile storage media. Examples of non-limiting non-volatile storage devices may include solid-state storage devices, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, and / or the like), multimedia memory cards (MMC), secure digital storage (SD) cards, smart media cards, compact flash memory (CF) cards, memory sticks, and / or the like. Examples of non-limiting volatile storage may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0049] like Figure 2As further shown, the embedded memory 206 also includes an embedded memory core circuitry arrangement 210. The embedded memory core circuitry arrangement 210 includes various electrical components necessary for the operation of the embedded memory 206 and for interfacing with the embedded memory 206. For example, the embedded memory core circuitry arrangement 210 may include a memory core. The memory core includes various electrical components configured to store information and / or state. For example, storage transistors or metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0050] The embedded memory core circuitry 210 may also include input / output (I / O) circuitry. I / O circuitry includes various electrical components configured to facilitate the transfer of read data from the memory core and / or the transfer of write data to the memory core.

[0051] The embedded memory core circuitry 210 also includes control circuitry. The control circuitry includes various electronic components configured to control access to the memory core. For example, the control circuitry can enable reading from and / or writing to the memory core via read and write enable signals, chip select signals, etc.

[0052] The embedded memory core circuitry 210 also includes a decoder circuitry. The decoder circuitry includes various electronic components configured to determine the memory location within the memory core based on a provided address.

[0053] like Figure 2 As further shown, the embedded memory 206 includes a fixed BIST switch circuit device 208. The fixed BIST switch circuit device 208 is contained within the embedded memory 206 and includes various circuits, including hardware and / or software for selecting between a BIST memory signal 212 and an operational memory signal 214 to generate a fixed BIST output 213 based on a test state 215. The fixed BIST switch circuit device 208 can be a combination and / or a mixture of sequential elements based on requirements. Because the fixed BIST switch circuit device 208 is contained within the embedded memory 206, the setup time, hold time, and other timing characteristics of the fixed BIST output 213 are fixed during the manufacture of the embedded memory 206 based on the BIST memory signal 212, the operational memory signal 214, and the test state 215 received at the input pins of the embedded memory 206.

[0054] In some embodiments, the fixed BIST switching circuitry 208 may be configured to select between a BIST memory signal 212 and an operational memory signal 214 based on a test state 215. The test state 215 includes any signal configured to indicate test conditions of the SoC 200 relative to the embedded memory 206. For example, a high logic signal (1) may indicate that the SoC 200 is performing BIST on the embedded memory 206. A low logic signal (0) may indicate that the embedded memory 206 is in normal operation. In some embodiments, in an example where the test state 215 indicates that the SoC 200 is performing BIST on the embedded memory 206, the BIST memory signal 212 may be transmitted as a fixed BIST output 213. Furthermore, in some embodiments, when the test state 215 indicates that the SoC 200 is in normal operation, the operational memory signal 214 may be transmitted as a fixed BIST output 213.

[0055] BIST memory signals 212 include any memory control or memory data signals transmitted to the fixed BIST switch circuitry 208 for use during BIST execution. BIST memory signals 212 may include data transfer signals, such as data signals and mask signals. BIST memory signals 212 may also include memory control signals, such as address signals, chip select signals, write enable signals, etc.

[0056] Similarly, the operating memory signal 214 includes any memory control or memory data signals transmitted to the fixed BIST switching circuit device 208 for use during the operation of the embedded memory.

[0057] Because the fixed BIST switch circuitry 208 is located within the embedded memory 206, once the embedded memory 206 is manufactured, the timing of the BIST memory signal 212 and the operational memory signal 214 passing through the fixed BIST switch circuitry 208 can be maintained without modification. Therefore, in some embodiments, the BIST memory signal 212 and the operational memory signal 214 may not include timing-critical memory signals.

[0058] Timing-critical memory signals are any memory signals on the critical path of embedded memory 206. The critical path of embedded memory 206 is the combined path of embedded memory with the maximum timing delay between registers and memory. The maximum clock rate of embedded memory 206 and interface circuitry can be defined by the critical path.

[0059] In embodiments where the fixed BIST switching circuitry 208 does not manage timing-critical memory signals, the fixed BIST switching circuitry 208, including the embedded memory 206, can save area. For example, the fixed BIST switching circuitry 208 may include fixed BIST transistors. The type of transistor including the fixed BIST transistor can be selected based on performance requirements. For example, the transistor type can be selected to prioritize size over speed. For example, a high voltage threshold (HVT) transistor can be used to reduce the leakage power of the fixed BIST transistor including the fixed BIST switching circuitry 208.

[0060] In some embodiments, the BIST memory signal 212 may utilize data clustering to reduce the size of the BIST memory signal 212 input to the embedded memory 206. Reference Figure 5 Further discussion of technologies related to data clustering.

[0061] like Figure 2 As further illustrated, the exemplary SoC 200 includes a dynamic BIST switch circuitry 204. The dynamic BIST switch circuitry 204 is external to the embedded memory 206 and includes various circuitry, including hardware and / or software, for selecting between a time-critical BIST memory signal 216 and a time-critical operational memory signal 218 to generate a dynamic BIST output 217 based on a test state 215. Because the dynamic BIST switch circuitry 204 is external to the embedded memory 206, the dynamic BIST switch circuitry, including the time-critical BIST memory signal 216, the time-critical operational memory signal 218, and the embedded memory 206, can be modified based on the characteristics and requirements of the SoC 200.

[0062] For example, various components of the dynamic BIST switching circuitry 204 can be modified or adjusted to change the setup time, hold time, and other timing characteristics of the dynamic BIST output 217. In this way, the time-critical BIST memory signal 216 and the time-critical operation memory signal 218 can exhibit dynamic set time and dynamic hold time. In some embodiments, the dynamic BIST switching circuitry 204 may include a dynamic BIST transistor. The type of transistor including the dynamic BIST transistor can be selected based on performance requirements. The technology and / or characteristics of the dynamic BIST transistor can be changed to alter the timing characteristics of the time-critical BIST memory signal 216 and the time-critical operation memory signal 218. For example, in some embodiments, the dynamic BIST transistor may include a low-voltage threshold (LVT) transistor. An LVT transistor can occupy more area; however, an LVT transistor can also achieve a faster switching speed. This speed prioritization in the dynamic BIST transistor can reduce the setup and / or hold time of the dynamic BIST switching circuitry 204.

[0063] In some embodiments, the dynamic BIST switching circuitry 204 may be configured to select between a time-critical BIST memory signal 216 and a time-critical operation memory signal 218 based on a test state 215. In some embodiments, when the test state 215 indicates that the SoC 200 is performing BIST operation on the embedded memory 206, the time-critical BIST memory signal 216 may be transmitted as a dynamic BIST output 217. Furthermore, in some embodiments, when the test state 215 indicates that the SoC 200 is in normal operation, the time-critical operation memory signal 218 may be sent as a dynamic BIST output 217.

[0064] As described herein, the time-critical BIST memory signal 216 includes any time-critical memory signals sent to the dynamic BIST switching circuitry 204 for use during BIST execution on the embedded memory 206. The time-critical BIST memory signal 216 may include data transfer signals, such as data signals and mask signals. The time-critical BIST memory signal 216 may also include memory control signals, such as address signals, chip select signals, write enable signals, etc.

[0065] Similarly, the time-critical operation memory signal 218 includes any time-critical memory signals transmitted to the dynamic BIST switching circuitry 204 for use during standard operation of the embedded memory 206.

[0066] Because the dynamic BIST switch circuitry 204 is external to the embedded memory 206, the timing of the time-critical BIST memory signal 216 and the time-critical operation memory signal 218 via the dynamic BIST switch circuitry 204 can be optimized after the embedded memory 206 is manufactured. Therefore, the dynamic BIST switch circuitry 204 provides flexibility in adjusting the timing of certain memory signals. Furthermore, selecting the dynamic BIST output 217 external to the embedded memory 206 reduces the number of inputs required to support BIST operation at the embedded memory 206. Therefore, the complexity of signal routing in and around the embedded memory 206 can be reduced.

[0067] like Figure 2 As further illustrated, the example SoC 200 includes a controller 202. The controller 202 includes any processor, microcontroller, or other processing device configured to instruct operations required to perform BIST on the embedded memory. For example, the controller 202 may be configured to determine a test state 215 of the SoC 200. In some embodiments, the controller 202 may initiate BIST at predetermined intervals at startup based on the state of the SoC 200, and / or be initiated by an external user or computing system. In the example of initiating BIST, the controller may trigger a test state 215 signal to indicate the start of the BIST process. Furthermore, the controller may be configured to provide a BIST memory signal 212 and a time-critical BIST memory signal 216 to test the embedded memory 206. For example, the controller 202 may configure various memory signals to write BIST patterns to one or more portions of the embedded memory 206 and subsequently read the written portions of the embedded memory 206. The controller 202 may further analyze the read memory data to determine the correct operation of the embedded memory 206.

[0068] In some embodiments, controller 202 may include a central processing unit (CPU). In such embodiments, controller 202 may also be configured to perform all necessary processing operations of SoC 200. Such operations may include configuring operation memory signal 214 and time-critical operation memory signal 218 for using embedded memory 206 during operation. Although operation memory signal 214 and time-critical operation memory signal 218 are from... Figure 2 The controller 202 in the SoC 200 is derived from the operating memory signal 214, but the operating memory signal 214 and the time-critical operating memory signal 218 can be derived from any number of electronic sources on or outside the SoC 200. Regarding Figure 7 Describes an example configuration for controller 202.

[0069] Now for reference Figure 3An example embodiment of an embedded memory 206 is provided, comprising a hybrid BIST switching circuitry device including a dynamic BIST switching circuitry device 204 and a fixed BIST switching circuitry device 208. For example... Figure 3 As shown, the embedded memory 206 includes an embedded memory core circuit device 210 and a fixed BIST switch circuit device 208. The fixed BIST switch circuit device 208 is configured to receive data signals and mask signals as BIST memory signals 212 and operation memory signals 214, and generate a fixed BIST output based on the test state 215. Figure 3 The description further illustrates that the dynamic BIST switch circuitry 204 is external to the embedded memory 206. The dynamic BIST switch circuitry 204 is configured to receive various memory control signals as time-critical BIST memory signals 216 and time-critical operation memory signals 218, and generate a dynamic BIST output 217 based on the test state 215.

[0070] like Figure 3 As shown, embedded memory 206 includes embedded memory core circuitry 210. Example embedded memory core circuitry 210 includes control circuitry, core circuitry, decoding circuitry, and input / output circuitry (IO). The control circuitry is configured to receive various memory control signals, including address bits (A0-Aj), chip select signals (CSN), and write enable signals (WEN). In some embodiments, one or more memory control signals may be timing-critical memory signals. For example, one or more memory control signals may include a portion of the critical path of embedded memory 206. Thus, the memory control signals are selected by a dynamic BIST switching circuitry 204 external to embedded memory 206. By utilizing the dynamic BIST switching circuitry 204 to select the memory control signals, the selection of memory control signals can be optimized based on timing constraints / requirements.

[0071] like Figure 3As shown, the dynamic BIST switching circuit device 204 includes multiple multiplexers. Each multiplexer is configured to receive bits of the time-critical operation memory signal 218 (e.g., A0-Aj, CSN, WEN) and corresponding bits of the time-critical BIST memory signal 216 (e.g., TA0-TAj, TCSN, TWEN). In the example where BIST operation is performed as indicated by the test state 215 signal, the time-critical BIST memory signal 216 (e.g., TA0-TAj, TCSN, TWEN) is selected as the dynamic BIST output 217. Alternatively, under normal operation of the embedded memory 206, as indicated by the test state 215 signal, the time-critical operation memory signal 218 (e.g., A0-Aj, CSN, WEN) is selected as the dynamic BIST output 217. Therefore, the selection of the timing-critical memory control signal is performed outside of the embedded memory 206.

[0072] like Figure 3 As further shown, the example embedded memory core circuit device 210 includes a core circuit (CORE). The core circuit is configured to receive various data transmission signals, including data bits (D0-Dn) and mask bits (M0-Mn). The data bits and mask bits enable corresponding data to be written to the target memory location. For example... Figure 3 As shown, the data transmission signal is not a timing-critical memory signal. Therefore, the data transmission signal is selected by the fixed BIST switch circuit device 208 within the embedded memory 206. Using the fixed BIST switch circuit device 208 to control the selection of the data transmission signal provides area savings and fixed timing characteristics for memory signals that are not timing-critical.

[0073] like Figure 3 As shown, the fixed BIST switch circuit device 208 includes multiple multiplexers. Each multiplexer is configured to receive one bit (e.g., D0-Dn, M0-Mn) of the operating memory signal 214 and the corresponding bit (e.g., TD0-TDn, TM0-TMn) of the BIST memory signal 212. In an example where BIST operation is performed as indicated by the test state 215 signal, the BIST memory signal (e.g., TD0-TDn, TM0-TMn) is selected as the fixed BIST output 213. Alternatively, under normal operation of the embedded memory 206, as indicated by the test state 215 signal, the operating memory signal 214 (e.g., D0-Dn, M0-Mn) is selected as the fixed BIST output 213. Therefore, the selection of data transmission signals is performed within the embedded memory 206.

[0074] Now for reference Figure 4An example embodiment of an embedded memory 206 is provided, comprising a hybrid BIST switching circuitry device including a dynamic BIST switching circuitry device 204 for controlling data transmission signals and a fixed BIST switching circuitry device 208 for controlling memory control signals. For example... Figure 4 As shown, the embedded memory 206 includes an embedded memory core circuit device 210 and a fixed BIST switch circuit device 208. The fixed BIST switch circuit device 208 is configured to receive various memory control signals as BIST memory signals 212 and operation memory signals 214, and generate a fixed BIST output 213 based on a test state 215. Figure 4 The description further illustrates that the dynamic BIST switch circuit device 204 is external to the embedded memory 206. The dynamic BIST switch circuit device 204 is configured to receive various data transmission signals as time-critical BIST memory signals 216 and time-critical operation memory signals 218, and generate a dynamic BIST output 217 based on the test state 215.

[0075] like Figure 4 As shown, embedded memory 206 includes embedded memory core circuitry 210. Example embedded memory core circuitry 210 includes control circuitry, core circuitry, decoding circuitry, and input / output circuitry (IO). The control circuitry is configured to receive various memory control signals, including address bits (A0-Aj), chip select signals (CSN), and write enable signals (WEN). In some embodiments, the memory control signals may not include timing-critical memory signals. Therefore, the timing characteristics of embedded memory 206 may not benefit from increased speed of the switching circuitry associated with the memory control signals. In this embodiment, the memory control signals may be selected by a fixed BIST switching circuitry 208 within embedded memory 206. Figure 4 As shown, the fixed BIST switch circuit device 208 may include multiple multiplexers, each configured to receive bits of the operating memory signal 214 (e.g., A0-Aj, CSN, WEN) and corresponding bits of the BIST memory signal 212 (e.g., TA0-TAj, TCSN, TWEN). Selecting the memory control signals within the embedded memory 206 enables area savings and provides established timing characteristics for the memory control signals of the embedded memory 206.

[0076] like Figure 4 The text further describes how the core circuitry is configured to receive various data transmission signals, including data bits (D0-Dn) and mask bits (M0-Mn). The data bits and mask bits enable the corresponding data to be written to the target memory location. For example...Figure 4 As shown, in some embodiments, the data transmission signal may include a timing-critical memory signal. For example, based on the size or shape of the embedded memory 206, the data transmission signal can be configured to travel a greater distance. Therefore, as Figure 4 As shown, the data transmission signal is selected by a dynamic BIST switching circuit device 204 external to the embedded memory 206. Using the dynamic BIST switching circuit device 204 to control the selection of the timing-critical data transmission signal allows for optimization of the dynamic BIST switching circuit device 204. For example, a dynamic BIST transistor including the dynamic BIST switching circuit device 204 can be selected to optimize speed. For example, an LVT transistor can be used in the dynamic BIST switching circuit device 204.

[0077] like Figure 5 As further shown, the dynamic BIST switching circuit device 204 includes multiple multiplexers. Each multiplexer is configured to receive bits (e.g., D0-Dn, M0-Mn) of the time-critical operation memory signal 218 and corresponding bits (e.g., TD0-TDn, TM0-TMn) of the time-critical BIST memory signal 216. In the example where BIST operation is performed as indicated by the test state 215 signal, the time-critical BIST memory signal 216 (e.g., TD0-TDn, TM0-TMn) is selected as the dynamic BIST output 217. Alternatively, under normal operation of the embedded memory 206, as indicated by the test state 215 signal, the time-critical operation memory signal 218 (e.g., D0-Dn, M0-Mn) is selected as the dynamic BIST output 217. Thus, the selection of the timing-critical memory control signal is performed outside of the embedded memory 206.

[0078] Now for reference Figure 5 An example embodiment of an embedded memory 206 utilizing a data cluster is provided. For example... Figure 5 As shown, the embedded memory 206 includes an embedded memory core circuit device 210 and a fixed BIST switch circuit device 208. The fixed BIST switch circuit device 208 is configured to receive a data signal and a mask signal as an operational memory signal 214. The fixed BIST switch circuit device 208 is further configured to receive a test data signal 550 and a test mask signal 552 during BIST execution as a BIST memory signal 212. The embedded memory 206 is configured to generate a fixed BIST output 213 from the operational memory signal 214 and the BIST memory signal 212 based on a test state 215. Figure 5The description further illustrates that the dynamic BIST switch circuitry 204 is external to the embedded memory 206. The dynamic BIST switch circuitry 204 is configured to receive various memory control signals as time-critical BIST memory signals 216 and time-critical operation memory signals 218, and generate a dynamic BIST output 217 based on the test state 215.

[0079] like Figure 6 As shown, during BIST operation utilizing the data cluster, routing complexity can be reduced at or near embedded memory 206 by decreasing the number of wires dedicated to data and mask signals. During BIST operation, certain repeating data patterns can be written to all or a portion of the memory locations in embedded memory 206. For example, all memory locations can be written to 1, or all memory locations can be written to 0. In some embodiments, repeating test patterns can be written to memory locations. For example, sequential memory locations can be written with alternating 1s and 0s (e.g., 10101010…). In some embodiments, the test pattern may include writing two 1s followed by two 0s (e.g., 110011001100…), four 1s followed by four 0s (e.g., 1111000011110000…), and so on. The data cluster utilizes repeating test data patterns to reduce the number of bits (e.g., data cluster bits) required for the data and mask signals during BIST operation.

[0080] For example, the alternating test pattern of 1s and 0s can be represented by a test data signal 550 consisting of only two bits ('01'). The test data signal 550 can be used to write sequential data blocks in test data mode, and then repeat for the next set of sequential data blocks, and so on. Therefore, during BIST operation, the entire memory can be written based on a reduced number of data cluster bits. Similarly, the mask signal 552 can be reduced based on the test pattern.

[0081] In some embodiments, the number of bits in the data cluster constituting the test data signal 550 can be 2 bits, 4 bits, 8 bits, or 16 bits. However, the number of bits in the data collection can be any number up to the size of the embedded memory 206.

[0082] Now for reference Figure 6 A sample SoC 660, including the pipeline register 662, is provided. Figure 6As shown, the example SoC 660 includes embedded memory 206, which includes embedded memory core circuitry 210 and fixed BIST switch circuitry 208. Fixed BIST switch circuitry 208 is configured to provide a fixed BIST output 213 to embedded memory core circuitry 210. The example SoC 660 also includes a dynamic BIST switch circuitry 204 external to embedded memory 206. Dynamic BIST switch circuitry 204 is configured to generate a dynamic BIST output 217 containing one or more memory signals and to transmit the dynamic BIST output 217 to embedded memory 206. Figure 6 The description further illustrates that the dynamic BIST output 217 passes through a pipeline register 662 located between the dynamic BIST switching circuitry 204 and the embedded memory 206. The SoC 200 also includes a controller 202 configured to generate a BIST memory signal 212 and an operational memory signal 214 for the fixed BIST switching circuitry 208; a time-critical BIST memory signal 216 and a time-critical operational memory signal 218 for the dynamic BIST switching circuitry 204; and a test status signal 215.

[0083] like Figure 7 As shown, the example SoC 660 includes a pipelined register 662 located between the dynamic BIST switching circuitry 204 and the embedded memory 206. The pipelined register 662 is any memory or information storage device configured to store one or more data elements. The pipelined register 662 may include flip-flops, such as D flip-flops. The pipelined register 662 can be synchronized with a clock signal. One or more pipelined registers can provide further flexibility when determining the timing characteristics of the time-critical BIST memory signal 216 and the time-critical operation memory signal 218. For example, the pipelined register 662 can be located between the dynamic BIST switching circuitry 204 and the embedded memory 206 to reduce the time between data storage points on the data path. By reducing the time between data storage points, the clock speed of the embedded memory 206 can be increased. Based on the timing characteristics of the SoC 660 and the embedded memory 206, multiple pipelined registers 662 can be located before, within, or after the dynamic BIST switching circuitry 204.

[0084] Now for reference ​This illustration shows an example controller 202 according to at least some example embodiments of the present disclosure. The controller 202 includes a processor 702, input / output circuitry 704, data storage medium 706, and communication circuitry 708. In some embodiments, the controller 202 is configured to use one or more sets of circuitry 702, 704, 706, and / or 708 to execute and perform the operations described herein.

[0085] Although components are described with respect to functional limitations, it should be understood that a particular implementation necessarily involves the use of specific computing hardware. It should also be understood that in some embodiments, certain components described herein include similar or common hardware. For example, two sets of circuits can utilize the same processor, network interface, storage medium, etc., to perform their associated functions, so that each set of circuits does not require duplicate hardware. Therefore, the term "circuit" as used herein with respect to components of the device described herein should be understood by the user to include specific hardware configured to perform functions associated with the specific circuits described herein.

[0086] Specifically, the term "circuit" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuit" includes processing circuitry, storage media, network interfaces, input / output devices, etc. Alternatively or additionally, in some embodiments, other elements of the controller 202 provide or supplement the functionality of other specific groups of circuitry. For example, in some embodiments, the processor 702 provides processing functionality to any group of circuitry, the data storage medium 706 provides storage functionality to any group of circuitry, the communication circuitry 708 provides network interface functionality to any group of circuitry, etc.

[0087] In some embodiments, processor 702 (and / or coprocessor or any other auxiliary or otherwise associated processing circuitry) communicates with data storage medium 706 via a bus to transfer information between components of controller 202. In some embodiments, for example, data storage medium 706 is non-transitory and may include, for example, one or more volatile and / or non-volatile memories. In other words, for example, in some embodiments, data storage medium 706 includes or embodies an electronic storage device (e.g., a computer-readable storage medium). In some embodiments, data storage medium 706 is configured to store information, data, content, applications, instructions, etc., to enable controller 202 to perform various functions according to exemplary embodiments of this disclosure.

[0088] Processor 702 can be implemented in a variety of different ways. For example, in some exemplary embodiments, processor 702 includes one or more processing devices configured to execute independently. Additionally or alternatively, in some embodiments, processor 702 includes one or more processors configured to be cascaded via a bus to enable independent execution of instructions, pipelined operation, and / or multithreading. The terms “processor” and “processing circuitry” should be understood to include single-core processors, multi-core processors, multiple processors within controller 202, and / or one or more remote or “cloud” processors external to controller 202.

[0089] In example embodiments, processor 702 is configured to execute instructions stored in data storage medium 706 or accessible to the processor. Alternatively, or additionally, in some embodiments, processor 702 is configured to perform hard-coded functionality. Thus, whether configured by hardware or software methods, or by a combination thereof, processor 702 represents an entity (e.g., physically contained in circuitry) capable of performing operations according to embodiments of this disclosure, and is configured accordingly. Alternatively or additionally, as another example in some exemplary embodiments, when processor 702 is implemented as an executor of software instructions, these instructions specifically configure processor 702 to perform the algorithms implemented in the specific operations described herein when executing such instructions.

[0090] In some embodiments, controller 202 includes input / output circuitry 704 that provides output to a user and, in some embodiments, receives indications of user input. In some embodiments, input / output circuitry 704 communicates with processor 702 to provide this functionality. Input / output circuitry 704 may include one or more user interfaces (e.g., user interfaces) and, in some embodiments, includes a display that includes interfaces presented as web user interfaces, application user interfaces, user devices, backend systems, etc. Processor 702 and / or input / output circuitry 704 including the processor may be configured to control one or more functions of one or more user interface elements via computer program instructions (e.g., software and / or firmware) stored in processor-accessible memory (e.g., data storage medium 706, etc.). In some embodiments, input / output circuitry 704 includes or utilizes user-oriented applications to provide input / output functionality to client devices and / or other displays associated with the user.

[0091] In some embodiments, controller 202 includes communication circuitry 708. Communication circuitry 708 includes any device, such as a device or circuit implemented in hardware or a combination of hardware and software, configured to receive and / or transmit data from / to a network and / or any other device, circuitry, or module communicating with controller 202. In this regard, for example, in some embodiments, communication circuitry 708 includes a network interface for enabling communication with wired or wireless communication networks. Additionally, or alternatively, in some embodiments, communication circuitry 708 includes one or more network interface cards, antennas, buses, switches, routers, modems, and supporting hardware, firmware, and / or software, or any other device suitable for enabling communication via one or more communication networks. Additionally, or alternatively, communication circuitry 708 includes circuitry for interacting with antennas and / or other hardware or software to induce signal transmission via the antenna or to process reception of signals received via the antenna. In some embodiments, communication circuitry 708 enables the transmission of data to and / or the reception of data from client devices communicating with controller 202.

[0092] Additionally or optionally, in some embodiments, one or more sets of circuits 702-708 are composable. Additionally or optionally, in some embodiments, one or more sets of circuits perform some or all of the functions associated with another component. For example, in some embodiments, one or more sets of circuits 702-708 are combined into a single module implemented in hardware, software, firmware, and / or a combination thereof.

[0093] While the detailed description has illustrated some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments, based on various modifications and improvements. For example, those skilled in the art will recognize that the principles described can be applied to any electronic device configured to perform a built-in self-test on a memory device.

[0094] In the appended claims, unless the specific terms “apparatus for…” or “steps for…” are used in a given claim, the claims are not intended to be interpreted in accordance with paragraph 6 of 35 U.S.SC §112.

[0095] The use of broader terms such as “comprising,” “including,” and “having” should be understood to support narrower terms such as “consisting of,” “substantially composed of,” and “substantially constitutes.” The use of terms such as “optionally,” “may,” “possibly,” etc., relative to any element of the implementation means that the element is not required, or alternatively, the element is required, both of which are within the scope of the implementation. Furthermore, references to examples are provided for illustrative purposes only and are not intended to be exclusive.

Claims

1. A system on chip integrated circuit comprising: a dynamic built-in system test (BIST) switch circuitry device configured to generate a dynamic BIST output based on a test state; and an embedded memory configured to receive the dynamic BIST output, the embedded memory further comprising: a fixed BIST switch circuitry device configured to generate a fixed BIST output based on the test state, wherein the fixed BIST switch circuitry device is internal to the embedded memory; wherein the dynamic BIST switch circuitry device is external to the embedded memory.

2. The system on chip integrated circuit of claim 1, wherein the dynamic BIST output is a timing critical memory signal.

3. The system on chip integrated circuit of claim 2, wherein one or more pipeline registers are added to the dynamic BIST output between the dynamic BIST switch circuitry device and the embedded memory.

4. The system on chip integrated circuit of claim 2, wherein a dynamic setup time for the dynamic BIST switch circuitry device is reduced relative to a fixed setup time for the fixed BIST switch circuitry device.

5. The system on chip integrated circuit of claim 2, wherein the fixed BIST output is not a timing critical memory signal.

6. The system on chip integrated circuit of claim 1, wherein one or more dynamic BIST transistors comprising the dynamic BIST switch circuitry device are low voltage threshold (LVT) transistors.

7. The system on chip integrated circuit of claim 1, wherein one or more fixed BIST transistors comprising the fixed BIST switch circuitry device are high voltage threshold (HVT) transistors.

8. The system on chip integrated circuit of claim 1, wherein the dynamic BIST switch circuitry device comprises a multiplexer (mux).

9. The system on chip integrated circuit of claim 1, wherein the embedded memory is a static random access memory (SRAM).

10. A system on chip integrated circuit comprising: a dynamic built-in system test (BIST) switch circuitry device configured to generate one or more memory control signals based on a test state; and an embedded memory configured to receive the one or more memory control signals from the dynamic BIST switch circuitry device, the embedded memory further comprising: a fixed BIST switch circuitry device configured to generate one or more data transfer signals based on the test state, wherein the fixed BIST switch circuitry device is internal to the embedded memory; wherein the dynamic BIST switch circuitry device is external to the embedded memory.

11. The system on chip integrated circuit of claim 10, wherein the one or more memory control signals are timing critical memory signals.

12. The system on chip integrated circuit of claim 10, wherein the one or more memory control signals comprise at least an address signal, a chip select signal, or a write enable signal.

13. The system on chip integrated circuit of claim 10, wherein the one or more data transfer signals comprise at least a data signal or a mask signal.

14. The system on chip integrated circuit of claim 10, wherein the one or more data transfer signals are based on a test data signal.

15. The system on chip integrated circuit of claim 14, wherein the test data signal comprises bits that define a number of data clusters of a repeating test data pattern, and wherein the test data pattern is repeated for each number of input / output (IO) blocks.

16. The system on chip integrated circuit of claim 15, wherein the number of data clusters is 2, 4, 8, or 16.

17. A system on chip integrated circuit, comprising: a dynamic built-in system test (BIST) switch circuit device configured to generate one or more data transfer signals based on a test state; and an embedded memory configured to receive the one or more data transfer signals from the dynamic BIST switch circuit device, the embedded memory further comprising: a fixed BIST switch circuit device configured to generate one or more memory control signals based on the test state; wherein the fixed BIST switch circuit device is internal to the embedded memory; wherein the dynamic BIST switch circuit device is external to the embedded memory.

18. The system on chip integrated circuit of claim 17, wherein the one or more data transfer signals are timing critical memory signals.

19. The system on chip integrated circuit of claim 17, wherein the one or more data transfer signals comprise at least a data signal or a mask signal.

20. The system on chip integrated circuit of claim 17, wherein the one or more memory control signals comprise at least an address signal, a chip select signal, or a write enable signal.

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