Multilayer solving method for accelerating circuit simulation, electronic equipment and storage medium

Abstract

The invention provides a multilayer solving method for accelerating circuit simulation, electronic equipment and a storage medium, and the method comprises the steps: carrying out the recursion division of a circuit into sub-circuits of a plurality of hierarchies, and forming a hierarchical structure from fine to coarse; on the basis of circuit delay attributes, marking and simplifying inactive parts in each level of sub-circuit, and constructing a mapping relation between levels at the same time; based on the hierarchical structure and the mapping relation, assembling a to-be-solved linear equation set; a multi-layer class method is adopted to solve the linear equation set, and the multi-layer class method comprises the steps that smoothing is carried out on a fine layer before iteration, a residual error is transmitted to a coarse layer, a direct method is adopted to solve the coarsest layer, and then a solving result is extended back to the fine layer and smoothing is carried out after iteration; and repeating the solving step of the multi-layer class method until the linear equation set converges. The system of linear equations is established based on a multi-level circuit structure and is solved by using a multi-level method, so that the solving time and memory occupation of the system of linear equations in circuit simulation are greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit computer-aided design, and in particular to a multi-layer class solving method for accelerating circuit simulation, an electronic device and a storage medium. BACKGROUND

[0002] With the continuous expansion of integrated circuit scale, modern analog and mixed-signal circuits exhibit strong nonlinearity, multiple time constants, and large-scale coupling. In full-chip simulation, traditional SPICE-level simulators face serious challenges in solving large-scale sparse linear equations formed by the circuit admittance matrix. This solving process is the most time-consuming part of simulation, especially in SoC (System on Chip) and multi-physical field coupled circuit design, the circuit scale leads to an increase in the degree of matrix ill-conditioning, making direct solving methods consume huge memory and iterative solving methods converge slowly.

[0003] Existing technologies mostly use direct methods for solving, but when dealing with super-large-scale circuits, limited by computer memory and computing power, it is difficult to balance accuracy and efficiency. Therefore, there is an urgent need for an efficient linear equation solving scheme that can significantly reduce computational complexity and memory usage and is suitable for large-scale circuit simulation. SUMMARY

[0004] To solve the defects of the prior art, the purpose of the present application is to provide a multi-layer class solving method for accelerating circuit simulation, an electronic device and a storage medium, which can greatly improve the efficiency of circuit simulation while ensuring accuracy.

[0005] To achieve the above purpose, the present application provides a multi-layer class solving method for accelerating circuit simulation, comprising: recursively dividing the circuit into multiple levels of sub-circuits to form a hierarchical structure from fine to coarse; based on the circuit delay attribute, labeling and simplifying the inactive part in each level of sub-circuit, and constructing the mapping relationship between levels; based on the hierarchical structure and the mapping relationship, assembling the linear equations to be solved; solving the linear equations using a multi-layer class method, which includes smoothing before iteration in the fine layer and passing the residual to the coarse layer, using a direct method to solve in the coarsest layer, and then extrapolating the solution back to the fine layer and performing post-smoothing; repeating the solving steps of the multi-layer class method until the linear equations converge.

[0006] Further, the step of recursively dividing the circuit into multiple levels of sub-circuits to form a hierarchical structure from fine to coarse, further comprises: The termination condition of the recursive division depends on the size of the coarsest layer sub-circuit, and the division is stopped when the solving calculation amount of the coarsest layer sub-circuit is lower than a preset threshold.

[0007] Further, the step of marking and simplifying the inactive part in each layer sub-circuit based on the circuit delay attribute and constructing the mapping relationship between layers further comprises: Based on the delay attribute of the circuit function module, the inactive part in each layer sub-circuit is marked, and the circuit simplification is performed on the inactive part.

[0008] Further, the simplification method is that when a coarser layer sub-circuit is constructed, only the active part of the current layer is aggregated to the coarse layer, and the inactive part is retained in the current layer.

[0009] Further, the mapping relationship includes a restriction mapping for transmitting residual errors from a fine layer to a coarse layer, and a continuation mapping for transmitting solution vectors from the coarse layer to the fine layer.

[0010] Further, the step of solving the linear equation set by using the multilayer method further comprises that the iteration method used after the pre-smoothing and the post-smoothing is the Jacobi iteration method or the Gauss-Seidel iteration method.

[0011] Further, the multilayer method is directly used to solve the overall equation set, or is used as a preprocessing sub-step in the iteration framework of the generalized minimal residual method.

[0012] Further, the direct method is the LU decomposition method or the Cholesky decomposition method.

[0013] To achieve the above object, the application further provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor is used to execute the computer program stored in the memory to realize the multilayer method for accelerating circuit simulation.

[0014] To achieve the above object, the application further provides a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to realize the multilayer method for accelerating circuit simulation.

[0015] The multilayer method for accelerating circuit simulation provided by the application establishes a linear equation set based on a multilayer circuit structure and solves the linear equation set by using a multilayer method, which effectively reduces the time and space complexity of solving the linear equation set, so that a larger scale circuit can be processed under limited hardware resources in chip-level circuit simulation, and the simulation process is significantly accelerated.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description, or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings: Figure 1 Flow chart of multi-level class solving method for accelerating circuit simulation according to embodiments of the present application; Figure 2 Hierarchical structure diagram of circuit partition according to embodiments of the present application; Figure 3 Process diagram of multi-level class solving method according to embodiments of the present application; Figure 4 Structure diagram of electronic device according to embodiments of the present application. DETAILED DESCRIPTION

[0018] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are merely intended to illustrate and explain the present application, and should not be used to limit the scope of the present application.

[0019] Embodiments of the present application will be described in more detail by referring to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments described herein, but rather, these embodiments are provided to make the present application more thorough and complete. It should be understood that the drawings and embodiments of the present application are merely for illustrative purposes, and should not be used to limit the scope of the present application.

[0020] The term "comprising" and variations thereof as used in the present application are open-ended, and mean "including but not limited to". The term "based on" means "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related terms are defined as follows.

[0021] It should be noted that the terms "first", "second", etc. mentioned in the present application are merely used to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0022] It should be noted that the modification of "one", "a plurality of" mentioned in the present application is illustrative but not restrictive, and those skilled in the art should understand that "one or more" should be understood unless otherwise explicitly indicated in the context. "A plurality" should be understood as two or more.

[0023] In the present application, some key terms are explained for the convenience of understanding: Circuit function module: refers to a sub-unit in an integrated circuit with a specific electrical function, which can be independently analyzed and modeled (for example: operational amplifier, filter, phase-locked loop, logic gate circuit, etc.). These modules are the basic units of circuit division.

[0024] Delay (Latency) attribute: refers to the characteristic that the response of the output of the circuit function module to the change of the input in the transient simulation has a period of silence or changes very slowly. In the present application, the module in this period is marked as "inactive", and its internal state can be considered as approximately invariant; otherwise, it is "active".

[0025] Multi-layer class method: a numerical solution technique inspired by the multi-layer grid method used in the present application. The core idea is to build a series of layers from fine (fine) to coarse (coarse), smooth high-frequency errors on fine layers, and correct low-frequency errors on coarse layers, so as to accelerate the overall convergence. In the present application, "layer" corresponds to a circuit network of different scales.

[0026] Pre-smoothing and post-smoothing: refers to several simple iterative solutions (such as Jacobi iteration) performed on the current layer before the residual is passed to the coarse layer and after the correction is received from the coarse layer, aiming to preliminarily eliminate errors.

[0027] Restriction mapping and prolongation mapping: restriction mapping is an operator that aggregates residual information of fine layer network to coarse layer network; prolongation mapping is an operator that interpolates the solution of coarse layer network back to fine layer network. They together constitute the bridge of information transmission between layers.

[0028] Aggregation: in the present application, aggregation is a structural coarsening operation based on circuit topology, which generates an equivalent coarse layer circuit model by merging fine layer units to achieve problem scale reduction.

[0029] Embodiment 1 Figure 1 The flowchart of the multi-layer class solution method for accelerating circuit simulation according to Embodiment 1 of the present application is as follows: Figure 1 The multi-layer class solution method for accelerating circuit simulation of the present application is described in detail.

[0030] First, in step 101: the circuit is recursively divided into multiple levels of sub-circuits, forming a hierarchical structure from fine to coarse. In the embodiments of this application, the original circuit to be simulated (i.e., the finest layer) is recursively divided into several sub-circuits according to its physical connections and the boundaries of functional modules. For example, a large analog circuit can be divided into PLL modules, ADC modules, power management modules, etc., where each functional module is regarded as a basic sub-circuit. When constructing the coarse layer, they are regarded as new nodes, and their internal connections are aggregated to form a smaller and more abstract coarse-layer circuit. This process is recursively performed until a preset recursion termination condition is met. For example, multiple functional sub-circuits such as power management modules (where each module itself is a sub-circuit) are aggregated with other types of sub-circuits (such as PLL modules and ADC modules) to form a coarser circuit layer, until the scale of the coarsest layer circuit is small enough that even if a direct method (such as LU decomposition) is used to solve it, its computational load is comparable to one iteration of the fine layer, and it no longer constitutes a computational bottleneck.

[0031] The recursion termination condition can be preset by the user, for example, the number of nodes in the coarsest layer is less than or equal to a preset threshold N (e.g., N=50), or the order of the coarsest layer circuit matrix is ​​lower than a certain threshold.

[0032] like Figure 2 As shown, from top to bottom, they represent the original circuit, the coarse-layer circuit, and the coarsest layer circuit, respectively. The middle coarse (or fine) layers are relative: they are coarse relative to the upper layers and fine relative to the lower layers. There can even be several coarse layers (determined by the actual coarsening method and the size of the coarsest layer circuit).

[0033] Step 102: Simplify the sub-circuits of each level based on circuit delay attributes and construct the mapping relationship between each level. In the embodiments of this application, during or after the division in step 101, the sub-circuits of each level are dynamically labeled according to the delay attributes of their respective circuit functional modules to distinguish between active and inactive parts. For inactive parts (such as bias circuits in a stable holding state, digital modules that do not flip within a specific time period), the circuit model is simplified at its current level, for example, it is equivalent to a constant voltage source, a constant current source, or a simple impedance. When constructing a coarser layer of circuit, only the active parts of the current layer are aggregated to the coarser layer. Inactive parts, because their dynamic changes are slow, their effects are already included in the simplified model, so they are not propagated upwards, but they still remain at their original level to participate in the smoothing calculation of that layer.

[0034] Simultaneously, a mapping relationship between adjacent layers is constructed based on the relationships between layers. This step includes: defining a constraint mapping operator from fine layers to coarse layers (for propagating residuals), and an extension mapping operator from coarse layers to fine layers (for propagating solution vectors).

[0035] In the embodiments of the present application, the mapping relationship between adjacent levels is established, mainly the corresponding relationship between circuit nodes of adjacent levels, which specifically includes: On the one hand, a restriction mapping relationship is established: defining which circuit node(s) on the fine layer is represented or aggregated by a single circuit node on the coarse layer. This determines the aggregation path of the residual information when it is transmitted from the fine layer to the coarse layer.

[0036] On the other hand, a continuation mapping relationship is established: defining which circuit node(s) on the fine layer corresponds to a single circuit node on the coarse layer. This determines the correction path of the solution vector when it is transmitted from the coarse layer to the fine layer.

[0037] Based on the restriction mapping relationship and the continuation mapping relationship, and combined with the connection characteristics (such as admittance, current weight or geometric correlation degree) between circuit nodes, the restriction mapping operator and the continuation mapping operator can be defined numerically. The restriction mapping operator is a matrix, the element value of which is determined according to the restriction mapping relationship and the weight between nodes, and its function is to aggregate the residual vectors of the fine layer by weighting to generate the right-hand side vector of the coarse layer. The continuation mapping operator is also a matrix, the element value of which is determined according to the continuation mapping relationship and the weight between nodes, and its function is to correct (or distribute) the solution vector of the coarse layer to the fine layer, for correcting the solution of the fine layer.

[0038] In step 103: based on the hierarchical structure and the mapping relationship, assemble the linear equation set to be solved. In the embodiments of the present application, based on the multi-level circuit structure constructed in step 101 and the mapping relationship established in step 102, the corresponding linear equation set of each layer is assembled. Let the layer number be , where represents the finest layer (original circuit), represents the coarsest layer. Then the linear equation set of each layer can be expressed as: ; In the formula, is the admittance matrix of the th layer, is the node voltage vector to be solved of the th layer, is the right-hand side of the equation of the th layer.

[0039] In step 104: solve the linear equation set by using the multi-layer method.

[0040] This step is the core solving process, which is executed in an iterative manner, and a single cycle process includes: Pre-smoothing stage: In each layer except the coarsest layer, an iterative method with low computational cost (such as Jacobi iteration or Gauss-Seidel iteration) is used to approximate the solution, and the residuals are passed to the next coarser layer through a mapping relationship; Coarse mesh solution stage: At the coarsest layer with the smallest scale, a high-precision direct method (such as LU decomposition) is used to solve accurately; Fine-mesh extension and post-smoothing stage: The solution of the coarsest layer is interpolated back to the previous fine-mesh layer through a mapping relationship, and then smoothed again using an iterative method in that fine-mesh layer to eliminate errors. This process is carried out layer by layer until the finest layer (original circuit layer) is returned.

[0041] The following example uses a multi-level solution method with a three-layer mesh (H = 3) to illustrate the single-loop process. (Reference) Figure 3 From the finest layer ( Starting from the coarsest layer () The layer preceding ) performs the following steps: (1) Pre-smoothing and residual propagation (downward phase): First, perform pre-smoothing: for the equations of the current layer Execute n times (usually) The iterative smoothing (e.g., using the Gauss-Seidel iterative method) yields the updated solution vector. (This represents an intermediate solution that has been smoothed but has not yet undergone coarse layer correction).

[0042] Calculate the residuals: The residual vector of the current layer is equal to .

[0043] Constraint transitivity: Passing the residuals through the constraint mapping operator (express The residual constraint of the layer is passed on to The layer is passed to the next coarser layer. ), as the new right-hand term of this coarse layer: .

[0044] This process is repeated recursively until the coarsest layer is reached. The right-hand item was constructed. .

[0045] (2) Accurate solution for coarse layers: In the coarsest layer ( Since the circuit size is already small enough, the direct method is used to solve the equations with high accuracy. The solution vector on the coarse layer is obtained. .

[0046] (3) Result continuation and post-smoothing (ascending stage): From the coarsest layer ( ) Start, return to the fine layer, and perform the following steps: Extension correction: the solution vector of the coarse layer is mapped by the extension mapping operator to the current fine layer, and the solution vector of the fine layer is updated as: ; where is the solution vector of the current layer, is the solution vector of the previous coarse layer, and is the solution correction of the coarse layer to the current layer.

[0047] Post-smoothing: on the current layer, the updated solution vector is further smoothed n times to obtain a smoother solution.

[0048] This process is recursively performed until the solution of the finest layer is returned ( ) and updated.

[0049] In step 105: iteratively repeat step 104 until convergence.

[0050] After completing a single cycle of step 104, the residual norm of the linear system of the finest layer ( ) is calculated = . If ( is the preset convergence accuracy), the current solution is output, and the simulation is completed. Otherwise, return to step 104, and use the solution of the current finest layer as the initial solution to iteratively repeat the entire multilevel-like method solving process until convergence.

[0051] In some preferred embodiments, the multilevel-like method (step 104) described above can be embedded as a preconditioner in the framework of the generalized minimal residual method (PGMRES), i.e., the entire linear system is solved using the preconditioned generalized minimal residual method (PGMRES), and the preconditioning equation is solved using the multilevel-like method. In this mode, the preconditioning operation required in each step of the PGMRES iteration is approximated by executing one cycle of the multilevel-like method with an intermediate vector as the right-hand side. At this time, the multilevel-like method does not directly solve the original equation, but serves as an efficient inner loop accelerator for the PGMRES iteration. When judging convergence, the output of the multilevel-like method processing step is returned to the PGMRES outer iteration, and the PGMRES uses the preconditioned vector to update the solution and judge whether the overall residual satisfies the convergence accuracy. If not, the entire process is repeated until convergence.

[0052] The multi-layer class solving method for accelerating circuit simulation has the following beneficial effects: First, the simulation efficiency is significantly improved: through the multi-layer class method, most of the calculation amount is distributed on the coarse layer circuit with small scale, and the efficient direct method is used for solving in the coarsest layer, thereby avoiding direct solving on the whole large-scale original circuit, and the solving time of linear equations is greatly reduced.

[0053] Second, the memory consumption is effectively reduced: based on the circuit delay attribute, the inactive part is simplified and locally processed, and the layered structure is utilized, so that the matrix scale to be stored and calculated in each layer is far less than the original circuit matrix, and the demand for computer memory resources is greatly reduced.

[0054] Third, the convergence and robustness of the algorithm are enhanced: the multi-layer class method has inherent multi-resolution characteristics, and can effectively solve the convergence problem caused by multiple time constants and ill-conditioned matrices. When combined with advanced iterative methods such as PGMRES as a preconditioner, the convergence can be further accelerated and the numerical stability can be improved.

[0055] Fourth, the adaptive balance of computing resources is realized: the termination condition of recursive division and the construction strategy of mapping relationship can be dynamically adjusted according to the computing resources, so as to realize the optimal balance between calculation amount and accuracy under the fixed hardware condition, thereby maximizing the size of the circuit that can be simulated.

[0056] Fifth, the simulation accuracy is maintained: through the pre-smoothing and post-smoothing iteration correction in the fine layer and the accurate solving in the coarsest layer, the accuracy of the final solution is ensured, so that the necessary simulation accuracy is not sacrificed while the efficiency is improved.

[0057] In the embodiments of the present application, an electronic device is also provided, Figure 4 The schematic structural diagram of the electronic device according to the embodiments of the present application is shown in Figure 4As shown, the electronic device of the present application comprises a processor 201 and a memory 202, wherein the memory 202 stores a computer program, and the computer program, when read and executed by the processor 201, performs the steps in the multi-layer class solving method embodiment for accelerating circuit simulation as described above. Embodiment 3 In the embodiments of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, wherein the computer program is configured to perform the steps in the multi-layer class solving method embodiment for accelerating circuit simulation as described above when running. In the present embodiment, the computer readable storage medium described above can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0058] Those skilled in the art can understand that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments or make equivalent replacements to some technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-layered class solving method for accelerating circuit simulation, characterized by, The method comprises the following steps: recursively dividing the circuit into multiple hierarchical sub-circuits to form a hierarchical structure from fine to coarse; based on the circuit delay attribute, marking and simplifying the inactive part in each hierarchical sub-circuit, and constructing the mapping relationship between the hierarchies; based on the hierarchical structure and the mapping relationship, assembling the linear equation set to be solved; solving the linear equation set by using a multilevel method, which comprises: performing pre-iteration smoothing in the fine layer, transmitting the residual to the coarse layer, solving the coarsest layer by using a direct method, and then extrapolating the solution back to the fine layer and performing post-iteration smoothing; iteratively repeating the step of solving the linear equation set by using the multilevel method until the linear equation set converges.

2. The multi-layered class solving method of accelerating circuit simulation according to claim 1, wherein, The step of recursively dividing the circuit into multiple hierarchical sub-circuits to form a hierarchical structure from fine to coarse further comprises: The termination condition of the recursive division depends on the size of the coarsest layer sub-circuit, and the division is stopped when the computation amount of solving the coarsest layer sub-circuit is lower than a preset threshold.

3. The multi-layered class solving method of accelerating circuit simulation according to claim 1, wherein, The step of marking and simplifying the inactive part in each hierarchical sub-circuit based on the circuit delay attribute, and constructing the mapping relationship between the hierarchies further comprises: Based on the delay attribute of the circuit function module, the inactive part in each hierarchical sub-circuit is marked and simplified.

4. The multi-layered class solving method of accelerating circuit simulation according to claim 3, wherein, The simplification method is to aggregate only the active part of the current layer to the coarse layer when constructing a coarser layer sub-circuit, and the inactive part is retained in the current layer.

5. The method of claim 1, wherein, The mapping relationship comprises a restriction mapping for transmitting the residual from the fine layer to the coarse layer, and an extrapolation mapping for transmitting the solution vector from the coarse layer to the fine layer.

6. The method of claim 1, wherein, The step of solving the linear equation set by using a multilevel method further comprises: the pre-iteration smoothing and the post-iteration smoothing, and the iterative method used is the Jacobi iteration method or the Gauss-Seidel iteration method.

7. The method of claim 1, wherein, The multilevel method is directly used to solve the overall equation set, or is used as a preprocessing sub-step in the iteration framework of the generalized minimal residual method.

8. The method of claim 1, wherein, The direct method is the LU decomposition method or the Cholesky decomposition method.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is configured to execute the computer program stored in the memory to implement the multilevel method for accelerating circuit simulation according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the processor loads and executes the computer program to implement the multilevel method for accelerating circuit simulation according to any one of claims 1 to 8.

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