Circuit board layout method and system, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a layout method and system of a circuit board, electronic equipment and a storage medium. The layout method and system are used for improving the layout efficiency and the layout effect of the circuit board. The embodiment of the invention provides a layout method of a circuit board, and the method comprises the steps: carrying out the semantic understanding of the layout defect information of the circuit board through a large language model, so as to obtain a layout defect description result of the circuit board; calling a target detection tool according to the circuit board layout defect description result, and performing circuit board defect detection through the target detection tool to determine information of to-be-optimized electronic components on a target circuit board; generating a target optimization instruction according to the information of the to-be-optimized electronic component on the target circuit board; and performing layout optimization on the electronic components on the target circuit board according to the target optimization instruction to obtain the target circuit board after layout optimization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a circuit board layout method and system, electronic equipment and storage medium. BACKGROUND

[0002] When electronic components are laid out on a printed circuit board (PCB), there may be a PCB layout problem. For example, when designing an electronic device, multiple electronic components are arranged on a PCB, and the multiple electronic components are connected by wires.

[0003] Currently, in the layout scheme for the PCB, a software dedicated to PCB design is needed, which provides a design platform and practical tools, and then a PCB design user performs PCB layout on the software. Based on artificial experience, the PCB design user can complete the layout of electronic components on the PCB after multiple attempts. This PCB layout scheme relies on artificial design, and has problems of low PCB layout efficiency and poor PCB layout effect. SUMMARY

[0004] The embodiments of the present application provide a circuit board layout method and system, electronic equipment and storage medium, which are used to improve the layout efficiency and effect of the circuit board.

[0005] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0006] In a first aspect, the embodiments of the present application provide a circuit board layout method, comprising:

[0007] performing semantic understanding on the circuit board layout defect information by a large language model to obtain a circuit board layout defect description result;

[0008] calling a target detection tool according to the circuit board layout defect description result, and performing circuit board defect detection by the target detection tool to determine information of an electronic component to be optimized on a target circuit board;

[0009] generating a target optimization instruction according to the information of the electronic component to be optimized on the target circuit board;

[0010] performing layout optimization on the electronic component on the target circuit board according to the target optimization instruction to obtain a target circuit board after layout optimization, and the electronic component on the target circuit board includes the electronic component to be optimized.

[0011] In the technical solution, first, the layout defect information of the circuit board is acquired, then semantic understanding is performed on the layout defect information of the circuit board by using a large language model to obtain a layout defect description result of the circuit board, a target detection tool is called according to the layout defect description result of the circuit board, and the target detection tool is used to detect defects of the circuit board to determine information of an electronic component to be optimized on a target circuit board. Next, a target optimization instruction is generated according to the information of the electronic component to be optimized on the target circuit board, and the electronic component on the target circuit board is optimized according to the target optimization instruction. In the embodiment, semantic understanding can be performed on the layout defect information of the circuit board by using the large language model, the target detection tool is called to detect defects of the circuit board, and after the information of the electronic component to be optimized is determined, the electronic component on the target circuit board is optimized according to the target optimization instruction. In the embodiment, the layout optimization of the electronic component on the target circuit board does not need to use artificial experience to optimize the layout of the circuit board, the layout efficiency of the circuit board is improved, the circuit structure of the circuit board is optimized, and therefore, the layout effect of the circuit board is improved.

[0012] With reference to the first aspect, in a possible implementation manner of the first aspect, the method further includes: acquiring historical circuit board layout optimization information and historical circuit board layout defect information corresponding to the historical circuit board layout optimization information.

[0013] The semantic understanding of the circuit board layout defect information by using the large language model includes: semantic understanding of the historical circuit board layout defect information by using the large language model.

[0014] In the technical solution, the layout system of the circuit board can store the historical circuit board layout optimization information and the historical circuit board layout defect information, thereby providing input information for subsequent layout optimization of a target circuit board, improving the layout efficiency of the circuit board, optimizing the circuit structure of the circuit board, and improving the layout effect of the circuit board.

[0015] With reference to the first aspect, in a possible implementation manner of the first aspect, the layout optimization of the electronic component on the target circuit board according to the target optimization instruction includes:

[0016] The layout optimization of the electronic component on the target circuit board according to the historical circuit board layout optimization information and the target optimization instruction.

[0017] In the technical solution, the layout system of the circuit board can detect defects of the circuit board and generate target optimization instructions through the target detection tool. The layout system of the circuit board can optimize the layout of the electronic components on the target circuit according to the target optimization instructions and the historical circuit board layout optimization information, and output the target circuit board after layout optimization. Since the historical circuit board layout optimization information and the target optimization instructions are used together to optimize the layout of the electronic components on the target circuit board, the layout efficiency of the circuit board can be improved, and the circuit structure of the circuit board can be optimized, thereby improving the layout effect of the circuit board.

[0018] In combination with the first aspect, in a possible implementation manner of the first aspect, the layout optimization of the electronic components on the target circuit board according to the historical circuit board layout optimization information and the target optimization instructions comprises:

[0019] The historical circuit board layout optimization information and the target optimization instructions are input into a circuit board layout engine, and the circuit board layout engine is used to infer the layout optimization of the electronic components on the target circuit board based on the historical circuit board layout optimization information and the target optimization instructions.

[0020] In the technical solution, the circuit board layout engine can be pre-set in the layout system of the circuit board. The circuit board layout engine is used to optimize the layout of the electronic components on the target circuit board according to the target optimization instructions and with the historical circuit board layout optimization information as a reference, so as to adjust the layout of the electronic components on the target circuit board. Since the historical circuit board layout optimization information can provide important reference value for the layout optimization of the target circuit board, the layout efficiency of the circuit board can be improved, and the circuit structure of the circuit board can be optimized, thereby improving the layout effect of the circuit board.

[0021] In combination with the first aspect, in a possible implementation manner of the first aspect, the method further comprises:

[0022] At least one of the following information is stored: the historical circuit board layout optimization information, the circuit board layout defect information, and the target circuit board after layout optimization.

[0023] In the technical solution, the memory module can be set in the layout system of the circuit board. At least one of the historical circuit board layout optimization information, the circuit board layout defect information, and the target circuit board after layout optimization is stored in the memory module, and is used for layout optimization of the next target circuit board. The layout system of the circuit board can read the information stored in the memory module to provide input information for layout optimization of the next target circuit board, improve the layout efficiency of the circuit board, and optimize the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0024] In a possible implementation of the first aspect, the historical circuit board layout optimization information comprises at least one of: historical circuit board layout results, and circuit board layout result constraint information.

[0025] In the above technical solution, the historical circuit board layout optimization information can be obtained by a layout system of the circuit board optimizing the layout results of previous electronic components, and the historical circuit board layout results comprise results obtained after optimizing the layout of the electronic components in one or more previous rounds. The circuit board layout result constraint information refers to the design constraint conditions of the circuit board in one or more previous rounds, and the corresponding design constraint conditions of the circuit board need to be met when optimizing the layout of the electronic components on the target circuit board.

[0026] In a possible implementation of the first aspect, the historical circuit board layout results comprise: names of the electronic components on the target circuit board and corresponding placement positions, connection relationships between the electronic components on the target circuit board, and placement ranges of the electronic components on the target circuit board in corresponding frames.

[0027] In the above technical solution, the historical circuit board layout results can comprise results obtained after optimizing the layout of the electronic components on the target circuit board, for example, the layout of the names of the electronic components on the target circuit board and the corresponding placement positions, the connection relationships between the electronic components on the target circuit board, and the placement ranges of the electronic components on the target circuit board in corresponding frames. The above three kinds of layout results included in the historical circuit board layout results can provide input information for the layout optimization of the current target circuit board, improve the layout efficiency of the circuit board, and optimize the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0028] In a possible implementation of the first aspect, the circuit board layout result constraint information comprises: matching results of the historical circuit board layout results and hard constraint conditions, and matching results of the historical circuit board layout results and soft constraint conditions.

[0029] The hard constraint conditions comprise hard constraint indexes that need to be met when the electronic components are laid out on the target circuit board.

[0030] The soft constraint conditions comprise soft constraint indexes that are selectively met when the electronic components are laid out on the target circuit board, and when there are multiple soft constraint indexes, there will be a layout conflict of the electronic components on the target circuit board.

[0031] In the technical solution, the matching results of the hard constraint condition and the soft constraint condition included in the layout result constraint condition information can provide input information for the layout optimization of the target circuit board, improve the layout efficiency of the circuit board, optimize the circuit structure of the circuit board, and thus improve the layout effect of the circuit board.

[0032] With reference to the first aspect, in a possible implementation manner of the first aspect, the circuit board layout defect information includes at least one of the following: a layout defect corresponding to a placement position of an electronic component on the target circuit board, and description information of the layout defect.

[0033] In the technical solution, the circuit board layout defect information can refer to a layout defect corresponding to a placement position of an electronic component on the target circuit board, for example, a layout defect caused by improper placement of the electronic component. The circuit board layout defect information can further include description information of the layout defect. The description information of the layout defect can specifically describe the cause of the layout defect, the defect degree, or a solution corresponding to the defect.

[0034] With reference to the first aspect, in a possible implementation manner of the first aspect, the method further includes:

[0035] generating a detection tool calling record after the target detection tool is called according to the circuit board layout defect description result;

[0036] storing the detection tool calling record.

[0037] In the technical solution, the layout system of the circuit board can call a target detection tool matched with the circuit board layout defect description result according to the circuit board layout defect description result. Then, the detection tool calling record is generated according to the calling of the target detection tool. The detection tool calling record can record the calling of the target detection tool. The layout system of the circuit board stores the detection tool calling record, provides input information for the layout optimization of the target circuit board in the next time, improves the layout efficiency of the circuit board, optimizes the circuit structure of the circuit board, and thus improves the layout effect of the circuit board.

[0038] With reference to the first aspect, in a possible implementation manner of the first aspect, the target optimization instruction is generated according to the information of the electronic component to be optimized on the target circuit board, and includes:

[0039] The target optimization instruction is generated according to the information of the electronic component to be optimized on the target circuit board and the detection tool calling record.

[0040] In the technical solution, the layout system of the circuit board determines the information of the electronic component to be optimized on the target circuit board through the target detection tool. In order to perform layout optimization on the information of the electronic component to be optimized, a target optimization instruction can be generated according to the information of the electronic component to be optimized on the target circuit board and the detection tool calling record. Since the detection tool calling record can record the calling of the target detection tool, the target optimization instruction generated based on the information of the electronic component to be optimized and the detection tool calling record can indicate the called target detection tool, which facilitates subsequent layout optimization and further improves the layout effect of the circuit board.

[0041] With reference to the first aspect, in a possible implementation manner of the first aspect, the target detection tool is called according to the circuit board layout defect description result, and the circuit board defect detection is performed through the target detection tool to determine the information of the electronic component to be optimized on the target circuit board, including:

[0042] The tool calling instruction is obtained according to the circuit board layout defect description result, and the target detection tool is called from a detection tool library according to the tool calling instruction;

[0043] The circuit board defect detection is performed on the circuit board layout defect description result through the target detection tool;

[0044] The information of the electronic component to be optimized on the target circuit board is obtained from the target detection tool.

[0045] In the above solution, the layout system of the circuit board can generate a tool calling instruction according to the circuit board layout defect description result, retrieve a detection tool library according to the tool calling instruction, obtain a target detection tool matched with the circuit board layout defect description result from the detection tool library, and indicate the calling mode of the target detection tool in the detection tool library through the tool calling instruction. The layout system of the circuit board calls the target detection tool according to the tool calling instruction, performs the circuit board defect detection on the circuit board layout defect description result through the target detection tool, and thus obtains a target optimization instruction.

[0046] In the second aspect, the embodiments of the present application further provide a layout system of a circuit board, including a semantic understanding module, a tool calling module, an instruction generating module and a layout optimization module, wherein the semantic understanding module is connected to the tool calling module, and the tool calling module is connected to the layout optimization module.

[0047] The semantic understanding module is configured to perform semantic understanding on circuit board layout defect information through a large language model to obtain a circuit board layout defect description result.

[0048] The tool calling module is configured to call a target detection tool according to the circuit board layout defect description result, and perform circuit board defect detection by using the target detection tool to determine information of electronic components to be optimized on the target circuit board.

[0049] The instruction generation module is configured to generate a target optimization instruction according to the information of the electronic components to be optimized on the target circuit board.

[0050] The layout optimization module is configured to perform layout optimization on the electronic components on the target circuit board according to the target optimization instruction to obtain a target circuit board after layout optimization, and the electronic components on the target circuit board include the electronic components to be optimized.

[0051] In the above technical solution, first, the circuit board layout defect information is obtained, then semantic understanding is performed by using a large language model to obtain a circuit board layout defect description result, a target detection tool is called according to the circuit board layout defect description result, and circuit board defect detection is performed by using the target detection tool to determine information of electronic components to be optimized on a target circuit board, next, a target optimization instruction is generated according to the information of the electronic components to be optimized on the target circuit board, and layout optimization is performed on the electronic components on the target circuit board according to the target optimization instruction. In the embodiment of the application, semantic understanding can be performed by using a large language model, a target detection tool is called to perform circuit board defect detection, after the information of the electronic components to be optimized is determined, layout optimization is performed on the electronic component information on the target circuit board according to the target optimization instruction. In the embodiment of the application, layout optimization is not required for the electronic components on the target circuit board, which uses artificial experience to perform layout optimization on the circuit board, improves the layout efficiency of the circuit board, and optimizes the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0052] In combination with the second aspect, in a possible implementation manner of the second aspect, the system includes a state acquisition module,

[0053] The state acquisition module is configured to acquire historical circuit board layout optimization information and historical circuit board layout defect information corresponding to the historical circuit board layout optimization information.

[0054] The semantic understanding module is specifically configured to perform semantic understanding on the historical circuit board layout defect information by using a large language model.

[0055] In combination with the second aspect, in a possible implementation manner of the second aspect, the layout optimization module is specifically configured to perform layout optimization on the electronic components on the target circuit board according to the historical circuit board layout optimization information and the target optimization instruction.

[0056] With reference to the second aspect, in a possible implementation of the second aspect, the layout optimization module comprises a circuit board layout engine,

[0057] The instruction generation module is further configured to input the historical circuit board layout optimization information and the target optimization instruction into the circuit board layout engine.

[0058] The circuit board layout engine is configured to perform inference on the layout optimization of the electronic components on the target circuit board based on the historical circuit board layout optimization information.

[0059] With reference to the second aspect, in a possible implementation of the second aspect, the system further comprises a memory module,

[0060] The memory module is configured to store at least one of the following information: the historical circuit board layout optimization information, the circuit board layout defect information, and the target circuit board after layout optimization.

[0061] With reference to the second aspect, in a possible implementation of the second aspect, the historical circuit board layout optimization information comprises at least one of the following: historical circuit board layout results, circuit board layout result constraint condition information.

[0062] With reference to the second aspect, in a possible implementation of the second aspect, the historical circuit board layout results comprise at least one of the following: names of electronic components on the target circuit board and corresponding placement positions, connection relationships between electronic components on the target circuit board, and placement ranges of electronic components in corresponding frames on the target circuit board.

[0063] With reference to the second aspect, in a possible implementation of the second aspect, the circuit board layout result constraint condition information comprises at least one of the following: matching results of the historical circuit board layout results and hard constraint conditions, and matching results of the historical circuit board layout results and soft constraint conditions.

[0064] The hard constraint condition comprises a hard constraint index that needs to be met when the electronic components are laid out on the target circuit board.

[0065] The soft constraint condition comprises a soft constraint index that is selectively met when the electronic components are laid out on the target circuit board, and when there are multiple soft constraint indexes, there will be a layout conflict of the electronic components on the target circuit board.

[0066] With reference to the second aspect, in a possible implementation of the second aspect, the circuit board layout defect information comprises at least one of the following: a layout defect corresponding to a placement position of an electronic component on the target circuit board, and description information of the layout defect.

[0067] With reference to the second aspect, in a possible implementation manner of the second aspect, the system further includes a memory module, and the memory module is configured to store the detection tool calling record.

[0068] The tool calling module is configured to, after calling the target detection tool according to the circuit board layout defect description result, generate a detection tool calling record.

[0069] The memory module is configured to store the detection tool calling record.

[0070] With reference to the second aspect, in a possible implementation manner of the second aspect, the instruction generation module is specifically configured to generate the target optimization instruction according to information of an electronic component to be optimized on the target circuit board and the detection tool calling record.

[0071] With reference to the second aspect, in a possible implementation manner of the second aspect, the tool calling module is specifically configured to acquire a tool calling instruction according to the circuit board layout defect description result, and call the target detection tool from a detection tool library according to the tool calling instruction.

[0072] Perform circuit board defect detection on the circuit board layout defect description result by using the target detection tool.

[0073] Acquire information of an electronic component to be optimized on the target circuit board from the target detection tool.

[0074] With reference to the second aspect, in a possible implementation manner of the second aspect, the system further includes the detection tool library.

[0075] The detection tool library includes a plurality of detection tools, and the plurality of detection tools include the target detection tool.

[0076] The plurality of detection tools are configured to detect and locate a plurality of circuit board layout defects.

[0077] In the second aspect of the present application, the component module of the circuit board layout system can also perform the steps described in the foregoing first aspect and various possible implementation manners, and details are described in the foregoing description of the first aspect and various possible implementation manners.

[0078] In a third aspect, a computer readable storage medium is provided, and the computer readable storage medium stores instructions. When the instructions are run on a computer, the computer performs the method in the first aspect.

[0079] In a fourth aspect, a computer program product is provided, and the computer program product includes instructions. When the instructions are run on a computer, the computer performs the method in the first aspect.

[0080] In a fifth aspect, an electronic device is provided. The electronic device can include a terminal device or a chip, and the electronic device includes a processor and a memory. The memory is configured to store instructions. The processor is configured to execute the instructions in the memory, so that the electronic device performs the method in any one of the first aspect or any possible implementation of the first aspect.

[0081] In a sixth aspect, a chip system is provided. The chip system includes a processor, which is configured to support the electronic device to implement the functions in the above aspects, for example, to send or process the data and / or information in the above method. In a possible design, the chip system further includes a memory. The memory is configured to store necessary program instructions and data of the electronic device. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0082] In a seventh aspect, a chip is provided. The chip includes one or more interface circuits and one or more processors. The interface circuit is configured to receive a signal from a memory of an electronic device and send a signal to the processor. The signal includes computer instructions stored in the memory. When the processor executes the computer instructions, the electronic device performs the layout method of the circuit board in the first aspect or any possible implementation of the first aspect.

[0083] The seventh aspect and any possible implementation of the seventh aspect correspond to the first aspect and any possible implementation of the first aspect, respectively. For details, refer to the technical effects of the first aspect and any possible implementation of the first aspect, which are not described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0084] Figure 1 FIG. 1 is a schematic diagram of an architecture of a data center according to an embodiment of the present application;

[0085] Figure 2a FIG. 2 is a schematic diagram of an exemplary system according to an embodiment of the present application;

[0086] Figure 2b FIG. 3 is another schematic diagram of an exemplary system according to an embodiment of the present application;

[0087] Figure 3 FIG. 4 is a schematic diagram of an embodiment of a layout method of a circuit board according to an embodiment of the present application;

[0088] Figure 4 FIG. 5 is a schematic diagram of an application framework of a layout system of a circuit board according to an embodiment of the present application;

[0089] Figure 5 FIG. 6 is a schematic diagram of a composition structure of a state acquisition module according to an embodiment of the present application;

[0090] Figure 6 is a component structure schematic diagram of a semantic understanding module provided by an embodiment of the present application;

[0091] Figure 7 is a component structure schematic diagram of a tool calling module provided by an embodiment of the present application;

[0092] Figure 8 is a component structure schematic diagram of an instruction generation module and a detection tool library provided by an embodiment of the present application;

[0093] Figure 9a is a schematic diagram of a state token provided by an embodiment of the present application;

[0094] Figure 9b is a schematic diagram of a state token provided by an embodiment of the present application;

[0095] Figure 9c is a schematic diagram of a state token provided by an embodiment of the present application;

[0096] Figure 10 is a module architecture schematic diagram of a circuit board layout engine provided by an embodiment of the present application;

[0097] Figure 11 is an embodiment schematic diagram of a circuit board layout system provided by an embodiment of the present application;

[0098] Figure 12 is a structure schematic diagram of a computing device provided by an embodiment of the present application;

[0099] Figure 13 is a structure schematic diagram of a computing device cluster provided by an embodiment of the present application;

[0100] Figure 14 is a structure schematic diagram of a computing device cluster provided by an embodiment of the present application. DETAILED DESCRIPTION

[0101] The present application provides a circuit board layout method, system, electronic device and storage medium, which can improve the layout efficiency and effect of the circuit board.

[0102] The embodiments of the present application are described below in conjunction with the accompanying drawings. The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0103] Those skilled in the art can know that, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0104] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not expressly listed or inherent to those processes, methods, products, or apparatus.

[0105] PCB layout issues involve complex scenarios, such as System-on-Chip (SoC), radio frequency (RF), and power supply, requiring a high degree of generalization in PCB design solutions. PCB layout involves multiple requirements, including electronic component placement, signal integrity, power and ground design, thermal design, and electromagnetic compatibility (EMC) design. These requirements are often interrelated and mutually restrictive, necessitating the finding of a suitable balance in PCB design. For example, changing the electronic component layout may affect signal transmission paths, thus impacting signal integrity. For electronic products that need to process RF signals, such as communication equipment and radar systems, RF circuit design has special requirements, such as considering RF signal transmission paths, impedance matching, and signal coupling in PCB layout.

[0106] Due to the complexity of PCB layout issues, PCB designers need extensive experience and deep expertise to effectively solve various design challenges. Furthermore, solving PCB layout problems requires highly versatile PCB design solutions that can adapt to different types of electronic products and diverse design scenarios to provide accurate and reliable solutions.

[0107] In addition, current PCB layout problems involve numerous design constraints, and some design rules are difficult to quantify. Examples are as follows:

[0108] For example, there is a problem that process spacing is difficult to determine: various process requirements need to be considered in PCB manufacturing, such as the spacing between pads and vias, line width and line spacing, and the spacing between electronic components. These process spacings are to ensure the reliability of PCB production, prevent soldering problems, and improve manufacturing efficiency.

[0109] For example, there is the challenge of designing structural avoidance: PCB layout needs to avoid collisions or interference between different structures, such as between electronic components, between electronic components and frames, and between vias and traces. These structural avoidance requirements ensure the structural integrity and assembly reliability of the PCB.

[0110] For example, there is the challenge of multi-objective optimization: PCB design often requires considering multiple objectives simultaneously, such as minimizing board size, optimizing signal transmission paths, and maximizing component placement density. These objectives may lead to placement conflicts of electronic components on the target circuit board, necessitating multi-objective optimization to find a balance. Some PCB design rules are difficult to quantify with specific values, such as routing ability. Routing ability refers to the ease of finding routing paths in the PCB layout and whether there are any local routing difficulties.

[0111] The PCB design rules exemplified above often require PCB designers to rely on experience and intuition for judgment, resulting in low PCB layout efficiency and poor layout quality. Furthermore, there are also issues with unreasonable PCB circuit structures, leading to high production costs and long production cycles.

[0112] This application provides a circuit board layout method that can be applied to a computing device cluster, which may include one or more computing devices.

[0113] The type of computing device is not limited here. For example, any computing device can be a terminal device, a cloud server, a container, or a virtual machine, etc.

[0114] The computing device cluster can provide a data processing platform to implement the circuit board layout method of the embodiments of this application. Specifically, a data processing platform can be provided in the terminal device and in the cloud server. Based on the respective data processing platforms of the terminal device or the cloud server, consistency and computing accuracy between the terminal side and the cloud side can be achieved, while also making full use of the differences in computing power between different devices. The specific form of the computing device cluster and the corresponding data processing platform is not limited here.

[0115] In one example, the cluster of computing devices can be used to implement a cloud management platform; in other words, the data processing platform of this application embodiment can be implemented through a cloud management platform.

[0116] A cloud management platform is used to manage the infrastructure that provides cloud services. It can provide computing, networking, and storage capabilities based on hardware and software resources. For example, a cloud management platform may include one or more data centers to provide cloud resources through one or more data centers.

[0117] The following is combined Figure 1 The diagram shown illustrates an architecture for a data center.

[0118] Figure 1 In this data center, the cloud management platform communicates with one or more servers (such as...) via the data center's internal network. Figure 1 Servers 1 and 2 interact with each other. The server comprises a hardware layer and a software layer. The hardware layer includes the server's hardware configuration, such as peripheral component interconnect (PCI) devices (e.g., network cards, graphics processing units, GPUs, offloading cards, etc.) that can be plugged into peripheral component interconnect (PCI) or peripheral component interconnect express (PCIe) slots. The software layer includes the operating system installed and running on the server (the operating system relative to the virtual machine can be called the host operating system). The host operating system contains a virtual machine manager (also called a hypervisor), whose role is to implement computational virtualization, network virtualization, and storage virtualization of the virtual machine, and to manage the virtual machine. A virtual machine (virtual machine) refers to a complete computer system simulated by software, possessing full hardware system functionality, and running in a completely isolated environment. Figure 1 In the system architecture shown, a data center contains multiple servers, which can be used to run virtual machines. The specifications of the virtual machines can be the same or different. These virtual machines can also be called Elastic Compute Service (ECS), Elastic Instances, etc., and different cloud service providers may use different names.

[0119] In one example of the embodiments of this application, the cloud management platform can be a public cloud platform. In this case, cloud service providers such as individuals or software developers with cloud resource development capabilities can provide cloud services to users. Users obtain cloud services through the Internet, but do not own cloud computing resources.

[0120] Specifically, in Figure 1 In the example shown, the cloud management platform can provide an access interface (such as a user interface or application programming interface (API)). Users of the cloud management platform and cloud service providers can operate the client to remotely access the access interface to register a cloud account and password on the cloud management platform. After the cloud management platform successfully authenticates the cloud account and password, they can log in to the cloud management platform to create, manage, log in to and operate virtual machines in the cloud data center, thereby performing corresponding tasks through the cloud resources of the cloud management platform.

[0121] For example, such as Figure 2a In the example shown, the data processing platform that implements the circuit board layout method in the embodiments of this application can be provided to users in the form of cloud services.

[0122] When data processing tasks require cross-device storage of graph data, some enterprises, organizations, or individuals can purchase cloud services that include the data processing platform. They can then use the cloud resources of the cloud management platform to perform the relevant data processing tasks and obtain the processing results of the input data from the cloud management platform.

[0123] This data processing platform can be implemented based on cloud resources such as one or more cloud data centers in the cloud management platform.

[0124] This data processing platform can be provided to users as an independent cloud service, and it is also compatible with computing frameworks such as TensorFlow and PyTorch. In other words, it can be used as an operator in computing frameworks such as TensorFlow and PyTorch, providing functions such as preprocessing, computation, feature extraction and / or other data processing for real-time and offline data.

[0125] Of course, the cloud management platform can also be other types of cloud management platforms, and this application embodiment does not limit this.

[0126] In another example, such as Figure 2bAs shown, the data processing platform can be provided to the user in the form of a software product or a functional service within a software product. The software product can be deployed on the user's terminal device or the enterprise user's server cluster. The user can purchase a software license to obtain the right to use the software product and, within the license period, implement the circuit board layout method of the embodiments of this application through the software product.

[0127] The following section uses the layout of circuit boards as an example to illustrate the practical application of a data processing platform that implements the layout method of circuit boards.

[0128] In one exemplary application scenario, a user might want to transmit PCB layout defect information to a cloud server for storage, sharing, or further processing. The user uses computing frameworks such as TensorFlow and PyTorch to encode the PCB layout defect information using an AI model, and then sends the encoded bitstream via a transmission network between the mobile phone and the cloud server. This computing framework can be deployed on the client device or on the cloud server. After receiving the compressed PCB layout defect information, the cloud management platform utilizes cloud resources to process the information. For example, the cloud management platform might include a large language model, a detection tool library, and a PCB layout engine. The platform performs semantic understanding of the PCB layout defect information to obtain a defect description, uses a target detection tool to detect defects in the description, and derives optimization instructions based on the detected electronic components on the target PCB. Finally, the platform optimizes the layout of these electronic components based on these optimization instructions.

[0129] It is understood that the above example is only an exemplary introduction to one application scenario. The circuit board layout method of this application embodiment can be applied to multiple fields and is not limited here.

[0130] To address the current reliance on manual experience and limited experimentation for PCB design, this application provides a Large Language Model (LLM)-driven intelligent PCB layout method and corresponding system. For example, the layout method provided in this application trains on a comprehensive set of knowledge and learns from human experience to create a model. The layout method is based on logical reasoning, enabling decision-making across multiple conflicts under multi-objective optimization. Furthermore, the layout method is continuously evolving and improves, significantly enhancing layout efficiency and results compared to layout schemes relying on manual experience.

[0131] like Figure 3As shown, the circuit board layout system can interact with the terminal device, and the executed circuit board layout method may include steps 301-304.

[0132] 301. Terminal equipment sends information about circuit board layout defects.

[0133] The terminal device can be operated by the user who designed the circuit board, and it can acquire circuit board layout defect information. For example, the circuit board layout defect information can describe defects existing in the circuit board layout. For instance, the circuit board layout defect information may include at least one of the following: excessively large or small process spacing, inability to achieve structural avoidance, or circuit board size being too large. The method of implementing the circuit board layout defect information is not limited.

[0134] For example, circuit board designers can describe layout defects in their designs using text, voice, or diagrams. The terminal device can then acquire this information and send it to the circuit board's layout system. A communication connection can be established between the terminal device and the layout system, using methods such as... Figure 1 and Figure 2a , Figure 2b The system architecture.

[0135] In some embodiments of this application, the circuit board layout defect information includes at least one of the following: layout defects corresponding to the placement of electronic components on the target circuit board, and descriptive information of the layout defects.

[0136] The circuit board layout defect information can refer to the layout defects corresponding to the placement of electronic components on the target circuit board. For example, it can be a layout defect caused by improper placement of electronic components. The circuit board layout defect information can also include descriptive information of the layout defect, which can specifically describe the cause of the layout defect, the degree of the defect, or the corresponding solution.

[0137] In some embodiments of this application, the circuit board may be a printed circuit board (PCB) or other circuit boards, as long as it can carry electronic components and there is an electrical connection between the electronic components, it can be used as the circuit board in the embodiments of this application.

[0138] 302. The circuit board layout system uses a large language model to perform semantic understanding of circuit board layout defect information in order to obtain circuit board layout defect description results.

[0139] The circuit board layout system can pre-set a large language model, which can be trained based on comprehensive knowledge of circuit board design. The training data for the large language model can come from prior circuit board design cases and extensive human experience. This embodiment does not limit the training method of the large language model. The circuit board layout system has semantic understanding capabilities. In this embodiment, the large language model is used to perform semantic understanding of circuit layout defect information, thereby converting the user's natural language description of circuit board layout into circuit board layout defects that are easier for detection tools to recognize. After receiving circuit board layout defect information, the large language model can be used for semantic understanding to obtain a description of the circuit board layout defects. This circuit board layout defect information can be used to indicate defects in the circuit board layout. For example, circuit board layout defect information may include: excessively large or small process spacing, inability to achieve structural avoidance, or excessively large circuit board size.

[0140] For example, the layout system of a circuit board has a semantic understanding function. It understands the description of the layout defect information of the circuit board through a large language model and outputs the layout defect description result. The layout defect description result can include the encoded answer output by the large language model after semantic understanding.

[0141] For example, the layout system of a circuit board uses a large language model, which can specifically be a generative pre-trained converter. The architecture of such a large language model includes, but is not limited to, the following: GPT-4 / GPT3.5 large model, Llama 2b large model, Pangu large model, Mistral large model, etc. This application embodiment will not further describe each of the aforementioned large language models individually.

[0142] 303. The circuit board layout system calls the target detection tool based on the circuit board layout defect description results, and uses the target detection tool to detect circuit board defects in order to determine the information of electronic components to be optimized on the target circuit board.

[0143] In this embodiment, the circuit board layout system, through semantic understanding, can obtain a description of circuit board layout defects. This description can be identified by one or more detection tools. This embodiment can configure one or more detection tools to detect one or more circuit board layout defects to determine the information of electronic components to be optimized on the target circuit board. In this embodiment, the circuit board layout system calls a target detection tool that matches the circuit board layout defect description. This target detection tool can be one or more detection tools, and is not limited here. Using this detection tool, defects can be detected to determine the information of electronic components to be optimized.

[0144] Furthermore, in some embodiments of this application, the PCB layout system can be pre-configured with a detection tool library, also known as an "external tool library." This library can include various detection tools, each with different detection functions. Specifically, after obtaining a PCB layout defect description, the PCB layout system searches the detection tool library based on this description. It then retrieves a target detection tool from the library that matches the PCB layout defect description. This target detection tool can be one or more detection tools, without limitation. Using this detection tool, defects can be detected to determine information about electronic components to be optimized.

[0145] For example, the testing tools can include diagnostic and location tools that integrate various defects in the corresponding circuit board layout. Defects refer to those that fail to meet circuit board design requirements. The testing tools examine the connections and positional relationships between various electronic components and determine the compliance status of circuit board design constraints based on various indicators. This includes, but is not limited to: diagnosing insufficient surface traces in important modules surrounding the chip, and diagnosing fan-out surface traces of the chip. The testing tools can be implemented in various ways. For example, they can include testing tools for surface traces of devices other than chips, testing tools for fan-out surface traces of chips, testing tools for surface traces of important modules surrounding the chip, testing tools for flying wire crossings in inner layer traces within modules, testing tools for the adsorption and proximity placement of devices other than chips, and calibration tools for capacitor layouts within the same power supply.

[0146] In this embodiment of the application, a target inspection tool is used to detect defects in a circuit board. This tool can output information about electronic components on the target circuit board that need optimization. Specifically, this information may include: the name of the electronic component to be optimized, the corresponding defect description, and the optimization method for the electronic component. For example, when using a target inspection tool to detect defects in a circuit board, the output information about the electronic component to be optimized may include: the electronic component to be optimized is an electronic component other than a chip; the defect description is that the number of surface lines on the component other than the chip is insufficient; and the optimization method is to increase the number of surface lines on the component other than the chip.

[0147] 304. The circuit board layout system generates target optimization instructions based on the information of the electronic components to be optimized on the target circuit board.

[0148] In this embodiment of the application, the circuit board layout system uses a target detection tool to determine the information of the electronic components to be optimized on the target circuit board. In order to optimize the layout of the electronic components to be optimized, a target optimization instruction can be generated based on the information of the electronic components to be optimized on the target circuit board. The target optimization instruction can indicate the information of the electronic components to be optimized on the target circuit board. For example, the target optimization instruction can indicate the optimization method for the electronic components on the target circuit board.

[0149] For example, target inspection tools may include tools for inspecting surface lines of devices other than chips. Specifically, target optimization instructions may include increasing the number of surface lines of devices other than chips.

[0150] For example, target inspection tools may include tools for inspecting fan-out surface lines of a chip. Specifically, target optimization instructions may include increasing the number of fan-out surface lines of a chip.

[0151] For example, target detection tools may include tools for detecting surface lines of important modules around a chip. Specifically, target optimization instructions may include increasing the number of surface lines of important modules around a chip.

[0152] For example, target detection tools may include tools for detecting flying wire crossings of inner layer traces within a module. Specifically, target optimization instructions may include reducing the number of flying wire crossings of inner layer traces within a module.

[0153] For example, target detection tools can include detection tools for adsorbing and placing devices other than chips nearby. Specifically, target optimization instructions can include increasing the number of devices other than chips that can be adsorbed and placed nearby.

[0154] For example, target detection tools may include calibration tools for capacitor layout of the same power supply. Specifically, target optimization instructions may include adjusting the capacitor layout of the same power supply so that the capacitors are arranged in order from smallest to largest.

[0155] 305. The layout system of the circuit board optimizes the layout of electronic components on the target circuit board according to the target optimization instructions to obtain the optimized target circuit board.

[0156] The electronic components on the target circuit board include the electronic components to be optimized. For example, the layout optimization of the electronic components on the target circuit board is performed according to the target optimization instruction. This can be for the electronic components to be optimized on the target circuit board, or it can be for the layout optimization of other electronic components on the target circuit board, in order to achieve the layout optimization of the target circuit board.

[0157] In this embodiment, the circuit board layout system uses a target detection tool to detect circuit board defects and generate target optimization instructions. Based on these instructions, the system optimizes the layout of electronic components on the target circuit board, outputting an optimized target circuit board. This optimization addresses design defects in the target circuit board. Specifically, the system can pre-set a circuit board layout engine, trained on an initial motion prediction model. Using this engine, the electronic components on the target circuit board can be optimized according to the optimization instructions, thus adjusting the layout of the electronic components on the target circuit board.

[0158] In this embodiment, the circuit board layout system can obtain circuit board layout defect information by interacting with the terminal device, then perform semantic understanding through a large language model to obtain a circuit board layout defect description result, perform circuit board defect detection through a target detection tool in the detection tool library to obtain target optimization instructions, and finally optimize the layout of electronic components on the target circuit board according to the target optimization instructions. This circuit board layout system can realize interactive layout optimization with the terminal device, improve the layout efficiency of the circuit board and optimize the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0159] In addition to performing the aforementioned step 302, the circuit board layout method provided in this application embodiment may also include the following steps:

[0160] A1. The circuit board layout system obtains historical circuit board layout optimization information and historical circuit board layout defect information corresponding to the historical circuit board layout optimization information.

[0161] Before optimizing the layout of the current target circuit board, the circuit board layout system can also obtain historical circuit board layout optimization information. This historical layout optimization information can be obtained by optimizing the electronic component layout results of the previous one or more rounds through the circuit board layout system. In addition, the circuit board layout system can also obtain historical circuit board layout defect information corresponding to the historical circuit board layout optimization information. This historical circuit board layout defect information refers to the electronic component layout defects on the target circuit board in the previous one or more rounds obtained from the terminal device before optimizing the layout of the current target circuit board.

[0162] In this embodiment of the application, the circuit board layout system can store historical circuit board layout optimization information and historical circuit board layout defect information, thereby providing input information for subsequent layout optimization of the target circuit board, thereby improving the layout efficiency of the circuit board and optimizing the circuit structure of the circuit board, thus improving the layout effect of the circuit board.

[0163] In the implementation scenario of step A1, the circuit board layout system in step 302 performs semantic understanding of the circuit board layout defect information through a large language model, including:

[0164] A2. The circuit board layout system uses a large language model to semantically understand historical circuit board layout defect information.

[0165] Specifically, the circuit board layout system has semantic understanding capabilities. After receiving historical circuit board layout defect information, it can use a large language model to perform semantic understanding and obtain a description of the historical circuit board layout defects. This historical circuit board layout defect information can be used to indicate defects existing in the target circuit board layout in the previous round or multiple rounds.

[0166] Furthermore, in some embodiments of this application, in the implementation scenarios of the aforementioned steps A1 and A2, step 305, the circuit board layout system optimizes the layout of electronic components on the target circuit board according to the target optimization instructions, including:

[0167] A3. The layout system of the circuit board optimizes the layout of electronic components on the target circuit board based on historical circuit board layout optimization information and target optimization instructions.

[0168] The circuit board layout system uses a target inspection tool to detect circuit board defects and generate target optimization instructions. Based on these optimization instructions and historical circuit board layout optimization information, the system optimizes the layout of electronic components on the target circuit and outputs the optimized target circuit board. By using historical circuit board layout optimization information and target optimization instructions to optimize the layout of electronic components on the target circuit board, the system can improve the layout efficiency and optimize the circuit structure, thereby improving the overall layout effect.

[0169] Furthermore, in some embodiments of this application, the aforementioned step A3, the layout system of the circuit board, optimizes the layout of electronic components on the target circuit board based on historical circuit board layout optimization information and target optimization instructions, including:

[0170] A31. The circuit board layout system inputs historical circuit board layout optimization information and target optimization instructions into the circuit board layout engine. The circuit board layout engine then infers the layout optimization of electronic components on the target circuit board based on the historical circuit board layout optimization information and target optimization instructions.

[0171] Specifically, a PCB layout engine can be pre-set in the PCB layout system. Using this engine, the electronic components on the target PCB can be optimized according to the target optimization instructions and with reference to historical PCB layout optimization information. This adjusts the layout of the electronic components on the target PCB. Since historical PCB layout optimization information can provide important reference value for the layout optimization of the target PCB, the layout efficiency of the PCB can be improved and the circuit structure of the PCB can be optimized, thereby improving the layout effect of the PCB.

[0172] In addition to performing the foregoing steps, the method provided in this application embodiment may also include the following steps:

[0173] B1. The layout system of the circuit board stores at least one of the following information: historical circuit board layout optimization information, circuit board layout defect information, and the target circuit board after layout optimization.

[0174] The circuit board layout system can include a memory module that stores at least one of the following: historical circuit board layout optimization information, circuit board layout defect information, and the optimized target circuit board. This memory module is used for the next layout optimization of the target circuit board. The circuit board layout system can read the information stored in the memory module to provide input information for the next layout optimization of the target circuit board, thereby improving the layout efficiency and optimizing the circuit structure of the circuit board, and ultimately improving the layout effect.

[0175] For example, the layout system of a circuit board optimizes the layout of electronic components on a target circuit board according to the target optimization instructions, and obtains the target circuit board layout optimization information. The target circuit board layout optimization information is used to indicate the target circuit board after layout optimization. The layout system of the circuit board can also store the target circuit board layout optimization information.

[0176] In some embodiments of this application, the historical circuit board layout optimization information includes at least one of the following: historical circuit board layout results and circuit board layout result constraint information.

[0177] Historical PCB layout optimization information can be obtained by optimizing previous electronic component layouts using the PCB layout system. Historical PCB layout results include those obtained after one or more rounds of electronic component layout optimization. PCB layout result constraint information refers to the design constraints of the PCB in the previous one or more rounds. When optimizing the layout of electronic components on the target PCB, these design constraints must be met.

[0178] Furthermore, in some embodiments of this application, the historical circuit board layout results include: the names of electronic components on the target circuit board and their corresponding placement positions, the connection relationships between electronic components on the target circuit board, and the placement range of electronic components on the target circuit board within the corresponding border.

[0179] The historical circuit board layout results can include the results obtained after optimizing the layout of electronic components on the target circuit board. For example, the layout can be optimized by matching the names and corresponding positions of electronic components on the target circuit board, optimizing the connections between electronic components, and optimizing the placement range of electronic components within their corresponding borders. These three types of layout results from the historical circuit board layout provide input information for optimizing the layout of the current target circuit board, improving layout efficiency and optimizing the circuit structure, thereby enhancing the overall layout effect.

[0180] Furthermore, in some embodiments of this application, the circuit board layout result constraint information includes: the matching result of historical circuit board layout results with hard constraints, and the matching result of historical circuit board layout results with soft constraints.

[0181] Hard constraints include: hard constraint indicators that need to be met when placing electronic components on the target circuit board;

[0182] Soft constraints include: soft constraint indicators that are selectively satisfied when placing electronic components on the target circuit board. When there are multiple soft constraint indicators, there may be layout conflicts of electronic components on the target circuit board.

[0183] Hard constraints refer to the mandatory requirements that must be met in the layout of a circuit board. Specifically, hard constraints can include at least one of the following: overlap constraints, boundary constraints, and spacing constraints. Violating any hard constraint will result in an illegal placement of electronic components. Soft constraints refer to the requirements that do not need to be strictly met in the layout of a circuit board. When there are multiple soft constraints, there may be layout conflicts of electronic components on the target circuit board, and multiple soft constraints may conflict and influence each other.

[0184] In this embodiment of the application, the matching results of hard and soft constraints included in the circuit board layout result constraint information can provide input information for the layout optimization of the current target circuit board, improve the layout efficiency of the circuit board and optimize the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0185] In some embodiments of this application, in addition to performing the foregoing steps, the method provided in this application may also include the following steps:

[0186] C1. After the circuit board layout system calls the target detection tool based on the circuit board layout defect description, it generates a detection tool call record.

[0187] C2. Circuit board layout system storage detection tool call records.

[0188] The circuit board layout system can call target detection tools that match the circuit board layout defect description results. Then, based on the calling of the target detection tools, it generates a detection tool call record. This record records the calling of the target detection tools. The circuit board layout system stores the detection tool call record, providing input information for the next layout optimization of the target circuit board, improving the layout efficiency of the circuit board and optimizing the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0189] Furthermore, in some embodiments of this application, step 304, the circuit board layout system, generates target optimization instructions based on information about the electronic components to be optimized on the target circuit board, including:

[0190] D1. The circuit board layout system generates target optimization instructions based on the information of the electronic components to be optimized on the target circuit board and the test tool call records.

[0191] In this embodiment, the circuit board layout system uses a target detection tool to determine the information of the electronic components to be optimized on the target circuit board. In order to optimize the layout of the electronic components to be optimized, a target optimization instruction can be generated based on the information of the electronic components to be optimized on the target circuit board and the detection tool call record. Since the detection tool call record can record the calling of the target detection tool, the target optimization instruction generated based on the information of the electronic components to be optimized and the detection tool call record can instruct the called target detection tool, which facilitates the subsequent layout optimization process and further improves the layout effect of the circuit board.

[0192] In some embodiments of this application, step 303, the circuit board layout system calls a target detection tool based on the circuit board layout defect description results, and performs circuit board defect detection using the target detection tool to determine information about the electronic components to be optimized on the target circuit board, including:

[0193] E1. The circuit board layout system obtains tool call instructions based on the circuit board layout defect description results, and calls the target detection tool from the detection tool library according to the tool call instructions;

[0194] E2. The circuit board layout system uses target detection tools to detect circuit board defects based on the circuit board layout defect description results.

[0195] E3. Obtain information about the electronic components to be optimized on the target circuit board from the target inspection tool.

[0196] The circuit board layout system can generate tool invocation instructions based on the circuit board layout defect description results. Then, it retrieves the detection tool library according to the tool invocation instructions and obtains the target detection tool that matches the circuit board layout defect description results from the detection tool library. The tool invocation instructions indicate the invocation method of the target detection tool in the detection tool library. The circuit board layout system calls and uses the target detection tool according to the tool invocation instructions, and performs circuit board defect detection on the circuit board layout defect description results through the target detection tool, thereby obtaining the target optimization instructions. For an explanation of the target optimization instructions, please refer to the foregoing embodiments.

[0197] For example, the testing tool library integrates diagnostic and location tools for various defects in corresponding circuit board layouts. Defects refer to those that fail to meet circuit board design requirements. The testing tool library examines the connections and positional relationships between various electronic components and determines the compliance of circuit board design constraints based on various indicators. This includes, but is not limited to, diagnosing insufficient surface traces in important modules surrounding chips and diagnosing fan-out surface traces. The testing tool library includes various testing tools, such as tools for testing surface traces of devices other than chips, tools for testing fan-out surface traces of chips, tools for testing surface traces of important modules surrounding chips, tools for testing flying wire crossings in inner layer traces within modules, tools for testing the adsorption and proximity placement of devices other than chips, and calibration tools for capacitor layouts within the same power supply.

[0198] As illustrated by the examples in the foregoing embodiments, the circuit board layout system can obtain circuit board layout defect information by interacting with the terminal device. Then, it can perform semantic understanding through a large language model to obtain a description of the circuit board layout defects. The system can then perform circuit board defect detection using a target detection tool in the detection tool library to obtain target optimization instructions. Finally, it can optimize the layout of electronic components on the target circuit board according to the target optimization instructions. This circuit board layout system can achieve interactive layout optimization with the terminal device, improve the layout efficiency of the circuit board and optimize the circuit structure of the circuit board, thereby improving the layout effect of the circuit board.

[0199] To facilitate a better understanding and implementation of the above-described solutions in the embodiments of this application, specific examples of corresponding application scenarios are provided below.

[0200] In subsequent embodiments, a printed circuit board (PCB) is used as a specific example. PCB layout refers to the arrangement of various electronic components on the PCB during the design of electronic devices, as well as the wiring and lines connecting these components. Electronic components can be of various types, such as chips, resistors, and capacitors. This application does not limit the types of electronic components. This application's embodiments can improve the layout efficiency and results of PCB layout, which not only improves circuit performance and reliability but also reduces production costs and manufacturing cycles, providing strong support for the successful design and manufacturing of electronic devices.

[0201] like Figure 4 The diagram shown is an application framework diagram of a circuit board layout system provided in an embodiment of this application. The circuit board layout system provided in this embodiment of this application may specifically include: a Large Language Model Agent (LLM Agent), a detection tool library, and a circuit board layout engine.

[0202] The large language model agent includes at least one of the following: a state acquisition module, a semantic understanding module, a tool invocation module, an instruction generation module, and a memory module. The large language model agent can interact with detection tool libraries and circuit board layout engines; see subsequent examples for details.

[0203] An intelligent agent (AGT) is a computational entity that resides in multiple application environments, can continuously and autonomously play a role, and possesses characteristics such as residency, responsiveness, sociality, and initiative.

[0204] like Figure 4 As shown, this application provides a large language model-driven intelligent PCB layout framework. This application trains the large language model with all available knowledge, learning from human experience to create the model. Based on logical reasoning, this application enables decision-making in multi-objective optimization with multiple conflicts. This application allows for continuous improvement and evolution; compared to manual layout, this application can significantly improve the layout efficiency of circuit boards.

[0205] Specifically, this application embodiment utilizes the understanding of PCB layout defects provided by the terminal device to describe the current layout result state of the PCB, achieving interactive layout optimization and improving PCB layout efficiency and quality. This application embodiment proposes a large language model-driven intelligent PCB layout framework. Through multi-round interaction between the terminal device and the large language model agent, and comparison with manual layout, a significant improvement in layout efficiency is achieved.

[0206] The circuit board layout system provided in this application embodiment can specifically be a modeling software system integrated into PCB design software. The circuit board layout system provided in this application embodiment can be widely applied to various scenarios involving PCB design.

[0207] The functions of each module in the circuit board layout system provided in this application embodiment will be described next.

[0208] (1) User Description Module

[0209] The main function of the user description module is to obtain the current layout defect description information generated during the PCB design process, record the current layout defect description information, and output the description content to the large language model agent.

[0210] (2) Large Language Model Intelligent Agent

[0211] A large language model agent can include five modules: state acquisition module, semantic understanding module, tool invocation module, instruction generation module, and memory module.

[0212] 1) Status Acquisition Module

[0213] The status acquisition module is used to obtain the layout results of the previous round or multiple rounds, as well as the layout defects described by the user.

[0214] The layout results used by the status acquisition module and the corresponding layout defects described by the user include the following: layout results, electronic component names and their corresponding placement positions, connection relationships between electronic components, and the placement range of electronic components. The placement range of electronic components refers to the area within the outer frame where the electronic components are placed.

[0215] The layout defect description includes the following: the name of the module on the circuit board that caused the placement defect and the defect description information on the circuit board.

[0216] Figure 5 This is a schematic diagram of the composition structure of a status acquisition module provided in an embodiment of this application. For example, the number of surface lines of important modules around chip 1 is insufficient, which may affect the communication between modules.

[0217] 2) Semantic understanding module

[0218] The semantic understanding module uses a large language model to understand the user's description of layout defects and outputs a semantically encoded result, which is used by the tool to call the module. Here, encoding refers to the description result generated based on the layout defects.

[0219] Figure 6This is a schematic diagram of the composition structure of a semantic understanding module provided in an embodiment of this application. For example, the semantic understanding module understands the user's description of layout defects through a large language model. This description is the encoding output by the state acquisition module.

[0220] The output of the semantic understanding module will be used by the tool to call the module. Semantic understanding uses large language models, the architecture of which includes, but is not limited to, the following: GPT-4 / GPT3.5 large model, Llama 2b large model, Pangu large model, and Mistral large model.

[0221] For example, in the embodiments of this application, in-context learning is used for reasoning.

[0222] Examples of input and output are as follows. The output of the status acquisition module is: In design case 21, the layout of identical and similar modules is inconsistent, resulting in a lack of consistency in the overall design. Isolated component blocks were found, which reduces the performance efficiency of the circuit board. Alternatively, if multiple issues exist, please help resolve them one by one. Based on your provided natural language input, provide a solution Python script.

[0223] The output of the semantic encoding result is as follows:

[0224] The solution script is:

[0225] import Single_Chip_API from API

[0226] api=Single_Chip_API("case21")

[0227] result_1=api.similar_placement()

[0228] result_2=api.isolated_symbols()

[0229] 3) Tool Call Module

[0230] The tool invocation module parses the encoded response from the semantic understanding module and outputs instructions to select a tool from the detection tool library.

[0231] Figure 7 This is a schematic diagram illustrating the structural composition of a tool invocation module provided in an embodiment of this application. For example, the tool invocation module parses the semantic encoding results of the semantic understanding module and outputs a tool invocation instruction to select a tool from the detection tool library.

[0232] For example, the detection tool can be described as follows, where the tool name and corresponding function description can be included, as illustrated in the following example:

[0233] symbol_surface_line: "Insufficient number of surface lines for devices other than chips".

[0234] chips_fanout_surface_line: "Insufficient number of fanout surface lines on the chip".

[0235] important_module_surface_line: "Insufficient number of surface lines for important modules around the chip".

[0236] inner_layer_line: "Too many flying wires crossing each other in the inner layer of the module"

[0237] `placed_nearby`: "Place devices other than chips nearby to meet the requirement of not having enough."

[0238] capacitor_placement: "The capacitor placement for the same power supply does not satisfy the requirement of smaller capacitors first, then larger ones".

[0239] It is not limited to this application; other detection tools may also be configured in the embodiments of this application. This is only an example and is not intended to limit the embodiments of this application.

[0240] 4) Instruction generation module

[0241] The instruction generation module generates corresponding target optimization instructions based on the tool selected by the tool calling module. These target optimization instructions may include tool calling code, which transmits the electronic component information to be optimized to the circuit board layout engine.

[0242] Figure 8 This is a schematic diagram illustrating the structural composition of an instruction generation module and a detection tool library provided in an embodiment of this application. The instruction generation module generates corresponding detection tool library call code based on the tool call instructions generated by the tool call module; it executes the code and passes the device information that needs optimization to the placement engine.

[0243] The instruction generation module uses large language models, and the model architecture includes, but is not limited to: Llama2, GPT4, and Pangu large models.

[0244] 5) Memory module

[0245] The memory module, also known as the storage module, is used to store historical layout optimization information, tool call records, user description information, and layout results output by the previous or multiple rounds of the layout engine, in order to improve the efficiency of the next layout optimization. The historical layout optimization information includes multiple rounds of layout results for different PCB use cases, but does not include the previous or multiple rounds of layout results for the current use case.

[0246] For example, the memory module is used to store historical layout tuning information, tool call records, and user description information. Historical layout tuning information includes: layout results, tool call records, the satisfaction status of soft and hard constraints in the layout, and the hyperparameters of the layout engine.

[0247] The types of memory modules include the following two:

[0248] The long-term memory module uses a large language model combined with historical layout optimization information to accelerate layout optimization. Historical layout optimization information and call records are stored in a database and input into the large language model using context learning. The large language model recommends layout parameters based on this information, thereby achieving layout acceleration under optimal parameters. The large language model can be simply referred to as the large model.

[0249] The short-term memory module uses a large language model to combine user descriptions and layout optimization information of the current use case. It inputs the existing optimization information of the current optimization use case into the large model through context learning. The large model recommends layout parameters based on this information, thereby improving the quality of the layout.

[0250] For example, the memory module uses large language models, and the model architecture includes, but is not limited to, the following: GPT-4 / GPT3.5 large model, Llama2b large model, Pangu large model, and Mistral large model.

[0251] (3) Circuit board layout engine

[0252] The PCB layout engine is a module that optimizes PCB layout. It takes the information of the electronic components to be optimized and the layout results from the previous one or more rounds of layout engine input, and outputs an optimized layout result through model inference. The output of the PCB layout engine will strive to meet the PCB design layout description and requirements.

[0253] Figure 10This is a schematic diagram of the module architecture of a PCB layout engine provided in an embodiment of this application. For example, the input of the PCB layout engine is the device information to be optimized and the current layout result. The PCB layout engine outputs the optimized layout result through reasoning on the Causal Transformer model.

[0254] The inputs to the PCB placement engine include state S, action a, reward R, and circuit representation HI. Action a contains three pieces of information: the x-coordinate and y-coordinate of the currently placed device, and the rotation angle r.

[0255] Figure 9a , Figure 9b and Figure 9c This is a schematic diagram of a state token provided in an embodiment of this application; the state token for state S consists of three parts:

[0256] View mask: A view mask consists of 0 or 1 values ​​and provides a global view of the current PCB layout. For example... Figure 9c As shown, a grid cell with a value of 1 indicates that the module occupies this cell;

[0257] Position mask: Indicates the possible placement positions of the next module. For example... Figure 9a As shown, a mesh cell value of 0 indicates that the location is valid, meaning that if the next module is placed at that location, it will satisfy all hard constraints.

[0258] Wire mask: This mask is a continuous matrix containing the half-perimeter wirelength (HPWL) value added by the next placement module. For example... Figure 9b As shown, for example, a grid cell with a value of 2 means that if the next module is placed in that location, the overall HPWL will increase by 2.

[0259] exist Figure 10 In the diagram, module t has coordinates (x, y, r). The circuit represents HI, the state S at time t-1, action a, and reward R. The input action reasoning model is used, and the PCB layout engine infers the action a at time t based on the input, storing it in the replay buffer. The PCB layout engine then predicts the next device to be placed based on the current replay buffer.

[0260] (4) Detection Tool Library

[0261] The inspection tool library integrates diagnostic and location tools for various defects in PCB layout. These include, but are not limited to, diagnosing insufficient surface traces in critical modules surrounding chips and diagnosing fan-out surface traces of chips.

[0262] The inspection tool library integrates diagnostic and location tools for various PCB layout defects. Defects refer to situations where hard and soft constraints are not met. The inspection tool library examines the connections and positional relationships between components and determines the satisfaction status of hard and soft constraints based on various indicators. This includes, but is not limited to, diagnosing insufficient surface traces of important modules around chips and diagnosing fan-out surface traces of chips.

[0263] The diagnostic tools in the detection tool library handle the following defect issues respectively:

[0264] The number of surface lines on devices other than chips is insufficient;

[0265] The chip has insufficient number of fan-out surface lines;

[0266] The number of surface lines for important modules around the chip is insufficient. Important modules refer to devices with high placement priority, such as inner ring devices that are close to the main chip.

[0267] The number of flying wires crossing within the inner layer of the module is too high;

[0268] For devices other than chips, adsorption can be performed by placing them nearby to meet the requirement of having a sufficient number of devices; for example, if device A adsorbs device B, then A and B need to be placed close together.

[0269] The capacitor layout for the same power supply does not meet the requirement of ensuring that the inner ring of the capacitors in the same network is smaller than the outer ring.

[0270] The basic process of this application embodiment is described below. When a PCB designer needs to optimize the current layout result and points out the shortcomings of the current layout, the intelligent agent framework provided in this application embodiment begins inference. The large language model intelligent agent inputs the description content of the PCB designer to the semantic understanding module and the state acquisition module, and inputs the current layout result to the state acquisition module; the tool invocation module outputs a tool invocation instruction to select a tool from the detection tool library by parsing the output of the semantic understanding module; after understanding the tool selection instruction, the instruction generation module generates the corresponding tool invocation code, executes the code, and outputs the target tuning instruction, which includes the list information of the components to be optimized, and passes the target tuning instruction to the circuit board layout engine; the circuit board layout engine receives the current layout result and the component information to be optimized, outputs the optimized layout result, and then judges the layout result to decide whether to enter the next round of optimization, such as continuing to receive user description information to continue multiple rounds of optimization; when the indicators can no longer be improved, the layout optimization will no longer continue.

[0271] As illustrated by the examples above, LLM is used to understand the intent of the PCB layout design input information, enabling the scheduling and use of inspection tools. The solution provided in this application achieves a 100% success rate in successfully calling the inspection tool library in both single-tool and multi-tool scenarios.

[0272] This application embodiment uses an LLM Agent to achieve multi-round feedback iterative optimization of the layout, taking user feedback and historical layout results as input to the layout engine to improve layout quality.

[0273] Through multiple rounds of interactive layout optimization, the conflict between soft and hard constraints is effectively resolved, enabling decision-making under multi-objective optimization with multiple conflicts, and rapidly improving layout accuracy.

[0274] As shown in Table 1 below:

[0275]

[0276] For example, the layout results achieve 70% of the quality of expert placement, with some results exceeding the quality of manual placement, demonstrating the ability to continuously evolve. Expert placement quality refers to the quality of layout results completed by PCB layout personnel with many years of experience. This indicator, provided by business experts, suggests that achieving 70% already improves the efficiency of PCB layout engineers.

[0277] The names of the chip layout use cases are given by the scoring system, with a maximum score of 100; the indicators include soft constraints and hard constraints.

[0278] This application's embodiments introduce a long short-term memory mechanism to feed user feedback and historical layout results back to the large model, thereby improving optimization iteration efficiency. For example, after evaluating the circuit board layout system mentioned in this application's embodiments, the single-round layout time for electronic components on the mobile phone motherboard is expected to be shortened from 3 days to 0.5 days.

[0279] In this embodiment, LLM is used to understand the intent of the input information for PCB layout design, enabling the scheduling and use of inspection tools. Furthermore, an LLM Agent is used to implement multi-round feedback iterative optimization of the layout, using user feedback and historical layout results as input to the PCB layout engine, thereby improving the layout efficiency and effectiveness of the PCB.

[0280] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0281] To facilitate better implementation of the above-described solutions in the embodiments of this application, related apparatus for implementing the above-described solutions is also provided below.

[0282] Please see Figure 11 As shown in the figure, a circuit board layout system 1100 provided in this application embodiment may include: a semantic understanding module 1101, a tool invocation module 1102, an instruction generation module 1103, and a layout optimization module 1104, wherein,

[0283] The semantic understanding module is connected to the tool invocation module, the tool invocation module is connected to the instruction generation module, and the instruction generation module is connected to the layout optimization module.

[0284] The semantic understanding module is used to perform semantic understanding on the circuit board layout defect information through a large language model in order to obtain the circuit board layout defect description result.

[0285] The tool invocation module is used to invoke the target detection tool based on the circuit board layout defect description result, and to perform circuit board defect detection through the target detection tool to determine the information of the electronic components to be optimized on the target circuit board.

[0286] The instruction generation module is used to generate target optimization instructions based on the information of the electronic components to be optimized on the target circuit board.

[0287] The layout optimization module is used to optimize the layout of electronic components on the target circuit board according to the target optimization instruction, so as to obtain a layout-optimized target circuit board, wherein the electronic components on the target circuit board include the electronic components to be optimized.

[0288] In this embodiment, the module is an example of a software functional unit, and the layout system of the circuit board may include code running on computing instances. The computing instance may be at least one of a physical host (computing device), a virtual machine, a container, or other computing devices. Further, the aforementioned computing device may be one or more. For example, the layout system of the circuit board may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the application may be distributed in the same region or in different regions. The multiple hosts / virtual machines / containers used to run the code may be distributed in the same available zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0289] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a single region. Communication between two VPCs within the same region, and between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0290] As an example of a hardware functional unit, a circuit board layout system can include at least one computing device, such as a server. Alternatively, the circuit board layout system can also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex PLD (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0291] The PCB layout system includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the PCB layout system includes multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the PCB layout system includes multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0292] This application also provides a computing device 130. For example... Figure 12 As shown, the computing device 130 includes a bus 132, a processor 134, a memory 136, and a communication interface 138. The processor 134, the memory 136, and the communication interface 138 communicate with each other via the bus 132. The computing device 130 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 130.

[0293] Bus 132 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 12 The bus 134 is represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 134 may include a path for transmitting information between various components of the computing device 130 (e.g., memory 136, processor 134, communication interface 138).

[0294] The processor 134 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0295] Memory 136 may include volatile memory, such as random access memory (RAM). Processor 134 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0296] The memory 136 stores executable program code, and the processor 134 executes the executable program code to implement the functions of the aforementioned acquisition module and training module, thereby realizing the layout method of the circuit board applied to the computing device cluster in the above embodiment. That is, the memory 136 stores instructions for executing the layout method of the circuit board applied to the computing device cluster in the above embodiment.

[0297] The communication interface 138 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 130 and other devices or communication networks.

[0298] This application also provides a computing device cluster. The computing device cluster includes at least one computing device. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0299] like Figure 13 As shown, the computing device cluster includes at least one computing device 130. The memory 136 in one or more computing devices 130 in the computing device cluster may store the same instructions for executing the layout method of the circuit board.

[0300] In some possible implementations, the memory 136 of one or more computing devices 130 in the computing device cluster may also store partial instructions for executing the layout method of the circuit board. In other words, a combination of one or more computing devices 130 can jointly execute instructions for executing the layout method of the circuit board.

[0301] It should be noted that the memory 136 in different computing devices 130 within the computing device cluster can store different instructions, each used to execute a portion of the functions of the circuit board layout method. That is, the instructions stored in the memory 136 of different computing devices 130 can implement one or more functions of the acquisition module.

[0302] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN), a local area network (LAN), or similar. Figure 13 One possible implementation is shown. For example... Figure 13 As shown, two computing devices 130A and 130B are connected via a network. Specifically, they are connected to the network through communication interfaces in each computing device. In this type of possible implementation, the memory 136 in computing device 130A may store instructions for executing the functions of the first processing module. Simultaneously, the memory 136 in computing device 130B may store instructions for executing the functions of the second processing module. Alternatively, the memory 136 in computing device 130A may store instructions for executing some functions of the second processing module, while the memory 136 in computing device 130B may store instructions for executing another part of the functions of the second processing module, and so on.

[0303] It should be understood that Figure 14 The functions of the computing device 130A shown can also be performed by multiple computing devices 130. Similarly, the functions of the computing device 130B can also be performed by multiple computing devices 130.

[0304] This application also provides another computing device cluster. The connection relationships between the computing devices in this computing device cluster can be similarly referred to... Figure 12 and Figure 13 The connection method of the computing device cluster. The difference is that the memory 136 of one or more computing devices 130 in the computing device cluster can store the same instructions for executing the layout method of the circuit board.

[0305] In some possible implementations, the memory 136 of one or more computing devices 130 in the computing device cluster may also store partial instructions for executing the layout method of the circuit board. In other words, a combination of one or more computing devices 130 can jointly execute instructions for executing the layout method of the circuit board.

[0306] It should be noted that the memory 136 in different computing devices 130 within the computing device cluster can store different instructions for executing some functions of the circuit board layout method. That is, the instructions stored in the memory 136 of different computing devices 130 can implement one or more functions of the processing module.

[0307] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform a circuit board layout method.

[0308] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center that includes one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform a circuit board layout method.

[0309] This application also provides a chip system including a processor for implementing the steps performed by the aforementioned computing device cluster. In one possible design, the chip system may further include a memory for storing necessary program instructions and data. This chip system may be composed of chips or may include chips and other discrete devices.

[0310] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0311] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0312] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0313] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0314] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A layout method of a wiring board, characterized by, include: Semantic understanding of circuit board layout defect information is performed using a large language model to obtain the circuit board layout defect description results. The target detection tool is invoked based on the circuit board layout defect description results, and the circuit board defect is detected by the target detection tool to determine the information of the electronic components to be optimized on the target circuit board. Target optimization instructions are generated based on the information of the electronic components to be optimized on the target circuit board; The electronic components on the target circuit board are laid out according to the target optimization instructions to obtain a layout-optimized target circuit board, wherein the electronic components on the target circuit board include the electronic components to be optimized.

2. The method of claim 1, wherein, The method further includes: obtaining historical circuit board layout optimization information and historical circuit board layout defect information corresponding to the historical circuit board layout optimization information; The step of semantically understanding the circuit board layout defect information using a large language model includes: semantically understanding the historical circuit board layout defect information using a large language model.

3. The method of claim 2, wherein, The step of optimizing the layout of electronic components on the target circuit board according to the target optimization instructions includes: The electronic components on the target circuit board are optimized based on the historical circuit board layout optimization information and the target optimization instructions.

4. The method of claim 3, wherein, The step of optimizing the layout of electronic components on the target circuit board based on the historical circuit board layout optimization information and the target optimization instructions includes: The historical circuit board layout optimization information and the target optimization instruction are input into the circuit board layout engine. The circuit board layout engine then infers the layout optimization of the electronic components on the target circuit board based on the historical circuit board layout optimization information and the target optimization instruction.

5. The method according to any one of claims 2 to 4, characterized in that, The method further includes: Store at least one of the following information: the historical circuit board layout optimization information, the circuit board layout defect information, and the target circuit board after layout optimization.

6. The method according to any one of claims 2 to 5, characterized in that, The historical circuit board layout optimization information includes at least one of the following: historical circuit board layout results and circuit board layout result constraint information.

7. The method of claim 6, wherein, The historical circuit board layout results include: the names of electronic components on the target circuit board and their corresponding placement positions, the connection relationships between the electronic components on the target circuit board, and the placement range of the electronic components on the target circuit board within the corresponding borders.

8. The method of claim 6, wherein, The circuit board layout result constraint information includes: the matching result of the historical circuit board layout result with hard constraints, and the matching result of the historical circuit board layout result with soft constraints. The hard constraints include: the hard constraint indicators that need to be met when laying out electronic components on the target circuit board; The soft constraint conditions include: soft constraint indicators that are selectively satisfied when laying out electronic components on the target circuit board. When there are multiple soft constraint indicators, there will be layout conflicts of electronic components on the target circuit board.

9. The method according to any one of claims 1 to 8, characterized in that, The circuit board layout defect information includes at least one of the following: layout defects corresponding to the placement of electronic components on the target circuit board, and descriptive information of the layout defects.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: After the target detection tool is invoked according to the layout defect description result of the circuit board, a detection tool invocation record is generated; The detection tool invocation record is stored.

11. The method of claim 10, wherein, The target optimization instruction is generated according to information of electronic components to be optimized on the target circuit board, and includes: The target optimization instruction is generated according to information of electronic components to be optimized on the target circuit board and the detection tool invocation record.

12. The method according to any one of claims 1 to 11, characterized in that, The target detection tool is invoked according to the layout defect description result of the circuit board, and the target detection tool is used to detect defects of the circuit board to determine information of electronic components to be optimized on the target circuit board, and includes: A tool invocation instruction is obtained according to the layout defect description result of the circuit board, and the target detection tool is invoked from a detection tool library according to the tool invocation instruction; The layout defect description result of the circuit board is detected by the target detection tool; Information of electronic components to be optimized on the target circuit board is obtained from the target detection tool.

13. A layout system for a circuit board, characterized by The system includes a semantic understanding module, a tool invocation module, an instruction generation module, and a layout optimization module, wherein the semantic understanding module is connected to the tool invocation module, and the tool invocation module is connected to the layout optimization module; The semantic understanding module is configured to perform semantic understanding on circuit board layout defect information by using a large language model to obtain a circuit board layout defect description result; The tool invocation module is configured to invoke a target detection tool according to the circuit board layout defect description result, and perform circuit board defect detection by using the target detection tool to determine information of electronic components to be optimized on a target circuit board; The instruction generation module is configured to generate a target optimization instruction according to the information of electronic components to be optimized on the target circuit board; The layout optimization module is configured to perform layout optimization on electronic components on the target circuit board according to the target optimization instruction to obtain a target circuit board after layout optimization, and the electronic components on the target circuit board include the electronic components to be optimized.

14. The system of claim 13, wherein, The system includes a state acquisition module, The state acquisition module is configured to acquire historical circuit board layout optimization information and historical circuit board layout defect information corresponding to the historical circuit board layout optimization information; The semantic understanding module is specifically configured to perform semantic understanding on the historical circuit board layout defect information by using a large language model.

15. The system of claim 14, wherein, The layout optimization module is specifically configured to perform layout optimization on electronic components on the target circuit board according to the historical circuit board layout optimization information and the target optimization instruction.

16. The system of claim 15, wherein, The layout optimization module includes a circuit board layout engine, The instruction generation module is further configured to input the historical circuit board layout optimization information and the target optimization instruction into the circuit board layout engine; The circuit board layout engine is configured to infer layout optimization of the electronic components on the target circuit board based on the historical circuit board layout optimization information.

17. The system of any one of claims 14 to 16, wherein, The system further includes a memory module, The memory module is configured to store at least one of the following information: the historical circuit board layout optimization information, the circuit board layout defect information, and the target circuit board after layout optimization.

18. The system of any one of claims 14 to 17, wherein, The historical circuit board layout optimization information comprises at least one of the following: historical circuit board layout results and circuit board layout result constraint information.

19. The system of claim 18, wherein, The historical circuit board layout results comprise the names of electronic components on the target circuit board and corresponding placement positions, connection relationships between the electronic components on the target circuit board, and placement ranges of the electronic components in corresponding frames on the target circuit board.

20. The system of claim 18, wherein, The circuit board layout result constraint information comprises matching results of the historical circuit board layout results and hard constraint conditions, and matching results of the historical circuit board layout results and soft constraint conditions. The hard constraint conditions comprise hard constraint indexes that need to be met when the electronic components are laid out on the target circuit board. The soft constraint conditions comprise soft constraint indexes that are selectively met when the electronic components are laid out on the target circuit board, and there is a layout conflict of the electronic components on the target circuit board when there are multiple soft constraint indexes.

21. The system of any one of claims 13 to 20, wherein, The circuit board layout defect information comprises at least one of the following: layout defects corresponding to the placement positions of the electronic components on the target circuit board and description information of the layout defects.

22. The system of any one of claims 13 to 21, wherein, The system further comprises a memory module. The tool calling module is configured to generate detection tool calling records after calling the target detection tool according to the circuit board layout defect description results. The memory module is configured to store the detection tool calling records.

23. The system of claim 22, wherein, The instruction generation module is specifically configured to generate the target optimization instruction according to information of the electronic components to be optimized on the target circuit board and the detection tool calling records.

24. The system of any one of claims 13 to 23, wherein, The tool calling module is specifically configured to obtain tool calling instructions according to the circuit board layout defect description results, and call the target detection tool from a detection tool library according to the tool calling instructions. The target detection tool is used to perform circuit board defect detection on the circuit board layout defect description results. Information of the electronic components to be optimized on the target circuit board is obtained from the target detection tool.

25. The system of claim 24, wherein, The system further comprises the detection tool library. The detection tool library comprises a plurality of detection tools, and the plurality of detection tools comprise the target detection tool. The plurality of detection tools are used to detect and locate a plurality of circuit board layout defects.

26. An electronic device, comprising a processor and a memory, the memory and the processor being coupled, and the processor being configured to execute the method of any one of claims 1 to 12.

27. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 12.

28. A computer program product comprising instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 12.

29. A chip, characterized by An electronic device comprising one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal from a memory of the electronic device, and send the signal to the processor, the signal comprising computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device is caused to perform the method of any one of claims 1-12.

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