Layout collaborative design method for super-large-scale wafer-level substrate

Abstract

The invention discloses a Layout collaborative design method for a super-large-scale wafer-level substrate, and the method comprises the steps: loading all devices into a substrate, and enabling a network connection relation to be consistent with a netlist; the devices are arranged according to the network connection relation and the position requirement, and the substrate is divided into corresponding parts through dividing lines according to the number of designers of common design; opening interconnected fly lines of all parts and performing highlighting treatment; a wiring layer of interconnection lines is planned, each designer processes a corresponding part, all other devices are deleted, and a board frame is reserved; enabling the designers to walk the interconnection lines to a segmentation line area, aligning the interconnection lines in a manner of adjusting grid points, and completing the rest of wiring; the designer exports the designed substrates into files matched with the third-party software; placing the lines in each file in a graph in a copying manner; and completely connecting the disconnected interconnection lines by using a third-party software line drawing command. According to the method, in the design process, the jamming condition hardly occurs, the design efficiency is improved, and the project period is shortened.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a layout co-design method for ultra-large scale wafer-level substrates. Background Technology

[0002] With the development of chip integration technology, the scale of a single chip has generally reached the level of 50,000 pins, and even a single substrate of a microsystem has exceeded 400,000 pins.

[0003] The layout design of such a large-scale microsystem substrate is unprecedented, and the resulting Cadence software lag has become a pain point and challenge in the design process. As the number of vias, connections, and shapes increases, the amount of data becomes almost incalculable. For example, adding a new via may take 1 minute initially, but at least several minutes or even tens of minutes later, which seriously affects design efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a layout collaborative design method for ultra-large scale wafer-level substrates to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a layout co-design method for ultra-large-scale wafer-level substrates, comprising the following steps:

[0006] Step 1: Load all devices into the substrate and ensure that the network connection relationship is completely consistent with the netlist;

[0007] Step 2: Arrange the components according to the network connection relationship and position requirements, and divide the substrate into corresponding parts according to the number of designers involved in the joint design;

[0008] Step 3: Open the connecting wires of each part and highlight them;

[0009] Step 4: Plan the interconnection layers reasonably, with each designer handling their respective section, deleting all other components, and retaining only the board outline;

[0010] Step 5: Each designer routes the interconnects to the dividing line area, aligns the interconnects by adjusting the grid points, and completes the remaining routing.

[0011] Step 6: Each designer exports the completed substrate design as a file compatible with third-party software.

[0012] Step 7: Copy the lines from each file and place them on one map;

[0013] Step 8: Connect the disconnected interconnects using the line drawing command of third-party software.

[0014] This invention provides a layout collaborative design method for ultra-large scale wafer-level substrates. This method differs from the board-splitting method built into CAD design software. It can flexibly divide the substrate into several independent blocks, each of which is designed independently. Finally, the blocks are assembled using third-party software. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a layout co-design method for ultra-large scale wafer-level substrates.

[0016] Figure 2 This is a schematic diagram of the overall layout of the substrate.

[0017] Figure 3 This is a diagram of the highlighted interconnects.

[0018] Figure 4 This is a schematic diagram of the interconnecting lines on the left and right sides.

[0019] Figure 5 This is a circuit diagram of file M.

[0020] Figure 6 This is a circuit diagram for file N.

[0021] Figure 7 This is a schematic diagram of the circuit after integrating files M and N.

[0022] Figure 8 This is a diagram illustrating the connection using third-party software. Detailed Implementation

[0023] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the layout collaborative design method for ultra-large-scale wafer-level substrates proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0024] This invention provides a layout co-design method for ultra-large scale wafer-level substrates, the process of which is as follows: Figure 1 As shown, it includes the following steps:

[0025] Step 1: Load all devices into the substrate and ensure that the network connection relationship is completely consistent with the netlist;

[0026] Step 2: Lay out the components according to the network connection relationships and location requirements. Taking a design jointly by designers A and B as an example, for instance... Figure 2 The dividing line indicated by the arrow divides the substrate into left and right parts.

[0027] Step 3: Open the connecting wires on both sides and highlight them, such as... Figure 3 A wide diagonal line in the upper left corner as shown;

[0028] Step 4: Plan the interconnect layers reasonably. If designer A is working on the left side, delete all components on the right side of the dividing line to reduce the amount of substrate data and alleviate the problem of design software lag. Similarly, designer B deletes all components on the left side of the dividing line and retains the outline.

[0029] Step 5: Designers A and B each route the interconnects to the split line area, such as... Figure 4 The circled areas can be aligned as much as possible by adjusting the grid points, and the remaining traces on the left and right sides can be completed separately.

[0030] Step 6: Designers A and B each export the completed substrate design to a third-party software, such as... Figure 5 The file M shown and as follows Figure 6 The file N shown is shown.

[0031] Step 7: Copy the lines from file M and file N to a single diagram, such as... Figure 7 The circled area indicates the point where the connection needs to be broken.

[0032] Step 8: Reconnect the disconnected interconnects using a third-party software's drawing command, such as... Figure 8 As shown.

[0033] The design is now complete. Thanks to the method described above, both sides experienced very few glitches during the design process, greatly improving design efficiency and shortening the project cycle.

[0034] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A layout co-design method for ultra-large scale wafer-level substrates, characterized in that, Comprising the following steps: Step 1, load all devices into the substrate, ensure that the network connection relationship is completely consistent with the netlist; Step 2, layout the devices according to the network connection relationship and position requirements, divide the substrate into corresponding parts according to the number of jointly designed designers with partition lines; Step 3, open the flying wire of each part interconnection and do highlight processing; Step 4, reasonably plan the routing layer of the interconnection line, each designer processes the corresponding part, deletes all other devices, and keeps the board frame; Step 5, each designer walks the interconnection line to the partition line area, aligns the interconnection line through the adjustment of the grid point, and completes the remaining routing respectively; Step 6, each designer respectively exports the file of the designed substrate suitable for the third-party software; Step 7, place the lines in each file in one picture through copying; Step 8, connect the disconnected interconnection lines with the line command of the third-party software.

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