Dual-channel universal logic chip testing device and testing method

Abstract

The invention discloses a dual-channel universal logic chip testing device and a testing method. The testing device comprises an STM32F103C8T6 core control module, a man-machine interaction module, a dual-channel chip testing interface module, a result indication module and a power supply module, wherein the man-machine interaction module is composed of a matrix keyboard and an LCD display screen, and the dual-channel chip testing interface module is composed of a multi-way switch array and a universal chip socket. After a chip to be tested is placed on the universal chip socket, a tester inputs the model of the chip on the matrix keyboard, the microcontroller automatically applies a test signal to the chip and acquires a response by controlling the multi-way switch array, the function judgment of the dual-channel chip can be synchronously completed, and a test result is synchronously output through the LCD display screen and the LED indicating lamp. According to the invention, double-channel parallel automatic testing is realized, the method has the advantages of high efficiency, strong universality and simple operation, and the problems of blind chip replacement and low testing efficiency caused by lack of a convenient testing tool in a teaching experiment are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement and automation technology, and in particular to a dual-channel general logic chip testing device and testing method. Background Technology

[0002] General-purpose logic chips, such as various gate circuits, flip-flops, and counters, are fundamental core components in experimental teaching of courses such as electronics and digital circuits. In teaching practice, when students' circuit experiments exhibit abnormal phenomena or results, due to the lack of convenient and reliable verification methods, students often habitually and one-sidedly attribute the fault to chip damage, leading to frequent instances of "blindly replacing chips" in experimental classes. The main reason for this is that existing teaching laboratories generally lack a dedicated testing device that is easy to operate and can quickly verify chip functionality. This makes it impossible to confirm the most basic question of "whether the chip is intact" in a timely manner, seriously affecting the efficiency and quality of experimental teaching.

[0003] To address the needs of chip testing, several solutions exist in current technology, but they still have varying degrees of limitations and cannot effectively adapt to teaching and experimental scenarios. Specifically:

[0004] (1) In terms of versatility: Many existing testing devices are designed for specific chip types or packages. For example, the patents “An experimental device for testing integrated operational amplifier chips” (application number CN202420170580.8) and “An experimental device for testing radio frequency filter chips and its usage method” (application number CN202510355243.5) have limited types of chips that can be tested and cannot be adapted to the wide variety of general logic chips such as the 74 series used in teaching experiments, resulting in poor versatility.

[0005] (2) In terms of testing efficiency: Most teaching-grade testing equipment only supports single-channel testing. For example, the patents "A Logic Chip Testing Device" (application number CN201811021915.5) and "An Automatic Testing Device for Chip Testing" (application number CN202411567326.2) can only test one chip at a time. Their core architecture is still single-channel, which cannot meet the needs of rapid verification in teaching experiments.

[0006] (3) In terms of automation and ease of use: Some solutions are not sufficiently automated and rely on manual intervention. For example, although the patents "FPGA-based Degradation Chip Testing System" (application number CN202111131685.X) and "A Semi-Automatic Chip Testing System" (application number CN202011644904.X) have achieved partial automation, when testing different chips, the operator still needs to manually switch the test circuit or configure complex hardware connections, which is not suitable for students to use quickly in the classroom.

[0007] (4) In terms of hardware adaptation: In order to connect different chips, existing technologies often rely on dedicated adapters, which not only increases the complexity and cost of the system, but also reduces the convenience of testing in the frequently changing teaching environment.

[0008] In summary, although existing technologies offer a variety of chip testing approaches, they generally suffer from poor versatility, limited testing channels, insufficient automation, and low hardware compatibility, making them difficult to promote and apply in cost-sensitive teaching and experimental environments that prioritize efficiency and convenience. Summary of the Invention

[0009] The purpose of this invention is to address the problems of poor versatility, low testing efficiency, insufficient automation, and reliance on dedicated adapters in existing general-purpose logic chip testing devices, and to provide a dual-channel general-purpose logic chip testing device and method based on a microcontroller. Specifically, it is as follows:

[0010] ① Provides an efficient parallel testing solution: By designing a dual-channel test architecture, it is possible to simultaneously or independently test two logic chips of the same or different models, thereby improving testing efficiency;

[0011] ② Provides a highly versatile hardware adaptation solution: By constructing a programmable test interface consisting of a multi-channel switch array and a dual-channel universal chip socket, a single hardware system can be compatible with general logic chips with various packages and pin definitions;

[0012] ③ Provides an efficient and convenient testing process: users only need to input the chip model on the keyboard to automatically complete the testing of the logic function chip;

[0013] ④ Provide a multi-level, intuitive result prompting solution: By combining an LCD display screen with LED indicator lights, detailed test information can be output simultaneously, improving the human-computer interaction experience;

[0014] ⑤ Provide a low-cost, high-reliability solution for teaching scenarios: create a dedicated teaching device that is cost-effective, easy to operate, and reliable in results, so as to fundamentally solve the pain point of chip verification in teaching experiments and ensure the smooth conduct of experimental teaching.

[0015] To achieve the above objectives, the present invention adopts the following technical solution: a dual-channel general logic chip testing device, comprising a core control unit, a chip testing interface module, a human-machine interaction module, a result indication module, and a power supply module.

[0016] The core control unit uses an STM32F103C8T6 microcontroller to control the dual-channel general logic chip test process, generate test signals, read responses, judge results, and drive the display.

[0017] The chip test interface module includes a multi-channel switch array and a dual-channel A / B universal chip socket. The multi-channel switch array uses a combination of six 74HC4051 chips. The dual-channel A / B universal chip socket uses two 24-pin zero-insertion-force sockets. The chip test interface module is connected to an STM32F103C8T6 microcontroller. Under the control of the microcontroller, the microcontroller's I / O ports are dynamically connected from the multi-channel switch array to different pins of the universal chip socket.

[0018] The human-computer interaction module includes a matrix keyboard and an LCD display screen; wherein, the matrix keyboard is a 4×3 matrix keyboard and the LCD display screen is a 1602 liquid crystal display screen; the human-computer interaction module is connected to an STM32F103C8T6 microcontroller to complete the input, confirmation and display of the model of the chip to be tested, as well as test reminders and test result feedback human-computer interaction;

[0019] The result indication module includes red and green indicator lights for channel A and channel B; each test channel corresponds to a set of red and green indicator lights to provide test result feedback. When the green indicator light is on, it indicates that the chip test has passed; when the red indicator light is on, it indicates that the chip test has failed.

[0020] The power supply module provides stable +5V and GND power to the chip test interface module, human-machine interaction module and result indication module, and provides stable +3.3V and GND power to the core control unit STM32F103C8T6.

[0021] Furthermore, the connection between the chip test interface module and the STM32F103C8T6 microcontroller refers to the connection between the STM32F103C8T6 microcontroller and the multiplexer array, and the connection between the multiplexer array and the universal chip sockets for channels A and B. Specifically, the connection between the STM32F103C8T6 microcontroller and the multiplexer array is as follows:

[0022] PB0(18) of STM32F103C8T6 is connected to the address pin A0(11) of 6 74HC4051 chips;

[0023] PB1(19) of STM32F103C8T6 is connected to the address terminal A1(10) of 6 74HC4051 chips;

[0024] PB2(39) of STM32F103C8T6 is connected to the address pin A2(9) of 6 74HC4051 chips;

[0025] PA8(29) of STM32F103C8T6 is connected to the enable pin E(6) of the first 74HC4051;

[0026] PA9(30) of STM32F103C8T6 is connected to the enable pin E(6) of the second 74HC4051;

[0027] PA10(31) of STM32F103C8T6 is connected to the enable terminal E(6) of the third 74HC4051;

[0028] PA11(32) of STM32F103C8T6 is connected to the enable terminal E(6) of the fourth 74HC4051;

[0029] PA12(33) of STM32F103C8T6 is connected to the enable terminal E(6) of the fifth 74HC4051;

[0030] PA15(38) of STM32F103C8T6 is connected to the enable pin E(6) of the sixth 74HC4051;

[0031] PB10(21) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the first 74HC4051;

[0032] PB11(22) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the second 74HC4051;

[0033] PB12(25) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the third 74HC4051;

[0034] PB13(26) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the fourth 74HC4051;

[0035] PB14(27) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the fifth 74HC4051;

[0036] PB15(28) of STM32F103C8T6 is connected to the common input / output terminal Z(3) of the sixth 74HC4051.

[0037] The multi-channel switch array is connected to the universal chip sockets for channels A and B, as detailed below:

[0038] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the first 74HC4051 are connected to pins 1~8 of the channel A socket in sequence.

[0039] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the second 74HC4051 are connected to pins 9~16 of the channel A socket in sequence.

[0040] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the third 74HC4051 are connected to pins 17~24 of the channel A socket in sequence.

[0041] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the fourth 74HC4051 are connected to pins 1~8 of the channel B socket in sequence.

[0042] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the fifth 74HC4051 are connected to pins 9~16 of the channel B socket in sequence.

[0043] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the sixth 74HC4051 chip are connected to pins 17~24 of the channel B socket in sequence.

[0044] Furthermore, the dynamic connection of the microcontroller's I / O ports to different pins of the universal chip socket via a multiplexer array refers to using time-division multiplexing to ensure that only one output from PA8-12 and 15 of the STM32F103C8T6 microcontroller is low within different microsecond-level time segments. This makes the enable pin of only one 74HC4051 chip active, and then the high and low levels of the microcontroller's PB0-2 outputs are adjusted so that the microcontroller I / O port corresponding to the common input / output terminal Z of the 74HC4051 chip can be connected to the corresponding address pin of a certain channel socket. Specifically, this is expressed as follows:

[0045] When only PA8 outputs a low level among PA8-12 and 15 of STM32F103C8T6, according to the outputs of microcontrollers PB0-2 being '000'-'111' respectively, microcontroller PB10 is connected to pins 1-8 of channel A socket in sequence;

[0046] When only PA9 outputs a low level among PA8-12 and 15 of STM32F103C8T6, according to the outputs of PB0-2 of the microcontroller being '000'-'111' respectively, the microcontroller PB11 is connected to pins 9-16 of channel A socket in sequence;

[0047] When only PA10 outputs a low level among PA8-12 and 15 of STM32F103C8T6, according to the outputs of PB0-2 of the microcontroller being '000'-'111' respectively, the microcontroller PB12 is connected to Pin17-24 of Channel A socket in sequence.

[0048] When only PA11 of PA8-12 and 15 of STM32F103C8T6 is low, according to the outputs of microcontrollers PB0-2 being '000'-'111' respectively, microcontroller PB13 is connected to pins 1-8 of channel B socket in sequence.

[0049] When only PA12 outputs a low level among PA8-12 and 15 of STM32F103C8T6, according to the outputs of PB0-2 of the microcontroller being '000'-'111' respectively, the microcontroller PB14 is connected to pins 9-16 of channel B socket in sequence.

[0050] When only PA15 outputs a low level among PA8-12 and 15 of STM32F103C8T6, according to the outputs of PB0-2 of the microcontroller being '000' to '111' respectively, the microcontroller PB15 is connected to pins 17-24 of channel B socket in sequence.

[0051] Furthermore, the human-computer interaction module is connected to the STM32F103C8T6 microcontroller, meaning that the STM32F103C8T6 microcontroller is connected to the matrix keyboard and the STM32F103C8T6 microcontroller is connected to the LCD display screen.

[0052] The connection between the STM32F103C8T6 microcontroller and the matrix keyboard refers to connecting the PA1-4 pins of the STM32F103C8T6 microcontroller, as output ports, to the four row lines of the matrix keyboard via a series 220Ω resistor, as shown below:

[0053] PA1(11) of STM32F103C8T6 —→ Series 220Ω resistor —→ The first row line of the matrix keyboard;

[0054] PA2(12) of STM32F103C8T6 —→ Series 220Ω resistor —→ The second row line of the matrix keyboard;

[0055] PA3(13) of STM32F103C8T6 —→ Series 220Ω resistor —→ The 3rd row line of the matrix keyboard;

[0056] PA4(14) of STM32F103C8T6 —→ Series 220Ω resistor —→ The 4th row line of the matrix keyboard.

[0057] Additionally, PA5-7 of the STM32F103C8T6 microcontroller are used as input ports, and are connected to the three column lines of the matrix keypad via 4.7kΩ pull-up resistors, as shown below:

[0058] PA5(15) of STM32F103C8T6 ←—Pull-up 4.7kΩ resistor ←—First column line of matrix keyboard;

[0059] PA6(16) of STM32F103C8T6 ←—Pull-up 4.7kΩ resistor ←—Second column line of matrix keyboard;

[0060] PA7(17) of STM32F103C8T6 ←—Pull-up 4.7kΩ resistor ←—3rd column line of matrix keyboard.

[0061] The STM32F103C8T6 microcontroller is connected to the LCD display, as shown in the following details:

[0062] The PB4(40) of the STM32F103C8T6 is connected to the register select input RS(4) of the LCD 1602;

[0063] The STM32F103C8T6's PB5(41) is connected to the LCD 1602's read / write enable pin E(6);

[0064] The PB6 (42) of the STM32F103C8T6 is connected to the bidirectional data bus 4-bit DB4 (11) of the LCD 1602;

[0065] The PB7 (43) of the STM32F103C8T6 is connected to the 5-bit DB5 (12) bidirectional data bus of the LCD 1602;

[0066] The STM32F103C8T6's PB8 (45) is connected to the LCD 1602's bidirectional data bus 6-bit DB6 (13);

[0067] The PB9 (46) of the STM32F103C8T6 is connected to the 7-bit DB7 (14) bidirectional data bus of the LCD 1602.

[0068] A testing method for a dual-channel general-purpose logic chip, based on the aforementioned dual-channel general-purpose logic chip testing apparatus, includes the following steps:

[0069] Step 1: The tester places the two chips under test into the universal chip sockets of channel A and channel B, respectively, with the right side facing each other.

[0070] Step 2: The tester inputs the model number of the chip under test on sockets A and B via the matrix keypad. The user can press the "Cancel" key to undo the input and the "OK" key to save. Once the STM32F103C8T6 microcontroller detects the "OK" key being pressed, it will display the model number of the chip under test on the LCD screen for sockets A and B, and simultaneously locate the pinout diagram of the chip under test internally. A prompt to adjust the power jumper will then appear on the LCD screen.

[0071] For example, if the tester enters "17400274160", it means that the chip under test for channel A is 74LS00 and the chip under test for channel B is 74LS160. After pressing the "OK" button, the LCD screen will display "Channel A: 74LS00, Channel B: 74LS160", and then a new line will appear on the LCD screen displaying "Channel A Getjumper: pin19, Channel B Getjumper: pin20".

[0072] Step 3: Using jumper caps, the tester connects the prompt pins of Channel A and Channel B to the +5V power supply, and then presses the "START" key on the matrix keypad.

[0073] Step 4: The STM32F103C8T6 microcontroller automatically executes the following:

[0074] ◆The microcontroller internally searches for the truth tables and pin definitions of the chip under test in channels A and B;

[0075] ◆The microcontroller controls a multi-channel switch array to test each logic function of the chip under test in channel A and channel B in sequence according to the truth table;

[0076] ◆ Compare the test results of the chip under test in channels A and B with the expected results in the truth table. If they match, the chip in that channel has passed the test; otherwise, the test has failed.

[0077] Step 5: Display the test results:

[0078] If the Channel A chip test passes, the green indicator light for Channel A will illuminate, and the LCD will display "Channel A: PASS"; if the Channel A chip test fails, the red indicator light for Channel A will illuminate, and the LCD will display "Channel A: FAIL".

[0079] If the Channel B chip test passes, the green indicator light for Channel B will illuminate, and the LCD will display "Channel B: PASS"; if the Channel B chip test fails, the red indicator light for Channel B will illuminate, and the LCD will display "Channel B: FAIL".

[0080] Step 6: Wait for the tester to remove the chip before proceeding to the next test.

[0081] Compared with the prior art, the beneficial effects of the present invention are mainly reflected in:

[0082] (1) Increased efficiency: Based on a dual-channel parallel testing architecture, this invention can test two chips at the same time, and the testing efficiency is nearly doubled compared with the traditional single-channel method, thus optimizing the pace of teaching experiments.

[0083] (2) Multi-functional: This invention achieves broad compatibility with various chip models and packages by combining a programmable multiplexer array with a universal socket, completely eliminating the dependence on dedicated adapters and making it highly versatile.

[0084] (3) Intelligent operation: This invention realizes a fully automatic testing process of "plug and test, one-click completion", which eliminates human error and has a very low operation threshold.

[0085] (4) Intuitive feedback: The present invention combines LCD detail display with LED status indication, making human-computer interaction efficient and user-friendly.

[0086] (5) Significant value: This invention solves the core pain point in teaching with low-cost equipment, which not only saves equipment and chip resources, but also guides students to establish scientific verification thinking, and has outstanding teaching and economic value. Attached Figure Description

[0087] Figure 1 This is a system module block diagram of a dual-channel general logic chip testing device according to the present invention;

[0088] Figure 2 This is an external view of the 4×3 matrix keyboard of the present invention;

[0089] Figure 3 This is a block diagram illustrating the principle of a dual-channel general-purpose logic chip testing method according to the present invention. Detailed Implementation

[0090] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that those skilled in the art can better understand the advantages and features of the present invention, thereby making a clearer definition of the scope of protection of the present invention. The embodiments described in this invention are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0091] A dual-channel general-purpose logic chip testing device, as shown in the attached figure. Figure 1As shown, it includes a core control unit, a chip test interface module, a human-machine interaction module, a result indication module, and a power supply module.

[0092] The core control unit uses an STM32F103C8T6 microcontroller to control the dual-channel general logic chip testing process, generate test signals, read responses, judge results, and drive the display.

[0093] The chip test interface module comprises two parts: a multi-channel switch array and a dual-channel (A and B) universal chip socket. The multi-channel switch array uses a combination of six 74HC4051 chips; the dual-channel (A and B) universal chip socket uses two 24-pin zero-insertion-force sockets. The connection between the core control unit (STM32F103C8T6 microcontroller) and the multi-channel switch array (74HC4051 chip combination) is shown in Table 1.

[0094] Table 1. Connection between STM32F103C8T6 microcontroller and 74HC4051 chip combination

[0095]

[0096] The connection between the multi-channel switch array (74HC4051 chipset) and the dual-channel universal chip socket is shown below:

[0097] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the first 74HC4051 ←→ Pins 1~8 of the channel A socket;

[0098] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the second 74HC4051 ←→ Pins 9~16 of the channel A socket;

[0099] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the third 74HC4051 ←→ Pins 17~24 of the channel A socket;

[0100] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the fourth 74HC4051 ←→ Pins 1~8 of the channel B socket;

[0101] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the fifth 74HC4051 ←→ Pins 9~16 of the channel B socket;

[0102] The independent input / output terminals Y0~7 (13-15,12,1,5,2,4) of the 6th chip 74HC4051 ←→ Pins 17~24 of the channel B socket.

[0103] By using time-division multiplexing, only one output from PA8-12 and PA15 of the STM32F103C8T6 microcontroller is set to low level within different microsecond-level time segments, ensuring that only one 74HC4051 chip's enable pin is active. Then, by adjusting the high and low levels of the microcontroller's PB0-2 outputs, the microcontroller I / O port corresponding to the common input / output terminal Z of the 74HC4051 chip can be connected to the corresponding address pin of a specific channel socket, as shown in Table 2.

[0104] Table 2 Dynamic Connections Between Microcontroller I / O Ports and Universal Socket Pins

[0105]

[0106] The human-computer interaction module comprises a 4×3 matrix keypad and a 1602 LCD display, enabling the input, confirmation, and display of the model number of the chip under test, as well as providing test reminders and test result feedback. The layout of the 4×3 matrix keypad is shown in the attached image. Figure 2 The connection between the core control unit (STM32F103C8T6 microcontroller) and the 4x3 matrix keyboard is shown in Table 3:

[0107] Table 3. Connection between STM32F103C8T6 microcontroller and 4x3 matrix keyboard

[0108]

[0109] The connection between the core control unit (STM32F103C8T6 microcontroller) and the LCD 1602 display screen is shown in Table 4:

[0110] Table 4. Connection between STM32F103C8T6 microcontroller and LCD 1602 display screen

[0111]

[0112] The result indication module includes red and green indicator lights for channel A and channel B. Each test channel corresponds to a set of red and green indicator lights, providing the most intuitive feedback on the test results. When the green indicator light is on, it indicates that the chip test has passed; when the red indicator light is on, it indicates that the chip test has failed.

[0113] The power supply module provides stable +5V and GND power to the chip test interface module, human-machine interaction module and result indication module, and provides stable +3.3V and GND power to the core control unit STM32F103C8T6.

[0114] A test method for a dual-channel general-purpose logic chip, as shown in the appendix. Figure 3 As shown, it includes the following steps:

[0115] Step 1: The tester places the two chips under test into the universal chip sockets of channel A and channel B, respectively, with the right side facing each other.

[0116] Step 2: The tester inputs the model number of the chip under test on sockets A and B via the matrix keypad. The user can press the "Cancel" key to undo the input and the "OK" key to save. Once the STM32F103C8T6 microcontroller detects the "OK" key being pressed, it will display the model number of the chip under test on the LCD screen for sockets A and B, and simultaneously locate the pinout diagram of the chip under test internally. A prompt to adjust the power jumper will then appear on the LCD screen.

[0117] For example, if the tester enters "17400274160", it means that the chip under test for channel A is 74LS00 and the chip under test for channel B is 74LS160. After pressing the "OK" button, the LCD screen will display "Channel A: 74LS00, Channel B: 74LS160", and then a new line will appear on the LCD screen displaying "Channel A Getjumper: pin19, Channel B Getjumper: pin20".

[0118] Step 3: Using jumper caps, the tester connects the prompt pins of Channel A and Channel B to the +5V power supply, and then presses the "START" key on the matrix keypad.

[0119] Step 4: The STM32F103C8T6 microcontroller automatically executes the following:

[0120] ◆The microcontroller internally searches for the truth tables and pin definitions of the chip under test in channels A and B;

[0121] ◆The microcontroller controls a multi-channel switch array to test each logic function of the chip under test in channel A and channel B in sequence according to the truth table;

[0122] ◆ Compare the test results of the chip under test in channels A and B with the expected results in the truth table. If they match, the chip in that channel has passed the test; otherwise, the test has failed.

[0123] Step 5: Display the test results:

[0124] If the Channel A chip test passes, the green indicator light for Channel A will illuminate, and the LCD will display "Channel A: PASS"; if the Channel A chip test fails, the red indicator light for Channel A will illuminate, and the LCD will display "Channel A: FAIL".

[0125] If the Channel B chip test passes, the green indicator light for Channel B will illuminate, and the LCD will display "Channel B: PASS"; if the Channel B chip test fails, the red indicator light for Channel B will illuminate, and the LCD will display "Channel B: FAIL".

[0126] Step 6: Wait for the tester to remove the chip before proceeding to the next test.

[0127] Example:

[0128] Considering that the two chips to be tested are 74LS20 and 74LS160, the testing method for the dual-channel general-purpose logic chip of this invention has the following steps:

[0129] Step 1: The tester places the 74LS20 and 74LS160 chips into the universal chip sockets of channels A and B, respectively, with the right side facing each other.

[0130] Step 2: The tester enters "17420274160" through the matrix keypad and presses the "OK" key to save; the LCD screen displays "Channel A:74LS20, Channel B:74LS160", and then the LCD screen displays a reminder to adjust the power jumper cap "Channel A Getjumper:pin19, Channel B Getjumper:pin20".

[0131] Step 3: Using jumper caps, the user connects the prompt pins of Channel A and Channel B to the +5V power supply, and then presses the "START" key on the matrix keypad.

[0132] Step 4: The STM32F103C8T6 microcontroller automatically performs the following tests on the 74LS20 chip on channel A:

[0133] ◆The microcontroller internally searches for the truth table and pin definitions of the 74LS20 chip on channel A.

[0134] ◆The microcontroller controls the multiplexer array and tests each logic function of the first group of four-input NAND gates of the 74LS20 chip on channel A according to the truth table.

[0135] First, set the inputs (1A=0, 1B=0, 1C=0, 1D=0), and read the output (1Y) of the 4-input NAND gate. The specific steps are as follows:

[0136] Step F41. Assign value to pin 1A: Locate pin 1A connected to Y5 of the first 4051 chip, set PA8 of the STM32F103C8T6 microcontroller to low level (the first 4051 chip is selected), PB0~2 output level is '101' (corresponding to Y5), PB10 (corresponding to Z of the first 4051 chip) outputs low level, then the input of pin 1A of the chip under test is low level.

[0137] Step F42. Assign value to pin 1B: Locate pin 1B connected to Y6 of the first 4051 chip, set PA8 of the STM32F103C8T6 microcontroller to output low level (the first 4051 chip is selected), PB0~2 output level is '110' (corresponding to Y6), PB10 (corresponding to Z of the first 4051 chip) outputs low level, then the input of pin 1B of the chip under test is low level.

[0138] Step F43. Assign value to pin 1C: Locate pin 1C connected to Y0 of the second 4051 chip, set PA9 of the STM32F103C8T6 microcontroller to output low level (the second 4051 chip is selected), PB0~2 output level is '000' (corresponding to Y0), PB11 (corresponding to Z of the second 4051 chip) outputs low level, then the pin 1C input of the chip under test is low level.

[0139] Step F44. Assign value to 1D pin: Locate the Y1 pin connected to the second 4051 chip, set the PA9 output of the STM32F103C8T6 microcontroller to low level (the second 4051 chip is selected), the output level of PB0~2 to '001' (corresponding to Y1), and the output level of PB11 (corresponding to Z of the second 4051 chip) to low level. Then the 1D pin input of the chip under test will be low level.

[0140] Step F45. Read the 1Y pin: Locate the 1Y pin connected to Y2 of the second 4051 chip. Set the PA9 output of the STM32F103C8T6 microcontroller to low level (the second 4051 chip is selected), set the output levels of PB0~2 to '010' (corresponding to Y2), and set PB11 (corresponding to Z of the second 4051 chip) to high-impedance input mode. Read the level. If a high level is read, the combination is correct, continue to the next step;

[0141] Otherwise, end the test in step 4.

[0142] Then, iterate through the other 15 input combinations in the truth table: (0,0,0,1), (0,0,1,0), (0,0,1,1), (0,1,0,0), (0,1,0,1), (0,1,1,0), (0,1,1,1), (1,0,0,0), (1,0,0,1), (1,0,1,0), (1,0,1,1), (1,1,0,0), (1,1,0,1), (1,1,1,0), (1,1,1,1), (1,1,1,1), following steps similar to F41 to F45, and verify the 1Y output.

[0143] ◆The microcontroller controls the multiplexer array and tests each logic function of the second group of four-input NAND gates of the 74LS20 chip on channel A according to the truth table.

[0144] First, set the inputs (2A=0, 2B=0, 2C=0, 2D=0), and read the output (2Y) of the 4-input NAND gate. The specific steps are as follows:

[0145] Step S41. Assign value to pin 2A: Locate pin 2A connected to Y1 of the third 4051 chip, set PA10 of the STM32F103C8T6 microcontroller to low level (the third 4051 chip is selected), set PB0~2 output level to '001' (corresponding to Y1), and PB12...

[0146] If the Z pin of the chip under test (corresponding to the third 4051 chip) outputs a low level, then the 2A pin input of the chip under test will be low.

[0147] Step F42. Assign value to pin 2B: Locate pin 2B connected to Y0 of the third 4051 chip, set PA10 of the STM32F103C8T6 microcontroller to low level (the third 4051 chip is selected), set PB0~2 output level to '000' (corresponding to Y0), and PB12...

[0148] If the Z pin of the chip under test (corresponding to the third 4051 chip) outputs a low level, then the 2B pin input of the chip under test will be low.

[0149] Step S43. Assign value to pin 2C: Locate pin 2C connected to Y6 of the second 4051 chip, set PA9 of the STM32F103C8T6 microcontroller to output low level (second 4051 chip selected), PB0~2 output level to '110' (corresponding to Y6), PB11 (corresponding to Z of the second 4051 chip) output low level, then the input of pin 2C of the chip under test is low level.

[0150] Step S44. Assign 2D pin: Locate the 2D pin connected to Y5 of the second 4051 chip, set PA9 of the STM32F103C8T6 microcontroller to output low level (the second 4051 chip is selected), PB0~2 output level is '101' (corresponding to Y5), PB11 (corresponding to Z of the second 4051 chip) outputs low level, then the 2D pin input of the chip under test is low level.

[0151] Step S45. Read the 2Y pin: Locate the 2Y pin connected to Y4 of the second 4051 chip. Set the PA9 output of the STM32F103C8T6 microcontroller to low level (the second 4051 chip is selected), set the output levels of PB0~2 to '100' (corresponding to Y4), and set PB11 (corresponding to Z of the second 4051 chip) to high-impedance input mode. Prepare to read the level. If a high level is read, the combination is correct, and continue to the next step; otherwise, end the test in step 4.

[0152] Then, iterate through the other 15 input combinations in the truth table: (0,0,0,1), (0,0,1,0), (0,0,1,1), (0,1,0,0), (0,1,0,1), (0,1,1,0), (0,1,1,1), (1,0,0,0), (1,0,0,1), (1,0,1,0), (1,0,1,1), (1,1,0,0), (1,1,0,1), (1,1,1,0), (1,1,1,1), (1,1,1,1), following steps similar to S41-5, to verify the 2Y output. If all input combinations tested in the truth table are correct, the 74LS20 chip on channel A passes the test.

[0153] Step 5. The STM32F103C8T6 microcontroller automatically performs the test on the 74LS160 chip on channel B:

[0154] ◆The microcontroller internally searches for the truth table and pin definitions of the 74LS160 chip on channel B (CR:1, CP:2, D0~D3:3~6, EP:7,

[0155] LD:9, ET:10, Q3~Q0:11~14, CO:15).

[0156] ◆The microcontroller controls the multiplexer array and tests each logic function of the 74LS160 chip on channel B according to the truth table.

[0157] Step S51. Asynchronous Clear Function Test

[0158] Assigning a value to the CR pin is at a low level. (Set the microcontroller's PA11 output to low level, PB0~2 output to '100', and PB13 output to low level).

[0159] Then read whether the Q3~Q0 pins are '0000'. (Set the microcontroller PA12 output to low level and PB0~2 output level to '110', then read whether PB14 is low level; set the microcontroller PA12 output to low level and PB0~2 output level to '111', then read whether PB14 is low level; set the microcontroller PA15 output to low level and PB0~2 output level to '000', then read whether PB15 is low level; set the microcontroller PA15 output to low level and PB0~2 output level to '001', then read whether PB15 is low level). If all reads are low level, the asynchronous clear function is normal; otherwise, end the test in step 5.

[0160] Step S52. Synchronous Parallel Data Setting Function Test

[0161] Assigning a value to the CR pin at a high level (Set the microcontroller's PA11 output to low level, PB0~2 output to '100', and PB13 output to high level.) Assign a low level to the LD pin. (Set the microcontroller's PA12 output to low level, PB0~2 output to '100', and PB14 output to low level).

[0162] Assign the values ​​'1000' to pins D3 through D0. (Set microcontroller PA12 to low level, PB0-2 to '001', and PB14 to high level; set microcontroller PA12 to low level, PB0-2 to '000', and PB14 to low level; set microcontroller PA11 to low level, PB0-2 to '111', and PB13 to low level; set microcontroller PA11 to low level, PB0-2 to '110', and PB13 to low level).

[0163] Generate a clock rising edge (Set the microcontroller PA11 output to low level and PB0~2 output to '101'. First set PB13 output to low level, then set PB13 output to high level, and then set PB13 output to low level again.)

[0164] Then read whether pins Q3 to Q0 are '1000'. (Set the microcontroller's PA12 output to low level and PB0-2 output levels to '110', then read whether PB14 is high level; set the microcontroller's PA12 output to low level and PB0-2 output levels to '111', then read whether PB14 is low level; set the microcontroller's PA15 output to low level and PB0-2 output levels to '000', then read whether PB15 is low level; set the microcontroller's PA15 output to low level and PB0-2 output levels to '001', then read whether PB15 is low level), and Read if the CO pin is low.(Set the microcontroller's PA15 output to low level and PB0~2 output levels to '010', then read whether PB15 is low). If the readings are correct, the synchronous parallel data setting function is normal; otherwise, end the test in step 5.

[0165] Step S53. Decimal addition counting function test

[0166] Set the LD pin to high level. (Set the microcontroller's PA12 output to low level, PB0~2 output levels to '100', and PB14 output to high level). Assign a high level to the EP pin. (Set the microcontroller's PA12 output to low level, PB0~2 output levels to '010', and PB14 output to high level). Set the ET pin to high level. (Set the microcontroller's PA12 output to low level, PB0~2 output to '101', and PB14 output to high level).

[0167] Generate a clock rising edge (Set the microcontroller PA11 output to low level and PB0~2 output to '101'. First set PB13 output to low level, then set PB13 output to high level, and then set PB13 output to low level again.) Read Q3~Q0 Is the foot '1001'?

[0168] (Set the microcontroller's PA12 output to low level and PB0~2 output levels to '110', then read whether PB14 is high level; set the microcontroller's PA12 output to low level and PB0~2 output levels to '111', then read whether PB14 is low level; set the microcontroller's PA15 output to low level and PB0~2 output levels to '000', then read whether PB15 is low level; set the microcontroller's PA15 output to low level and PB0~2 output levels to '001', then read whether PB15 is high level.) And the CO pin should be at a high level. (Set the microcontroller PA15 output to low level, PB0~2)

[0169] The output level is '010'. Check if PB15 is high. If the reading is correct, continue testing; otherwise, end step 5.

[0170] Generate another clock rising edge (Set the microcontroller PA11 output to low level and PB0~2 output to '101'. First set PB13 output to low level, then set PB13 output to high level, and then set PB13 output to low level again.) Read Q3~Q0 Is the pin '0000'?

[0171] (Set the microcontroller's PA12 output to low level and PB0~2 output levels to '110', then read whether PB14 is low level; set the microcontroller's PA12 output to low level and PB0~2 output levels to '111', then read whether PB14 is low level; set the microcontroller's PA15 output to low level and PB0~2 output levels to '000', then read whether PB15 is low level; set the microcontroller's PA15 output to low level and PB0~2 output levels to '001', then read whether PB15 is low level.) And the CO pin should be at a low level. (Set the microcontroller PA15 output to low level, PB0~2)

[0172] The output level is '010'. Check if PB15 is low. If the reading is correct, the decimal addition counting function is normal; otherwise, end the test in step 5.

[0173] Step S54. Retention Function Test

[0174] Assign a low level to the EP pin. (Set the microcontroller's PA12 output to low level, PB0~2 output levels to '010', and PB14 output to low level), or Assign a low level to the ET pin. (Set the microcontroller PA12 output to low level, PB0~2 output to '101', and PB14 output to low level).

[0175] Generate a clock rising edge (Set the microcontroller PA11 output to low level and PB0~2 output to '101'. First set PB13 output to low level, then set PB13 output to high level, and then set PB13 output to low level again.)

[0176] Then Check if pins Q3 to Q0 are '0000' (Set microcontroller PA12 output to low level and PB0-2 output level to '110', then read if PB14 is low level; set microcontroller PA12 output to low level and PB0-2 output level to '111', then read if PB14 is low level; set microcontroller PA15 output to low level and PB0-2 output level to '000', then read if PB15 is low level; set microcontroller PA15 output to low level and PB0-2 output level to '001', then read if PB15 is low level). If all reads are correct, the function remains normal, indicating that the 74LS160 chip on channel B has passed the test.

[0177] Step 6. Display the test results

[0178] If the Channel A chip test passes, the green indicator light for Channel A will illuminate, and the LCD will display "Channel A: PASS"; if the Channel A chip test fails, the red indicator light for Channel A will illuminate, and the LCD will display "Channel A: FAIL".

[0179] If the Channel B chip test passes, the green indicator light for Channel B will illuminate, and the LCD will display "Channel B: PASS"; if the Channel B chip test fails, the red indicator light for Channel B will illuminate, and the LCD will display "Channel B: FAIL".

[0180] Step 7. Wait for the tester to remove the chip so that the next test can begin.

[0181] In summary, this invention achieves dual-channel parallel automated testing, which has the advantages of high efficiency, strong versatility, and simple operation. It effectively solves the problem of blindly replacing chips and low testing efficiency caused by the lack of convenient testing tools in teaching experiments.

[0182] The descriptions and practices disclosed in this invention are readily apparent and understandable to those skilled in the art, and various modifications and refinements can be made without departing from the principles of this invention. Therefore, any modifications or improvements made without departing from the spirit of this invention should also be considered within the scope of protection of this invention.

Claims

1. A dual channel universal logic chip testing apparatus, characterized by, The core control unit, the chip test interface module, the man-machine interaction module, the result indication module and the power module are included. The core control unit uses an STM32F103C8T6 single-chip microcomputer, is responsible for controlling the double-channel general logic chip test process, generating test signals, reading responses, judging results and driving display. The chip test interface module includes a multi-way switch array and A and B double-channel universal chip sockets; the multi-way switch array is composed of six 74HC4051 chips; the A and B double-channel universal chip sockets adopt two 24Pin zero-insertion force sockets; the chip test interface module is connected with the STM32F103C8T6 single-chip microcomputer, and under the control of the single-chip microcomputer, the I / O port of the single-chip microcomputer is dynamically connected to different pins of the universal chip socket through the multi-way switch array; The man-machine interaction module includes a matrix keyboard and an LCD display screen; the matrix keyboard adopts a 4*3 matrix keyboard, and the LCD display screen adopts a 1602 liquid crystal display screen; the man-machine interaction module is connected with the STM32F103C8T6 single-chip microcomputer, and the input, determination and display of the chip to be tested, test reminding and test result feedback man-machine interaction are completed. The result indication module includes red and green indicator lights of the A channel and red and green indicator lights of the B channel; each test channel corresponds to a set of red and green indicator lights, and test result feedback is provided; when the green indicator light is on, it indicates that the chip test is passed; when the red indicator light is on, it indicates that the chip test is failed. The power module provides stable +5V and GND power supply for the chip test interface module, the man-machine interaction module and the result indication module, and provides stable +3.3V and GND power supply for the core control unit STM32F103C8T6.

2. A dual channel universal logic chip testing apparatus according to claim 1, wherein: The chip test interface module is connected with the STM32F103C8T6 single-chip microcomputer, which means that the STM32F103C8T6 single-chip microcomputer is connected with the multi-way switch array, and the multi-way switch array is connected with the A and B channel universal chip sockets; wherein the STM32F103C8T6 single-chip microcomputer is connected with the multi-way switch array, and the specific connection is as follows: PB0 (18) of the STM32F103C8T6 is connected with the address end A0 (11) of the six 74HC4051 chips; PB1 (19) of the STM32F103C8T6 is connected with the address end A1 (10) of the six 74HC4051 chips; PB2 (39) of the STM32F103C8T6 is connected with the address end A2 (9) of the six 74HC4051 chips; PA8 (29) of the STM32F103C8T6 is connected with the enable end E (6) of the first 74HC4051 chip; PA9 (30) of the STM32F103C8T6 is connected with the enable end E (6) of the second 74HC4051 chip; PA10 (31) of the STM32F103C8T6 is connected with the enable end E (6) of the third 74HC4051 chip; PA11 (32) of the STM32F103C8T6 is connected with the enable end E (6) of the fourth 74HC4051 chip; PA12 (33) of STM32F103C8T6 is connected with the enable end E (6) of the 5th piece 74HC4051; PA15 (38) of STM32F103C8T6 is connected with the enable end E (6) of the 6th piece 74HC4051; PB10 (21) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 1st piece 74HC4051; PB11 (22) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 2nd piece 74HC4051; PB12 (25) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 3rd piece 74HC4051; PB13 (26) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 4th piece 74HC4051; PB14 (27) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 5th piece 74HC4051; PB15 (28) of STM32F103C8T6 is connected with the common input / output end Z (3) of the 6th piece 74HC4051; Wherein, the multi-way switch array is connected with the A, B channel universal chip socket, and the specific representation is as follows: The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 1st piece 74HC4051 are connected with Pin1~8 of the channel A socket in sequence; The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 2nd piece 74HC4051 are connected with Pin9~16 of the channel A socket in sequence; The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 3rd piece 74HC4051 are connected with Pin17~24 of the channel A socket in sequence; The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 4th piece 74HC4051 are connected with Pin1~8 of the channel B socket in sequence; The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 5th piece 74HC4051 are connected with Pin9~16 of the channel B socket in sequence; The independent input / output ends Y0~7 (13-15, 12, 1, 5, 2, 4) of the 6th piece 74HC4051 are connected with Pin17~24 of the channel B socket in sequence.

3. The dual channel universal logic chip testing apparatus of claim 1, wherein: The dynamic connection of the I / O port of the single-chip microcomputer to the different pins of the universal chip socket through the multi-way switch array refers to that, in different microsecond time segments, only one of the PA8~12, 15 of the STM32F103C8T6 single-chip microcomputer outputs low level, so that only the enable end of the 74HC4051 chip is effective, and then the high and low levels of the PB0~2 of the single-chip microcomputer are adjusted, so that the common input / output end Z of the 74HC4051 chip is connected to the corresponding address pin of the channel socket, and the specific representation is as follows: When only PA8 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB10 is connected to Pin1~8 of channel A socket in turn; When only PA9 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB11 is connected to Pin9~16 of channel A socket in turn; When only PA10 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB12 is connected to Pin17~24 of channel A socket in turn; When only PA11 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB13 is connected to Pin1~8 of channel B socket in turn; When only PA12 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB14 is connected to Pin9~16 of channel B socket in turn; When only PA15 in PA8~12, 15 of STM32F103C8T6 outputs low level, according to the output of single-chip microcomputer PB0~2 is 000~111 respectively, single-chip microcomputer PB15 is connected to Pin17~24 of channel B socket in turn.

4. The dual channel universal logic chip testing apparatus of claim 1, wherein: The man-machine interaction module is connected with the STM32F103C8T6 single-chip microcomputer, which means that the STM32F103C8T6 single-chip microcomputer is connected with the matrix keyboard and the LCD display screen; In the connection between the STM32F103C8T6 single-chip microcomputer and the matrix keyboard, PA1~4 of the STM32F103C8T6 single-chip microcomputer are used as output ports and are connected with four row line ports of the matrix keyboard in series with 220Ω resistors, which is represented as follows: PA1 (11) of STM32F103C8T6--→220Ω resistor in series--→the first row line of the matrix keyboard; PA2 (12) of STM32F103C8T6--→220Ω resistor in series--→the second row line of the matrix keyboard; PA3 (13) of STM32F103C8T6--→220Ω resistor in series--→the third row line of the matrix keyboard; PA4 (14) of STM32F103C8T6--→220Ω resistor in series--→the fourth row line of the matrix keyboard; In addition, PA5~7 of the STM32F103C8T6 single-chip microcomputer are used as input ports and are connected with three column line ports of the matrix keyboard through 4.7kΩ pull-up resistors, which is represented as follows: PA5 (15) of STM32F103C8T6←—4.7kΩ resistor for pull-up←—1st column line of matrix keyboard; PA6 (16) of STM32F103C8T6←—4.7kΩ resistor for pull-up←—2nd column line of matrix keyboard; PA7 (17) of STM32F103C8T6←—4.7kΩ resistor for pull-up←—3rd column line of matrix keyboard; Wherein, the STM32F103C8T6 single-chip microcomputer is connected with the LCD display screen, and the specific representation is as follows: PB4 (40) of STM32F103C8T6 is connected with register selection input end RS (4) of LCD 1602; PB5 (41) of STM32F103C8T6 is connected with read-write enable end E (6) of LCD 1602; PB6 (42) of STM32F103C8T6 is connected with bidirectional data bus 4 bits DB4 (11) of LCD 1602; PB7 (43) of STM32F103C8T6 is connected with bidirectional data bus 5 bits DB5 (12) of LCD 1602; PB8 (45) of STM32F103C8T6 is connected with bidirectional data bus 6 bits DB6 (13) of LCD 1602; PB9 (46) of STM32F103C8T6 is connected with bidirectional data bus 7 bits DB7 (14) of LCD 1602.

5. A method for testing a dual-channel general logic chip, based on the dual-channel general logic chip testing device of any one of claims 1-4, characterized in that, Comprise the following steps: Step 1, the tester will be two pieces of chip to be tested respectively right into the channel A and channel B universal chip socket; Step 2, the tester inputs the channel A, B socket through the matrix keyboard respectively the chip model to be tested, and simultaneously presses the cancel key to cancel this input, and the determination key is saved; once the STM32F103C8T6 single-chip microcomputer detects that the determination key is pressed, the channel A, B socket can display the chip model to be tested on the LCD liquid crystal screen, and simultaneously internally searches the pin structure diagram of the chip to be tested, and then displays the prompt of adjusting the power jump cap on the LCD liquid crystal screen; Step 3, through the jump cap, the tester connects the prompt pin of channel A and channel B to +5V power supply, and then presses the START key of the matrix keyboard; Step 4, the STM32F103C8T6 single-chip microcomputer automatically executes as follows: ◆ the single-chip microcomputer internally searches the truth table and pin definition of the channel A and channel B chip to be tested; ◆ the single-chip microcomputer controls the multi-way switch array, and tests each logic function of the channel A and channel B chip to be tested in turn according to the truth table; ◆ the test result of the channel A and channel B chip to be tested is compared with the expected result of the truth table, if consistent, the channel chip test passes, otherwise, the test fails; Step 5, the test result is displayed; If the channel A chip test passes, the green indicator light of channel A is lit, and the LCD displays Channel A: PASS; if the channel A chip test fails, the red indicator light of channel A is lit, and the LCD displays Channel A: FAIL; If the Channel B chip test passes, the green indicator light of Channel B is lit up, and the LCD displays Channel B: PASS; if the Channel B chip test fails, the red indicator light of Channel B is lit up, and the LCD displays Channel B: FAIL; Step 6, wait for the tester to remove the chip and proceed to the next test.

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