Display device and display panel

Abstract

The invention provides a display device and a display panel, and belongs to the technical field of display driving. The display panel comprises a first power line, a second power line, a third power line and a plurality of pixel units arranged in an array, wherein each pixel unit comprises a light-emitting device and a pixel driving circuit; the pixel driving circuit comprises a first transistor, a first reset sub-circuit and a first capacitor; the first reset sub-circuit is used for resetting the anode of the light-emitting device according to the reset signal transmitted by the third power line; the first transistor and the light-emitting device are sequentially connected in series between the first power line and the second power line; the control electrode of the first transistor and the first end of the first capacitor are connected to a first node; the second end of the first capacitor is connected with the third power line, and the first capacitor maintains the potential of the first node based on the reset signal, so that the potential of the first node is kept stable in the display period. Therefore, display anomalies such as color cast and the like can be avoided on the premise of not additionally arranging a signal line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a display device and a display panel. BACKGROUND

[0002] Low-frequency refresh mode is one of the solutions of low-power function of display devices. The low-frequency refresh mode reduces the number of pixel data updates in unit time by reducing the refresh frequency of the picture (for example, below 30Hz), thereby significantly reducing the working power consumption of the driving chip and the pixel circuit. The low-frequency refresh mode is widely used in mobile terminals such as smart phones, tablet computers, notebook computers, and the like. In particular, in static picture display scenarios, such as reading e-books, displaying pictures, and the like, the low-frequency refresh mode can effectively prolong the battery life. At present, in the low-frequency refresh mode, the complete display period of a frame of image is composed of two parts of refresh frame and holding frame. The refresh frame is a data writing stage, and the driving circuit transmits new image data to the pixel array to control the light-emitting state of each pixel, thereby completing the update of a frame of picture. The holding frame is a picture maintaining stage. In order to ensure the visual continuity of the picture, new data writing is not performed, the pixel array needs to maintain the light-emitting state set in the refresh frame stage, and the potential of the data writing node of the pixel circuit is maintained stable until the next refresh frame. The holding time of the holding frame will be prolonged with the reduction of the refresh frequency. For example, when the refresh frequency is reduced from 60Hz to 15Hz, the total time of a frame is prolonged from about 16.7ms to 66.7ms.

[0003] However, with the prolongation of the holding frame time, the data writing node of the pixel circuit is easily affected by the inherent leakage current of the thin film transistor, the capacitor and the like, so that the potential of the data writing node drifts in the holding frame, resulting in color deviation of the displayed image. SUMMARY

[0004] Embodiments of the present application provide a display device and a display panel to at least partially solve the above technical problems.

[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, a display device is provided, comprising a first power line, a second power line, a third power line and a plurality of pixel units arranged in an array, the pixel unit comprising a light-emitting device and a pixel driving circuit; The pixel driving circuit comprises a first transistor, a first reset sub-circuit and a first capacitor; The first reset sub-circuit is connected with the anode of the light-emitting device and the third power line respectively, and is configured to reset the anode of the light-emitting device according to a reset signal transmitted by the third power line; The first transistor and the light-emitting device are connected in series between the first power line and the second power line; the control electrode of the first transistor is connected to the first terminal of the first capacitor at the first node; the second terminal of the first capacitor is connected to the third power line. Specifically, during at least one hold frame in the display cycle of an image frame, the first capacitor maintains the potential of the first node based on the reset signal, thereby keeping the potential of the first node stable during the display cycle.

[0006] Optionally, the display cycle further includes a refresh frame, in which the first reset sub-circuit is connected to a reset signal with an amplitude of a reference amplitude via the third power line.

[0007] Optionally, during at least one of the hold frames in the display period of the frame image, the first capacitor is connected to a reset signal with an amplitude of a target amplitude via the third power line; wherein the reference amplitude and the target amplitude are different.

[0008] Optionally, the hold frame includes a hold phase in which the amplitude of the reset signal connected to the first capacitor via the third power line is different during the hold phase of at least two hold frames in the display cycle.

[0009] Optionally, the holding frame further includes a reset phase, during which the first reset sub-circuit is connected to the reset signal with an amplitude of the reference amplitude via the third power line.

[0010] Optionally, the first reset sub-circuit includes a second transistor; The second transistor includes a control electrode for receiving a reset control signal, a first electrode connected to the third power line, and a second electrode connected to the anode of the light-emitting device. In this process, the second transistor is turned on under the drive of the reset control signal during the reset phase of the refresh frame and the reset phase of the hold frame, so as to reset the anode of the light-emitting device by the reset signal of the reference amplitude.

[0011] Optionally, the pixel driving circuit further includes a writing sub-circuit, a light-emitting sub-circuit, a connection sub-circuit, a second reset sub-circuit, and a second capacitor; The write sub-circuit is connected to the first electrode of the first transistor at the second node, and the connection sub-circuit is connected to the second electrode of the first transistor at the third node and connected to the first node. The light-emitting sub-circuit is connected in series between the first power line and the second power line to control the light emission of the light-emitting device; The second reset sub-circuit is connected to the first node and is used to reset the first node; The second capacitor is connected between the first power line and the first node, and is used to store the data signal accessed by the write sub-circuit.

[0012] Optionally, the writing sub-circuit includes a third transistor, the light-emitting sub-circuit includes a fourth transistor and a fifth transistor, the connection sub-circuit includes a sixth transistor, and the second reset sub-circuit includes a seventh transistor; The third transistor includes a first electrode for receiving data signals, a second electrode connected to the second node, and a control electrode for receiving scan signals; The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the second node, and a control electrode for receiving a light emission control signal; The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the light-emitting device, and a control electrode for receiving the light-emitting control signal; The sixth transistor includes a first electrode connected to the third node, a second electrode connected to the first node, and a control electrode for receiving the scan signal; The seventh transistor includes a first electrode for receiving the gate reset voltage, a second electrode connected to the second node, and a control electrode for receiving the gate reset signal.

[0013] Optionally, it also includes a gate driver and a source driver; The gate driver is used to output a scan signal within the refresh frame to control the writing sub-circuit and the connection sub-circuit to be turned on. The source driver is used to output a data signal within the refresh frame, so that the data signal is transmitted to the second capacitor through the writing sub-circuit, the first transistor and the connection sub-circuit to complete the writing of the data signal.

[0014] According to a second aspect of this application, a display panel is provided, including a first power line, a second power line, a third power line, and a plurality of pixel units arranged in an array, wherein the pixel unit includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a first transistor, a first reset circuit, and a first capacitor; The first reset circuit is connected to the anode of the light-emitting device and the third power line respectively, and is used to reset the anode of the light-emitting device according to the reset signal transmitted by the third power line. The first transistor and the light-emitting device are connected in series between the first power line and the second power line; the control electrode of the first transistor is connected to the first terminal of the first capacitor at the first node; the second terminal of the first capacitor is connected to the third power line. In one of the at least one hold frames in the display cycle of an image frame, the first capacitor maintains the potential of the first node based on a reset signal, so that the potential of the first node remains stable in the display cycle.

[0015] In summary, in this application, the light-emitting device and the first transistor between the first power line, the second power line, and the first power line form the light-emitting path of the pixel. The different currents in the light-emitting path are caused by the conduction degree of the first transistor, thereby enabling the light-emitting device to emit light at the correct brightness. The first reset circuit can reset the anode of the light-emitting device according to the reset signal of the third power line, ensuring that the initial state of the light-emitting device remains consistent. At the same time, the third power line and the first node are connected through the first capacitor, thereby multiplexing the reset signal transmitted on the third power line to stabilize the potential of the first node within the holding frame. This avoids large leakage current of the first node due to excessively long holding frame duration. Thus, without adding any signal lines, the potential of the first node can be ensured to remain stable within the display cycle, avoiding display abnormalities such as color shift.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a timing diagram of low-frequency display achieved through frame interpolation in related technologies; Figure 2 This is an architecture diagram of pixel circuits in related technologies; Figure 3 This is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 4 This is a timing diagram of the pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 5This is a schematic diagram illustrating the determination of the reset signal amplitude provided in an exemplary embodiment of this disclosure; Figure 6 This is a circuit diagram of the pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of a display device provided in an exemplary embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures: 10, pixel unit; 20, power management chip; 30, gate driver; 40, data driver; VDD, first power supply voltage; VSS, second power supply voltage; VI_ANO, reset signal; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; Cst1, first capacitor; Cst2, second capacitor. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] First, based on the content in the background section, the background of this application will be further elaborated. (Refer to...) Figure 1 , Figure 1This example demonstrates low-frequency display achieved through frame interpolation. Frame interpolation refers to using the base frequency as the smallest time unit, combining one frame of data refresh with multiple frames of image retention to achieve a low-frequency refresh effect. Taking a display device with a base frequency of 120Hz as an example, the basic duration of each frame is the base frequency frame, which is approximately 8.33ms (1s / 120Hz). In base frequency display, there are no retention frames; each base frequency frame is refreshed. In low-frequency mode, the complete display period of one frame is an integer multiple of the duration of the base frequency frame. The first base frequency frame is the refresh frame, and all subsequent base frequency frames are retention frames. During refresh frames, data is written via a scan signal, while during retention frames, the scan signal does not output a valid pulse, so no data is written, maintaining the pixel state of the refresh frame. The number of retention frames is inversely proportional to the target low frequency; specifically, the number of retention frames can be expressed as (base frequency / target low frequency) - 1. Continuing with the 120Hz base frequency as an example, when the target low frequency is 60Hz, the display cycle of one frame includes one refresh frame and one hold frame, both of which are 8.33ms. However, when the target low frequency is 10Hz, the display cycle of one frame includes one refresh frame and eleven hold frames, with a total hold frame duration of 11 × 8.33ms ≈ 91.63ms. Therefore, in low-frequency displays, the lower the target low frequency, the more hold frames there are, and the longer the total hold frame duration. As the hold frame duration increases, the leakage current at node N in the pixel circuit continues to act for a longer period, resulting in more severe potential drift and ultimately causing abnormalities such as color shift in the display effect.

[0023] Reference Figure 2 Currently, to address the issue of potential drift at data write node N, a storage capacitor Cst can be installed at data write node N, connected to an independent power line Data_scan. When the display device experiences brightness changes due to potential fluctuations while maintaining a frame, the voltage transmitted on the power line Data_scan can be adjusted accordingly, changing the potential of data write node N through the coupling effect of the storage capacitor Cst. For example, when the display brightness decreases, if the driving transistor Tr is an N-type device, the voltage transmitted on the power line Data_scan can be increased to compensate for the potential drop at data write node N caused by leakage current. Alternatively, if the driving transistor Tr is a P-type device, its threshold voltage may drift positively during long-term driving, causing a potential drop at data write node N and resulting in an abnormal increase in display brightness. In this case, the voltage transmitted on the power line Data_scan can also be adjusted to compensate for the potential of data write node N, avoiding color shift caused by an abnormal drop in the potential of data write node N. However, the above methods require an independent power line Data_scan, increasing costs. Based on this, the technical solution of this application is proposed.

[0024] According to the first aspect of this application, referring to Figure 3 This disclosure provides a display device including a first power line, a second power line, a third power line, and a plurality of pixel units 10 arranged in an array. Each pixel unit 10 includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a first transistor T1, a first reset circuit, and a first capacitor Cst1. The first reset circuit is connected to the anode of the light-emitting device and the third power line, respectively, and is used to reset the anode of the light-emitting device according to a reset signal VI_ANO transmitted from the third power line. The first transistor T1 and the light-emitting device are connected in series between the first power line and the second power line. The control electrode of the first transistor T1 is connected to the first terminal of the first capacitor Cst1 at a first node N1. The second terminal of the first capacitor Cst1 is connected to the third power line.

[0025] Specifically, during at least one hold frame in the display cycle of an image frame, the first capacitor Cst1 maintains the potential of the first node N1 based on the reset signal VI_ANO, so that the potential of the first node N1 remains stable during the display cycle.

[0026] Reference Figure 4 In (a), the display cycle of one frame of an image also includes a refresh frame, in which the potential of the first node N1 is determined by the data signal written. In the hold frame, the amplitude of the reset signal VI_ANO transmitted on the third power line can be increased to maintain the potential of the first node N1 stable through the coupling effect of the first capacitor Cst1 on the first node N1, so as to make the light emission effect consistent between each hold frame and between the hold frame and the write frame.

[0027] In the above embodiment, the first power line, the second power line, and the light-emitting device between the first power line and the second power line, along with the first transistor T1, form the light-emitting path of the pixel. The conduction level of the first transistor T1 causes different currents in the light-emitting path, thereby enabling the light-emitting device to emit light at the correct brightness. The first reset circuit can reset the anode of the light-emitting device according to the reset signal VI_ANO from the third power line, ensuring that the initial state of the light-emitting device remains consistent. Simultaneously, the third power line and the first node N1 are connected through the first capacitor Cst1, thereby multiplexing the reset signal VI_ANO transmitted on the third power line to stably maintain the potential of the first node N1 within the holding frame. This avoids excessive leakage current in the first node N1 due to an excessively long holding frame duration. Thus, without adding any signal lines, the potential of the first node N1 can be ensured to remain stable within the display cycle, preventing display abnormalities such as color shift.

[0028] In some embodiments, the display cycle further includes a refresh frame. Within the refresh frame, the first reset sub-circuit is connected to a reset signal with an amplitude of a reference amplitude via a third power line to perform a reset operation within the refresh frame.

[0029] In some embodiments, during at least one hold frame of the display cycle of a frame image, the first capacitor Cst1 is connected to a reset signal VI_ANO with an amplitude of a target amplitude via a third power line; wherein the reference amplitude and the target amplitude are different.

[0030] As an example, the hold frame includes a hold phase in which the amplitude of the reset signal VI_ANO, connected to the first capacitor Cst1 via the third power line, is different during the hold phase of at least two hold frames in the display cycle. That is, the target amplitude of the reset signal VI_ANO can be different in different hold phases of the hold frame. The hold frame also includes a reset phase in which the first reset sub-circuit is connected to a reset signal VI_ANO with a reference amplitude via the third power line during the reset phase of each hold frame.

[0031] Each hold frame includes a hold phase and a reset phase. During the reset phase of the hold frame, the first reset sub-circuit performs an anode reset by connecting a reset signal VI_ANO with a reference amplitude via the third power line. During the hold phase of the hold frame, the first capacitor Cst1 compensates for the potential of the first node N1 by connecting the reset signal VI_ANO via the third power line. By adjusting the amplitude of the reset signal VI_ANO differently during the hold phase of at least two hold frames in the display cycle, differentiated adjustment of the potential of the first node N1 within each hold frame can be achieved. Compared to using the same target amplitude reset signal VI_ANO for all hold frames, the compensation effect for the first node N1 is better, making the potential of the first node N1 more stable, thereby further improving the display quality.

[0032] In the above embodiment, firstly, the reset signal VI_ANO transmitted on the third power line is multiplexed between the third power line and the first node N1 via the first capacitor Cst1. Secondly, by distinguishing between the reference amplitude and the target amplitude of the reset signal, and adjusting the amplitude of the reset signal VI_ANO at each stage of different holding frames, it is possible to ensure that the reset operation is performed during the reset stage, and to provide differential compensation for the potential of the first node N1 through the differential adjustment of the amplitude of the reset signal VI_ANO in different holding stages.

[0033] Reference Figure 5 and Figure 7In some embodiments, the display device further includes a power management chip 20. The power management chip 20 is connected to a first power line, a second power line, and a third power line, and is used to output a first power supply voltage VDD to the first power line, a second power supply voltage VSS to the second power line, and a reset signal VI_ANO to the third power line.

[0034] The following describes how the reset signal VI_ANO is adjusted during the hold phase of each hold frame. As an example, a target amplitude table can be determined from several preset amplitude tables based on the set refresh rate, and the amplitude of the reset signal VI_ANO during the hold phase of each hold frame can be adjusted according to the target amplitude table to output the amplitude-adjusted reset signal VI_ANO to the third power line.

[0035] The preset amplitude table stores the amplitude of the reset signal VI_ANO corresponding to the hold phase of each hold frame in an image frame. The reset signal VI_ANO is an analog signal, and the power management chip 20 determines the amplitude of the reset signal VI_ANO by looking up the table.

[0036] As an example, the power management chip 20 pre-stores multiple preset amplitude tables. Different refresh rates correspond to different amplitude tables, and the number of amplitude values ​​for the reset signal VI_ANO in the amplitude tables matches the number of hold frames at that refresh rate. Furthermore, due to different refresh rates, the amplitude values ​​of the reset signal VI_ANO corresponding to the hold phase of each hold frame can be the same or different. (Refer to...) Figure 5 In (a), continuing with the example of a base frequency of 120Hz, when the set refresh rate is 10Hz, the corresponding target amplitude table is the first amplitude table, and the number of hold frames at this refresh rate is 11. Figure 5 In (b), M is 11. The first amplitude table contains 11 different reset signal VI_ANO amplitudes, corresponding to 11 hold frames, namely VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8, VI9, VI10, and VI11. When the set refresh rate is 20Hz, the corresponding target amplitude table is the second amplitude table. The number of hold frames at this refresh rate is 5. Figure 5 In (b), M is 5, and the second amplitude table contains the amplitudes of 5 different reset signals VI_ANO, corresponding to 5 hold frames, namely VI1, VI2, VI3, VI4, and VI5. When the set refresh rate is 30Hz, the corresponding target amplitude table is the third amplitude table, and the number of hold frames at this refresh rate is 3. Figure 5In (b) of the diagram, M is 3. The third amplitude table contains three different reset signal VI_ANO amplitudes, corresponding to three hold frames, namely VI1, VI2, and VI. It is important to note that identical identifiers in different amplitude tables (such as VI1 in the first amplitude table and VI1 in the second amplitude table) can represent different amplitudes, and the amplitudes of the reset signals VI_ANO in the same amplitude table (such as VI1 to VI11 in the first amplitude table) can also be different. Thus, the corresponding amplitude table can be matched according to the set refresh rate, and the corresponding reset signal VI_ANO amplitude can be matched within each hold frame to improve the accuracy of stabilizing the potential of the first node N1.

[0037] Reference Figure 4 In example (b), after determining the amplitude of the reset signal VI_ANO for each holding frame from the amplitude table, such as VI1, VI2, ..., VIM, the power management chip 20 adjusts the amplitude of the reset signal VI_ANO in the timing corresponding to each holding frame so as to transmit the reset signal VI_ANO to the first capacitor Cst1 through the third power line, thereby stabilizing the potential of the first node N1 through the coupling of the first capacitor Cst1.

[0038] The system pre-stores multiple preset amplitude tables, which can be set through actual testing. At each target refresh rate, the brightness changes and color shift during each hold frame can be observed visually, or the brightness attenuation data of each hold frame can be captured and quantified using image quality testing equipment. The required amplitude of the reset signal VI_ANO can then be determined based on the brightness drift of different hold frames. For example, at a certain low refresh rate, if the image quality testing equipment detects no significant brightness attenuation in the first hold frame, the amplitude of the reset signal VI_ANO can be set to a value suitable for this state. If different degrees of brightness attenuation occur in subsequent hold frames, the amplitude of the reset signal VI_ANO in each hold frame can be adjusted accordingly. The amplitude of the reset signal VI_ANO for each hold frame is determined through frame-by-frame calibration to form the amplitude table corresponding to that refresh rate.

[0039] In the above embodiment, the power management chip 20 automatically matches the corresponding amplitude table according to the currently set refresh rate, quickly determines the amplitude of the reset signal VI_ANO for each holding frame by looking up the table, and outputs the corresponding amplitude reset signal VI_ANO to the third power line in each holding frame through the power management chip 20, thereby realizing dynamic compensation of the potential of the first node N1, so that the first capacitor Cst1 can provide accurate potential compensation to the first node N1 in each holding frame to offset the potential drift of the first node N1 caused by leakage current.

[0040] In some embodiments, the power management chip 20 is further configured to: output a reset signal VI_ANO of the reference amplitude to the third power line during the reset phase of the hold frame; and during the hold phase of the hold frame, determine the target amplitude of the current hold frame according to the target amplitude table, so as to output a reset signal VI_ANO of the target amplitude to the third power line.

[0041] As an example, since the third power line is also used to reset the anode of the light-emitting device, the power management chip 20 can output a reset signal VI_ANO of the reference amplitude to the third power line during the refresh frame. Additionally, if the anode of the light-emitting device also needs to be reset within the hold frame, the power management chip 20 can still output a reset signal VI_ANO of the reference amplitude to the third power line during the reset phase of the hold frame to maintain the consistency of the anode potential of the light-emitting device.

[0042] Reference Figure 4 (b) Figure 4 (b) An example is given of the amplitude change of the reset signal VI_ANO during the sustain phase of a hold frame (the reset phase of the hold frame is not shown). The target amplitude of the reset signal VI_ANO can be output to the third power line according to the target amplitude of each hold frame, so that the hold phase of each hold frame can provide accurate potential compensation to the first node N1 through the reset signal VI_ANO.

[0043] Reference Figure 6 In some embodiments, the first reset sub-circuit includes a second transistor T2. The second transistor T2 includes a control electrode connected to a reset control signal, a first electrode connected to a third power supply line, and a second electrode connected to the anode of a light-emitting device.

[0044] Specifically, during the reset phase of the refresh frame and the reset phase of the hold frame, the second transistor T2 is turned on under the drive of the reset control signal to reset the anode of the light-emitting device using the reset signal VI_ANO with a reference amplitude. As an example, during the hold phase of the hold frame, the second transistor T2 is turned off under the drive of the reset control signal to avoid the reset signal VI_ANO with varying amplitude interfering with the anode potential of the light-emitting device.

[0045] Reference Figure 6In some embodiments, the pixel driving circuit further includes a write sub-circuit, a light-emitting sub-circuit, a connection sub-circuit, a second reset sub-circuit, and a second capacitor Cst2. The write sub-circuit is connected to the first electrode of the first transistor T1 at the second node N2. The connection sub-circuit is connected to the second electrode of the first transistor T1 at a third node and is also connected to the first node N1. The light-emitting sub-circuit is connected in series between the first power line and the second power line to control the light emission of the light-emitting device. The second reset sub-circuit is connected to the first node N1 to reset the first node N1. The second capacitor Cst2 is connected between the first power line and the first node N1 to store the data signal input by the write sub-circuit.

[0046] Reference Figure 6 In some embodiments, the write sub-circuit includes a third transistor T3, the light-emitting sub-circuit includes a fourth transistor T4 and a fifth transistor T5, the connection sub-circuit includes a sixth transistor T6, and the second reset sub-circuit includes a seventh transistor T7. The third transistor T3 includes a first electrode for receiving a data signal, a second electrode connected to the second node N2, and a control electrode for receiving a scan signal. The fourth transistor T4 includes a first electrode connected to a first power line, a second electrode connected to the second node N2, and a control electrode for receiving a light-emitting control signal. The fifth transistor T5 includes a first electrode connected to the third node, a second electrode connected to the light-emitting device, and a control electrode for receiving a light-emitting control signal. The sixth transistor T6 includes a first electrode connected to the third node, a second electrode connected to the first node N1, and a control electrode for receiving a scan signal. The seventh transistor T7 includes a first electrode for receiving a gate reset voltage, a second electrode connected to the second node N2, and a control electrode for receiving the gate reset signal VI_ANO.

[0047] Reference Figure 6 PSCAN[n] represents the scan signal, PSCAN[n-1] represents the gate reset signal VI_ANO, EM represents the light emission control signal, VI_Gate represents the gate reset voltage, and Vdata represents the data signal. As an example, within a refresh frame, firstly, the gate reset signal VI_ANO drives the seventh transistor T7 to conduct, resetting the potential of the first node N1 and clearing the data signal from the previous frame. Next, the scan signal drives the third transistor T3, the sixth transistor T6, and the second transistor T2 to conduct. The sixth transistor T6 and the third transistor T3 write the data signal to the first node N1, and the second transistor T2 resets the anode of the light-emitting device. Then, the light emission control signal drives the fourth transistor T4 and the fifth transistor T5 to conduct, and at this time, the first transistor T1 conducts according to the potential of the first node N1, causing the light-emitting device to start emitting light.

[0048] In some embodiments, the display device further includes a gate driver 30 and a source driver. The gate driver 30 is used to output a scan signal within a refresh frame to control the conduction of the write sub-circuit and the connection sub-circuit. The source driver is used to output a data signal within a refresh frame, so that the data signal is transmitted through the write sub-circuit, the first transistor T1, and the connection sub-circuit to the second capacitor Cst2 to complete the writing of the data signal.

[0049] As an example, such as Figure 7 As shown, Figure 7 This is a schematic diagram of a display device provided in an embodiment of this application. The gate driver 30 is used to send a scan signal, a light emission control signal, and a reset control signal to the pixel unit 10. The data driver 40 is used to send a data signal to the pixel unit 10. The power management chip 20 sends a first power supply voltage VDD, a second power supply voltage VSS, and a reset signal VI_ANO to the pixel unit 10 through a first power supply line, a second power supply line, and a third power supply line, respectively, thereby driving each pixel unit 10 to perform light emission display.

[0050] The gate driver 30 is connected to each pixel unit 10 via scan lines G1-Gn, and is used to send scan signals to each pixel unit 10 via the scan lines. The data driver 40 is connected to each pixel unit 10 via data lines D1-Dm, and is used to send data signals to each pixel unit 10 via the data lines. During the process of the gate driver 30, data driver 40, and power management chip 20 jointly driving each pixel unit 10 to emit light for display, the gate driver 30 first sends a scan signal to the first row of pixel units 10 via scan line Gn to select the first row of pixel units 10. The data driver 40 then sends a data voltage to the first row of pixel units 10 via the data signal line Data. Then, the gate driver 30 continues to select the next row of pixel units 10, and the data driver 40 sends the corresponding data signal to the next row of pixel units 10. This process continues until all rows are selected and data voltages have been received. Under the control of the light emission control signal, the power management chip 20 outputs the voltage signal required by the light emission device to each pixel unit 10, so as to control the light emission device in the pixel unit 10 to emit light and complete the display of one frame of image. By repeating the above process, the display device can display continuous images.

[0051] Combination Figure 6The power management chip 20 provides each pixel unit 10 with a first power supply voltage VDD and a second power supply voltage VSS required for light emission, thereby driving the light-emitting devices in each pixel unit 10 to emit light and realize the light-emitting display function of each pixel unit 10. Simultaneously, during the refresh frame and hold frame reset phases within a frame of an image display, the power management chip 20 outputs a reference amplitude reset signal VI_ANO to reset the anode during the light emission period. During the hold frame maintenance phase within a frame of an image display, based on the target amplitude determined in the amplitude table, it outputs a corresponding target amplitude reset signal VI_ANO within each hold frame. This allows the reset signal VI_ANO to dynamically compensate the potential of the first node N1 through the first capacitor Cst1, maintaining the stability of the first node N1 potential and thus ensuring the consistency of the display in each hold frame during low-frequency display, avoiding color shift and other phenomena.

[0052] According to a second aspect of this application, a display panel is provided, including a first power line, a second power line, a third power line, and a plurality of pixel units 10 arranged in an array. Each pixel unit 10 includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a first transistor T1, a first reset circuit, and a first capacitor Cst1. The first reset circuit is connected to the anode of the light-emitting device and the third power line, respectively, and is used to reset the anode of the light-emitting device according to a reset signal VI_ANO transmitted from the third power line. The first transistor T1 and the light-emitting device are connected in series between the first power line and the second power line. The control electrode of the first transistor T1 is connected to the first terminal of the first capacitor Cst1 at a first node N1. The second terminal of the first capacitor Cst1 is connected to the third power line.

[0053] Specifically, during at least one hold frame in the display cycle of an image frame, the first capacitor Cst1 maintains the potential of the first node N1 based on the reset signal VI_ANO, so that the potential of the first node N1 remains stable during the display cycle.

[0054] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0055] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0056] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0057] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display device, characterized by comprising: The display panel comprises a first power line, a second power line, a third power line and a plurality of pixel units arranged in an array, wherein each pixel unit comprises a light emitting device and a pixel driving circuit; The pixel driving circuit comprises a first transistor, a first reset sub-circuit and a first capacitor; The first reset sub-circuit is connected with the anode of the light emitting device and the third power line, and is configured to reset the anode of the light emitting device according to a reset signal transmitted by the third power line; The first transistor and the light emitting device are connected in series between the first power line and the second power line; the control electrode of the first transistor is connected with the first end of the first capacitor at a first node; and the second end of the first capacitor is connected with the third power line. In at least one holding frame in a display period of one frame of image, the first capacitor maintains the electric potential of the first node based on the reset signal, so that the electric potential of the first node is kept stable in the display period.

2. The display device according to claim 1, wherein The display period further comprises a refresh frame, and in the refresh frame, the first reset sub-circuit accesses the reset signal with a reference amplitude via the third power line.

3. The display device according to claim 2, wherein In at least one holding frame in the display period of the one frame of image, the first capacitor accesses the reset signal with a target amplitude via the third power line; wherein the reference amplitude and the target amplitude are different.

4. The display device according to claim 3, wherein The holding frame comprises a maintaining stage, and in the maintaining stage of at least two holding frames in the display period, the first capacitor accesses the reset signal with different amplitudes via the third power line.

5. The display device according to claim 3, wherein: The holding frame further comprises a reset stage, and in the reset stage of each holding frame, the first reset sub-circuit accesses the reset signal with the reference amplitude via the third power line.

6. The display device according to claim 4, wherein The first reset sub-circuit comprises a second transistor; The second transistor comprises a control electrode for accessing a reset control signal, a first electrode connected with the third power line, and a second electrode connected with the anode of the light emitting device; In the reset stage of the refresh frame and the reset stage of the holding frame, the second transistor is turned on under the drive of the reset control signal to reset the anode of the light emitting device by the reset signal with the reference amplitude.

7. The display device according to any one of claims 3 to 5, wherein The pixel driving circuit further comprises a writing sub-circuit, a light emitting sub-circuit, a connecting sub-circuit, a second reset sub-circuit and a second capacitor; The writing sub-circuit is connected with the first electrode of the first transistor at a second node, and the connecting sub-circuit is connected with the second electrode of the first transistor at a third node and connected with the first node; The light emitting sub-circuit is connected in series between the first power line and the second power line, and is configured to control the light emitting of the light emitting device; The second reset sub-circuit is connected with the first node, and is configured to reset the first node; The second capacitor is connected between the first power line and the first node, and is configured to store a data signal accessed by the writing sub-circuit.

8. The display device according to claim 7, wherein The write sub-circuit comprises a third transistor, the light emitting sub-circuit comprises a fourth transistor and a fifth transistor, the connection sub-circuit comprises a sixth transistor, and the second reset sub-circuit comprises a seventh transistor; The third transistor comprises a first electrode for accessing a data signal, a second electrode connected to the second node, and a control electrode for accessing a scan signal; The fourth transistor comprises a first electrode connected to the first power supply line, a second electrode connected to the second node, and a control electrode for accessing a light emitting control signal; The fifth transistor comprises a first electrode connected to the third node, a second electrode connected to the light emitting device, and a control electrode for accessing the light emitting control signal; The sixth transistor comprises a first electrode connected to the third node, a second electrode connected to the first node, and a control electrode for accessing the scan signal; The seventh transistor comprises a first electrode for accessing a gate reset voltage, a second electrode connected to the second node, and a control electrode for accessing a gate reset signal.

9. The display device according to claim 7, wherein Further comprising a gate driver and a source driver; The gate driver is configured to output a scan signal in the refresh frame to control the write sub-circuit and the connection sub-circuit to be turned on, and the source driver is configured to output a data signal in the refresh frame, so that the data signal is transmitted through the write sub-circuit, the first transistor, and the connection sub-circuit to the second capacitor to complete the writing of the data signal.

10. A display panel, characterized by, The pixel driving circuit comprises a first transistor, a first reset sub-circuit, and a first capacitor; The first reset sub-circuit is connected to the anode of the light emitting device and the third power supply line, respectively, and is configured to reset the anode of the light emitting device according to a reset signal transmitted by the third power supply line; The first transistor and the light emitting device are connected in series between the first power supply line and the second power supply line; the control electrode of the first transistor and the first end of the first capacitor are connected to a first node; and the second end of the first capacitor is connected to the third power supply line; In at least one holding frame in a display period of one frame of image, the first capacitor maintains the potential of the first node based on the reset signal, so that the potential of the first node remains stable in the display period. ​

Images