Pixel driving circuit, driving method thereof and display device

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display device, and the pixel driving circuit comprises a driving sub-circuit which is configured to provide a driving signal for a third node under the control of signals of a first node and a second node; the first initial sub-circuit is configured to provide a signal of a first input signal end to a first node under the control of a signal of a first scanning signal end; the coupling sub-circuit is configured to couple a signal of a data signal end or a second input signal end to a third node under the control of a signal of at least one scanning signal end; the holding sub-circuit is configured to store a voltage difference of signals of the first node and the third node; and the light-emitting control sub-circuit is electrically connected with the first light-emitting signal end, the first power supply end and the second node, and is configured to provide the signal of the first power supply end to the second node under the control of the signal of the first light-emitting signal end.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a pixel driving circuit and driving method thereof, as well as a display device.

[0005] In a first aspect, this disclosure provides a pixel driving circuit, including: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0007] The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal, and the first node, respectively, and is configured to provide the signal from the first input signal terminal to the first node under the control of the signal from the first scan signal terminal;

[0008] The coupling sub-circuit is electrically connected to at least one scan signal terminal, a data signal terminal, a second input signal terminal, and a third node, respectively, and is configured to couple the signal of the data signal terminal or the second input signal terminal to the third node under the control of the signal of at least one scan signal terminal;

[0009] The holding sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference between the signals of the first node and the third node;

[0010] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the first power supply terminal, and the second node, respectively, and is configured to provide the signal from the first power supply terminal to the second node under the control of the signal from the first light-emitting signal terminal.

[0011] In an exemplary embodiment, at least one scan signal terminal includes: a second scan signal terminal and a third scan signal terminal, and the coupling sub-circuit includes: a second transistor, a fourth transistor, and a second capacitor;

[0012] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0013] The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0014] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the third node.

[0015] In an exemplary embodiment, at least one scan signal terminal includes: a second scan signal terminal, and the coupling sub-circuit includes: a second transistor and a second capacitor;

[0016] The control electrode of the second transistor is electrically connected to the second scan signal terminal. The first electrode of the second transistor is electrically connected to the data signal terminal for a part of the time period and to the second input signal terminal for a part of the time period. The second electrode of the second transistor is electrically connected to the fourth node.

[0017] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the third node.

[0018] In an exemplary embodiment, the first initial sub-circuit includes a first transistor, the holding sub-circuit includes a first capacitor, and the driving sub-circuit includes a third transistor;

[0019] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0020] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0021] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0022] In an exemplary embodiment, the first initial sub-circuit includes: a first transistor; the holding sub-circuit includes: a first capacitor; and the driving sub-circuit includes: a third transistor, the third transistor including: a first control electrode and a second control electrode.

[0023] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0024] The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0025] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0026] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device to emit light, and the light-emitting control sub-circuit includes: a fifth transistor;

[0027] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0028] The light-emitting devices are electrically connected to the third node and the second power supply terminal, respectively.

[0029] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device to emit light, and the light-emitting control sub-circuit is also electrically connected to the second light-emitting signal terminal, the third node and the fifth node. The light-emitting control sub-circuit includes a fifth transistor and a sixth transistor.

[0030] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0031] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0032] The light-emitting device is electrically connected to the fifth node and the second power supply terminal, respectively.

[0033] In an exemplary embodiment, it further includes: a second initial sub-circuit;

[0034] The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the third node, respectively, and is configured to provide the signal from the third input signal terminal to the third node under the control of the signal from the fourth scan signal terminal.

[0035] In an exemplary embodiment, the second initial sub-circuit includes: a seventh transistor;

[0036] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node.

[0037] In an exemplary embodiment, it further includes: a second initial sub-circuit;

[0038] The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the fifth node, respectively, and is configured to provide the signal from the third input signal terminal to the fifth node under the control of the signal from the fourth scan signal terminal.

[0039] In an exemplary embodiment, the second initial sub-circuit includes: a seventh transistor;

[0040] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0041] In an exemplary embodiment, it further includes: a third initial sub-circuit;

[0042] The third initial sub-circuit is electrically connected to the fifth scan signal terminal, the fourth input signal terminal, and the second node, respectively, and is configured to provide the signal from the fourth input signal terminal to the second node under the control of the signal from the fifth scan signal terminal.

[0043] In an exemplary embodiment, the third initial sub-circuit includes: an eighth transistor;

[0044] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0045] In an exemplary embodiment, the signal received by the first input signal terminal connected to the same pixel driving circuit and the first power supply terminal is the same signal.

[0046] In an exemplary embodiment, the signals received by the first input signal terminal and the second input signal terminal connected to the same pixel driving circuit are the same signals.

[0047] In an exemplary embodiment, the signals received by the second input signal terminal and the third input signal terminal connected to the same pixel driving circuit are the same signals.

[0048] In an exemplary embodiment, the second input signal terminal and the fourth input signal terminal connected to the same pixel driving circuit receive the same signal.

[0049] In an exemplary embodiment, the signal received by the second scanning signal terminal connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal are the same signal; or, the signal received by the second scanning signal terminal connected to the i-th row pixel driving circuit and the signal received by the first scanning signal terminal of the (i-1)-th row pixel driving circuit are the same signal.

[0050] In an exemplary embodiment, the signals received by the fourth scan signal terminal and the fifth scan signal terminal connected to the same pixel driving circuit are the same signals.

[0051] In an exemplary embodiment, the signals received by the third scanning signal terminal connected to the pixel driving circuit of the i-th row and the fourth scanning signal terminal of the pixel driving circuit of the (i+K)-th row are the same signal, where K is a positive integer greater than 1.

[0052] Secondly, this disclosure also provides a display device, including: the aforementioned pixel driving circuits arranged in an array.

[0053] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0054] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0055] The first initial sub-circuit provides the first input signal terminal signal to the first node under the control of the signal at the first scanning signal terminal;

[0056] Under the control of a signal at at least one scan signal terminal, the coupler circuit couples the signal from the data signal terminal or the second input signal terminal to the third node;

[0057] Maintain the voltage difference between the signals stored in the first and third nodes in the sub-circuit;

[0058] Under the control of the signal at the first light-emitting signal terminal, the light-emitting control sub-circuit provides the signal at the first power supply terminal to the second node.

[0059] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0060] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0061] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0062] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0063] Figure 2 The equivalent circuit diagram of the first initial sub-circuit;

[0064] Figure 3 To maintain the equivalent circuit diagram of the sub-circuit;

[0065] Figure 4 Equivalent circuit for driving sub-circuit Figure 1 ;

[0066] Figure 5 Equivalent circuit for driving sub-circuit Figure 2 ;

[0067] Figure 6 Equivalent circuit of the coupler sub-circuit Figure 1 ;

[0068] Figure 7 Equivalent circuit of the coupler sub-circuit Figure 2 ;

[0069] Figure 8 Equivalent circuit of the light-emitting control sub-circuit Figure 1 ;

[0070] Figure 9 Equivalent circuit of the light-emitting control sub-circuit Figure 2 ;

[0071] Figure 10 A schematic diagram of a pixel driving circuit provided in an exemplary embodiment;

[0072] Figure 11 for Figure 10 The equivalent circuit diagram of the second initial sub-circuit in the diagram;

[0073] Figure 12 A schematic diagram of the structure of a pixel driving circuit provided for another exemplary embodiment;

[0074] Figure 13 for Figure 12 Equivalent circuit of the second initial sub-circuit in Figure 1 ;

[0075] Figure 14 for Figure 12 Equivalent circuit of the second initial sub-circuit in Figure 2 ;

[0076] Figure 15 A schematic diagram of the structure of a pixel driving circuit provided in yet another exemplary embodiment;

[0077] Figure 16 The equivalent circuit diagram of the third initial sub-circuit;

[0078] Figure 17 An equivalent circuit for a pixel driving circuit Figure 1 ;

[0079] Figure 18 An equivalent circuit for a pixel driving circuit Figure 2 ;

[0080] Figure 19 for Figure 18 The provided pixel driving circuit driving timing Figure 1 ;

[0081] Figure 20 for Figure 18 The provided pixel driving circuit driving timing Figure 2 ;

[0082] Figure 21 An equivalent circuit for a pixel driving circuit Figure 3 ;

[0083] Figure 22 An equivalent circuit for a pixel driving circuit Figure 4 ;

[0084] Figure 23 for Figure 22 The provided pixel driving circuit driving timing Figure 1 ;

[0085] Figure 24 for Figure 22 The provided pixel driving circuit driving timing Figure 2 ;

[0086] Figure 25 for Figure 22 The provided pixel driving circuit driving timing Figure 3 ;

[0087] Figure 26 for Figure 22 The provided pixel driving circuit driving timing Figure 4 ;

[0088] Figure 27 for Figure 22 The provided pixel driving circuit driving timing Figure 5 ;

[0089] Figure 28 for Figure 22 The provided pixel driving circuit driving timing Figure 6 ;

[0090] Figure 29 for Figure 22 The provided pixel driving circuit driving timing Figure 7 ;

[0091] Figure 30 for Figure 22 The provided pixel driving circuit driving timing Figure 8 ;

[0092] Figure 31 An equivalent circuit for a pixel driving circuit Figure 5 ;

[0093] Figure 32 An equivalent circuit for a pixel driving circuit Figure 6 ;

[0094] Figure 33 An equivalent circuit for a pixel driving circuit Figure 7 ;

[0095] Figure 34 for Figure 32 and Figure 33 The provided pixel driving circuit driving timing Figure 1 ;

[0096] Figure 35 for Figure 32 and Figure 33 The provided pixel driving circuit driving timing Figure 2 ;

[0097] Figure 36 An equivalent circuit for a pixel driving circuit Figure 8 ;

[0098] Figure 37 An equivalent circuit for a pixel driving circuit Figure 9 ;

[0099] Figure 38 An equivalent circuit for a pixel driving circuit Figure 10 ;

[0100] Figure 39 An equivalent circuit for a pixel driving circuit Figure 10 one;

[0101] Figure 40 An equivalent circuit for a pixel driving circuit Figure 10 two;

[0102] Figure 41 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 1 ;

[0103] Figure 42 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 2 ;

[0104] Figure 43 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 3 ;

[0105] Figure 44 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 4 ;

[0106] Figure 45 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 5 ;

[0107] Figure 46 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 6 ;

[0108] Figure 47 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 7 ;

[0109] Figure 48 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 8 . Detailed Implementation

[0110] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0111] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0112] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0113] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0114] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0115] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0116] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0117] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0118] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0119] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0120] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0121] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0122] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0123] The display product includes at least one sub-pixel, which comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The gate electrode of the driving transistor is connected to multiple transistors, resulting in a large parasitic capacitance value coupled to the gate electrode of the driving transistor. This reduces the follow-up ratio of the gate electrode voltage and source electrode voltage of the pixel driving circuit, causing a deviation in the driving signal voltage maintained between the gate electrode and source electrode of the driving transistor. This reduces the consistency of the display brightness of the display product and affects the display effect of the display substrate.

[0124] Therefore, this disclosure provides a pixel driving circuit.

[0125] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 1 As shown, the pixel driving circuit provided in this embodiment may include: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit.

[0126] The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0127] The first initial sub-circuit is electrically connected to the first input signal terminal IN1, the first scan signal terminal Gate1, and the first node N1, respectively, and is configured to provide the signal of the first input signal terminal IN1 to the first node N1 under the control of the signal of the first scan signal terminal Gate1.

[0128] The coupling sub-circuit is electrically connected to at least one scan signal terminal Gate, a data signal terminal Data, a second input signal terminal IN2, and a third node N3, respectively, and is configured to couple the signal of the data signal terminal Data or the signal of the second input signal terminal IN2 to the third node N3 under the control of the signal of at least one scan signal terminal Gate.

[0129] The holding sub-circuit, electrically connected to the first node N1 and the third node N3 respectively, is configured to store the voltage difference between the signals of the first node N1 and the third node N3.

[0130] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the first power supply terminal VDD, and the second node N2, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 under the control of the signal from the first light-emitting signal terminal EM1.

[0131] In an exemplary embodiment, the first power supply terminal VDD can continuously provide a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0132] In this disclosure, the first initial sub-circuit connected to the first node is only electrically connected to the first input signal terminal and the first scan signal terminal. This means that the number of transistors connected to the first node is relatively small. Furthermore, the setting of the coupling sub-circuit can couple the data from the data signal terminal to the third node connected to the driving sub-circuit, reducing the number of transistors directly coupled to the first node connected to the driving sub-circuit. It can also achieve normal data writing and threshold compensation. Therefore, the pixel driving circuit provided in this disclosure embodiment can reduce the parasitic capacitance coupled to the first node N1 while ensuring normal display. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0133] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device L to emit light.

[0134] In an exemplary embodiment, the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device is electrically connected to a pixel driving circuit, and the cathode of the light-emitting device is electrically connected to a second power supply terminal VSS.

[0135] In an exemplary embodiment, the second power supply terminal VSS can continuously provide a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0136] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0137] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0138] Figure 2 This is the equivalent circuit diagram of the first initial sub-circuit. For example... Figure 2 As shown, in an exemplary embodiment, the first initial sub-circuit includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0139] In an exemplary embodiment, the first input signal terminal IN1 can receive a first initial signal. The first transistor T1 can be referred to as the first initial transistor. Under the signal control of the first scan signal terminal Gate1, the first transistor T1 writes the first initial signal into the first node N1.

[0140] Figure 2 The diagram only shows one exemplary structure of the first initial sub-circuit, and those skilled in the art will readily understand that the implementation of the first initial sub-circuit is not limited to this.

[0141] Figure 3 To preserve the equivalent circuit diagram of the sub-circuit. For example... Figure 3 As shown, in an exemplary embodiment, the holding sub-circuit includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to a first node N1, and the second terminal of the first capacitor C1 is electrically connected to a third node N3.

[0142] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal of the first node N1 and improve the reliability of the pixel driving circuit.

[0143] Figure 3 The diagram shows only one exemplary structure of the holding sub-circuit, and those skilled in the art will readily understand that the implementation of the holding sub-circuit is not limited to this.

[0144] Figure 4 Equivalent circuit for driving sub-circuit Figure 1 .like Figure 4 As shown, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a single-gate transistor. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0145] Figure 5 Equivalent circuit for driving sub-circuit Figure 2 .like Figure 5 As shown, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a dual-gate transistor. The third transistor T3 includes a first control electrode and a second control electrode. The first control electrode of the third transistor T3 is electrically connected to a first node N1, the second control electrode of the third transistor T3 is electrically connected to a third node N3, the first electrode of the third transistor T3 is electrically connected to a second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0146] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The connection method of the third transistor in this disclosure can improve the output saturation characteristics of the third transistor T3.

[0147] Figure 4 and Figure 5 The diagram illustrates two exemplary structures of the driver sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to these.

[0148] Figure 6 Equivalent circuit of the coupler sub-circuit Figure 1 .like Figure 6As shown, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2 and a third scan signal terminal Gate3. The coupling sub-circuit may include a second transistor T2, a fourth transistor T4, and a second capacitor C2. Specifically, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0149] In an exemplary embodiment, the second input signal terminal IN2 can receive a second initial signal. The second transistor T2 can be referred to as the second initial transistor. Under the signal control of the second scan signal terminal Gate2, the second transistor T2 writes the second initial signal into the fourth node N4.

[0150] In an exemplary embodiment, the data signal terminal Data can receive data signals. The fourth transistor T4 can be referred to as the write transistor. Under the control of the signal at the third scan signal terminal Gate3, the fourth transistor T4 writes data signals to the fourth node N4.

[0151] Figure 7 Equivalent circuit of the coupler sub-circuit Figure 2 .like Figure 7 As shown, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2. The coupling sub-circuit may include a second transistor T2 and a second capacitor C2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2; the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of a time period and to the second input signal terminal IN2 for a portion of a time period; the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0152] In an exemplary embodiment, the second input signal terminal IN2 can receive the second initial signal, and the data signal terminal Data can receive the data signal. Under the control of the signal from the second scan signal terminal Gate2, the second transistor T2 writes the data signal to the fourth node N4 for a portion of the time period and writes the second initial signal to the fourth node N4 for a portion of the time period.

[0153] Figure 6 and Figure 7Two exemplary structures of the coupling sub-circuit are shown in the figure. It will be readily understood by those skilled in the art that the implementation of the coupling sub-circuit is not limited to these.

[0154] In an exemplary embodiment Figure 7 The provided coupler sub-circuit and Figure 6 Compared to the provided coupling sub-circuit, it includes fewer transistors, which can reduce the area occupied by the pixel driving circuit and the number of connected signal lines, and can achieve a high PPI in the display device.

[0155] Figure 8 Equivalent circuit of the light-emitting control sub-circuit Figure 1 .like Figure 8 As shown, in an exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0156] In an exemplary embodiment, the first power supply terminal VDD can receive a first power signal, and the fifth transistor T5 can be referred to as a light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power signal into the second node N2.

[0157] like Figure 8 As shown, the light-emitting device L is electrically connected to the third node N3 and the second power supply terminal VSS.

[0158] Figure 9 Equivalent circuit of the light-emitting control sub-circuit Figure 2 .like Figure 9 As shown, in an exemplary embodiment, the light-emitting control sub-circuit is also electrically connected to the second light-emitting signal terminal EM2, the third node N3, and the fifth node N5. The light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0159] In an exemplary embodiment, the first power supply terminal VDD can receive a first power supply signal, and the fifth transistor T5 can be referred to as the first light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power supply signal into the second node N2. The sixth transistor T6 can be referred to as the second light-emitting transistor. Under the signal control of the second light-emitting signal terminal EM2, the sixth transistor T6 writes the drive signal output from the third node N3 into the fifth node N5.

[0160] like Figure 9 As shown, the light-emitting device L is electrically connected to the fifth node N5 and the second power supply terminal VSS.

[0161] Figure 8 and Figure 9 The diagram illustrates two exemplary structures of the light-emitting control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to these.

[0162] In an exemplary embodiment Figure 9 The provided light-emitting control sub-circuit isolates the third node N3 from the light-emitting device L, thus avoiding the influence of the parasitic capacitance of the light-emitting device on the signal of the third node N3.

[0163] Figure 10 This is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. Figure 10 As shown, in an exemplary embodiment, when the light-emitting device is electrically connected to the third node N3, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the third node N3, and is configured to provide the signal of the third input signal terminal IN3 to the third node N3 under the control of the signal from the fourth scan signal terminal Gate4.

[0164] Figure 11 for Figure 10 The equivalent circuit diagram of the second initial sub-circuit in the diagram. For example... Figure 11 As shown, the second initial sub-circuit may include: a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3.

[0165] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 to initialize the third node N3. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times, to initialize the anode of the light-emitting device, or to bias the third transistor T3.

[0166] Figure 12 A schematic diagram of the pixel driving circuit provided in another exemplary embodiment. (See diagram below.) Figure 12 As shown, in an exemplary embodiment, when the light-emitting device is electrically connected to the fifth node N5, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and one of the third node N3 and the fifth node N5, respectively, and is configured to provide the signal of the third input signal terminal IN3 to one of the third node N3 and the fifth node N5 under the control of the signal from the fourth scan signal terminal Gate4.

[0167] Figure 13 for Figure 12 Equivalent circuit of the second initial sub-circuit in Figure 1 , Figure 14 for Figure 12 Equivalent circuit of the second initial sub-circuit in Figure 2 .like Figure 13 and Figure 14 As shown, in an exemplary embodiment, the second initial sub-circuit includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the third node N3 and the fifth node N5. Figure 13 This explanation uses the electrical connection between the second terminal of the seventh transistor and the third node N3 as an example. Figure 14 This explanation uses the example of the electrical connection between the second terminal of the seventh transistor and the fifth node N5.

[0168] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 or the fifth node N5, thus initializing the third node N3 or the fifth node N5. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times; this disclosure does not limit this. When the second terminal of the seventh transistor T7 is electrically connected to the third node N3, the conduction of the seventh transistor T7 can initialize the second terminal of the third transistor T3, or bias the third transistor T3. When the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5, the conduction of the seventh transistor T7 can initialize the anode of the light-emitting device.

[0169] Figure 11 , Figure 13 and Figure 14 An exemplary structure of the second initial sub-circuit is shown, and it will be readily understood by those skilled in the art that the implementation of the second initial sub-circuit is not limited thereto.

[0170] Figure 15 This is a schematic diagram of the structure of a pixel driving circuit provided as another exemplary embodiment. For example... Figure 15 As shown, in an exemplary embodiment, the pixel driving circuit may further include a third initial sub-circuit. This third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal from the fifth scan signal terminal Gate5.

[0171] Figure 16 This is the equivalent circuit diagram of the third initial sub-circuit. (Example:) Figure 16 As shown, in an exemplary embodiment, the third initial sub-circuit includes an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0172] In an exemplary embodiment, the fourth input signal terminal IN4 can receive a fourth initial signal. The eighth transistor T8 can be referred to as the fourth initial transistor. Under the signal control of the fifth scan signal terminal Gate5, the eighth transistor T8 writes the fourth initial signal into the second node N2, thereby initializing or biasing the second node N2.

[0173] The second initial sub-circuit and the third initial sub-circuit in this disclosure can initialize the second node before the light-emitting device emits light, thereby ensuring the consistency of the light emission brightness in the display device.

[0174] Figure 16 An exemplary structure of the third initial sub-circuit is shown, and it will be readily understood by those skilled in the art that the implementation of the third initial sub-circuit is not limited thereto.

[0175] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the first power supply terminal VDD connected to the same pixel driving circuit can be the same signal.

[0176] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the second input signal terminal IN2 connected to the same pixel driving circuit can be the same signal.

[0177] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the third input signal terminal IN3 connected to the same pixel driving circuit can be the same signal.

[0178] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the fourth input signal terminal IN4, which are connected to the same pixel driving circuit, can be the same signal.

[0179] In an exemplary embodiment, the voltage value of the third initial signal received by the third input signal terminal IN3 is less than the sum of the voltage value of the signal at the second power supply terminal and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0180] In an exemplary embodiment, the first initial signal received by the first input signal terminal IN1 is a positive voltage signal to ensure that the third transistor T3 can be turned on normally, thereby improving the reliability of the pixel driving circuit.

[0181] In an exemplary embodiment, the voltage value of the first initial signal received by the first input signal terminal IN1 may be equal to the voltage value of the second initial signal received by the second input signal terminal IN2, the voltage value of the first initial signal received by the first input signal terminal IN1 may be greater than the voltage value of the third initial signal received by the third input signal terminal IN3, and the voltage value of the third initial signal received by the third input signal terminal IN3 may be greater than the voltage value of the fourth initial signal received by the fourth input signal terminal IN4.

[0182] In an exemplary embodiment, the signal received by the second scanning signal terminal Gate2 connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal EM1 are the same signal; or, the signal received by the second scanning signal terminal Gate2 connected to the i-th row pixel driving circuit and the first scanning signal terminal Gate1 of the (i-1)-th row pixel driving circuit are the same signal.

[0183] In an exemplary embodiment, when the pixel driving circuit is electrically connected to the fourth scanning signal terminal and the fifth scanning signal terminal respectively, the signals received by the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 connected to the same pixel driving circuit are the same signals.

[0184] In an exemplary embodiment, the signals received by the third scanning signal terminal Gate3 connected to the pixel driving circuit of the i-th row and the fourth scanning signal terminal Gate4 of the pixel driving circuit of the (i+K)-th row are the same signal, where K is a positive integer greater than 1.

[0185] In an exemplary embodiment, having at least two signal terminals connected to the pixel driving circuit receive the same signal can reduce the number of signal lines connected to the pixel driving circuit, thereby achieving a high PPI for the display device.

[0186] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0187] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0188] In an exemplary embodiment, any one of the first capacitors C1 to the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any one of the first capacitors C1 to the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any one of the first capacitors C1 to the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0189] Figure 17 An equivalent circuit for a pixel driving circuit Figure 1 .like Figure 17 As shown, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light-emitting control sub-circuit. The first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2 and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light-emitting control sub-circuit includes a fifth transistor T5. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1; the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1; the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2; the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time; the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the second node N2; and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively... The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0190] In an exemplary embodiment Figure 17 At least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 is an N-type transistor. For example, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0191] Figure 18 An equivalent circuit for a pixel driving circuit Figure 2 .like Figure 18 As shown, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figure 18The following description uses a pixel driving circuit comprising a second initial sub-circuit and a third initial sub-circuit as an example. The first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, and the light emission control sub-circuit includes a fifth transistor T5. The second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, and the first electrode of the third transistor T3 is electrically connected to the second node N2. The second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0192] In an exemplary embodiment Figure 18At least one of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 is an N-type transistor. For example, the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 are all N-type transistors, or the first transistor T1, second transistor T2, third transistor T3, seventh transistor T7, and eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0193] Figure 18 The seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 18 The working process of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 in the process is similar to Figure 17 The first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 operate in the same way. This disclosure only provides... Figure 18 The operation process of the provided pixel driving circuit Figure 17 The working process of the provided pixel driving circuit will not be described in detail here.

[0194] Figure 19 for Figure 18 The provided pixel driving circuit driving timing Figure 1 . Figure 19 Therefore Figure 18 The example provided uses N-type transistors as a case study. Figure 19 As shown, Figure 18 The operation of the provided pixel driving circuit may include:

[0195] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signal at the first light-emitting signal terminal (EM1) is low-level. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0196] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2, where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0197] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0198] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0199] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V dataWhen the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0200] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0201] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0202] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0203] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0204] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0205] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0206] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0207] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0208] I = K * (Vgs - Vth) 2

[0209] =K*(V1-V3-Vth)2

[0210] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0211] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0212] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0213] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0214] I = K * (Vgs - Vth) 2

[0215] =K*(V1-V3-Vth) 2

[0216] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0217] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0218] Figure 20 for Figure 18 The provided pixel driving circuit driving timing Figure 2 . Figure 20 Therefore Figure 18 The example provided uses N-type transistors as a case study. Figure 20 As shown, Figure 18 The operation of the provided pixel driving circuit may include:

[0219] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light emission signal terminal (EM1) and the fifth scan signal terminal (Gate5) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off.

[0220] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0221] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0222] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0223] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0224] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0225] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0226] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0227] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is high, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are low. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal (IN2) and the data signal terminal (Data). The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0228] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0229] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0230] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0231] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0232] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0233] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0234] I = K * (Vgs - Vth) 2

[0235] =K*(V1-V3-Vth) 2

[0236] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0237] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0238] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data(C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0239] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0240] I = K * (Vgs - Vth) 2

[0241] =K*(V1-V3-Vth) 2

[0242] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0243] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0244] Figure 20 The operation process of the provided pixel driving circuit and Figure 19 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0245] Figure 21 An equivalent circuit for a pixel driving circuit Figure 3 .like Figure 21As shown, the pixel driving circuit includes: a first initialization sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initialization sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second control electrode of the third transistor T3 is electrically connected to the third node N3. The first terminal of transistor T3 is electrically connected to the second node N2, and the second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of transistor T4 is electrically connected to the third scan signal terminal Gate3, the first terminal of transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light emission signal terminal EM1, the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of transistor T5 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1, and the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4, and the second terminal of capacitor C2 is electrically connected to the third node N3.

[0246] In an exemplary embodiment Figure 21 At least one of the first transistor T1 to the fifth transistor T5 is an N-type transistor. For example, the first transistor T1 to the fifth transistor T5 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are N-type transistors and the fifth transistor T5 is a P-type transistor.

[0247] Figure 22 An equivalent circuit for a pixel driving circuit Figure 4 .like Figure 22As shown, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of the second initial sub-circuit and the third initial sub-circuit. Figure 22 The following description uses a pixel driving circuit comprising a second initial sub-circuit and a third initial sub-circuit as an example. The first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; the light emission control sub-circuit includes a fifth transistor T5; the second initial sub-circuit includes a seventh transistor T7; and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3. The first terminal of transistor T4 is electrically connected to the data signal terminal Data; the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light-emitting signal terminal EM1; the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD; the second terminal of transistor T5 is electrically connected to the second node N2; the control terminal of transistor T7 is electrically connected to the fourth scan signal terminal Gate4; the first terminal of transistor T7 is electrically connected to the third input signal terminal IN3; the second terminal of transistor T7 is electrically connected to the third node N3; the control terminal of transistor T8 is electrically connected to the fifth scan signal terminal Gate5; the first terminal of transistor T8 is electrically connected to the fourth input signal terminal IN4; the second terminal of transistor T8 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1; the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4; the second terminal of capacitor C2 is electrically connected to the third node N3.

[0248] In an exemplary embodiment Figure 22At least one of the first transistor T1 to the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 is an N-type transistor. For example, the first transistor T1 to the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0249] Figure 22 The seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 22 The working process of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the process is similar to... Figure 21 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 operate in the same way. This disclosure only provides... Figure 22 The operation process of the provided pixel driving circuit Figure 21 The working process of the provided pixel driving circuit will not be described in detail here.

[0250] Figure 23 for Figure 22 The provided pixel driving circuit driving timing Figure 1 . Figure 23 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 23 This explanation is based on the example that the second scan signal terminal connected to the pixel driving circuit of row i receives the same signal as the first scan signal terminal connected to the pixel driving circuit of row (i-1), and the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receive the same signal. Figure 23 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0251] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0252] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where VIN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0253] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0254] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0255] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0256] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0257] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0258] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0259] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(Vdata -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0260] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0261] I = K * (Vgs - Vth) 2

[0262] =K*(V1-V3-Vth) 2

[0263] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0264] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0265] Figure 24 for Figure 22 The provided pixel driving circuit driving timing Figure 2 . Figure 24 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 24 This explanation is based on the example where the second scan signal terminal connected to the pixel driving circuit of row i receives the same signal as the first scan signal terminal connected to the pixel driving circuit of row (i-1), and the fifth scan signal terminal (Gate5) receives the valid level signal later than the fourth scan signal terminal (Gate4). Figure 24 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0266] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 is turned off.

[0267] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where VIN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0268] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0269] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0270] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0271] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0272] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0273] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0274] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0275] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0276] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + VOLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0277] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0278] I = K * (Vgs - Vth) 2

[0279] =K*(V1-V3-Vth) 2

[0280] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0281] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0282] Figure 24 The operation process of the provided pixel driving circuit and Figure 23 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0283] Figure 25 for Figure 22 The provided pixel driving circuit driving timing Figure 3 . Figure 25 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 25 This explanation uses the example of the second scan signal terminal and the first light emission signal terminal, both connected to the same pixel driving circuit, receiving the same signal, and the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receiving the same signal. Figure 25 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0284] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0285] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0286] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0287] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0288] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0289] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0290] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0291] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0292] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0293] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0294] I = K * (Vgs - Vth) 2

[0295] =K*(V1-V3-Vth) 2

[0296] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0297] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0298] Figure 26 for Figure 22 The provided pixel driving circuit driving timing Figure 4 . Figure 26 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 26 This explanation is based on the example where the signals received by the second scan signal terminal and the first light-emitting signal terminal, which are connected to the same pixel driving circuit, are the same, and the time when the fifth scan signal terminal (Gate5) receives the valid level signal is later than the time when the fourth scan signal terminal (Gate4) receives the valid level signal. Figure 26 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0299] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0300] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0301] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0302] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0303] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0304] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0305] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0306] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0307] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0308] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0309] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0310] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0311] I = K * (Vgs - Vth) 2

[0312] =K*(V1-V3-Vth) 2

[0313] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0314] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0315] Figure 26 The operation process of the provided pixel driving circuit and Figure 25Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0316] Figure 27 for Figure 22 The provided pixel driving circuit driving timing Figure 5 . Figure 27 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 27 This is explained by the fact that the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receive the same signal. For example... Figure 27 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0317] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0318] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0319] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0320] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0321] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0322] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0323] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0324] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0325] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0326] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0327] I = K * (Vgs - Vth) 2

[0328] =K*(V1-V3-Vth) 2

[0329] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0330] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0331] Figure 28 for Figure 22 The provided pixel driving circuit driving timing Figure 6 . Figure 28 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 28 This is explained by the fact that the time when the fifth scan signal terminal, Gate5, receives the valid level signal is later than the time when the fourth scan signal terminal, Gate4, receives the valid level signal. For example... Figure 28 As shown, Figure 22 The operation of the provided pixel driving circuit may include:

[0332] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0333] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0334] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0335] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V dataWhen the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0336] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0337] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0338] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0339] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2This is the voltage value of the signal at the second input signal terminal IN3.

[0340] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0341] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0342] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0343] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0344] I = K * (Vgs - Vth) 2

[0345] =K*(V1-V3-Vth) 2

[0346] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0347] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0348] Figure 28The operation process of the provided pixel driving circuit and Figure 27 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0349] Figure 29 for Figure 22 The provided pixel driving circuit driving timing Figure 7 . Figure 29 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 29 Provided driver timing and Figure 23 The only difference between the provided driving timing sequences is the duration of the active signal levels at the first scan signal terminal (Gate1) and the second scan signal terminal (Gate2). However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Figure 29 The operation process of the provided pixel driving circuit and Figure 23 The operation of the provided pixel driving circuit is exactly the same, and will not be described again in this disclosure.

[0350] Figure 30 for Figure 22 The provided pixel driving circuit driving timing Figure 8 . Figure 30 Therefore Figure 22 All transistors in the example are N-type transistors. Figure 30 Provided driver timing and Figure 24 The only difference between the provided driving timing sequences is the duration of the active signal levels at the first scan signal terminal (Gate1) and the second scan signal terminal (Gate2). However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Figure 30 The operation process of the provided pixel driving circuit and Figure 24 The operation of the provided pixel driving circuit is exactly the same, and will not be described again in this disclosure.

[0351] Figure 31 An equivalent circuit for a pixel driving circuit Figure 5 .like Figure 31As shown, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2 and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; and the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0352] In an exemplary embodiment Figure 31 At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 is an N-type transistor. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 may all be N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors, and the fifth transistor T5 and the sixth transistor T6 may be P-type transistors.

[0353] Figure 32 An equivalent circuit for a pixel driving circuit Figure 6 , Figure 33 An equivalent circuit for a pixel driving circuit Figure 7 .like Figure 32 and Figure 33 As shown, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of the second initial sub-circuit and the third initial sub-circuit. Figure 32 and Figure 33The following description uses a pixel driving circuit comprising a second initial sub-circuit and a third initial sub-circuit as an example. The first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, and the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1. The first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the nodes N3 and N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 32 This explanation uses the electrical connection between the second terminal and the third node of the seventh transistor as an example. Figure 33 This explanation uses the electrical connection between the second terminal of the seventh transistor and the fifth node as an example.

[0354] In an exemplary embodiment Figure 32 and Figure 33 At least one of the following transistors in the configuration is an N-type transistor: the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be N-type transistors, while the fifth transistor T5 and the sixth transistor T6 may be P-type transistors.

[0355] Figure 32 and Figure 33 The seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 27 and Figure 28 The working process of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 in the process is similar to... Figure 26 The first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 operate in the same way. This disclosure only provides... Figure 27 and Figure 28 The operation process of the provided pixel driving circuit Figure 26 The working process of the provided pixel driving circuit will not be described in detail here.

[0356] Figure 34 for Figure 32 and Figure 33 The provided pixel driving circuit driving timing Figure 1 . Figure 34 Therefore Figure 32 and Figure 33 All transistors in the example are N-type transistors. Figure 34 This explanation uses the example of the fourth scan signal terminal (Gate4) and the fifth scan signal terminal (Gate5) receiving the same signal. Figure 34 As shown, Figure 32 and Figure 33 The operation of the provided pixel driving circuit may include:

[0357] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1) and the second light-emitting signal terminal (EM2) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 and the sixth transistor T6 are turned off.

[0358] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0359] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0360] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0361] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0362] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0363] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vdata The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0364] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0365] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0366] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0367] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + VOLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0368] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0369] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0370] I = K * (Vgs - Vth) 2

[0371] =K*(V1-V3-Vth) 2

[0372] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0373] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0374] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0375] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0376] I = K * (Vgs - Vth)2

[0377] =K*(V1-V3-Vth) 2

[0378] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0379] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0380] Figure 35 for Figure 32 and Figure 33 The provided pixel driving circuit driving timing Figure 2 . Figure 35 Therefore Figure 32 and Figure 33 All transistors in the example are N-type transistors. Figure 35 This explanation uses the example of Gate 5 receiving a valid level signal at a time later than Gate 4 receiving a valid level signal at the fourth scan signal terminal. Figure 35 As shown, Figure 32 and Figure 33 The operation of the provided pixel driving circuit may include:

[0381] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0382] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0383] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0384] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0385] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V.IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0386] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0387] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0388] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -Vdata (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0389] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0390] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0391] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0392] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0393] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0394] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1-Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0395] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0396] I = K * (Vgs - Vth) 2

[0397] =K*(V1-V3-Vth) 2

[0398] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0399] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0400] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0401] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0402] I = K * (Vgs - Vth) 2

[0403] =K*(V1-V3-Vth) 2

[0404] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0405] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0406] Figure 36 An equivalent circuit for a pixel driving circuit Figure 8 .like Figure 36 As shown, the pixel driving circuit includes: a first initialization sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. Specifically, the first initialization sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N4. Node N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0407] In an exemplary embodiment Figure 36At least one of the first transistor T1 to the sixth transistor T6 is an N-type transistor. For example, the first transistor T1 to the sixth transistor T6 are all N-type transistors, or the first transistor T1 and the first transistor T4 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0408] Figure 37 An equivalent circuit for a pixel driving circuit Figure 9 , Figure 38 An equivalent circuit for a pixel driving circuit Figure 10 , Figure 39 An equivalent circuit for a pixel driving circuit Figure 10 one, Figure 40 An equivalent circuit for a pixel driving circuit Figure 10 2. For example Figures 37 to 40 As shown, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of the second initial sub-circuit and the third initial sub-circuit. Figure 37 and Figure 38 The explanation is based on an example of a pixel driving circuit including a second initial sub-circuit. Figure 39 and Figure 40The following description uses a pixel driving circuit comprising a second initial sub-circuit and a third initial sub-circuit as an example. The first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6; the second initial sub-circuit includes a seventh transistor T7; and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. Connections: The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, and the first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN. 3. Electrical connections: The second terminal of the seventh transistor T7 is electrically connected to the third node N3 or the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 37 and Figure 39This explanation uses the electrical connection between the second terminal of the seventh transistor T7 and the third node N3 as an example. Figure 38 and Figure 40 The following explanation uses the example of the electrical connection between the second terminal of the seventh transistor T7 and the fifth node N5.

[0409] In an exemplary embodiment Figure 39 and Figure 40 At least one of the first transistor T1 to the eighth transistor T8 is an N-type transistor. For example, the first transistor T1 to the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0410] Figures 37 to 40 The seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figures 37 to 40 The working process of the first transistor T1 to the sixth transistor T6 in the process and Figure 36 The first transistor T1 to the sixth transistor T6 in the circuit operate in the same way. Figure 39 and Figure 37 Compared to the previous version, only the eighth transistor T8 was added. Figure 39 The working process of the first transistor T1 to the seventh transistor T7 in the process is as follows Figure 37 The first transistor T1 to the seventh transistor T7 operate in the same way. Figure 40 and Figure 38 Compared to the previous version, only the eighth transistor T8 was added. Figure 40 The working process of the first transistor T1 to the seventh transistor T7 in the process is as follows Figure 38 The first transistor T1 to the seventh transistor T7 operate in the same way.

[0411] This disclosure is only for informational purposes. Figure 39 and Figure 40 The operation process of the provided pixel driving circuit Figure 36 , Figure 37 and Figure 39 The working process of the provided pixel driving circuit will not be described in detail here.

[0412] Figure 41 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 1 . Figure 41 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 41This explanation is based on the example where the second scan signal terminal connected to the pixel driving circuit of row i and the first scan signal terminal connected to the pixel driving circuit of row i-1 receive the same signal, and the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 receive the same signal. Figure 41 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0413] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the second transistor (T2), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the fifth transistor (T5) and the sixth transistor (T6) are turned off.

[0414] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0415] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0416] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0417] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0418] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0419] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0420] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0421] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0422] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0423] I = K * (Vgs - Vth) 2

[0424] =K*(V1-V3-Vth) 2

[0425] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0426] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0427] Figure 42 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 2 . Figure 42 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 42 This explanation is based on the example where the signals received by the second scan signal terminal connected to the pixel driving circuit of row i and the first scan signal terminal connected to the pixel driving circuit of row (i-1) are the same, and the effective level signal received by the fifth scan signal terminal Gate5 is received later than the effective level signal received by the fourth scan signal terminal Gate4. Figure 42 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0428] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1), the second transistor (T2), and the seventh transistor (T7) are turned on, while the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0429] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0430] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0431] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0432] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0433] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0434] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0435] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0436] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0437] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0438] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -VIN2 (C2 / C1+C2)

[0439] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0440] I = K * (Vgs - Vth) 2

[0441] =K*(V1-V3-Vth) 2

[0442] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0443] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0444] Figure 42 The operation process of the provided pixel driving circuit and Figure 42 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0445] Figure 43 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 3 . Figure 43 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 43 This explanation is based on the example where the second scan signal terminal and the first light-emitting signal terminal, connected to the same pixel driving circuit, receive the same signal, and the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receive the same signal. Figure 43 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0446] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0447] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0448] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0449] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0450] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0451] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0452] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0453] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0454] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0455] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0456] I = K * (Vgs - Vth) 2

[0457] =K*(V1-V3-Vth) 2

[0458] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0459] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0460] Figure 44 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 4 . Figure 44 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 44This explanation is based on the example where the signals received by the second scan signal terminal and the first light-emitting signal terminal, which are connected to the same pixel driving circuit, are the same, and the time when the fifth scan signal terminal (Gate5) receives the valid level signal is later than the time when the fourth scan signal terminal (Gate4) receives the valid level signal. Figure 44 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0461] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0462] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0463] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0464] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0465] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0466] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0467] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0468] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0469] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0470] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0471] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0472] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0473] I = K * (Vgs - Vth) 2

[0474] =K*(V1-V3-Vth) 2

[0475] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0476] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0477] Figure 44 The operation process of the provided pixel driving circuit and Figure 43 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0478] Figure 45 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 5 . Figure 45 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 45 This is explained by the fact that the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receive the same signal. For example... Figure 45 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0479] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0480] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0481] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0482] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0483] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0484] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0485] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0486] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0487] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0488] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0489] I = K * (Vgs - Vth) 2

[0490] =K*(V1-V3-Vth) 2

[0491] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0492] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0493] Figure 46 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 6 . Figure 46 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 46 This is explained by the fact that the time when the fifth scan signal terminal, Gate5, receives the valid level signal is later than the time when the fourth scan signal terminal, Gate4, receives the valid level signal. For example... Figure 46 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0494] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0495] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V.IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0496] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0497] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0498] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0499] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0500] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0501] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0502] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0503] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0504] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1-Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0505] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0506] I = K * (Vgs - Vth) 2

[0507] =K*(V1-V3-Vth) 2

[0508] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0509] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0510] Figure 46 The operation process of the provided pixel driving circuit and Figure 45 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0511] Figure 47 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 7 . Figure 47 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 47 This explanation will be based on the example of the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receiving the same signal. Figure 47 Provided driver timing and Figure 41 The difference between the provided drive timings lies in the duration of the valid signal at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. The duration of the valid signal at the second scan signal terminal Gate2 is longer than the duration of the valid signal at the first scan signal terminal Gate1.

[0512] like Figure 47 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0513] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals of the first light-emitting signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4 and the fifth transistor T5 are turned off.

[0514] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3. The sixth transistor T6 is turned on, connecting the signals at the fifth node N5 and the third node N3.

[0515] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0516] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0517] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0518] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0519] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0520] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0521] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0522] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0523] I = K * (Vgs - Vth) 2

[0524] =K*(V1-V3-Vth) 2

[0525] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0526] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0527] Figure 48 for Figure 39 and Figure 40 The provided pixel driving circuit driving timing Figure 8 . Figure 48 Therefore Figure 39 and Figure 40 All transistors in the example are N-type transistors. Figure 48 This explanation is based on the example where the time at which the fifth scan signal terminal, Gate5, receives the valid level signal is later than the time at which the fourth scan signal terminal, Gate4, receives the valid level signal. Figure 48 Provided driver timing and Figure 42 The difference between the provided drive timings lies in the duration of the valid signal at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. The duration of the valid signal at the second scan signal terminal Gate2 is longer than the duration of the valid signal at the first scan signal terminal Gate1.

[0528] like Figure 48 As shown, Figure 39 and Figure 40 The operation of the provided pixel driving circuit may include:

[0529] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals of the first light-emitting signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0530] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The sixth transistor T6 is turned on, connecting the signal at the fifth node N5 with the signal at the third node N3.

[0531] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0532] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0533] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0534] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(Vdata -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0535] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0536] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0537] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0538] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0539] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED+Vth-(V data -V IN2 (C2 / C1+C2)

[0540] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0541] I = K * (Vgs - Vth) 2

[0542] =K*(V1-V3-Vth) 2

[0543] =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0544] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0545] Figure 48 The operation process of the provided pixel driving circuit and Figure 47 Compared to the provided pixel driving circuit, the difference lies in that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0546] In an exemplary embodiment Figure 17 , Figure 18 , Figure 21 , Figure 22 , Figure 31 , Figure 32 , Figure 33 , Figures 36 to 40 The control electrode (i.e., the first node) of the third transistor (driving transistor) in the provided pixel driving circuit is only electrically connected to the first transistor T1. In other words, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, which makes the parasitic capacitance of the first transistor have a smaller impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0547] In an exemplary embodiment Figure 17 , Figure 18 , Figure 21 , Figure 22 , Figure 31 , Figure 32 , Figure 33 , Figures 36 to 40The control electrode (i.e., the first node) of the third transistor (driving transistor) in the provided pixel driving circuit is only electrically connected to the first transistor T1. In other words, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, which makes the parasitic capacitance of the first transistor have a smaller impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0548] In an exemplary embodiment, all transistors in the pixel driving circuit can be N-type transistors; or some transistors can be N-type transistors and some transistors can be P-type transistors. N-type transistors can be made of semiconductor oxide materials, while P-type transistors can be made of low-temperature polycrystalline silicon. P-type transistors have a higher MOB (Mean Optical Bound) and Ion (Ion) than N-type transistors, allowing for rapid switching on and off in scenarios with high light emission and anode reset frequencies. For example, the fifth transistor T5 can be a P-type transistor, meaning it is off when the signal at the first light emission signal terminal EM1 is high and on when the signal is low. Alternatively, the fifth and sixth transistors can be P-type transistors, or the fifth, sixth, and seventh transistors can be P-type transistors, which is beneficial for high-frequency refresh and suitable for PWM dimming scenarios. Alternatively, the fourth transistor can be a P-type transistor, which can improve data writing speed. In this case, the second scan signal terminal Gate2 and the third scan signal terminal Gate3 can receive the same signal.

[0549] In an exemplary embodiment Figure 17 , Figure 18 , Figure 21 , Figure 22 In the provided pixel driving circuit, before and after the signal at the fourth node N4 changes, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3.

[0550] [V3-(V IN1 -Vth)]*(C1+C OLED )+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0, where C OLED Let L be the parasitic capacitance of the light-emitting device.

[0551] V3=[C2 / (C1+C2+C OLED )]*(V IN2 -Vdata)+V IN1 -Vth

[0552] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2 + C OLED )]*(V IN2 -Vdata)+Vth

[0553] In an exemplary embodiment Figure 31 , Figure 32 , Figure 33 , Figures 36 to 40 In the provided pixel driving circuit, before and after the signal at the fourth node N4 changes, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3.

[0554] [V3-(V IN1 -Vth)]*C1+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0

[0555] V3=[C2 / (C1+C2)]*(V IN2 -Vdata)+V IN1 -Vth

[0556] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1 Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2)] * (V IN2 -Vdata)+Vth

[0557] Regarding the driving timing mentioned above, for embodiments including transistor T7: S1-S4 can be a refresh period. At the first driving frequency, a display frame can include one refresh period. The first driving frequency can be a frequency in high-frequency driving mode. At the second driving frequency, a display frame can include one refresh period and at least one hold period. The hold period can be defined as a self-scanning period where no data signal is written, the data signal written in the refresh period is held, and the pixel emits light. The second driving frequency can be a frequency in low-frequency driving mode. The hold period can include a first hold period and a second hold period. In the first hold period, only the seventh transistor T7 is turned on, and all other transistors are turned off to reset the anode of the light-emitting device, i.e., the signal at the fourth scan signal terminal Gate4 is an effective level signal. The seventh transistor T7 can be turned on multiple times, and the number of times is not limited. In the second hold period, the seventh transistor T7 is turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on, and the light-emitting device L emits light.

[0558] When the embodiment further includes an eighth transistor T8, the eighth transistor T8 may also be turned on during the first holding phase, writing the fourth initial signal into the second node N2 to bias the driving transistor; the turn-on time of the eighth transistor T8 may occur after the turn-on time of the seventh transistor T7, or it may be at the same time as the turn-on time of the seventh transistor T7. This disclosure does not limit this. The eighth transistor T8 may be turned on multiple times, and the number of times is not limited.

[0559] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving the pixel driving circuit may include:

[0560] Step 100: Under the control of the signal from the first node, the driving sub-circuit provides a driving signal to the third node;

[0561] Step 200: Under the control of the signal at the first scanning signal terminal, the first initial sub-circuit provides the signal at the first input signal terminal to the first node;

[0562] Step 300: Under the control of the signal at at least one scanning signal terminal, the coupling sub-circuit couples the signal at the data signal terminal or the second input signal terminal to the third node;

[0563] Step 400: Maintain the voltage difference between the signals of the first node and the third node stored in the sub-circuit;

[0564] Step 500: Under the control of the signal at the first light-emitting signal terminal, the light-emitting control sub-circuit provides the signal at the first power supply terminal to the second node.

[0565] This disclosure also provides a display device, including: any one of the aforementioned pixel driving circuits arranged in an array.

[0566] The display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, multiple scan signal terminals, multiple data signal lines, multiple light-emitting signal lines, and a pixel array. The timing controller is connected to the data driver, scan driver, and light-emitting driver. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The first and second light-emitting signal terminals connected to the pixel driving circuit are electrically connected to the light-emitting signal lines. At least one scan signal terminal connected to the pixel driving circuit is electrically connected to the scan signal line, and the data signal terminal connected to the pixel driving circuit is electrically connected to the data signal line.

[0567] The data driver is connected to multiple data signal lines, the scan driver is connected to multiple scan signal lines, and the light-emitting driver is connected to multiple light-emitting signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to the scan signal lines by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the scan signal lines. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An LED driver can generate transmit signals to be provided to the LED signal lines by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED driver can sequentially provide transmit signals with off-level pulses to the LED signal lines. For example, an LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal.

[0568] The display device may include a plurality of pixel units arranged in a matrix. At least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third sub-pixels are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third sub-pixels are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0569] In an exemplary embodiment, the first sub-pixel can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light.

[0570] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0571] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement, etc., and this disclosure does not limit the arrangement.

[0572] In an exemplary embodiment, the display device can be any product or component with display function, such as a wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0573] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0574] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0575] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, characterized in that, The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method.

2. The pixel driving circuit according to claim 1, characterized in that, The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method.

3. The pixel driving circuit of claim 1, wherein, The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method.

4. The pixel driving circuit of claim 1, wherein, The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. 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The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to a display driving circuit and a display driving method. The application relates to 5. The pixel driving circuit of claim 1, wherein, The first initial sub-circuit comprises a first transistor, the holding sub-circuit comprises a first capacitor, and the driving sub-circuit comprises a third transistor, and the third transistor comprises a first control electrode and a second control electrode; The control electrode of the first transistor is electrically connected with the first scan signal end, the first electrode of the first transistor is electrically connected with the first input signal end, and the second electrode of the first transistor is electrically connected with the first node; The first control electrode of the third transistor is electrically connected with the first node, the second control electrode of the third transistor is electrically connected with the third node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the third node.

6. The pixel driving circuit of claim 1, wherein, The pixel driving circuit is configured to drive the light emitting device to emit light, and the light emitting control sub-circuit comprises a fifth transistor. The control electrode of the fifth transistor is electrically connected with the first light emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node. The light emitting device is respectively electrically connected with the third node and the second power supply end.

7. The pixel driving circuit of claim 1, wherein, The pixel driving circuit is configured to drive the light emitting device to emit light, and the light emitting control sub-circuit is further electrically connected with the second light emitting signal end, the third node and the fifth node, and the light emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is electrically connected with the first light emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node. The control electrode of the sixth transistor is electrically connected with the second light emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fifth node. The light emitting device is respectively electrically connected with the fifth node and the second power supply end.

8. The pixel driving circuit according to claim 6 or 7, characterized in that, Further comprising: A second initial sub-circuit; The second initial sub-circuit is respectively electrically connected with the fourth scan signal end, the third input signal end and the third node, and is configured to provide the signal of the third input signal end to the third node under the control of the signal of the fourth scan signal end.

9. The pixel driving circuit of claim 8, wherein, The second initial sub-circuit comprises a seventh transistor. The control electrode of the seventh transistor is electrically connected with the fourth scan signal end, the first electrode of the seventh transistor is electrically connected with the third input signal end, and the second electrode of the seventh transistor is electrically connected with the third node.

10. The pixel driving circuit of claim 7, wherein, Further comprising: A second initial sub-circuit; The second initial sub-circuit is respectively electrically connected with the fourth scan signal end, the third input signal end and the fifth node, and is configured to provide the signal of the third input signal end to the fifth node under the control of the signal of the fourth scan signal end.

11. The pixel driving circuit of claim 10, wherein, The second initial sub-circuit comprises a seventh transistor. The control electrode of the seventh transistor is electrically connected with the fourth scan signal end, the first electrode of the seventh transistor is electrically connected with the third input signal end, and the second electrode of the seventh transistor is electrically connected with the fifth node.

12. The pixel driving circuit of claim 1, wherein, Further comprising: A third initial sub-circuit; The third initial sub-circuit is respectively electrically connected with the fifth scan signal end, the fourth input signal end and the second node, and is configured to provide the signal of the fourth input signal end to the second node under the control of the signal of the fifth scan signal end.

13. The pixel driving circuit of claim 1, 8, 10 or 12, wherein, The third initial sub-circuit comprises an eighth transistor. The control electrode of the eighth transistor is electrically connected with the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected with the second node.

14. The pixel driving circuit of claim 1, wherein, The signals received by the first input signal terminal and the first power supply terminal connected with the same pixel driving circuit are the same signals.

15. The pixel driving circuit of claim 1, wherein, The signals received by the first input signal terminal and the second input signal terminal connected with the same pixel driving circuit are the same signals.

16. The pixel driving circuit according to claim 8 or 10, characterized in that, The signals received by the second input signal terminal and the third input signal terminal connected with the same pixel driving circuit are the same signals.

17. The pixel driving circuit of claim 12, wherein, The signals received by the second input signal terminal and the fourth input signal terminal connected with the same pixel driving circuit are the same signals.

18. The pixel driving circuit of claim 1, wherein, The signals received by the second scan signal terminal and the first emitting signal terminal connected with the same pixel driving circuit are the same signals, or the signals received by the second scan signal terminal of the i-th row pixel driving circuit and the first scan signal terminal of the i-1-th row pixel driving circuit are the same signals.

19. The pixel driving circuit of claim 13, wherein, The signals received by the fourth scan signal terminal and the fifth scan signal terminal connected with the same pixel driving circuit are the same signals.

20. The pixel driving circuit according to claim 8 or 10, characterized in that, The signals received by the third scan signal terminal of the i-th row pixel driving circuit and the fourth scan signal terminal of the i+K-th row pixel driving circuit are the same signals, and K is a positive integer greater than 1.

21. A display device comprising: The pixel driving circuit comprises: The pixel driving circuit comprises:

22. A driving method of a pixel driving circuit, characterized by, The method is configured to drive the pixel driving circuit, and the method comprises: The driving sub-circuit provides a driving signal to the third node under the control of the signals at the first node and the second node; The first initial sub-circuit provides the signal of the first input signal terminal to the first node under the control of the signal of the first scan signal terminal; The coupling sub-circuit couples the signal of the data signal terminal or the second input signal terminal to the third node under the control of the signal of at least one scan signal terminal; The holding sub-circuit stores the voltage difference of the signals of the first node and the third node; The emitting control sub-circuit provides the signal of the first power supply terminal to the second node under the control of the signal of the first emitting signal terminal.

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