Nonvolatile memory device and operating method thereof

Abstract

A non-volatile memory device and an operating method thereof are provided. The nonvolatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a page buffer unit including a page buffer connected to the plurality of memory cells through the plurality of bit lines; and a control logic circuit configured to output at least one control signal to the page buffer unit based on a read command and an address to perform a read operation, the read operation including a word line setup operation, a pre-charge operation, a development operation, and a sensing operation. The control logic circuit is configured to detect a word line charging current, adjust at least one of the bit line voltage control signal sets after a word line setup operation, and adjust a bit line connection control signal during a development operation.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0123425, filed on September 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of the inventive concept relate to an electronic device, and more specifically, to a non-volatile memory device and a method of operating the same. Background Technology

[0003] Memory devices are used to store data and can be classified as volatile memory devices and non-volatile memory devices. With the development of semiconductor manufacturing technology, the operating speed of host devices is constantly increasing, and the capacity of content used in host devices is also constantly growing. Therefore, improving the reliability of data stored in memory devices can be advantageous. Summary of the Invention

[0004] Some exemplary embodiments of the inventive concept provide non-volatile memory devices and methods of operation thereof for improving data reliability.

[0005] According to some exemplary embodiments of the inventive concept, a non-volatile memory device is provided, comprising: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a page buffer unit including page buffers connected to the plurality of memory cells via the plurality of bit lines; and control logic circuitry configured to: output at least one control signal to the page buffer unit based on a read command and an address to perform a read operation, the read operation including: a word line establishment operation, a precharge operation, a development operation, and a sensing operation. The control logic circuitry is configured to: detect a word line charging current that varies based on the state of the plurality of memory cells during a preset detection time in the word line establishment operation; adjust at least one of a set of bit line voltage control signals after the word line establishment operation; and adjust a bit line connection control signal during the development operation based on the detected value of the word line charging current and at least one reference value.

[0006] According to some exemplary embodiments of the inventive concept, a non-volatile memory device is provided, comprising: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a page buffer unit including a page buffer connected to the plurality of memory cells via the plurality of bit lines; and control logic circuitry configured to output at least one control signal to the page buffer unit based on a write command and an address to perform a programming verification operation in each of a plurality of programming cycles. The programming verification operation includes: a word line establishment operation, at least one precharge operation, at least one development operation, and at least one sensing operation, and the control logic circuitry is configured to: detect a word line charging current varying based on the state of the plurality of memory cells during a preset detection time in the word line establishment operation, and adjust at least one of: a set of bit line voltage control signals after the word line establishment operation, and a bit line connection control signal during the at least one development operation based on the detected value of the word line charging current and at least one reference value.

[0007] According to some exemplary embodiments of the inventive concept, a method of operating a non-volatile memory device is provided, comprising: increasing the voltage level of multiple word lines to the voltage level of the multiple word line voltages; detecting a word line charging current related to the multiple word line voltages during a detection time equal to or less than a word line establishment period; determining an adjustment value for adjusting at least one of a set of bit line voltage control signals and a bit line connection control signal applied to the multiple bit lines based on the detected value of the word line charging current and at least one reference value; activating the set of bit line voltage control signals and the bit line establishment signal; activating the bit line connection control signal after the bit line establishment signal is deactivated; and activating at least one monitoring signal after the bit line connection control signal is deactivated.

[0008] According to some example embodiments of the inventive concept, the reliability of data stored in non-volatile memory can be improved. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram of a storage system according to some example embodiments.

[0011] Figure 2 This is a block diagram of a non-volatile memory device according to some example embodiments.

[0012] Figure 3 This is a perspective view of a memory block according to some example embodiments.

[0013] Figure 4 This is a perspective view of a memory block according to some example embodiments.

[0014] Figure 5 This is a circuit diagram of a memory block according to some example embodiments.

[0015] Figure 6 This is a diagram illustrating the main block of some example embodiments based on the inventive concept.

[0016] Figure 7A , Figure 7B , Figure 7C and Figure 7D This is a diagram illustrating sub-blocks according to some example embodiments of the inventive concept.

[0017] Figure 8A , Figure 8B , Figure 8C and Figure 8D This is a diagram illustrating an embodiment in which word line charging current is detected according to some example embodiments.

[0018] Figure 9 It is a block diagram of control logic circuitry according to some example embodiments.

[0019] Figure 10 This is a diagram illustrating a page buffer according to some example embodiments.

[0020] Figure 11 It is provided to Figure 10 Timing diagram of the page buffer signals.

[0021] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E This is a timing diagram of the current detection signal according to some example embodiments.

[0022] Figure 13A , Figure 13B and Figure 13C When detected Figure 12A Timing diagram of the control signal during the first current.

[0023] Figure 14A , Figure 14B and Figure 14C When detected Figure 12E The timing diagram of the control signal for the fifth current.

[0024] Figure 15 This is a diagram illustrating multiple programming loops according to some example embodiments.

[0025] Figure 16 This is a diagram illustrating a page buffer according to some example embodiments.

[0026] Figure 17 It is provided to Figure 16Timing diagram of the page buffer signals.

[0027] Figure 18 This is a flowchart describing the operation of detecting word line charging current in a programming loop according to some example embodiments.

[0028] Figure 19 This is a flowchart describing the operation of detecting word line charging current according to some example embodiments.

[0029] Figure 20 This is a flowchart illustrating a method of operating a non-volatile memory device according to some example embodiments.

[0030] Figure 21 This is a cross-sectional view showing a non-volatile memory device according to some example embodiments. Detailed Implementation

[0031] In the following sections, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0032] The terms “first,” “second,” etc., used herein may describe various components regardless of order and / or importance, and are used only to distinguish one component from another, without limiting the components. For example, “first user device” and “second user device” may refer to different user devices regardless of order or importance. For example, without departing from the scope of the rights described herein, a first component may be named a second component, and similarly, a second component may be renamed a first component.

[0033] Figure 1 This is a block diagram of a storage system 1 according to some example embodiments.

[0034] Reference Figure 1 The storage system 1 may include a host 10 and a storage device 100.

[0035] Host 10 can communicate with storage device 100 via an interface. This interface can be implemented as, for example, Non-Volatile Memory Fast (NVMe), NVMe Management Interface (MI), or NVMe over Memory (NVMeof). Host 10 can provide write requests, logical addresses, and data to storage device 100. Host 10 can also provide read requests and logical addresses to storage device 100.

[0036] Storage device 100 may include memory controller 110 and non-volatile memory 120. Memory controller 110 and non-volatile memory 120 may be integrated into a semiconductor device.

[0037] The memory controller 110 can control the non-volatile memory 120 to read data stored in the non-volatile memory 120 or write (or program) data into the non-volatile memory 120 in response to requests (e.g., write requests or read requests) provided from the host 10. Specifically, the memory controller 110 can provide command / address CMD / ADDR and / or control signal CTRL to the non-volatile memory 120 to control write operations (or programming operations), read operations, and erase operations on the non-volatile memory 120. Furthermore, data to be written or data to be read can be sent and received between the memory controller 110 and the non-volatile memory 120.

[0038] In some example embodiments, the memory controller 110 may provide a read command and a physical address to the non-volatile memory 120. The read command may be a command to read data stored in a memory cell (e.g., a page) connected to a selected word line among multiple word lines.

[0039] In some example embodiments, the memory controller 110 may provide write commands and physical addresses to the non-volatile memory 120. A write command may be a command to store data in a memory cell connected to a selected word line among multiple word lines.

[0040] The memory controller 110 can control a series of internal operations (e.g., performance control, merging, wear leveling, etc.) for the characteristics of the non-volatile memory 120 or for more efficient management of the non-volatile memory 120.

[0041] In some example embodiments, the non-volatile memory 120 may include a memory cell array 121, a page buffer unit 122, and control logic circuitry 123.

[0042] The memory cell array 121 may include multiple memory blocks. Each memory block may include multiple memory cells. The multiple memory cells may be connected to multiple word lines and multiple bit lines.

[0043] Page buffer unit 122 can be connected to multiple memory blocks via multiple bit lines. For example, page buffer unit 122 may include a page buffer connected to multiple memory cells via multiple bit lines.

[0044] In some example embodiments, control logic circuitry 123 may output at least one control signal to page buffer unit 122 for performing a read operation based on a read command and address. The read operation may include word line setup, precharge, develop, and sensing operations.

[0045] In some example embodiments, control logic circuitry 123 may control page buffer unit 122 to perform programming operations based on write commands and addresses. The programming operations may include multiple programming cycles. A programming cycle may include a programming execution operation and a programming verification operation. The programming verification operation may be similar to a read operation. For example, control logic circuitry 123 may output at least one control signal to page buffer unit 122 for performing a programming verification operation in each of the multiple programming cycles.

[0046] Figure 2 This is a block diagram of a non-volatile memory device 2000 according to some example embodiments.

[0047] Reference Figure 2 The non-volatile memory device 2000 can correspond to Figure 1 The non-volatile memory 120. The non-volatile memory device 2000 may include a memory cell array 2010, control logic circuitry 2020, a voltage generator 2030, a row decoder 2040, and a page buffer unit 2050. In some example embodiments, the non-volatile memory device 2000 may also include data input / output circuitry or an input / output interface.

[0048] The memory cell array 2010 may include multiple memory cells and may be connected to word lines WL, serial select lines SSL, ground select lines GSL, and multiple bit lines BL. For example, the memory cell array 2010 may be connected to the row decoder 2040 via word lines WL, serial select lines SSL, and ground select lines GSL, and may be connected to the page buffer unit 2050 via multiple bit lines BL.

[0049] The memory cell array 2010 may include multiple memory blocks BLK1 to BLKz. For example, each of the multiple memory blocks BLK1 to BLKz may have a three-dimensional (3D) structure (or a vertical structure). Specifically, each of the multiple memory blocks BLK1 to BLKz includes a structure extending upwards in a first direction to a third direction. For example, each of the multiple memory blocks BLK1 to BLKz includes multiple NAND strings extending upwards in a third direction. In this respect, the multiple NAND strings may be spaced apart by a specific distance in a first direction and a second direction. The multiple memory blocks BLK1 to BLKz may be selected by a row decoder 2040. For example, the row decoder 2040 may select a memory block corresponding to a block address from the multiple memory blocks BLK1 to BLKz.

[0050] In some example embodiments, each of the plurality of memory blocks BLK1 to BLKz can be implemented as the master block of the erase unit.

[0051] In some example embodiments, each of the plurality of memory blocks BLK1 to BLKz may include a plurality of sub-blocks. Each sub-block may be a block of erase units.

[0052] Each memory cell included in the memory cell array 2010 can store one or more bits. For example, a memory cell can be a single-level cell storing 1 bit of data. For example, a memory cell can be a multi-level cell storing 2 bits of data. For example, a memory cell can be a three-level cell storing 3 bits of data. For example, a memory cell can be a four-level (quad-level or quadruple-level) cell storing 4 bits of data. However, exemplary embodiments of the inventive concept are not limited to the above examples, and memory cells can store 5 or more bits of data.

[0053] In some example embodiments, the plurality of memory blocks BLK1 to BLKz may include at least one of the following: a single-level cell block including single-level cells, a multi-level cell block including multi-level cells, a three-level cell block including three-level cells, and a four-level cell block including four-level cells. A portion of the plurality of memory blocks BLK1 to BLKz may be single-level cell blocks, and other memory blocks may be multi-level cell blocks or three-level cell blocks.

[0054] When an erase voltage is applied to the memory cell array 2010, the memory cell can be in an erase state, and when a programming voltage is applied to the memory cell array 2010, the memory cell can be in a programming state. In this regard, each memory cell can have an erase state or at least one programming state classified according to a threshold voltage. That is, the state of a memory cell can include an erase state and at least one programming state, and a specific state of each memory cell can be an erase state or a specific programming state. For example, a single-level cell can have a threshold voltage distribution corresponding to an erase state or a threshold voltage distribution corresponding to a programming state. For example, a multi-level cell can have a threshold voltage distribution corresponding to an erase state, a threshold voltage distribution corresponding to a first programming state, a threshold voltage distribution corresponding to a second programming state, or a threshold voltage distribution corresponding to a third programming state. For example, a three-level cell can have eight threshold voltage distributions. For example, a four-level cell can have sixteen threshold voltage distributions. However, the example embodiments are not limited to the above examples, and when a memory cell stores 5 or more bits of data, the memory cell can have 32 or more threshold voltage distributions.

[0055] The control logic circuit 2020 typically controls various operations within the non-volatile memory device 2000. For example, the control logic circuit 2020 can output various control signals for writing data to or reading data from the memory cell array 2010 based on the command CMD, the address ADDR, and the control signal CTRL.

[0056] Various control signals output from the control logic circuit 2020 can be provided to the voltage generator 2030, the row decoder 2040, and the page buffer unit 2050. The control logic circuit 2020 can provide the voltage control signal CTRL_vol to the voltage generator 2030. The control logic circuit 2020 can provide the row address X-ADDR to the row decoder 2040. The control logic circuit 2020 can provide the column address Y-ADDR to the page buffer unit 2050.

[0057] In some example embodiments, during a programming verification operation or a read operation, the control logic circuit 2020 may detect the word line charging current Iwdc. The word line charging current Iwdc may be a current that varies according to the state of multiple memory cells. The word line charging current Iwdc may be a current generated simultaneously (e.g., simultaneously with the creation of multiple word lines WL or simultaneously with the charging of the voltages of multiple word lines WL) by multiple word line voltages VWL during a word line creation operation. Because the word line charging current Iwdc is a current generated when multiple word lines WL are created, it can be associated with multiple word line voltages VWL. See below. Figures 8A to 8D The word line charging current Iwdc is described. Control logic circuitry 2020 can detect the word line charging current Iwdc within a preset detection time. Control logic circuitry 2020 can compensate for cell currents that vary depending on the state (e.g., erase state or programming state) of pages included in a specific sub-block (e.g., an unselected sub-block) based on the detected value of the word line charging current Iwdc and at least one reference value. Referring below... Figure 6 as well as Figures 7A to 7D The unit current is described.

[0058] In some example embodiments, the control logic circuit 2020 can compensate for cell current by increasing or decreasing the voltage level of the selected bit line.

[0059] In some example embodiments, the control logic circuit 2020 can compensate for the cell current by increasing or decreasing the time used to discharge the voltage level of the selected bit line.

[0060] Voltage generator 2030 can be connected to memory cell array 2010 via multiple word lines WL. Voltage generator 2030 can generate various types of word line voltages VWL for performing programming, reading, and erasing operations on memory cell array 2010 based on external power supply voltage VEXT and voltage control signal CTRL_vol. For example, voltage generator 2030 can generate programming voltage, read voltage, erase voltage, pass voltage (e.g., programming pass voltage, read pass voltage, or verification pass voltage), erase enable voltage, and verification voltage (e.g., programming verification voltage or erase verification voltage) supplied to multiple word lines WL.

[0061] In some example embodiments, the external power supply voltage VEXT may correspond to the external voltage (EVC) consumed by the non-volatile memory device 2000 or as a boost voltage of Vpp consumed by the non-volatile memory device 2000.

[0062] Multiple word line voltages VWL generated by voltage generator 2030 can be provided to multiple word lines WL. For example, a programming voltage, a verification voltage, or a read voltage can be provided to selected word lines among the multiple word lines WL, and a pass voltage can be provided to unselected word lines among the multiple word lines WL. The selected word line can be at least one word line selected by the row address X-ADDR.

[0063] During the erase operation, voltage generator 2030 can apply an erase voltage to the well and / or common-source line of the memory block (e.g., Figure 5 (as indicated by "CSL" in the original text). Furthermore, voltage generator 2030 can apply an erase enable voltage (e.g., ground voltage) to all word lines WL of a memory block or a portion of word lines WL included in a sub-block, based on the erase address. During an erase verification operation, voltage generator 2030 can apply an erase verification voltage to all word lines WL of a memory block or apply an erase verification voltage on a word line basis.

[0064] During programming operations, voltage generator 2030 can apply a programming voltage to selected word lines among multiple word lines WL, and apply a programming pass voltage to unselected word lines among multiple word lines WL. Furthermore, during programming verification operations, voltage generator 2030 can apply a programming verification voltage to selected word lines and apply a verification pass voltage to unselected word lines.

[0065] During a read operation, voltage generator 2030 can apply a read voltage to selected word lines among multiple word lines WL, and apply a read pass voltage to unselected word lines.

[0066] The line decoder 2040 can select a specific word line from the word lines WL in response to the line address X-ADDR. For example, during a programming operation, the line decoder 2040 can send a programming voltage to the selected word line according to the line address X-ARRD. The line decoder 2040 can select a portion of the serial select line SSL or a portion of the ground select line GSL in response to the line address X-ARRD.

[0067] Page buffer unit 2050 can be connected to memory cell array 2010 via multiple bit lines BL. Page buffer unit 2050 can select a portion of the multiple bit lines BL in response to column address Y-ADDR. During verification operations (e.g., erase verification operations or program verification operations) or read operations, page buffer unit 2050 can operate as a sense amplifier to sense data stored in selected memory cells via the selected bit lines. Simultaneously, during programming operations, page buffer unit 2050 can operate as a write driver to input data to be stored in memory cell array 2010.

[0068] Page buffer unit 2050 can store data read from memory cell array 2010, or can store data to be stored in memory cell array 2010.

[0069] Page buffer unit 2050 may include multiple page buffers respectively connected to multiple bit lines BL. The multiple page buffers may be configured corresponding to corresponding bit lines, and each page buffer may include multiple latches. Hereinafter, page buffer unit 2050 is defined as including page buffers connected to each bit line. However, the terminology may be defined differently in embodiments, and for example, a page buffer may be provided corresponding to multiple bit lines.

[0070] Figure 3 This is a perspective view of a memory block BLKa according to some example embodiments.

[0071] Reference Figure 3The substrate SUB can be a polycrystalline silicon layer doped with impurities of a first conductivity type (e.g., p-type). The substrate SUB can include various materials and mixtures thereof. A common source line CSL extending in a first direction (e.g., Y-direction) and doped with impurities of a second conductivity type (e.g., n-type) can be disposed on the substrate SUB. A plurality of insulating layers IL extending in the first direction can be sequentially disposed in a third direction (e.g., Z-direction) in the region of the substrate SUB between adjacent common source lines CSL. A plurality of pillars P can be disposed in the third direction, passing through the plurality of insulating layers IL and contacting the substrate SUB. The surface layer S of each of the plurality of pillars P can be used as a channel region, and the inner layer I of each of the plurality of pillars P can include insulating material or an air gap. In the region between adjacent common source lines CSL, a charge storage layer CS can be disposed along the exposed surfaces of the insulating layers IL, the plurality of pillars P and the substrate SUB, and gate electrodes GE (such as ground select line GSL, string select line SSL and word lines WL1 to WL8) can be disposed on the exposed surfaces of the charge storage layer CS. A drain contact DR (or drain) doped with impurities of a second conductivity type may be disposed on each of the plurality of pillars P. Bit lines BL1 to BL3 extending in a second direction (e.g., the X direction) and spaced at a specific distance in the first direction may be disposed on the drain contact DR. The number of each of the ground select line GSL, string select lines SSL1 to SSL3, word lines WL1 to WL8, memory cells MC1 to MC8, and bit lines BL1 to BL3 included in the memory block BLKa is an example and may actually be more or less.

[0072] Figure 4 This is a perspective view of a memory block BLKb according to some example embodiments.

[0073] Reference Figure 4 , omitted with Figure 3 Description of redundant memory block BLKb. A first memory stack ST1 may be disposed on a substrate SUB. Within memory block BLKb, a second memory stack ST2, generated by the same method, may be attached to the first memory stack ST1 generated by the above method. Drain contacts DR (or drain terminals) are respectively disposed on a plurality of pillars P extending to the second memory stack ST2.

[0074] Figure 5 This is a circuit diagram of a memory block BLKc according to some example embodiments.

[0075] Reference Figure 5The memory block BLKc may include, for example, d strings STR (where d is an integer equal to, substantially equal to, or greater than 2) in which a plurality of memory cells are connected in series. Each string STR may include a plurality of memory cells, a string select transistor SST, and a ground select transistor GST. The number of strings STR, the number of word lines WL1 to WL15, and the number of bit lines BL (BL1 to BLd) may be varied in various ways according to some example embodiments.

[0076] In some example embodiments, the non-volatile memory device 2000 including memory block BLKc can perform programming operations on a per-page PG basis, corresponding to each of word lines WL1 to WL15. In some example embodiments, when the memory cell MC is a single-level cell, one page PG may correspond to each word line. For example, when the memory cell MC is a multi-level cell, each word line may correspond to a least significant bit (LSB) page and a most significant bit (MSB) page. For example, when the memory cell MC is a three-level cell, each word line may correspond to an LSB page, a center significant bit (CSB) page, and an MSB page.

[0077] In some example embodiments, when the non-volatile memory device 2000 supports sub-block mode, a memory block BLKc may include multiple sub-blocks. For example, the memory block BLKc may include first sub-blocks to third sub-blocks SB1, SB2, and SB3. Each sub-block may include memory cells MC connected to a portion of a word line. For example, the first sub-block SB1 may include memory cells MC connected to eleventh word line WL11 to fifteenth word line WL15. For example, the second sub-block SB2 may include memory cells MC connected to sixth word line WL6 to cross line WL10. For example, the third sub-block SB3 may include memory cells MC connected to first word line WL1 to fifth word line WL5. The number of sub-blocks included in the memory block BLKc and the number of each word line and memory cell included in a sub-block may be varied in various ways according to some example embodiments. An erase operation may be performed on each of the first to third sub-blocks SB1, SB2, and SB3 according to some example embodiments. That is, an erase operation may be performed on a sub-block basis.

[0078] Figure 6 This is a diagram illustrating the main block MBLK of some example embodiments of the inventive concept.

[0079] Reference Figure 6 The main block MBLK can be a memory block that does not include multiple sub-blocks. According to some example embodiments, erase operations can be performed on a main block MBLK basis. The main block MBLK may include first word lines WL1 through fifteenth word lines WL15. The number of word lines included in the main block MBLK can be determined in various ways according to some example embodiments.

[0080] In a non-volatile memory device 2000 including a main block MBLK, the order in which pages are programmed in the main block MBLK can be predetermined. For example, pages can be programmed sequentially from the fifteenth word line WL15 to the first word line WL1. Specifically, the page corresponding to the fifteenth word line WL15 can be programmed first, and the page corresponding to the first word line WL1 can be programmed last. In this case, the cell current Icc flowing through the first word line BL1 can flow in the direction from the fifteenth word line WL15 to the first word line WL1. The exemplary embodiments of the inventive concept are not limited to... Figure 6 The example embodiment is shown below. As another example, pages can be programmed sequentially from the first word line WL1 to the fifteenth word line WL15. In this case, the cell current Icc can flow in the direction from the first word line WL1 to the fifteenth word line WL15. The magnitude of the cell current Icc can be constant.

[0081] Because the order in which pages are programmed in the main block MBLK is determined, pages programmed before the currently selected word line Sel can be predicted to be in the programming state PGMed, and pages to be programmed after the currently selected word line Sel can be predicted to be in the erasure state ERS. Furthermore, compensation operations can be performed on memory cells during programming verification or read operations to accurately confirm the data. For example, suppose pages are programmed sequentially from the fifteenth word line WL15 to the first word line WL1, and the currently selected word line Sel is the eleventh word line WL11. In this case, all memory cells connected to the first word line WL1 through the crosshair WL10 can be in the erasure state ERS.

[0082] Figure 7A , Figure 7B , Figure 7C and Figure 7D The diagram illustrates the first to third sub-blocks SB1, SB2 and SB3, which are some example embodiments of the inventive concept.

[0083] Reference Figure 7A , Figure 7B , Figure 7C and Figure 7D Erasure operations can be performed on each of the first to third sub-blocks SB1, SB2, and SB3, and each of the first to third sub-blocks SB1, SB2, and SB3 may include a memory cell connected to five word lines. However, the example embodiments are not limited thereto, and the number of sub-blocks and the number of word lines included in each sub-block may vary according to some example embodiments.

[0084] As referenced above Figure 6The order in which pages are programmed in each of the first to third sub-blocks SB1, SB2, SB3 is determined. However, the order in which pages are programmed between the first and third sub-blocks SB1, SB2, SB3 is not determined. Therefore, when a sub-block different from the sub-block containing the currently selected word line Sel is called an unselected sub-block (or sister block), the unselected sub-block is included in the black box BB, and the control logic circuit 2020 does not know whether the pages included in the unselected sub-block have been programmed or erased.

[0085] Simultaneously, the magnitude of the cell current Icc can vary depending on the state of the pages included in the unselected sub-blocks (e.g., erase or programmable). For example, suppose the thirteenth word line WL13 included in the first sub-block SB1 is a selected word line, and the second sub-block SB2 and the third sub-block SB3 are unselected sub-blocks. (Refer to...) Figure 7A When all pages of the second sub-block SB2 and the third sub-block SB3 are in the erased state, the first unit current Icc1 with the maximum value can be generated. (Refer to...) Figure 7B When the ratio of pages in the programmed state to pages in the erased state in an unselected sub-block is 1:1 (e.g., all pages in the second sub-block SB2 are in the programmed state and all pages in the third sub-block SB3 are in the erased state, and vice versa), a second unit current Icc2, which is smaller than the first unit current Icc1, can be generated. (Refer to...) Figure 7C When there are more pages in the programmed state than pages in the erased state in the unselected sub-block, a third unit current Icc3, smaller than the second unit current Icc2, can be generated. (Refer to...) Figure 7D When all pages of the second sub-block SB2 and the third sub-block SB3 are in a programmed state, a fourth cell current Icc4 with a minimum value can be generated. Because memory cells can degrade with variations in the cell current Icc, the reliability of data stored in memory cells can also degrade.

[0086] In some example embodiments, the control logic circuit 2020 may perform a read operation based on a read command and an address corresponding to a specific word line in a selected sub-block included among a plurality of sub-blocks. For example, the control logic circuit 2020 may perform a first read operation based on a first read command and a first address representing the physical address of the fifteenth word line WL15 included in the first sub-block SB1.

[0087] In some example embodiments, the control logic circuit 2020 may perform programming operations based on a write command and an address corresponding to a specific word line in a selected sub-block included among a plurality of sub-blocks. In this regard, a programming verification operation may be performed on the specific word line for each programming cycle. For example, the control logic circuit 2020 may perform a programming execution operation and a programming verification operation on the thirteenth word line WL13 included in the first sub-block SB1 for each programming cycle.

[0088] During read or program verification operations, since the state of the black-box BB page is unknown, the control logic circuit 2020 can perform a compensation operation to ensure the reliability of the data stored in the selected memory cell. In this regard, the desired compensation amount in the compensation operation can vary depending on the state of the black-box BB page. However, since the state of the black-box BB page is unknown, the compensation amount of the cell current Icc can be determined by the word line charging current Iwdc corresponding to the cell current Icc that varies according to the state of the black-box BB page.

[0089] Figure 8A , Figure 8B , Figure 8C and Figure 8D This is a diagram illustrating an embodiment where the word line charging current Iwdc is detected, representing some example embodiments.

[0090] Reference Figure 8A , Figure 8B , Figure 8C and Figure 8D In some example embodiments, voltage generator 2030 may generate internal power supply voltage Vcp based on external power supply voltage VEXT, and generate word line voltage VWL based on internal power supply voltage Vcp.

[0091] In some example embodiments, the word line voltage VWL may include a first word line voltage VWL1 and a second word line voltage VWL2. The first word line voltage VWL1 may be a voltage provided to a selected word line among a plurality of word lines WL. For example, the first word line voltage VWL1 may correspond to a programming voltage, a read voltage, or a verification voltage. The second word line voltage VWL2 may be a voltage provided to an unselected word line among a plurality of word lines WL. For example, the second word line voltage VWL2 may correspond to a programming pass voltage, a read pass voltage, or a verification pass voltage.

[0092] In some example embodiments, the control logic circuit 2020 may provide a voltage control signal CTRL_vol to the voltage generator 2030 based on a command and an address. For example, the control logic circuit 2020 may output a voltage control signal CTRL_vol to generate a read voltage and a read pass voltage based on a read command and an address. For example, the control logic circuit 2020 may output a first voltage control signal to generate a programming voltage and a programming pass voltage during a programming execution operation, and a second voltage control signal to generate a programming verification voltage and a verification pass voltage during a programming verification operation, based on a write command and an address.

[0093] In some example embodiments, the control logic circuit 2020 can detect word line charging current Iwdc based on at least one of the external power supply voltage VEXT, internal power supply voltage Vcp, first word line voltage VWL1, and second word line voltage VWL2 (e.g., word line charging current Iwdc generated based on at least one of the external power supply voltage VEXT, internal power supply voltage Vcp, first word line voltage VWL1, and second word line voltage VWL2).

[0094] In such Figure 8A In some example embodiments shown, the control logic circuit 2020 can detect the current Ia generated by the external power supply voltage VEXT as the word line charging current Iwdc. According to some example embodiments, the current Ia may correspond to the EVC- or Vpp-based current consumed by the chip (e.g., the non-volatile memory device 2000).

[0095] In such Figure 8B In some example embodiments shown, voltage generator 2030 may include charge pump circuit 2031 and word line voltage generator 2032. Charge pump circuit 2031 generates internal power supply voltage Vcp by boosting an external power supply voltage VEXT. Word line voltage generator 2032 generates word line voltage VWL using the internal power supply voltage Vcp. Control logic circuitry 2020 can detect the current Ib generated by the internal power supply voltage Vcp as word line charging current Iwdc. According to some example embodiments, the current Ib may correspond to the current consumed by charge pump circuit 2031.

[0096] In such Figure 8C and Figure 8DIn some example embodiments shown, voltage generator 2030 may include charge pump circuit 2031 and word line voltage generator 2032. Word line voltage generator 2032 may include a first word line voltage generator 2032_1 and a second word line voltage generator 2032_2. The first word line voltage generator 2032_1 can generate a first word line voltage VWL1 to be provided to the selected word line using an internal power supply voltage Vcp. The second word line voltage generator 2032_2 can generate a second word line voltage VWL2 to be provided to the unselected word line using an internal power supply voltage Vcp.

[0097] like Figure 8C The control logic circuit 2020 shown, according to some example embodiments, can detect the current Ic generated by the first word line voltage VWL1 as the word line charging current Iwdc. According to some example embodiments, the current Ic can correspond to the current consumed by the first word line voltage generator 2032_1.

[0098] like Figure 8D The control logic circuit 2020 shown, according to some example embodiments, can detect the current Id generated by the second word line voltage VWL2 as the word line charging current Iwdc. According to some example embodiments, the current Id can correspond to the current consumed by the second word line voltage generator 2032_2.

[0099] According to the above embodiments, the word line charging current Iwdc, which varies according to the state of the page included in the unselected sub-block, can be detected, thereby limiting and / or preventing the degradation of the memory cell and / or improving the reliability of the data stored in the memory cell.

[0100] Figure 9 This is a block diagram of a control logic circuit 2020 according to some example embodiments.

[0101] Reference Figure 9 In some example embodiments, the control logic circuit 2020 may include a current detector 2021, a page buffer unit controller 2022, and a buffer 2023.

[0102] The current detector 2021 can detect the word line charging current Iwdc, which varies according to the state of multiple memory cells, during a preset detection time in a word line setup operation, and can output at least one current detection signal CDS based on the detected value of the word line charging current Iwdc and at least one reference value. An example embodiment of the detection of the word line charging current Iwdc is the same as described above. Figure 8A , Figure 8B , Figure 8C and Figure 8D The descriptions are the same.

[0103] In some example embodiments, the current detector 2021 may output a current detection signal CDS with an activation level when the detected value is greater than, equal to, or substantially equal to a reference value. The number of reference values ​​may be one or more, and two or more reference values ​​may be different values. The number of reference values ​​may be set according to a ratio (or proportion) of a first number of pages in an erased state to a second number of pages in a programmed state in an unselected sub-block. This ratio of the first to the second number may be referred to as the erase-programming ratio. For example, the erase-programming ratio may include 100:0 (%), 75:25 (%), 50:50 (%), 25:75 (%), and 0:100 (%). However, the example embodiments are not limited to the above examples, and the erase-programming ratio may be further subdivided than the above examples, or may be divided less than the above examples, and specific values ​​in the erase-programming ratio may be determined in various ways. As the types of erase-programming ratios are further subdivided, differences in cell current Icc between erase-programming ratios can be compensated for in more detail, thus further improving data reliability. On the other hand, the simpler the types of erase programming ratios are classified and implemented, the less computational overhead there is in compensating for the differences in cell current Icc between erase programming ratios, and thus resource efficiency can be improved.

[0104] Simultaneously, the current detection signal CDS can be a signal where the value of the word line charging current Iwdc of the notification page buffer unit controller 2022 is greater than, equal to, or substantially equal to a specific reference value. The number of current detection signals CDS can correspond to the number of reference values.

[0105] The page buffer unit controller 2022 can generate control signals to be provided to the bit lines based on the command CMD. For example, when the command CMD is a read command or a write command, the page buffer unit controller 2022 can generate a bit line off control signal BLSHF, a bit line clamp control signal BLCLAMP, a bit line establish control signal BLSETUP, a bit line connect control signal CLBLK, and at least one monitoring control signal MON during a read operation or a program verification operation. Each of the bit line off control signal BLSHF, bit line clamp control signal BLCLAMP, bit line establish control signal BLSETUP, bit line connect control signal CLBLK, and at least one monitoring control signal MON can have an active level at a specific time.

[0106] The page buffer unit controller 2022 can adjust at least one of the bit line voltage control signal set and the bit line connection control signal CLBLK based on at least one current detection signal CDS with an activation level.

[0107] The bit line voltage control signal set can be signals used to adjust the level of the voltage applied to the bit line. In some example embodiments, the bit line voltage control signal set may include at least one of a bit line turn-off control signal BLSHF and a bit line clamp control signal BLCLAMP.

[0108] In some example embodiments, the page buffer unit controller 2022 may adjust at least one control signal based on at least one of the first to third tables TBL1, TBL2 and TBL3 and at least one current detection signal CDS having an activation level.

[0109] According to some example embodiments, the first to third tables TBL1, TBL2, and TBL3 may include control parameters based on an activated current detection signal CDS. Control parameters may include, for example, the voltage level of the signal, the time for discharging a pre-charge voltage to the sensing node, or a combination thereof. The activated current detection signal CDS may be indicated as "Active CDS" in the first to third tables TBL1, TBL2, and TBL3. In some example embodiments, the number of current detection signals CDS may be 10, and the erase-programming ratio may include 0:100 (%), 10:90, 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:0, and 100:0. However, the example embodiments are not limited to the examples described above. The 10 current detection signals may be indicated as "CDSa" to "CDSj" in the first to third tables TBL1, TBL2, and TBL3. The erase / program ratio is represented as the "ERS:PGM ratio" in Tables 1 through 3 (TBL1, TBL2, and TBL3). The number of active current detection signals (CDS) can vary depending on the magnitude of the detected word line charging current (Iwdc), and the magnitude of the detected word line charging current (Iwdc) can vary depending on the erase / program ratio. Therefore, the number of active current detection signals (CDS) can correspond to the erase / program ratio, and in some cases, the erase / program ratio can be omitted from Tables 1 through 3 (TBL1, TBL2, and TBL3).

[0110] In some example embodiments, the control logic circuit 2020 may determine the activation level of at least one of the active bit line off control signal BLSHF and the bit line clamp control signal BLCLAMP by using a first table TBL1.

[0111] In some example embodiments, as shown in Table 1 below, the first table TBL1 may include an erase programming ratio and an activation level of a bit line voltage control signal based on the number of current detection signals (CDS) to be activated.

[0112] [Table 1]

[0113] In [Table 1], “N / A” indicates that all current sensing signals CDS are deactivated. “vBL” is the selected bit line voltage level during a read operation or programming verification operation, “vBLSHF” is the activation level of the bit line shutdown control signal BLSHF during a read operation or programming verification operation, and “vBLCLAMP” is the activation level of the bit line clamping control signal BLCLAMP during a read operation or programming verification operation. “vBL” can be a factor determined by “vBLSHF” and “vBLCLAMP”. That is, the page buffer unit controller 2022 can set at least one of “vBLSHF” and “vBLCLAMP” to set a specific voltage level for “vBL”. The magnitude can decrease in the order of “V1”, “V2”, “V3”, “V4”, “V5”, “V6”, “V7”, “V8”, “V9”, “V10”, and “V11”. That is, “V1” can be the largest, and “V11” can be the smallest. The magnitudes of each of “V1’”, “V2’”, “V3’”, “V4’”, “V5’”, “V6’”, “V7’”, “V8’”, “V9’”, “V10’”, and “V11’” are in the same order as the magnitudes of “V1” to “V11”. That is, “V1’” can be the largest, and “V11’” can be the smallest. “CDSa”, “CDSa to CDSb”, “CDSa to CDSc”, “CDSa to CDDSd”, “CDSa to CDSe”, “CDSa to CDDSf”, “CDSa to CDDSg”, “CDSa to CDDSh”, “CDSa to CDSi”, and “CDSa to CDDSj” can be active current detection signals. For example, “CDSa to CDSb” includes “CDSa” and “CDSb”, “CDSa to CDSc” includes “CDSa”, “CDSb” and “CDSc”, “CDSa to CDDSd” includes “CDSa”, “CDSb”, “CDSc” and “CDSd”, and similarly, “CDSa to CDSe”, “CDSa to CDDSf”, “CDSa to CDDSg”, “CDSa to CDDSh”, “CDSa to CDSi”, and “CDSa to CDDSj” also include multiple current detection signals similar to those mentioned above.

[0114] In some example embodiments, the control logic circuit 2020 may determine the activation period during which the bit line connection control signal CLBLK is activated by using a second table TBL2. The activation period during which the bit line connection control signal CLBLK is activated may correspond to the time used to discharge the pre-charge voltage to the sensing node.

[0115] In some example embodiments, as shown in Table 2 below, the second table TBL2 may include the erase programming ratio and the activation period of the bit line connection control signal CLBLK according to the number of current detection signals CDS to be activated.

[0116] [Table 2]

[0117] In [Table 2], “N / A”, “CDSa”, “CDSa and CDSb”, “CDSa to CDSc”, “CDSa to CDDSd”, “CDSa to CDSe”, “CDSa to CDDSf”, “CDSa to CDDSg”, “CDSa to CDDSh”, “CDSa to CDSi”, and “CDSa to CDDSj” are the same as in [Table 1]. “SO discharge time” is the time used to discharge the pre-charge voltage to the sensing node. “SO discharge time” can correspond to the activation period of the bit line connection control signal CLBLK. That is, the page buffer unit controller 2022 can set the “SO discharge time” by changing the activation period of the bit line connection control signal CLBLK. The value can decrease in the order of “t1”, “t2”, “t3”, “t4”, “t5”, “t6”, “t7”, “t8”, “t9”, “t10”, and “t11”. That is, “t1” can be the largest and “t11” can be the smallest.

[0118] In some example embodiments, the control logic circuit 2020 may determine the activation level of the bit line voltage control signal set (e.g., BLSHF / BLCLAMP) and the activation period of the bit line connection control signal CLBLK by using a third table TBL3.

[0119] In some example embodiments, the third table TBL3 is shown in Table 3 below.

[0120] [Table 3]

[0121] In [Table 3], “N / A”, “CDSa”, “CDSa and CDSb”, “CDSa to CDSc”, “CDSa to CDSd”, “CDSa to CDSe”, “CDSa to CDSf”, “CDSa to CDSg”, “CDSa to CDSh”, “CDSa to CDSi”, “CDSa to CDSj”, and “SO discharge time” are the same as those in [Table 1] and [Table 2]. Because “t12” to “t22”, “V12” to “V22”, “V12’” to “V22’”, and “V12’’” to “V22’’” are combined to compensate for the cell current Icc, unlike in [Table 1] and [Table 2], the magnitude relationship of each of “t12” to “t22”, “V12” to “V22”, “V12’” to “V22’”, and “V12’’” to “V22’’” is not uniformly determined and can be optimized in various ways according to some example embodiments.

[0122] In some example embodiments, when at least one control signal in the bit line voltage control signal set and the bit line connection control signal CLBLK is adjusted during a read operation or programming verification operation, the page buffer unit controller 2022 may store an adjustment value AJV for the control signal in a buffer 2023. The adjustment value AJV may include, for example, values ​​of “vBL” (e.g., “vBLSHF” and / or “vBLCLAMP”) and / or “SO discharge time” selected from the first to the third tables TBL1, TBL2, and TBL3.

[0123] In some example embodiments, the page buffer unit controller 2022 may store the address value PAV in the buffer 2023 during a read operation or a program verification operation. When the command CMD is a read command or a write command, the page buffer unit controller 2022 may determine, based on the address value PAV and the value of the currently received address ADDR, whether a sub-block of the page that is the target of the currently performed operation (e.g., a read operation or a program verification operation) is the same as a sub-block of the page that was the target of a previously performed operation. When the two sub-blocks are the same, during the currently performed operation, the page buffer unit controller 2022 may provide an activated detection stop signal DSS to the current detector 2021, and the current detector 2021 may stop or skip the operation of detecting the word line charging current Iwdc in response to the activated detection stop signal DSS. When the two sub-blocks are different, the page buffer unit controller 2022 may deactivate the detection stop signal DSS, and the current detector 2021 may detect the word line charging current Iwdc.

[0124] In some example embodiments, the page buffer unit controller 2022 may store the programming cycle value PLV currently being executed during the programming verification operation in buffer 2023. When the command CMD is a write command and the programming cycle value PLV stored in the current buffer 2023 is 1 or does not exist, the current programming cycle in the programming operation to be executed may be the initial programming cycle. During the programming verification operation of the initial programming cycle, the page buffer unit controller 2022 may deactivate the detection stop signal DSS. When the execution of the initial programming cycle is completed, the page buffer unit controller 2022 may activate the detection stop signal DSS.

[0125] Buffer 2023 may store data received from page buffer unit controller 2022 and may provide the stored data to page buffer unit controller 2022. In some example embodiments, buffer 2023 may store adjustment value AJV, address value PAV, and / or programming cycle value PLV.

[0126] According to the above embodiments, the control signal used in read operations or programming verification operations is adjusted based on the detected word line charging current Iwdc, thereby reducing memory cell degradation caused by variable cell current Icc and / or improving data reliability.

[0127] Figure 10 This is a diagram illustrating a page buffer PB according to some example embodiments.

[0128] exist Figure 10 In this context, the page buffer PB can be included in... Figure 1 and Figure 2 In page buffer units 122 and 2050. The page buffer PB can be connected to any bit line. See reference. Figure 10 For example, the page buffer PB can be connected to the first bit line BL1. However, the example embodiments are not limited to the examples described above.

[0129] Page buffer PB may include first transistors through fifth transistors TR1, TR2, TR3, TR4 and TR5, and a sense latch (S-latch) SL.

[0130] The first transistor TR1 can be connected between the first bit line BL1 and the first node N1, and can be driven by the bit line shutdown control signal BLSHF. The second transistor TR2 can be connected to the first node N1, and can be driven by the bit line clamp control signal BLCLAMP. When the bit line clamp control signal BLCLAMP is activated, the second transistor TR2 can clamp the voltage of the first node N1. The third transistor TR3 can be connected between the sensing node SO and the first node N1, and can be driven by the bit line connection control signal CLBLK. The fourth transistor TR4 can be connected to the sensing node SO, and can be driven by the bit line setup control signal BLSETUP. When the bit line setup control signal BLSETUP is activated, the fourth transistor TR4 can precharge the voltage of the sensing node SO to a precharge level. The fifth transistor TR5 can be connected between the sensing node SO and the sensing latch SL, and can be driven by the sensing monitoring control signal MON_S. For example, the first to fifth transistors TR1, TR2, TR3, TR4 and TR5 can be implemented as NMOS transistors. However, the example embodiment is not limited to the above example.

[0131] The sensing latch SL can store data in a memory cell or sense the threshold voltage of the memory cell during a read operation or a program verification operation. Furthermore, the sensing latch SL can be used to apply a programming bit line voltage or a programming disable voltage to the first bit line BL1 during a program execution operation.

[0132] Figure 11 It is provided to Figure 10 Timing diagram of the signals of the page buffer PB.

[0133] Reference Figure 11 Read operations and programming verification operations may include word line establishment operation (WLS), precharge operation (PRE), development operation (DEV), and sensing operation (SEN).

[0134] During the word line establishment operation (WLS) period, the voltage levels of multiple word lines (WL) increase. For example, when performing a read operation (WLS), a read voltage is applied to the selected word line among the multiple word lines (WL), and a read pass voltage is applied to the unselected word lines among the multiple word lines (WL). When the read operation (WLS) is completed, the voltage level of the selected word line reaches the read voltage level, and the voltage level vUWL of the unselected word line reaches the read pass voltage level. Similarly, when performing a program verification operation (WLS), a verification voltage is applied to the selected word line among the multiple word lines (WL), and a verification pass voltage is applied to the unselected word lines among the multiple word lines (WL). When the program verification operation (WLS) is completed, the voltage level of the selected word line reaches the verification voltage level, and the voltage level vUWL of the unselected word line reaches the verification pass voltage level.

[0135] During the precharge operation PRE, each of the bit line shutdown control signal BLSHF, bit line clamp control signal BLCLAMP, and bit line establishment control signal BLSETUP is activated. For example, when the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 of the page buffer PB are implemented as NMOS transistors, the signal level of each of the bit line shutdown control signal BLSHF, the bit line clamp control signal BLCLAMP, and the bit line establishment control signal BLSETUP can be increased to a specific signal level at the start of the precharge operation PRE. In this case, the voltage level vBL of the selected bit line can be increased. After each of the bit line shutdown control signal BLSHF, the bit line clamp control signal BLCLAMP, and the bit line establishment control signal BLSETUP is activated, the voltage level vSO of the sensing node SO can be increased.

[0136] When the development operation DEV is executed, the bit line setup control signal BLSETUP is deactivated. Simultaneously with the execution of development operation DEV, the bit line connection control signal CLBLK is activated. For example, when the third transistor TR3 and the fourth transistor TR4 of the page buffer PB are implemented as NMOS transistors, when development operation DEV begins, the signal level of the bit line setup control signal BLSETUP decreases to a specific signal level, and the signal level of the bit line connection control signal CLBLK increases to a specific signal level. During the period of execution of development operation DEV, the voltage pre-charged to the sensing node SO is discharged, and the voltage level vSO of the sensing node SO decreases. The degree (or slope) of the decrease in the voltage level vSO of the sensing node SO can vary depending on the threshold voltage distribution of the memory cell. When the memory cell is an on-cell, the voltage level vSO of the sensing node SO can rapidly decrease to a voltage level below the reference voltage level Vref. When the memory cell is an off-cell, the voltage level vSO of the sensing node SO can gradually decrease to a voltage level above the reference voltage level Vref.

[0137] During the period when the sensing operation SEN is performed, the sensing monitoring control signal MON_S can be activated. The sensing latch SL can store data (or sensing results) in the memory cell in response to the activated sensing monitoring control signal MON_S.

[0138] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E It is a timing diagram of the first current detection signal to the fourth current detection signal CDS1, CDS2, CDS3 and CDS4 according to some example embodiments.

[0139] Reference Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E , respectively in Figures 12A to 12E In the graph shown, the horizontal axis represents time (in microseconds). The vertical axis represents the current (in milliamperes (mA)). The current on the vertical axis of the graph corresponds to the word line charging current Iwdc based on the erase programming ratio. Figures 12A to 12E In this example, it is assumed that there are five types of erase programming ratios. For example, the five erase programming ratios could be 0:100 (%), 25:75, 50:50, 75:25, and 100:0. However, the example embodiments are not limited to this, and the number of erase programming ratios can be varied in various ways according to some example embodiments. Figures 12A to 12EThe curves shown can have similar shapes to each other. On the other hand, when the erase programming ratio is divided into 5, the number of the first to fourth current detection signals CDS1, CDS2, CDS3, and CDS4, and the number of the first to fourth reference currents Iref1, Iref2, Iref3, and Iref4, can be implemented as 4. For example... Figures 12A to 12E As shown, for example, among the first reference current to the fourth reference currents Iref1, Iref2, Iref3, and Iref4, the first reference current Iref1 may be the smallest, and the fourth reference current Iref4 may be the largest. The page buffer unit controller 2022 can detect the current corresponding to the word line charging current Iwdc by using the first current detection signals to the fourth current detection signals CDS1, CDS2, CDS3, and CDS4 and the first reference current to the fourth reference currents Iref1, Iref2, Iref3, and Iref4, thereby confirming the five erase programming ratios.

[0140] Reference Figure 12A The first current I1 can correspond to the word line charging current Iwdc detected when the erase programming ratio is 0:100 (%). In the word line establishment operation WLS, the magnitude of the first current I1 during the preset detection time Td can be less than the magnitude of the first reference current Iref1. In this case, the first current detection signal to the fourth current detection signals CDS1, CDS2, CDS3, and CDS4 of the current detector 2021 can be deactivated.

[0141] Reference Figure 12B The second current I2 corresponds to the word line charging current Iwdc detected when the erase programming ratio is 25:75 (%). The first current detection signal CDS1 of the current detector 2021 is activated when the magnitude of the second current I2 is greater than, equal to, or substantially equal to the magnitude of the first reference current Iref1. The activated first current detection signal CDS1 is deactivated when the detection time Td expires.

[0142] Reference Figure 12C The third current I3 corresponds to the word line charging current Iwdc detected when the erase programming ratio is 50:50 (%). The first current detection signal CDS1 of the current detector 2021 is activated when the magnitude of the third current I3 is greater than, equal to, or substantially equal to the magnitude of the first reference current Iref1. The second current detection signal CDS2 of the current detector 2021 is activated when the magnitude of the third current I3 is greater than, equal to, or substantially equal to the magnitude of the second reference current Iref2. When the detection time Td expires, the activated first current detection signal CDS1 and the second current detection signal CDS2 are deactivated.

[0143] Reference Figure 12DThe fourth current I4 corresponds to the word line charging current Iwdc detected when the erase programming ratio is 75:25 (%). Similar to the above description, each of the first to third current detection signals CDS1, CDS2, and CDS3 of the current detector 2021 can be activated when the magnitude of the fourth current I4 is greater than, equal to, or substantially equal to the magnitude of each of the first to third reference currents Iref1, Iref2, and Iref3. When the detection time Td expires, the activated first to third current detection signals CDS1, CDS2, and CDS3 can be deactivated.

[0144] Reference Figure 12E The fifth current I5 corresponds to the word line charging current Iwdc detected when the erase programming ratio is 100:0 (%). Similarly, when the magnitude of the fifth current I5 is greater than, equal to, or substantially equal to the magnitude of each of the first to fourth reference currents Iref1, Iref2, Iref3, and Iref4, each of the first to fourth current detection signals CDS1, CDS2, CDS3, and CDS4 of the current detector 2021 can be activated.

[0145] In some example embodiments, the detection time Td may be less than, equal to, or substantially equal to the time period during which the word line establishment operation WLS is performed.

[0146] Figure 13A , Figure 13B and Figure 13C When detected Figure 12A Timing diagram of the control signal when the first current I1 is reached.

[0147] Reference Figure 13A , Figure 13B and Figure 13CIn some example embodiments, to compensate for cell current Icc (or differences between cell currents), the page buffer cell controller 2022 may adjust at least one of the bit line voltage control signal set activated after the word line establishment operation WLS and the bit line connection control signal CLBLK activated in the development operation DEV based on the detected value of the word line charging current Iwdc and at least one reference value. The bit line voltage control signal set may include a bit line shutdown control signal BLSHF and a bit line clamping control signal BLCLAMP. The word line establishment operation WLS, the precharge operation PRE, and the development operation DEV are the same as described above, so their redundant description is omitted. The number of the first to fourth current detection signals CDS1, CDS2, CDS3, and CDS4 is an example and may be more or less according to some example embodiments. When the first current detection signal to the fourth current detection signal CDS1, CDS2, CDS3 and CDS4 are deactivated during the word line setup operation WLS, the smallest first current I1 among the first current to the fifth current I1, I2, I3, I4 and I5 can be detected, and the erase programming ratio can be 0:100 (%).

[0148] In some example embodiments, the page buffer unit controller 2022 may increase the activation level of at least one of the bit line off control signal BLSHF and the bit line clamp control signal BLCLAMP. (Refer to...) Figure 13A For example, to increase the bit line voltage level vBL above a specific level va3, the activation level of the bit line clamping control signal BLCLAMP can be higher than a specific level va2, and the activation level of the bit line shutdown control signal BLSHF can be higher than a specific level va1. In conjunction with... Figure 13A In some example embodiments different from those shown, only the activation level of the bit line off control signal BLSHF or the activation level of the bit line clamp control signal BLCLAMP may be increased. According to some example embodiments, the activation level of the bit line off control signal BLSHF and / or the activation level of the bit line clamp control signal BLCLAMP may be determined by a first table TBL1 as shown in [Table 1] above, and the page buffer unit controller 2022 may select "V1'" and / or "V1''" mapped to "N / A" in [Table 1] above.

[0149] In some example embodiments, the page buffer unit controller 2022 may increase the activation period of the bit line connection control signal CLBLK. (Refer to...) Figure 13BFor example, the activation period of the bit line connection control signal CLBLK can be increased from a first period tDEV1 to a second period tDEV2. When the activation period of the bit line connection control signal CLBLK increases from the first period tDEV1 to the second period tDEV2, the deactivation time of the activated bit line connection control signal CLBLK can be delayed. According to some example embodiments, the activation period of the bit line connection control signal CLBLK can be determined by a second table TBL2 as shown in [Table 2] above, and the page buffer unit controller 2022 can select "t1" mapped to "N / A" in [Table 2].

[0150] In some example embodiments, the page buffer unit controller 2022 can adjust the activation level of the bit line off control signal BLSHF, the activation level of the bit line clamp control signal BLCLAMP, and the activation period of the bit line connection control signal CLBLK. (Refer to...) Figure 13C For example, to increase the bit line voltage level vBL, the activation level of the bit line clamp control signal BLCLAMP and the activation level of the bit line shutdown control signal BLSHF can be increased, and the activation period of the bit line connection control signal CLBLK can be increased from the first period tDEV1 to the second period tDEV2. According to some example embodiments, the activation level of the bit line clamp control signal BLCLAMP, the activation level of the bit line shutdown control signal BLSHF, and the activation period of the bit line connection control signal CLBLK can be determined by the third table TBL3 as shown in [Table 3] above, and the page buffer unit controller 2022 can select "V12'", "V12''", and "t12" mapped to "N / A" in [Table 3].

[0151] In some example embodiments, the smaller the detected value of the word line charging current Iwdc, the higher the activation level of the bit line off control signal BLSHF and / or the bit line clamp control signal BLCLAMP, and the longer the activation period of the bit line connection control signal CLBLK. For example, because the detected value of the first current I1 is less than the value of the first reference current Iref1, the activation level of the bit line off control signal BLSHF and / or the bit line clamp control signal BLCLAMP and / or the activation period of the bit line connection control signal CLBLK can be increased.

[0152] Figure 14A , Figure 14B and Figure 14C When detected Figure 12E Timing diagram of the control signal for the fifth current I5. (Omitted) Figure 13A , Figure 13B and Figure 13C The description is redundant.

[0153] Reference Figure 14A , Figure 14B and Figure 14C In some example embodiments, to compensate for cell current Icc (or differences between cell currents), the page buffer cell controller 2022 may adjust at least one of the activation levels of the bit line voltage control signal set (e.g., BLSHF / BLCLAMP) and the activation period of the bit line connection control signal CLBLK based on the detected value of the word line charging current Iwdc and at least one reference value. When all four current detection signals CDS1, CDS2, CDS3, and CDS4 are activated during the word line setup operation WLS, the largest fifth current I5 among the first to fifth currents I1, I2, I3, I4, and I5 can be detected, and the erase-program ratio can be 100:0 (%).

[0154] In some example embodiments, the page buffer unit controller 2022 may reduce the activation level of at least one of the bit line off control signal BLSHF and the bit line clamp control signal BLCLAMP. (Refer to...) Figure 14A For example, to reduce the bit line voltage level vBL to below a specific level vb3, the activation level of the bit line clamping control signal BLCLAMP can be reduced to below a specific level vb2, and the activation level of the bit line shutdown control signal BLSHF can be reduced to below a specific level vb1. Figure 14A In some example embodiments different from those shown, the activation level of either the bit line off control signal BLSHF or the bit line clamp control signal BLCLAMP may be reduced. The activation level of the bit line off control signal BLSHF and / or the bit line clamp control signal BLCLAMP, according to some example embodiments, may be determined by a first table TBL1 as shown in [Table 1] above, and the page buffer unit controller 2022 may select “V11’” and / or “V11’’” mapped to “CDSa to CDSj” in [Table 1].

[0155] In some example embodiments, the page buffer unit controller 2022 may reduce the activation period of the bit line connection control signal CLBLK. (Refer to...) Figure 14B For example, the activation period of the bit line connection control signal CLBLK can be reduced from the third period tDEV3 to the fourth period tDEV4. When the activation period of the bit line connection control signal CLBLK is reduced from the third period tDEV3 to the fourth period tDEV4, the deactivation time of the activated bit line connection control signal CLBLK can be accelerated (e.g., advanced). The page buffer unit controller 2022 can select "t11" mapped to "CDSa to CDSj" in [Table 2] as the activation period of the bit line connection control signal CLBLK.

[0156] In some example embodiments, such as Figure 14C As shown, the activation level of the bit line off control signal BLSHF, the activation level of the bit line clamp control signal BLCLAMP, and the activation period of the bit line connection control signal CLBLK can be reduced. The page buffer unit controller 2022 can select “V22'”, “V22''”, and “t22” mapped to “CDSa to CDSj” in [Table 3].

[0157] In some example embodiments, as the detected value of the word line charging current Iwdc increases, the activation level of the bit line off control signal BLSHF and / or the bit line clamp control signal BLCLAMP and / or the activation period of the bit line connection control signal CLBLK can be reduced. For example, because the detected value of the fifth current I5 is greater than the value of each of the first to fourth reference currents Iref1, Iref2, Iref3, and Iref4, the activation level of the bit line off control signal BLSHF and / or the bit line clamp control signal BLCLAMP and / or the activation period of the bit line connection control signal CLBLK can be reduced.

[0158] Although not shown, when a word line charging current Iwdc corresponding to an erase programming ratio included in the range between 0:100 (%) and 100:0 (%) is detected, it is similar to... Figures 13A to 14C The example embodiment shown allows adjustment of the activation level of the bit line shutdown control signal BLSHF, the activation level of the bit line clamp control signal BLCLAMP, and / or the activation period of the bit line connection control signal CLBLK. For example, when a word line charging current Iwdc is detected, the activation level of the bit line shutdown control signal BLSHF, the activation level of the bit line clamp control signal BLCLAMP, and / or the activation period of the bit line connection control signal CLBLK can be determined according to the first to third tables TBL1, TBL2, and TBL3 described above, as well as the activated current detection signals according to [Table 1] to [Table 3].

[0159] Figure 15 This is a diagram illustrating multiple programming loops PL1 to PL21 according to some example embodiments.

[0160] Reference Figure 15The programming operation may include multiple programming cycles PL1 to PL21. According to some example embodiments, the number of programming cycles can be determined in various ways. Each of the multiple programming cycles PL1 to PL21 may include a programming execution operation PE and at least one programming verification operation PV. For example, when the memory cell is a three-level cell, the memory cell may be programmed to one of a first programming state P1 to a seventh programming state P7. In this case, at least one programming verification operation PV may include at least one of the following: a first programming verification operation VFY1 verifying the first programming state P1, a second programming verification operation VFY2 verifying the second programming state P2, a third programming verification operation VFY3 verifying the third programming state P3, a fourth programming verification operation VFY4 verifying the fourth programming state P4, a fifth programming verification operation VFY5 verifying the fifth programming state P5, a sixth programming verification operation VFY6 verifying the sixth programming state P6, and a seventh programming verification operation VFY7 verifying the seventh programming state P7. However, the example embodiments are not limited to the examples described above. According to some example embodiments, a programming verification operation PV for a single-level unit may include a first programming verification operation VFY1, and a programming verification operation PV for a multi-level unit may include a first programming verification operation to a third programming verification operation VFY1, VFY2 and VFY3.

[0161] Each of the first programming verification operations VFY1 through the seventh programming verification operation VFY7 may include a word line establishment operation WLS, a forced sensing operation FS, and a main sensing operation MS. The forced sensing operation FS represents performing a forced sensing or pre-verification operation. The main sensing operation MS represents performing a main sensing or main verification operation. Figure 15 Unlike those shown, in other embodiments, each of the first programming verification operation VFY1 through the seventh programming verification operation VFY7 may include a word line establishment operation WLS and a master sensing operation MS.

[0162] As the programming cycle progresses, memory cells may gradually become successfully programmed. Successful programming means the memory cell has entered the target threshold voltage region. For example, memory cells targeting the first programming state P1 with the lowest target threshold voltage can all be successfully programmed in the seventh programming cycle PL7. The programming operation finally ends after the seventh programming state P7, with the highest target threshold voltage, is successfully programmed.

[0163] Figure 16 This is a diagram illustrating a page buffer PB according to some example embodiments.

[0164] Reference Figure 16 Page buffers (PB) can be included in Figure 1 and Figure 2Page buffer cells 122 and 2050 are used. The page buffer PB can be connected to any bit line (e.g., the first bit line BL1). The page buffer PB may include first transistors TR1 through ninth transistors TR9, a sense latch SL, a forced latch (F-latch) FL, a high-order latch (M-latch) ML, a low-order latch (L-latch) LL, and a cache latch (C-latch) CL. First transistors through fifth transistors TR1, TR2, TR3, TR4, and TR5, and the sense latch SL are referenced above. Figure 10 Since the descriptions are identical, redundant descriptions are omitted.

[0165] A sixth transistor TR6 can be connected between the sensing node SO and the forced latch FL, and can be driven by the forced monitoring control signal MON_F. The forced latch FL can be used to improve the threshold voltage distribution during programming operations. The value stored in the forced latch FL can vary according to the threshold voltage of the memory cell during programming operations, and the voltage applied to the first bit line BL1 can vary according to the value stored in the forced latch FL during programming execution. When the sixth transistor TR6 is turned on by the forced monitoring control signal MON_F, the forced latch FL can be used to improve the threshold voltage distribution during programming operations. Specifically, for example, the forced latch FL can store forced data. The forced data can initially be set to "1", and then inverted to "0" when the threshold voltage of the memory cell enters the forced region that has not reached the target region. The forced latch FL can control the bit line voltage during programming execution operation PE by utilizing the forced data, and can form a narrower threshold voltage distribution.

[0166] The seventh transistor TR7 can be connected between the sensing node SO and the high-order latch ML, and can be driven by the high-order monitoring control signal MON_M. The eighth transistor TR8 can be connected between the sensing node SO and the low-order latch LL, and can be driven by the low-order monitoring control signal MON_L. When the seventh transistor TR7 and the eighth transistor TR8 are turned on by the high-order monitoring control signal MON_M and the low-order monitoring control signal MON_L, the high-order latch ML and the low-order latch LL, which store the target data, can be set according to the sense data stored in the sense latch SL. When the sensed data indicates that programming is complete, the high-order latch ML and the low-order latch LL can be switched to a programming-disable setting for the selected memory cell in subsequent programming cycles.

[0167] The ninth transistor TR9 can be connected between the sensing node SO and the cache latch CL, and can be driven by the cache monitoring control signal MON_C. When the ninth transistor TR9 is turned on by the cache monitoring control signal MON_C, the cache latch CL can receive data read from the memory cell from the sensing latch SL during a read operation, and output the data to the outside via the data output line DOUT. Furthermore, the cache latch CL can temporarily store input data provided from the outside. During a programming operation, the target data stored in the cache latch CL can be stored in the high-order latch ML and the low-order latch LL.

[0168] The high-order latch ML, low-order latch LL, and cache latch CL are used to store data input from an external source during programming operations and can be referred to as data latches. When programming 3 bits of data in a memory cell, the 3 bits of data can be stored in each of the high-order latch ML, low-order latch LL, and cache latch CL. The high-order latch ML, low-order latch LL, and cache latch CL retain the stored data until the programming of the memory cell is complete.

[0169] Figure 17 It is provided to Figure 16 Timing diagram of the signals of the page buffer PB.

[0170] Reference Figure 17 , Figure 17 The word line establishment operation (WLS) and main sensing operation (MS) shown can be included in the programming verification operation (PV) described above. For example, the word line establishment operation (WLS) and main sensing operation (MS) can be included in each of the first programming verification operations (VFY1) to the seventh programming verification operations (VFY7).

[0171] Word line creation operation WLS and above reference Figures 11 to 12E The description is the same. In some example embodiments, the word line charging current Iwdc can be detected during the period of performing the word line establishment operation WLS, and the current detector 2021 can activate or deactivate at least one current detection signal CDS based on the detected value of the word line charging current Iwdc and at least one reference value.

[0172] The forced sensing operation FS may include a first pre-charge operation PRE1, a first development operation DEV1, and a first sensing operation SEN1. The main sensing operation MS may include a second pre-charge operation PRE2, a second development operation DEV2, and a second sensing operation SEN2.

[0173] The bit line shutdown control signal BLSHF and the bit line clamp control signal BLCLAMP can be activated when the word line setup operation WLS completes. The bit line shutdown control signal BLSHF and the bit line clamp control signal BLCLAMP can be deactivated when the main sensing operation MS completes (e.g., when the second sensing operation SEN2 completes). In some example embodiments, as described above, the activation level of the bit line shutdown control signal BLSHF and / or the activation level of the bit line clamp control signal BLCLAMP can be adjusted according to the word line charging current Iwdc.

[0174] The bit line setup control signal BLSETUP can be activated during the time period of each of the first precharge operation PRE1 and the second precharge operation PRE2.

[0175] The bit line connection control signal CLBLK can be activated during the time period of each of the first development operation DEV1 and the second development operation DEV2. In some example embodiments, as described above, the activation period of the bit line connection control signal CLBLK (e.g., when the activated bit line connection control signal CLBLK is deactivated) can be adjusted according to the word line charging current Iwdc. For example, the first activation period of the bit line connection control signal CLBLK can be adjusted during the time period of the first development operation DEV1. Furthermore, the second activation period of the bit line connection control signal CLBLK can be adjusted during the time period of the second development operation DEV2.

[0176] During the execution of each of the first sensing operation SEN1 and the second sensing operation SEN2, the sensing monitoring control signal MON_S, the forced monitoring control signal MON_F, the high-order monitoring control signal MON_M, the low-order monitoring control signal MON_L, and / or the cache monitoring control signal MON_C may be activated. When the execution period of the first development operation DEV1 changes, the start time of the first sensing operation SEN1 may also change. Furthermore, when the execution period of the second development operation DEV2 changes, the start time of the second sensing operation SEN2 may also change.

[0177] In some example embodiments, the activation level of the bit line off control signal BLSHF, the activation level of the bit line clamp control signal BLCLAMP, and / or the activation period of the bit line connection control signal CLBLK can be determined based on a table, and the table can be configured as shown in [Table 4] below.

[0178] [Table 4]

[0179] In [Table 4], "First SO Discharge Time" refers to the first activation period of the bit line connection control signal CLBLK in the first development operation DEV1. "Second SO Discharge Time" refers to the second activation period of the bit line connection control signal CLBLK in the second development operation DEV2. In [Table 4], "Bit Line Precharge Level" can be used to determine the activation level of the bit line shutdown control signal BLSHF and / or the activation level of the bit line clamping control signal BLCLAMP. "t_vfy1" to "V_vfy11" used to compensate for the cell current Icc are not uniformly determined and can be optimized in various ways according to some example embodiments.

[0180] Figure 18 This is a flowchart describing the operation of detecting word line charging current Iwdc in a programming loop according to some example embodiments.

[0181] Reference Figure 18 In operation S100, the control logic circuit 2020 can confirm whether the current number of programming cycles is 1. When the current number of programming cycles is 1 (S100, Yes), in operation S110, the control logic circuit 2020 can detect the current during the word line establishment period (e.g., the detection time Td of the word line establishment operation WLS). After the start of the word line establishment operation WLS of the first programming cycle PL1, the operation of detecting the word line charging current Iwdc can be performed within a specific detection time Td, and the detected value of the word line charging current Iwdc can be stored in the control logic circuit 2020. When the current number of programming cycles is 2 or more (S100, No), in operation S120, the control logic circuit 2020 can skip the current detection during the word line establishment period (e.g., the detection time Td of the word line establishment operation WLS). Because the adjustment value AJV of the word line charging current Iwdc detected in the first programming cycle PL1 is stored in the control logic circuit 2020, the word line charging current Iwdc does not need to be detected in the programming cycles after the first programming cycle PL1.

[0182] In some example embodiments, the control logic circuitry 2020 may be in the initial programming loop (e.g., Figure 15 The word line charging current Iwdc is detected in the first programming loop (PL1). Furthermore, the control logic circuit 2020 can store control quantities (e.g., including at least one activation level and / or activation period) for adjusting at least one of the bit line voltage control signal set (e.g., BLSHF / BLCLAMP) and bit line connection control signal CLBLK. Figure 9 The adjustment value AJV). Furthermore, the control logic circuit 2020 can skip the operation of detecting the word line charging current Iwdc in each programming cycle after the initial programming cycle, and according to the stored control value (e.g., stored in...). Figure 9The adjustment value AJV in the buffer 2023 adjusts at least one of the bit line voltage control signal set and the bit line connection control signal CLBLK.

[0183] According to the above embodiment, the processing of detecting the word line charging current Iwdc is skipped, thereby reducing the redundant computational throughput, which in turn reduces power consumption and / or improves data reliability.

[0184] Figure 19 This is a flowchart describing the operation of detecting the word line charging current Iwdc according to some example embodiments.

[0185] Reference Figure 19 In operation S200, the control logic circuit 2020 can determine whether the sub-block (hereinafter referred to as the "current sub-block") that is the object of the currently to be executed operation (e.g., a read operation or a programming operation) is the same as the sub-block (hereinafter referred to as the "previous sub-block") that was the object of a previous operation (e.g., a read operation or a programming operation). If the current sub-block is different from the previous sub-block (S200, No), in operation S210, the control logic circuit 2020 can detect the current during the word line establishment period of the currently to be executed operation. If the current sub-block is the same as the previous sub-block (S200, Yes), an adjustment value AJV for the word line charging current Iwdc detected in the previously executed operation is stored in the control logic circuit 2020. Therefore, in operation S220, the control logic circuit 2020 can skip the operation of detecting the word line charging current Iwdc during the currently to be executed operation.

[0186] In some example embodiments, the control logic circuit 2020 may perform a first read operation based on a first address and a first read command. The first address may correspond to a specific target word line, and the specific target word line may be included in any sub-block. For example, the first address may correspond to a first target word line included in a first sub-block SB1. However, the example embodiments are not limited to the above examples. During the first read operation, the control logic circuit 2020 may store a first adjustment value. The control logic circuit 2020 may receive a second read command and a second address after the first read operation is completed. Based on whether the second target word line corresponding to the second address is included in the first sub-block SB1, the control logic circuit 2020 may skip the operation of detecting the word line charging current Iwdc in the second read operation according to the second read command, and adjust at least one control signal (e.g., BLSHF, BLCLAMP, and / or CLBLK) according to the first adjustment value.

[0187] In some example embodiments, the control logic circuit 2020 may perform a first programming operation based on a first address and a first write command. Assume that an example of the first address corresponds to the first sub-block SB1 as described above. The first programming operation may include at least one programming loop (e.g., Figure 15 (Multiple programming cycles PL1 to PL21). During the first programming operation, the control logic circuit 2020 may store a first adjustment value. After the first programming operation is completed, the control logic circuit 2020 may receive a second write command and a second address. Based on whether the second target word line corresponding to the second address is included in the first sub-block SB1, the control logic circuit 2020 may skip the operation of detecting the word line charging current Iwdc in the second programming operation according to the second write command, and adjust at least one control signal according to the first adjustment value.

[0188] According to the above embodiment, the processing of detecting the word line charging current Iwdc is skipped, thereby reducing the redundant computational throughput, which in turn reduces power consumption and / or improves data reliability.

[0189] Figure 20 This is a flowchart illustrating a method of operating a non-volatile memory device according to some example embodiments.

[0190] Reference Figure 20 Operation S300 involves detecting the word line charging current, which varies according to the state of multiple memory cells, within a detection time that is equal to, substantially equal to, or less than the word line establishment period. The word line establishment period is the period during which the word line establishment operation is performed, and can be the period during which the voltage levels of multiple word lines increase to the voltage levels of multiple word lines. An example implementation of operation S300 is shown above. Figures 12A to 12E As stated above.

[0191] Operation S310 performs an operation based on a detected value of the word line charging current and at least one reference value (e.g., a comparison between the detected value of the word line charging current and at least one reference value) to determine an adjustment value for adjusting at least one of a set of bit line voltage control signals and a bit line connection control signal applied to multiple bit lines. An example implementation of operation S310 is shown above. Figures 13A to 14C As stated above.

[0192] Operation S320 is performed to activate the bit line voltage control signal set and the bit line setup signal. Operation S320 may correspond to some example embodiments when the precharge operation PRE begins.

[0193] Operation S330 involves activating the bit line connection control signal after the bit line establishment signal is deactivated. Operation S330 may correspond to some example embodiments when the development operation DEV begins.

[0194] Operation S340 activates at least one monitoring signal after the bit line connection control signal is deactivated. Operation S340 may correspond to some example embodiments when the sensing operation SEN begins.

[0195] In some example embodiments, the set of bit line voltage control signals may include a bit line turn-off control signal and a bit line clamping control signal. In this regard, the adjustment value may be a value used to change the activation level of at least one of the bit line turn-off control signal and the bit line clamping control signal. The adjustment values ​​according to some example embodiments may be the same as those in [Table 1] above.

[0196] In some example embodiments, the adjustment value may be a value used to change the activation period of the bit line connection control signal. The adjustment values ​​according to some example embodiments may be the same as those in [Table 2] above.

[0197] In some example embodiments, at least one reference value may include a plurality of reference values ​​with different sizes. Operation S310 may include determining a maximum first adjustment value in response to a first detected value, which is a word line charging current, being less than the minimum reference value among the plurality of reference values; determining a second adjustment value, which is less than the first adjustment value and decreases as the second detected value increases, within a range from the maximum to the minimum reference value among the plurality of reference values, in response to a third detected value, which is greater than the maximum reference value, in response to a third detected value, which is greater than the maximum reference value, in response to an example embodiment of operation S310 being referenced above. Figure 9 and Figures 12A to 14C The descriptions are the same.

[0198] In some example embodiments, the word line charging current may be generated based on at least one of an external power supply voltage provided to the non-volatile memory device, an internal power supply voltage included in a voltage generator within the non-volatile memory device, and a plurality of word line voltages. The word line charging current according to some example embodiments is consistent with the above reference. Figures 8A to 8D The descriptions are the same.

[0199] Figure 21 This is a cross-sectional view showing a non-volatile memory device 500 according to some example embodiments.

[0200] Reference Figure 21The non-volatile memory device 500 may have a chip-to-chip (C2C) structure. The non-volatile memory device 500 may include at least one upper chip, which includes cell regions. For example, the non-volatile memory device 500 may be implemented to include two upper chips. However, the number of upper chips is not limited to this. When the non-volatile memory device 500 is implemented to include two upper chips, the non-volatile memory device 500 can be manufactured by separately manufacturing a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PER1, and then connecting the first upper chip, the second upper chip, and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. The first upper chip may be flipped and connected to the lower chip by a bonding method, and the second upper chip may also be flipped and connected to the first upper chip by a bonding method. In the following text, the upper and lower portions of each of the first and second upper chips are defined relative to the time before the first and second upper chips are flipped. In other words, in Figure 21 In this context, the upper portion of the lower chip may refer to the upper portion defined relative to the +Z axis direction, and the upper portion of each of the first and second upper chips may refer to the upper portion defined relative to the -Z axis direction. However, in some example embodiments, one of the first and second upper chips may be flipped and connected to the corresponding chip by a bonding method.

[0201] Each of the peripheral circuit region PERI and the first cell region CELL1 and the second cell region CELL2 of the non-volatile memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0202] The Peripheral Circuit Region (PERI) may include a first substrate 210, an interlayer insulating layer 215, and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. The interlayer insulating layer 215 may include one or more insulating layers on the plurality of circuit elements 220a, 220b, and 220c. A plurality of metal layers (e.g., first metal layers 230a, 230b, and 230c and second metal layers 240a, 240b, and 240c) connected to the plurality of circuit elements 220a, 220b, and 220c may be disposed within the interlayer insulating layer 215. In some example embodiments, the first metal layers 230a, 230b, and 230c may include tungsten, which has a relatively high resistivity, and the second metal layers 240a, 240b, and 240c may include copper, which has a relatively low resistivity. First metal layers 230a, 230b, and 230c and second metal layers 240a, 240b, and 240c are shown and described herein, but the exemplary embodiments are not limited thereto, and one or more additional metal layers may be formed on the second metal layers 240a, 240b, and 240c.

[0203] Interlayer insulating layer 215 may be disposed on first substrate 210 to cover multiple circuit elements 220a, 220b and 220c, first metal layers 230a, 230b and 230c and second metal layers 240a, 240b and 240c, and may include insulating material (such as silicon oxide, silicon nitride, etc.). However, the example embodiment is not limited thereto.

[0204] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and multiple word lines 430 (431 to 438) may be stacked on the third substrate 410 in a third direction (e.g., the Z-axis direction) perpendicular to the top surface of the third substrate 410. Each of the second substrate 310 and the third substrate 410 may include various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. However, the exemplary embodiments are not limited thereto. One or more channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0205] In some example embodiments, such as Figure 21As shown in A1 (an alternative embodiment of region A), a channel structure CH may be disposed in a bit line bonding region BLBA. The channel structure CH may include a lower channel LCH and an upper channel UCH, which are connected to each other. For example, the channel structure CH may be formed by a process relating to the lower channel LCH and a process relating to the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filler insulating layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filler insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal layer 350c and the second metal layer 360c. As the length of the channel increases, it may be difficult to form a channel with a uniform width due to the manufacturing process. According to some example embodiments, a non-volatile memory device 500 may include channels with improved width uniformity due to the sequentially formed lower channel LCH and upper channel UCH.

[0206] The channel structure CH includes, for example Figure 21 In the case of the lower channel LCH and upper channel UCH shown in A2 (as an alternative embodiment of region A), the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Optionally, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the general word lines, thereby reducing the impact of uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0207] At the same time, Figure 21 In A2, the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, the example embodiment is not limited to this. In another example, the number of lower word lines penetrated by the lower channel LCH may be equal to, substantially equal to, or greater than the number of upper word lines penetrated by the upper channel UCH. Furthermore, the structure and connection relationship of the channel structure CH disposed in the first cell region CELL1 described above can also be applied to the channel structure CH disposed in the second cell region CELL2.

[0208] In the bit line bonding region BLBA, a first through electrode THV1 may be disposed in the first cell region CELL1, and a second through electrode THV2 may be disposed in the second cell region CELL2. The first through electrode THV1 may penetrate the common source line 320 and multiple word lines 330. However, the first through electrode THV1 may further penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Optionally, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0209] In some example embodiments, the first through-electrode THV1 and the second through-electrode THV2 can be electrically connected to each other via a first through-metal pattern 372d and a second through-metal pattern 472d. The first through-metal pattern 372d can be formed at the bottom of a first upper chip including a first cell region CELL1, and the second through-metal pattern 472d can be formed at the top of a second upper chip including a second cell region CELL2. The first through-electrode THV1 can be electrically connected to a first metal layer 350c and a second metal layer 360c. A lower via 371d can be formed between the first through-electrode THV1 and the first through-metal pattern 372d, and an upper via 471d can be formed between the second through-electrode THV2 and the second through-metal pattern 472d. For example, the second through-electrode THV2 can be electrically connected to metal layers 450c and 460c. The first through-metal pattern 372d and the second through-metal pattern 472d can be connected to each other via a bonding method.

[0210] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 392 may be formed in the uppermost metal layer of the first cell region CELL1. In the bit line bonding area BLBA, a bit line 360c may be electrically connected to a page buffer included in the peripheral circuit region PERI. For example, a portion of the circuit element 220c in the peripheral circuit region PERI may provide a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c providing the page buffer via the upper bonding metal pattern 370c of the first cell region CELL1 and the upper bonding metal pattern 270c of the peripheral circuit region PERI.

[0211] In the word line bonding area (WLBA), the word line 330 of the first cell region CELL1 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (341 to 347). A first metal layer 350b and a second metal layer 360b may be sequentially connected to the plurality of cell contact plugs 340 connected to the word line 330. In the word line bonding area (WLBA), the plurality of cell contact plugs 340 may be connected to the peripheral circuit region PERI via the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI.

[0212] Multiple cell contact plugs 340 may be electrically connected to a line decoder included in the peripheral circuitry region (PERI). For example, a portion of circuitry element 220b in the PERI may provide a line decoder, and the multiple cell contact plugs 340 may be electrically connected to the circuitry element 220b providing the line decoder via the upper bonding metal 370b of the first cell region (CELL1) and the upper bonding metal 270b of the PERI. In some example embodiments, the operating voltage of the circuitry element 220b providing the line decoder may differ from the operating voltage of the circuitry element 220c providing the page buffer.

[0213] In the word line bonding area WLBA, the word line 430 of the second cell region CELL2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit region PERI via the upper metal pattern of the second cell region CELL2, the lower metal pattern and the upper metal pattern of the first cell region CELL1, and the cell contact plug 348.

[0214] In the word line bonding area WLBA, upper bonding metal 370b may be formed in the first cell area CELL1, and upper bonding metal 270b may be formed in the peripheral circuit area PERI. The upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal 370b and upper bonding metal 270b may comprise aluminum, copper, or tungsten.

[0215] In the external pad bonding area PA, a lower metal pattern 371e may be formed in the lower part of the first cell region CELL1, and an upper metal pattern 472a may be formed in the upper part of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 372a may be formed in the upper part of the first cell region CELL1, and the upper metal pattern 272a may be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0216] Common source electrode contact plugs 380 and 480 may be disposed in the external pad bonding region PA. Common source electrode contact plugs 380 and 480 may comprise metal, metal compound, or conductive material (such as, doped polysilicon). Common source electrode contact plug 380 of the first cell region CELL1 may be electrically connected to common source electrode 320, and common source electrode contact plug 480 of the second cell region CELL2 may be electrically connected to common source electrode 420. A first metal layer 350a and a second metal layer 360a may be sequentially stacked on the common source electrode contact plug 380 of the first cell region CELL1, and a first metal layer 450a and a second metal layer 460a may be sequentially stacked on the common source electrode contact plug 480 of the second cell region CELL2.

[0217] The first input / output pads to the third input / output pads 205, 405, and 406 can be disposed in the external pad mating area PA. The first input / output pad 205 can be as described in reference to Figure 21 As described, it is formed on the lower insulating layer 201. The first input / output pad 205 can be connected to at least one of the plurality of circuit elements 220a via the first input / output contact plug 203. The upper insulating layer 401 covering the top surface of the third substrate 410 can be formed on the third substrate 410. The second input / output pad 405 and / or the third input / output pad 406 can be disposed on the upper insulating layer 401. The second input / output pad 405 can be connected to at least one of the plurality of circuit elements 220a via the second input / output contact plugs 403 and 303, and the third input / output pad 406 can be connected to at least one of the plurality of circuit elements 220a via the third input / output contact plugs 404 and 304.

[0218] In some example embodiments, the third base 410 may not be located in the area where the input / output contact plugs are disposed. For example, as Figure 21As shown in Figure B, the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may be connected to the third input / output pad 406 via the interlayer insulation layer 415 of the second cell region CELL2. In this case, the third input / output contact plug 404 may be formed by various processes.

[0219] For example, such as Figure 21 As shown in B1 (as an optional embodiment of region B), the third input / output contact plug 404 may extend upward in a third direction, and the diameter of the third input / output contact plug 404 may increase toward the upper insulating layer 401. In other words, Figure 21 The diameter of the channel structure CH described in A1 may decrease toward the upper insulating layer 401, while the diameter of the third input / output contact plug 404 may increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are connected to each other by a bonding method.

[0220] In addition, such as Figure 21 As shown in B2 (an optional embodiment of region B), the third input / output contact plug 404 may extend upward in a third direction, and the diameter of the third input / output contact plug 404 may decrease towards the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may decrease towards the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are connected to each other by a bonding method.

[0221] In another example embodiment, the input / output contact plug may be stacked with the third substrate 410. For example, as Figure 21 As shown in Figure C, the second input / output contact plug 403 may be formed in a third direction (e.g., the Z-axis direction) through the interlayer insulation layer 415 of the second cell region CELL2, and may be electrically connected to the second input / output pad 405 via the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0222] For example, such as Figure 21As shown in C1 (as an alternative embodiment of region C), an opening 408 may be formed through the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in C1, the diameter of the second input / output contact plug 403 may increase toward the second input / output pad 405. However, the diameter of the second input / output contact plug 403 may decrease toward the second input / output pad 405.

[0223] For example, such as Figure 21 As shown in C2 (an alternative embodiment of region C), an opening 408 may be formed through the third substrate 410, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 can be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as Figure 21 As shown in C2, the diameter of contact 407 may increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are connected to each other by an engagement method, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are connected to each other by an engagement method.

[0224] In addition, for example, such as Figure 21 As shown in C3 (as an optional embodiment of region C), with Figure 21 Compared to C2, a stop member 409 may also be formed on the bottom surface of the opening 408 of the third substrate 410. The stop member 409 may be a metal layer formed in the same layer as the common source line 420. However, the stop member 409 may be a metal layer formed in the same layer as at least one word line in the word line 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 via the contact member 407 and the stop member 409. However, the example embodiment is not limited thereto.

[0225] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 in the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 in the first cell region CELL1 may decrease or increase toward the lower metal pattern 371e.

[0226] Meanwhile, in some example embodiments, the seam 411 may be formed in the third substrate 410. For example, the seam 411 may be formed at a specific location in the outer pad bonding area PA. For example, as Figure 21 As shown in D, when viewed in a plan view, slot 411 may be located between the second input / output pad 405 and the cell contact plug 440. However, slot 411 may be configured such that, when viewed in a plan view, the second input / output pad 405 may be located between slot 411 and the cell contact plug 440.

[0227] For example, such as Figure 21 As shown in D1 (an alternative embodiment of region D), the slit 411 may be formed to penetrate the third substrate 410. For example, the slit 411 may be used to reduce and / or prevent minor cracking of the third substrate 410 when the opening 408 is formed. However, the slit 411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 410.

[0228] In addition, for example, such as Figure 21 As shown in D2 (an alternative embodiment of region D), a conductive material 412 may be formed in the slot 411. For example, the conductive material 412 may be used to release leakage current that occurs during the driving of circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground wire.

[0229] In addition, for example, such as Figure 21 As shown in D3 (an optional embodiment of region D), insulating material 413 may be formed in the slot 411. For example, insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the outer pad bonding region PA from the word line bonding region WLBA. The insulating material 413 formed in the slot 411 thereby limits and / or prevents the voltage supplied through the second input / output pad 405 from affecting the metal layer disposed on the third substrate 410 in the word line bonding region WLBA.

[0230] Meanwhile, in some example embodiments, the first input / output pads to the third input / output pads 205, 405, and 406 may be selectively formed. For example, the non-volatile memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0231] Meanwhile, in some example embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 can be used as a sacrificial substrate and can be completely or partially removed before or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 310 of the first cell region CELL1 can be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then an insulating layer or a conductive layer for connection can be formed covering the top surface of the common source electrode 320. Similarly, the third substrate 410 of the second cell region CELL2 can be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 401 or a conductive layer for connection can be formed covering the top surface of the common source electrode 420.

[0232] One or more of the elements disclosed above may include or be implemented in processing circuitry (such as hardware including logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0233] While some exemplary embodiments of the inventive concept have been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A nonvolatile memory device comprising: an array of memory cells including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a page buffer unit including a page buffer connected to the plurality of memory cells through the plurality of bit lines; and control logic circuitry configured to output at least one control signal to the page buffer unit to perform a read operation based on a read command and an address, the read operation including a word line setup operation, a precharge operation, a development operation, and a sense operation, wherein the control logic circuitry is configured to: detect a word line charging current that varies based on a state of the plurality of memory cells during a preset detection time in the word line setup operation, and adjust a set of bit line voltage control signals after the word line setup operation and / or a bit line connection control signal during the development operation based on a detected value of the word line charging current and at least one reference value.

2. The nonvolatile memory device of claim 1, wherein: the set of bit line voltage control signals includes a bit line close control signal and a bit line clamp control signal, and the control logic circuitry is configured to adjust an activation level at which at least one of the bit line close control signal and the bit line clamp control signal is activated.

3. The nonvolatile memory device of claim 2, wherein: the control logic circuitry is configured to: increase the activation level based on the detected value being less than a first reference value, and decrease the activation level based on the detected value being greater than or equal to the first reference value. the control logic circuitry is configured to adjust an activation period in which the bit line connection control signal is activated.

4. The nonvolatile memory device of claim 1, wherein, 5. The nonvolatile memory device of claim 4, wherein: the control logic circuitry is configured to: increase the activation period based on the detected value being less than a first reference value, and decrease the activation period based on the detected value being greater than or equal to the first reference value.

6. The nonvolatile memory device of claim 1, wherein: the at least one reference value includes a plurality of reference values, and the control logic circuitry is configured to determine an adjustment value for adjusting the at least one control signal based on a comparison result between each of the plurality of reference values and the detected value.

7. The nonvolatile memory device of claim 1, further comprising: a voltage generator configured to: generate an internal supply voltage based on an external supply voltage, generate a read voltage based on the internal supply voltage, provide the read voltage to a selected word line among the plurality of word lines, and provide a read pass voltage to unselected word lines among the plurality of word lines, wherein the control logic circuitry is configured to: provide a voltage control signal based on the read command and the address, the voltage control signal instructing the voltage generator to generate the read voltage and the read pass voltage, and detect the word line charging current based on at least one of the external supply voltage, the internal supply voltage, the read voltage, and the read pass voltage.

8. The nonvolatile memory device of claim 1, wherein: the plurality of memory cells are included in a plurality of sub-blocks in an erase operation unit, the control logic circuitry is configured to: detect the word line charging current based on a state of the plurality of sub-blocks during the preset detection time in the word line setup operation, and adjust the set of bit line voltage control signals after the word line setup operation and / or the bit line connection control signal during the development operation based on a detected value of the word line charging current and at least one reference value. Each of the plurality of sub-blocks includes a portion of the plurality of memory cells connected to a portion of the plurality of word lines, and The control logic circuit is configured to perform a first read operation based on a first read command and a first address corresponding to a first target word line included in a first sub-block. 9.The non-volatile memory device of claim 8, wherein, The control logic circuit is configured to: based on the first read operation being performed, store a first adjustment value for adjusting the at least one control signal, based on the first read operation being completed, receive a second read command and a second address, and based on a second target word line corresponding to the second address being included in the first sub-block, skip an operation of detecting a word line charging current in a second read operation based on the second read command and adjust the at least one control signal according to the first adjustment value. 10.A non-volatile memory device, comprising: an array of memory cells including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a page buffer unit including a page buffer connected to the plurality of memory cells through the plurality of bit lines; and a control logic circuit configured to output at least one control signal to the page buffer unit to perform a program verify operation in each of a plurality of program loops based on a write command and an address, wherein the program verify operation includes a word line setup operation, at least one pre-charge operation, at least one development operation, and at least one sensing operation, and the control logic circuit is configured to: detect a word line charging current varying based on a state of the plurality of memory cells during a preset detection time in the word line setup operation, and based on a detected value of the word line charging current and at least one reference value, perform at least one of: adjusting a set of bit line voltage control signals after the word line setup operation, and adjusting a bit line connection control signal during the at least one development operation. 11.The non-volatile memory device of claim 10, wherein, the set of bit line voltage control signals includes a bit line close control signal and a bit line clamp control signal, and the control logic circuit is configured to adjust an activation level at which at least one of the bit line close control signal and the bit line clamp control signal is activated. 12.The non-volatile memory device of claim 10, wherein, the at least one development operation includes: a first development operation performed after the word line setup operation, and a second development operation performed after the first development operation, and the control logic circuit is configured to: adjust a first activation period during the first development operation in which the bit line connection control signal is activated, and adjust a second activation period during the second development operation in which the bit line connection control signal is activated. 13.The non-volatile memory device of claim 10, wherein, the at least one reference value includes a plurality of reference values, and the control logic circuit is configured to determine an adjustment value for adjusting the at least one control signal based on a comparison result between each of the plurality of reference values and the detected value.

14. The nonvolatile memory device of claim 10, wherein, the control logic circuit is configured to: detect a word line charging current in an initial programming cycle, store an adjustment value for adjusting at least one of a set of bit line voltage control signals and a bit line connection control signal, skip the operation of detecting the word line charging current in each of the plurality of programming cycles after the initial programming cycle, and adjust at least one of the set of bit line voltage control signals and the bit line connection control signal according to the adjustment value.

15. The nonvolatile memory device of claim 10, wherein, the plurality of memory cells are included in a plurality of sub-blocks in an erase operation unit, each of the plurality of sub-blocks includes a portion of the plurality of memory cells connected to a portion of the plurality of word lines, and the control logic circuit is configured to: perform a first programming operation including the plurality of programming cycles based on a first write command and a first address corresponding to a first target word line included in a first sub-block among the plurality of sub-blocks, store a first adjustment value for adjusting the at least one control signal during the first programming operation, after the first programming operation is completed, receive a second write command and a second address, and based on whether a second target word line corresponding to the second address is included in the first sub-block, skip the operation of detecting the word line charging current and adjust the at least one control signal according to the first adjustment value in a second programming operation according to the second write command.

16. An operating method of a nonvolatile memory device, the operating method comprising: detecting a word line charging current related to a plurality of word line voltages based on an increase of a voltage level of a plurality of word lines to voltage levels of the plurality of word line voltages during a detection time equal to or less than a word line setup period; determining an adjustment value for adjusting at least one of a set of bit line voltage control signals and a bit line connection control signal applied to a plurality of bit lines based on a detected value of the word line charging current and at least one reference value; activating the set of bit line voltage control signals and a bit line setup signal; activating the bit line connection control signal after the bit line setup signal is deactivated; and activating at least one monitoring signal after the bit line connection control signal is deactivated.

17. The operating method of claim 16, wherein, the set of bit line voltage control signals includes a bit line close control signal and a bit line clamp control signal, and the adjustment value is a value for changing an activation level at which at least one of the bit line close control signal and the bit line clamp control signal is activated.

18. The operating method of claim 16, wherein, the adjustment value is a value for changing an activation period in which the bit line connection control signal is activated.

19. The operating method of claim 16, wherein, the at least one reference value includes a plurality of reference values having different magnitudes from each other, the step of determining the adjustment value includes: in response to a first detected value that is the detected value being less than a smallest reference value among the plurality of reference values, determining a largest first adjustment value, in response to a second detected value that is the detected value being greater than a largest reference value among the plurality of reference values, determining a smallest second adjustment value, and in response to the first detected value being between the smallest reference value and the largest reference value, determining a third adjustment value between the largest first adjustment value and the smallest second adjustment value. determining a second adjustment value which is smaller than the first adjustment value and decreases as the second detection value increases, in response to a second detection value as the detection value being included in a range from a largest reference value to a smallest reference value among the plurality of reference values; and determining a smallest third adjustment value, in response to a third detection value as the detection value being greater than the largest reference value. 20.The operating method of claim 16, wherein the word line charging current is generated based on at least one of: an external power supply voltage provided to the non-volatile memory device, an internal power supply voltage of a voltage generator included in the non-volatile memory device, and the plurality of word line voltages.

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