Relay zero-crossing delay calibration circuit and electrical device

Abstract

The application provides a relay zero-crossing delay calibration circuit and an electrical device, the relay zero-crossing delay calibration circuit comprising: a sampling circuit, a comparison module, a logic circuit and an output interface for an external control device port; the sampling circuit is connected to the static contact and the moving contact of the relay respectively, and is used for sampling the voltage values of the static contact and the moving contact of the relay, and outputs the static contact voltage value through a first output end of the sampling circuit and outputs the moving contact voltage value through a second output end of the sampling circuit; the comparison module is connected to the first output end and the second output end respectively, and an output end is connected to the logic circuit; the comparison module is used for outputting an effective driving signal to the logic circuit in the case that the static contact voltage value is equal to the moving contact voltage value; and the logic circuit is connected to the output interface, and is used for pulling up or pulling down the potential of the output interface when the effective driving signal is received.

Description

Technical Field

[0001] This invention relates to the field of relay delay calibration technology, and in particular to a relay zero-crossing delay calibration circuit and electrical equipment. Background Technology

[0002] If a high voltage difference exists between the contacts of an AC relay at the moment of activation or deactivation, arcing can occur, leading to contact erosion, welding, and oxidation, severely impacting the relay's electrical life. Theoretically, controlling the relay's operation near the zero-crossing point of the AC voltage can greatly suppress arcing. However, the activation and deactivation times of relays exhibit significant individual and batch variations, as well as characteristics that change over time with aging. This results in the ineffectiveness of zero-crossing control methods with fixed delay values, and some relays may still generate arcing at non-zero-crossing points.

[0003] In the existing technology, there is a lack of a low-cost, high-reliability method that can measure the actual operating moment of a specific relay in real time and accurately, and assist software in determining the relay's operating delay time. Summary of the Invention

[0004] This invention provides a relay zero-crossing delay calibration circuit, comprising: a sampling circuit, a comparison module, a logic circuit, and an output interface for an external control device port;

[0005] The sampling circuit is connected to the stationary contact and the moving contact of the relay respectively. It is used to sample the voltage values ​​of the stationary contact and the moving contact of the relay. The stationary contact voltage value is output through the first output terminal of the sampling circuit, and the moving contact voltage value is output through the second output terminal of the sampling circuit.

[0006] The comparison module is connected to the first output terminal and the second output terminal respectively, and the output terminal is connected to the logic circuit; the comparison module is used to output a valid drive signal to the logic circuit when the static contact voltage value is equal to the moving contact voltage value.

[0007] The logic circuit is connected to the output interface and is used to pull up or pull down the potential of the output interface when the valid drive signal is received.

[0008] Optionally, the comparison module includes:

[0009] The first comparator circuit has a first input terminal connected to the first output terminal of the sampling circuit, a second input terminal connected to the second output terminal of the sampling circuit, and an output terminal connected to the logic circuit.

[0010] The second comparator circuit has its first input terminal connected to the second output terminal of the sampling circuit, its second input terminal connected to the first output terminal of the sampling circuit, and its output terminal connected to the logic circuit.

[0011] Optionally, the first comparator circuit includes: a first operational amplifier, a first resistor, and a second resistor;

[0012] The first end of the first resistor is connected to the first output terminal of the sampling circuit, and the second end is connected to the non-inverting input terminal of the first operational amplifier; the first end of the second resistor is connected to the second output terminal of the sampling circuit, and the second end is connected to the inverting input terminal of the first operational amplifier.

[0013] The second comparator circuit includes: a second operational amplifier, a third resistor, and a fourth resistor;

[0014] The first end of the third resistor is connected to the second output terminal of the sampling circuit, and the second end is connected to the non-inverting input terminal of the second operational amplifier; the first end of the fourth resistor is connected to the first output terminal of the sampling circuit, and the second end is connected to the inverting input terminal of the second operational amplifier.

[0015] The output terminals of the first operational amplifier and the second operational amplifier are electrically connected.

[0016] The logic circuit includes: a pull-up resistor;

[0017] The first end of the pull-up resistor is connected to the pull-up power supply, and the second end is electrically connected to the output terminal of the first operational amplifier and the output interface.

[0018] Optionally, the logic circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0019] The first end of the fifth resistor is connected to the output terminal of the first operational amplifier, and the second end is connected to the second end of the sixth resistor, the second end of the seventh resistor, and the first end of the eighth resistor; the first end of the sixth resistor is connected to the output terminal of the second operational amplifier; the first end of the seventh resistor is connected to a pull-up power supply, and the second end of the eighth resistor is connected to the output interface.

[0020] Optionally, the sampling circuit includes: a ninth resistor and a tenth resistor;

[0021] The first end of the ninth resistor is electrically connected to the stationary contact of the relay, and the second end serves as the first output terminal of the sampling circuit; the first end of the tenth resistor is electrically connected to the moving contact of the relay, and the second end serves as the second output terminal of the sampling circuit.

[0022] Optionally, the relay zero-crossing delay calibration circuit further includes: a driving circuit;

[0023] The drive circuit is connected to the coil control circuit of the relay, and the controlled end of the drive circuit is used to connect to the external control device.

[0024] The drive circuit is used to respond to the control signal of the external control device to turn on / off the coil control circuit of the relay, so as to realize the coil being energized or de-energized.

[0025] The present invention also proposes an electrical device, including a relay and a zero-crossing delay calibration circuit for the relay.

[0026] This invention provides a relay zero-crossing delay calibration circuit, comprising: a sampling circuit, a comparison module, a logic circuit, and an output interface for an external control device port; the sampling circuit is connected to the stationary contact and the moving contact of the relay, respectively, for sampling the voltage values ​​of the stationary contact and the moving contact, outputting the stationary contact voltage value through a first output terminal of the sampling circuit, and outputting the moving contact voltage value through a second output terminal of the sampling circuit; the comparison module is connected to the first output terminal and the second output terminal, and the output terminal is connected to the logic circuit; the comparison module is used to output a valid drive signal to the logic circuit when the stationary contact voltage value is equal to the moving contact voltage value; the logic circuit is connected to the output interface, and is used to pull up or pull down the potential of the output interface when the valid drive signal is received. This invention, through a series of pure hardware circuits of sampling, comparison, and logic control, converts the two physical states of the relay contacts, "connected" and "disconnected," into level transition signals that are easy for digital controllers to recognize in real time and without error. This method directly monitors the final action result (whether the contact voltage is consistent), avoiding errors caused by relying solely on theoretical delay parameters. It allows external control devices to obtain the actual delay data of each individual relay during each action, laying a solid foundation for dynamic adaptive zero-crossing control and fundamentally improving arc suppression and relay lifespan. The entire circuit structure is simple, low-cost, and highly reliable. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of the first embodiment of the relay zero-crossing delay calibration circuit of the present invention;

[0029] Figure 2 This is a schematic diagram of the second embodiment of the relay zero-crossing delay calibration circuit of the present invention;

[0030] Figure 3This is a schematic diagram of the third embodiment of the relay zero-crossing delay calibration circuit of the present invention;

[0031] Figure 4 This is a schematic diagram of the first structure of the fourth embodiment of the relay zero-crossing delay calibration circuit of the present invention;

[0032] Figure 5 This is a schematic diagram of the second structure of the fourth embodiment of the relay zero-crossing delay calibration circuit of the present invention.

[0033] Explanation of icon numbers:

[0034] 10. Sampling circuit; R1 to R10, first resistor to tenth resistor; 20. Comparison module; 30. Logic circuit; U1, first operational amplifier; U2, second operational amplifier.

[0035] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0037] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0038] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0039] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0040] The relay zero-crossing delay calibration circuit proposed in this invention includes a sampling circuit 10, a comparison module 20, a logic circuit 30, and an output interface. Its core lies in directly and in real-time detecting the voltage state between the two contacts of the relay through hardware circuitry. At the instant the contacts actually complete closing (equal voltage) or actually begin to open (voltage difference), a clear level transition signal is generated for external control equipment to capture. By comparing the moment the drive command is issued with the moment the transition signal is captured, the external control equipment can accurately calculate the actual engagement or release time of the relay under the current operating condition, and then dynamically correct the zero-crossing control delay for the next operation, achieving adaptive and precise zero-crossing control. In other words, this invention provides a relay zero-crossing delay calibration circuit, offering external control equipment (such as a microcontroller MCU) a direct and reliable hardware means to detect the actual completion time of the relay contacts, thereby accurately measuring the true engagement and release times of an individual relay.

[0041] In the first embodiment of the present invention, as Figure 1 As shown, the relay zero-crossing delay calibration circuit includes: a sampling circuit 10, a comparison module 20, a logic circuit 30, and an output interface for an external control device port;

[0042] The sampling circuit 10 is connected to the stationary contact and the moving contact of the relay respectively, and is used to sample the voltage values ​​of the stationary contact and the moving contact of the relay. The stationary contact voltage value is output through the first output terminal of the sampling circuit 10, and the moving contact voltage value is output through the second output terminal of the sampling circuit 10.

[0043] The comparison module 20 is connected to the first output terminal and the second output terminal respectively, and the output terminal is connected to the logic circuit 30; the comparison module 20 is used to output a valid drive signal to the logic circuit 30 when the static contact voltage value is equal to the moving contact voltage value.

[0044] The logic circuit 30 is connected to the output interface and is used to pull up or pull down the potential of the output interface when the valid drive signal is received.

[0045] Specifically, the output interface is connected to the port of an external control device, and the output interface is used to transmit the aforementioned level transition signal to the external control device. The external control device monitors the potential change of this interface through its input / output ports. The relay zero-crossing delay calibration circuit proposed in this invention maps the level of the output interface to the contact state of the relay, so that the external control device can know the timing of the relay's closing / opening.

[0046] The sampling circuit 10 is directly connected to the stationary and moving contacts of the relay under test. Its function is to sample the voltage across the two contacts in real time, obtaining the stationary and moving contact voltage values ​​of the relay. The sampling circuit 10 can also convert these values, outputting a first sampling voltage and a second sampling voltage suitable for subsequent low-voltage circuit processing. Typically, this can be achieved using a resistor divider network to proportionally attenuate the high voltage of the AC mains to a safe range.

[0047] The input terminal of the comparison module 20 is connected to the two output terminals of the sampling circuit 10, namely the stationary contact voltage value and the moving contact voltage value (or the converted first sampling voltage and the second sampling voltage). Its core function is to continuously compare the magnitude of these two voltage values. In a preferred embodiment, the comparison module 20 is configured to output a valid drive signal only when the voltage difference between the stationary and moving contacts approaches zero, i.e., when the two contacts are electrically connected (relay closed). When the relay is open and the voltages of the two contacts are inconsistent, the output state of the comparison module 20 ensures that a valid drive signal is not triggered.

[0048] The input terminal of the logic circuit 30 is connected to the output terminal of the comparison module 20, and its output terminal is connected to the output interface. The function of the logic circuit 30 is to actively change the level state of the output interface in response to a valid drive signal from the comparison module 20. Specifically, when no valid drive signal is received, the logic circuit 30 keeps the output interface at a first potential (e.g., low level); once a valid drive signal is received, the logic circuit 30 drives the output interface to jump to a second potential (e.g., high level), thereby forming a clear edge signal. This process can be implemented using a simple circuit that includes pull-up or pull-down resistors and basic logic gates (e.g., AND gates).

[0049] When an external control device commands the relay to engage, it first records the moment the drive signal is issued (T1), and then begins monitoring the output interface of the calibration circuit. Before the relay's mechanical contacts close, the voltages of its moving and stationary contacts are different, and the comparison module 20 outputs no valid drive signal. The logic circuit 30 keeps the output interface at an initial low level. After an inherent mechanical delay (i.e., the actual OperateTime), the relay contacts physically close, and the potentials of the moving and stationary contacts become equal. At this time, the comparison module 20 immediately detects this state change and outputs a valid drive signal. The logic circuit 30 then pulls the level of the output interface high. The external control device captures this rising edge and records the moment the contacts actually close (T2). Calculating the time difference between T2 and T1 yields the precise engagement time of the relay.

[0050] Similarly, when the control relay is disconnected, the external control device records the moment the drive signal is removed (T3). Before the contacts actually open, the output interface remains at a high level. Once the contacts open, the voltage difference between the moving and stationary contacts recovers, the comparison module 20 stops outputting a valid drive signal, and the logic circuit 30 controls the output interface level to drop. The external control device captures the falling edge to obtain the actual disconnection moment (T4), thereby calculating the precise release time.

[0051] This invention utilizes a series of pure hardware circuits involving sampling, comparison, and logic control to convert the physical states of relay contacts—"connected" and "disconnected"—in real-time and without error into level transition signals easily recognizable by digital controllers. This method directly monitors the final action result (whether the contact voltage is consistent), avoiding errors caused by relying solely on theoretical delay parameters. It allows external control devices to obtain the actual delay data of each individual relay during each action, laying a solid foundation for dynamic adaptive zero-crossing control and fundamentally improving arc suppression and relay lifespan. The entire circuit structure is simple, low-cost, and highly reliable.

[0052] In the second embodiment of the present invention, as Figure 2 As shown, the comparison module 20 is specifically configured to include two independent comparator circuits, namely a first comparator circuit and a second comparator circuit. This symmetrical dual-comparator structure design is the key to the ability of this solution to reliably detect the contact state throughout the entire AC voltage cycle.

[0053] The first comparator circuit has a first input terminal and a second input terminal. Its first input terminal is connected to the first sampled voltage (V_s1) output from the sampling circuit 10, representing the voltage of the relay's stationary contact. Its second input terminal is connected to the second sampled voltage (V_s2) output from the sampling circuit 10, representing the voltage of the relay's moving contact. Considering that voltage conversion may occur in the sampling circuit 10, the first sampled voltage value may or may not be equal to the relay's stationary contact voltage value, and the second sampled voltage value may or may not be equal to the relay's moving contact voltage value. It should be noted that the voltage gain from the relay's stationary contact to the first sampled voltage value and the voltage gain from the relay's moving contact to the second sampled voltage value are equal. In this configuration, the core function of the first comparator circuit is to perform a comparison between "V_s1" and "V_s2". The second comparator circuit also has a first input terminal and a second input terminal, but their connection relationship is exactly symmetrical to that of the first comparator circuit. That is, its first input terminal is connected to the second sampled voltage (V_s2) representing the voltage of the moving contact, and its second input terminal is connected to the first sampled voltage (V_s1) representing the voltage of the stationary contact. Therefore, the second comparator circuit performs a comparison between "V_s2 and V_s1". The outputs of both comparator circuits are connected to the subsequent logic circuit 30. They can be implemented using open-collector (or open-drain) output operational amplifiers or dedicated comparator chips.

[0054] Because the AC voltage constantly alternates between positive and negative, the polarity of the voltage across the relay contacts also changes accordingly. A single comparator cannot correctly respond to the "equal voltage" state in all phases. This embodiment uses two comparators with their inputs cross-symmetrically connected to form a full-cycle detection circuit.

[0055] It should be further noted that the function of logic circuit 30 is to convert the specific signal pattern output by the dual comparators throughout the entire AC cycle ((1,0) or (0,1) when open, (1,1) when closed) into a level-change signal for precise timing. Its function is that its output changes to a valid state (e.g., '1') only when both comparator outputs are the first logic value (e.g., '1'). A definite edge signal is generated to mark the exact moment the contacts are connected. This invention does not limit the specific form of logic circuit 30, but defines its function: to generate a level-change signal upon receiving the valid drive signal. This directly covers all circuit forms that can implement this function, including AND gates, wired AND gates, parallel switches, and various gate circuit combinations that mimic AND gates.

[0056] "AND gate" is the most direct and optimized path to achieve the above means and effects. The overall functional input-output relationship of the circuit composed of "NOR gate + inverter" or "NAND gate + inverter" is exactly the same as that of the "AND gate". Replacing the "AND gate" with other gate circuit combinations with exactly the same function does not change the function that this part of the circuit undertakes in the overall technical solution, the connection relationship with other components, and the final technical effect produced. This replacement belongs to the conventional design variation that those skilled in the art can think of without creative labor and should be认定为 falling within the protection scope required by this invention.

[0057] When the relay contact is open, V_s2 is an alternating voltage, and V_s1 is a fixed bias voltage (the voltage value can be zero or a preset value set by the R & D personnel). In the positive half cycle of the alternating current, V_s1 > V_s2, the first comparator outputs a high level, while the second comparator outputs a low level due to the relationship of its input terminals. In the negative half cycle of the alternating current, V_s1 < V_s2, and the situation is reversed, the first comparator outputs a low level, and the second comparator outputs a high level. Therefore, in the open state, the outputs of the two comparators are always one high and one low.

[0058] When the relay contact is closed, V_s1 and V_s2 become exactly the same (both follow the alternating current change). At this time, regardless of the phase of the alternating current, the voltages at the two input terminals of the two comparators are always equal. In an ideal situation, the output of the comparator may be in an uncertain critical state. However, in actual circuit design, with the cooperation of a specific logic circuit 30 (such as an AND gate) and a pull-up resistor, it can be ensured that in this state, the final output of the logic circuit 30 is driven to a definite stable level (such as a high level), thereby clearly indicating the "closed" state.

[0059] Through this ingenious cross-symmetric design in this embodiment, the comparison module 20 of this embodiment can convert the physical quantity of "whether the voltages of the two contacts are equal" into a specific combination mode of the output signals of the two comparators without omission at any alternating current phase, providing a solid foundation for the logic circuit 30 to finally generate a clean and jitter-free state indication signal.

[0060] In the third embodiment of the present invention, as Figure 3 shown, the first comparator circuit includes: a first operational amplifier U1, a first resistor R1, and a second resistor R2;

[0061] The first end of the first resistor R1 is connected to the first output end of the sampling circuit 10, and the second end is connected to the non-inverting input terminal of the first operational amplifier U1; the first end of the second resistor R2 is connected to the second output end of the sampling circuit 10, and the second end is connected to the inverting input terminal of the first operational amplifier U1;

[0062] The second comparator circuit includes: a second operational amplifier U2, a third resistor R3, and a fourth resistor R4;

[0063] The first end of the third resistor R3 is connected to the second output terminal of the sampling circuit 10, and the second end is connected to the non-inverting input terminal of the second operational amplifier U2; the first end of the fourth resistor R4 is connected to the first output terminal of the sampling circuit 10, and the second end is connected to the inverting input terminal of the second operational amplifier U2.

[0064] The output terminals of the first operational amplifier U1 and the second operational amplifier U2 are electrically connected;

[0065] The logic circuit 30 includes: a pull-up resistor;

[0066] The first end of the pull-up resistor is connected to the pull-up power supply, and the second end is electrically connected to the output terminal of the first operational amplifier U1 and the output interface.

[0067] Based on the dual comparator circuit structure, this embodiment further discloses a preferred and efficient implementation of the logic circuit 30.

[0068] It is important to note that the logic circuit 30 is specifically composed of an AND gate and a pull-up resistor. The AND gate is a digital logic device or circuit topology with two inputs and one output. The output of the first comparator circuit is connected to the first input of the AND gate, and the output of the second comparator circuit is connected to the second input of the AND gate. The AND gate performs a Boolean AND operation: its output is high ("1") only when both of its input signals are logic high ("1"); under any other input combination, its output is low ("0"). One end of the pull-up resistor is connected to a stable high-level power supply (e.g., a +3.3V or +5V power supply matched to the microcontroller's logic level), and the other end is directly connected to the output of the AND gate. Simultaneously, this output of the AND gate directly serves as the output interface of the entire calibration circuit, used to connect to the GPIO pin of an external control device (such as an MCU).

[0069] As mentioned earlier, when the relay is open, due to the symmetrical cross-connection of the two comparator inputs, their outputs are always complementary (one high, one low) during the positive and negative half-cycles of the AC current. According to the rules of the AND gate, as long as one input is low, the output is pulled low. Therefore, in the open state, regardless of the AC phase, the output of the AND gate is stably locked at a low level. When the relay is closed, the voltages at the inputs of the two comparators are equal. In practical circuit implementation, by appropriately setting the threshold and hysteresis of the comparators, or by utilizing their own output characteristics, it is possible to configure both comparators to output a high level in this state. At this time, both inputs of the AND gate are high, and according to its logic function, the output will become high.

[0070] The pull-up resistor plays a dual role here. First, it provides a definite high-level drive source for the output node of the AND gate. Second, and more importantly, it works perfectly with the possible open-collector or open-drain output structures of the two comparators. When either comparator outputs a low level (internally connected to ground), it strongly pulls the output interface potential down to a low level. When both comparators output high levels, the pull-up resistor pulls the output interface potential up to a high level. This structure ensures a clear voltage swing and reliable drive capability for the output signal.

[0071] This embodiment perfectly synthesizes the output signals of the dual comparators using a simple AND gate and a pull-up resistor, clearly, stably, and without jittering the two physical states of "contact open" and "contact closed" into "low level" and "high level" in digital logic. The entire logic circuit 30 has an extremely simple structure, very low cost, and the output signal is compatible with standard digital logic levels. The interface with the microcontroller is very simple and direct, requiring only a single GPIO pin to achieve high-precision timing capture, greatly simplifying software implementation.

[0072] Furthermore, it should be noted that, based on the dual comparator circuit structure, this embodiment specifically elaborates on the logic circuit 30 and its implemented "AND" function. It is important to clarify that the logic circuit 30 includes pull-up resistors and AND gates. Its core function is to limit the logic function implemented by this circuit module, namely: the logic circuit 30 drives the output interface to a high level only when both the first and second comparator circuits output valid high-level signals; otherwise, it drives the output interface to a low level. The specific physical structure for implementing this "AND" function can be diverse.

[0073] The following details the specific implementation methods of the two core components.

[0074] Method 1: Implementation based on "Wired-AND" connection;

[0075] This is the simplest and most economical preferred solution. In this solution, the "AND gate" does not refer to a separate digital integrated circuit, but rather a functionally equivalent AND gate formed by connecting a specific output structure of the front-end comparator circuit and a common pull-up resistor in a "wired-AND" manner. The specific circuit configuration is as follows: the operational amplifiers in both the first and second comparator circuits are configured as open-collector or open-drain outputs. The output pins of the first and second comparator circuits are directly electrically connected together, forming a common node. One end of the pull-up resistor is connected to the positive power supply, and the other end is connected to this common node. This common node is the output interface, used to connect to the detection pin of an external control device (MCU).

[0076] Its functional implementation process is as follows:

[0077] Logic '0' output (contact open state): When the relay is open, the voltages at the inputs of the two comparators are unequal. Throughout the entire AC cycle, the output states of the first and second comparator circuits are always complementary: one is actively low, and the other is high impedance. Because an actively low output from either comparator strongly pulls the common node down to near ground, the output interface stably presents a low level. This satisfies the AND logic: an input of '0' results in an output of '0'.

[0078] Logic '1' output (contact closed state): When the relay is closed and the contact voltages are equal, neither the first nor the second comparator circuit has a valid comparison difference, and both output a high-impedance state (logically equivalent to '1'). At this time, the internal output transistors of both comparators are turned off, and there is no pull-down effect on the common node. The node potential is entirely determined by the pull-up resistors, which pull it to a high level. This satisfies the AND logic: if all inputs are '1', the output is '1'.

[0079] The advantages of this approach are: by utilizing the open-collector output characteristics of a standard analog comparator, digital AND logic functions can be implemented using only one resistor, eliminating the need for independent logic gate chips. This approach offers the outstanding advantages of having the fewest circuit components, the lowest cost, and the highest reliability.

[0080] Method 2: Implementation based on discrete switching devices;

[0081] As an equivalent implementation, the "logical AND" function can also be constructed using a discrete array of active switching devices.

[0082] The specific circuit configuration is as follows: The logic circuit 30 includes a first switching transistor (such as an N-MOS transistor), a second switching transistor, and a pull-up resistor. The control terminals (gates) of the first and second switching transistors are respectively connected to the output terminals of the first operational amplifier U1 and the second operational amplifier U2. The current paths (source and drain) of the first switching transistor are connected in parallel between the output interface and the circuit ground (GND). The pull-up resistor is connected between the power supply and the output interface.

[0083] Its functional implementation process is as follows:

[0084] Logic '0' output: When the relay is off, the output levels of the first and second comparators drive at least one of the first and second switching transistors to turn on. The turned-on transistor forms a low-impedance path between the output interface and ground, pulling the output interface potential down to a low level. This achieves "low input, low output".

[0085] Logic '1' output: When the relay is closed, both the first and second comparators output a high level sufficient to turn off the switching transistors, thus simultaneously turning them off. At this time, both paths between the output interface and ground are in a high-impedance state, and their potentials are pulled high through the pull-up resistors. This achieves "all inputs high, output high".

[0086] The advantages of this approach are: it provides design flexibility, allowing the selection of different specifications of switching transistors according to system voltage, drive speed and other requirements, and can be used in conjunction with comparators with non-open-collector outputs.

[0087] Although the two specific implementations described above differ in physical structure, they achieve the same input-output logic relationship, both strictly adhering to the AND logic rule to reliably synthesize the states of the two comparators into a deterministic level signal. They implement the functional characteristics of logic circuit 30, including pull-up resistors and AND gates, in different ways. Those skilled in the art will understand that any other circuit variations capable of achieving the same logical decision function, such as combinations of NAND gates and inverters, are equivalent substitutions under the inventive concept and should fall within the scope of protection.

[0088] In the fourth embodiment, as Figure 4 As shown, the logic circuit 30 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8;

[0089] The first end of the fifth resistor R5 is connected to the output terminal of the first operational amplifier U1, and the second end is connected to the second end of the sixth resistor R6, the second end of the seventh resistor R7, and the first end of the eighth resistor R8; the first end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U2; the first end of the seventh resistor R7 is connected to the pull-up power supply, and the second end of the eighth resistor R8 is connected to the output interface.

[0090] This embodiment uses a resistor network to precisely construct the level offset and logic AND function, which is especially suitable for application scenarios that are extremely sensitive to cost control or require specific level matching.

[0091] The fifth resistor R5 and the sixth resistor R6 act as the combined resistors for signal coupling and logic AND. When either the first operational amplifier U1 or the second operational amplifier U2 outputs a low level, current flows through the corresponding resistor (the fifth resistor R5 or the sixth resistor R6) into the output stage of that operational amplifier, thereby pulling the output interface potential low. Only when both the first operational amplifier U1 and the second operational amplifier U2 output a high level can the output interface potential be pulled high by the seventh resistor R7.

[0092] The eighth resistor, R8, serves as an output current limiting and isolation resistor. On the one hand, it limits the current flowing from the output interface to the output interface, protecting the interface circuit. On the other hand, it isolates the impact of potential capacitive loads on the speed of the internal logic decision node (output interface) to a certain extent, thus improving the stability of the circuit.

[0093] This resistor network implements a truth table that is completely consistent with the standard AND gate. When the relay is open (the outputs of the first operational amplifier U1 and the second operational amplifier U2 are complementary), the potential at the output node is pulled low. When the relay is closed (both the first operational amplifier U1 and the second operational amplifier U2 output high), the potential at the output node is pulled high.

[0094] This solution is implemented entirely with general-purpose resistors, requiring no special logic chips or open-collector output comparators. It also has no special requirements for the output structure of the front-end operational amplifier, thus lowering the threshold for component selection and reducing overall costs.

[0095] In one example, the sampling circuit 10 includes: a ninth resistor R9 and a tenth resistor R10;

[0096] The first end of the ninth resistor R9 is electrically connected to the stationary contact of the relay, and the second end serves as the first output terminal of the sampling circuit 10; the first end of the tenth resistor R10 is electrically connected to the moving contact of the relay, and the second end serves as the second output terminal of the sampling circuit 10.

[0097] It is easy to understand that the first terminal of the ninth resistor R9 is directly electrically connected to the stationary contact of the relay. This stationary contact is typically connected to an AC power supply. The second terminal of the ninth resistor R9 serves as the first output terminal of the sampling circuit 10, outputting a first sampled signal representing the voltage of the stationary contact.

[0098] The first terminal of the tenth resistor R10 is directly electrically connected to the moving contact of the relay. This moving contact is connected to the stationary contact when the relay is closed, and is either floating or connected to a load when the relay is open. The second terminal of the tenth resistor R10 serves as the second output terminal of the sampling circuit 10, outputting a second sampling signal representing the voltage of the moving contact.

[0099] The core function of resistors R9 and R10 is to limit the current flowing into the low-voltage circuit by selecting sufficiently large resistance values ​​(e.g., in the megaohm range), ensuring the electrical safety of the system. Additionally, to enable the comparator circuit to reliably and easily determine "voltage inequality" when the relay is open, a defined reference potential can be provided for the stationary contact. This is achieved by connecting a bias circuit to the second terminal of resistor R9. Typically, this is done by connecting a suitable bias resistor to a stable DC bias voltage source (e.g., 1.65V). Thus, when the relay is open, the potential of the stationary contact is pulled to the bias voltage by this bias circuit, forming a stable DC potential that is distinct from the alternating voltage of the moving contact, allowing the comparator to easily detect the difference.

[0100] Additionally, it should be noted that the first resistor R1, the tenth resistor R10, and the third resistor R3 can be replaced by a single resistor; the second resistor R2, the fourth resistor R4, and the ninth resistor can also be replaced by a single resistor. For example... Figure 5 As shown.

[0101] In the fifth embodiment, the relay zero-crossing delay calibration circuit further includes: a driving circuit;

[0102] The drive circuit is connected to the coil control circuit of the relay, and the controlled end of the drive circuit is used to connect to the external control device.

[0103] The drive circuit is used to respond to the control signal of the external control device to turn on / off the coil control circuit of the relay, so as to realize the coil being energized or de-energized.

[0104] It should be understood that the core function of the calibration circuit protected in the above embodiments is passive detection and signal reporting: that is, when the state of the relay contacts changes for any reason, the circuit can generate a clear level transition signal for capture. The power supply and control source driving the relay can be other devices or controllers independent of the detection system.

[0105] This embodiment adds an optional drive circuit to the calibration circuit, thereby constructing an integrated adaptive closed-loop control system together with the calibration circuit and a shared external control device (such as an MCU). This scheme clarifies a specific preferred application scenario where "control" and "detection" are coordinated by the same controller.

[0106] Specifically, the driving circuit is added to the system, and its connection relationship and function are as follows:

[0107] The controlled terminal of the drive circuit is specifically used to connect to the external control device (i.e., MCU). The output terminal of the drive circuit is connected to the coil control circuit of the relay.

[0108] The function of the drive circuit is to act as the power interface of the MCU, responding to the digital control signals issued by the MCU, and precisely turn on or off the coil control circuit of the relay, thereby realizing the active control of the relay's engagement and disengagement.

[0109] In this integrated system, the MCU acts as the sole brain. It first issues action commands through the drive circuit (recording times t1 / t3), and then immediately listens for contact status feedback signals through the output interface of the calibration circuit (capturing times t2 / t4). This "command-listen" closed loop is synchronously completed by the same controller, ensuring absolute consistency of the time base and providing an ideal architecture for high-precision delay measurement and adaptive adjustment. It is important to reiterate that adding the drive circuit does not alter or weaken the independent function of the aforementioned calibration circuit. As a detection module, the calibration circuit's effectiveness does not depend on the presence of the drive circuit. The contribution of this embodiment lies in the fact that by adding this drive circuit and combining it with the calibration circuit, a new technical solution with more advanced functions (closed-loop self-calibration control) is formed.

[0110] A typical drive circuit can be constructed using an NPN transistor and a base-limiting current-limiting resistor. The MCU's GPIO pin is connected to the base of the NPN transistor via a resistor. The collector of the NPN transistor is connected to one end of the relay coil, and the other end of the coil is connected to the power supply. The emitter of the NPN transistor is grounded. When the GPIO output is high, the NPN transistor is saturated and conducting, energizing the coil; when the GPIO output is low, the NPN transistor is cut off, de-energizing the coil.

[0111] The present invention also proposes an electrical device, including a relay and a zero-crossing delay calibration circuit for the relay.

[0112] In this electrical equipment, the AC relay, acting as a main power switch or control switch, is arranged in the main circuit or critical control loop of the equipment, responsible for connecting or disconnecting the AC power supply and the load (such as a motor, heater, lighting system, etc.). The relay zero-crossing delay calibration circuit, as an intelligent monitoring and optimization auxiliary system for the relay, is integrated and installed on the control circuit board of the equipment.

[0113] By calibrating the individual operating delay of each relay online and in real time and implementing precise zero-crossing control, this device fundamentally curbs the arcing of its internal relay contacts. This allows the electrical life of relays—a component whose mechanical lifespan is typically far shorter than that of electronic parts—to approach or even match the overall lifespan of the equipment, solving a long-standing reliability bottleneck problem in electrical equipment.

[0114] The specific structure of the relay zero-crossing delay calibration circuit is as described in the above embodiments. Since this electrical device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0115] The electrical equipment of the present invention has broad application prospects, and typical examples include, but are not limited to:

[0116] Smart home and building automation: such as smart wall switches, smart sockets, air conditioner / underfloor heating thermostats, and smart distribution boxes.

[0117] Industrial automation and control: such as digital output modules of programmable logic controllers, motor drivers, soft starters, and industrial relay modules.

[0118] Power systems and energy management: such as automatic transfer switches, static transfer switches, capacitor switching switches, and load control switches within smart meters.

[0119] New energy vehicles and charging facilities: such as on-board chargers, contactor control inside DC charging piles, and high-voltage disconnection units in battery management systems.

[0120] Uninterruptible power supplies and photovoltaic inverters: Optimized control of relays or contactors for internal input / output / bypass switching.

[0121] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A relay zero-crossing delay calibration circuit, characterized in that, include: Sampling circuit, comparison module, logic circuit, and output interface for external control device ports; The sampling circuit is connected to the stationary contact and the moving contact of the relay respectively. It is used to sample the voltage values ​​of the stationary contact and the moving contact of the relay. The stationary contact voltage value is output through the first output terminal of the sampling circuit, and the moving contact voltage value is output through the second output terminal of the sampling circuit. The comparison module is connected to the first output terminal and the second output terminal respectively, and the output terminal is connected to the logic circuit. The comparison module is used to output a valid drive signal to the logic circuit when the stationary contact voltage value is equal to the moving contact voltage value. The logic circuit is connected to the output interface and is used to pull up or pull down the potential of the output interface when the valid drive signal is received. The comparison module includes: The first comparator circuit has a first input terminal connected to the first output terminal of the sampling circuit, a second input terminal connected to the second output terminal of the sampling circuit, and an output terminal connected to the logic circuit. The second comparator circuit has a first input terminal connected to the second output terminal of the sampling circuit, a second input terminal connected to the first output terminal of the sampling circuit, and an output terminal connected to the logic circuit. The first comparator circuit includes: a first operational amplifier, a first resistor, and a second resistor; The first end of the first resistor is connected to the first output terminal of the sampling circuit, and the second end is connected to the non-inverting input terminal of the first operational amplifier; the first end of the second resistor is connected to the second output terminal of the sampling circuit, and the second end is connected to the inverting input terminal of the first operational amplifier. The second comparator circuit includes: a second operational amplifier, a third resistor, and a fourth resistor; The first end of the third resistor is connected to the second output terminal of the sampling circuit, and the second end is connected to the non-inverting input terminal of the second operational amplifier; the first end of the fourth resistor is connected to the first output terminal of the sampling circuit, and the second end is connected to the inverting input terminal of the second operational amplifier. The output terminals of the first operational amplifier and the second operational amplifier are electrically connected. The logic circuit includes: a pull-up resistor; The first end of the pull-up resistor is connected to the pull-up power supply, and the second end is electrically connected to the output terminal of the first operational amplifier and the output interface.

2. The relay zero-crossing delay calibration circuit as described in claim 1, characterized in that, The logic circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The first end of the fifth resistor is connected to the output terminal of the first operational amplifier, and the second end is connected to the second end of the sixth resistor, the second end of the seventh resistor, and the first end of the eighth resistor; the first end of the sixth resistor is connected to the output terminal of the second operational amplifier; the first end of the seventh resistor is connected to a pull-up power supply, and the second end of the eighth resistor is connected to the output interface.

3. The relay zero-crossing delay calibration circuit as described in any one of claims 1 to 2, characterized in that, The sampling circuit includes: a ninth resistor and a tenth resistor; The first end of the ninth resistor is electrically connected to the stationary contact of the relay, and the second end serves as the first output terminal of the sampling circuit; the first end of the tenth resistor is electrically connected to the moving contact of the relay, and the second end serves as the second output terminal of the sampling circuit.

4. The relay zero-crossing delay calibration circuit as described in any one of claims 1 to 2, characterized in that, The relay zero-crossing delay calibration circuit further includes: a driving circuit; The drive circuit is connected to the coil control circuit of the relay, and the controlled end of the drive circuit is used to connect to the external control device. The drive circuit is used to respond to the control signal of the external control device to turn on / off the coil control circuit of the relay, so as to realize the coil being energized or de-energized.

5. An electrical device, characterized in that, Includes a relay and a relay zero-crossing delay calibration circuit as described in any one of claims 1 to 4.

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