Electrostatic discharge protection device

Abstract

The invention provides an electrostatic discharge protection device. The electrostatic discharge protection device comprises a voltage division adjusting circuit which is connected with a signal input end and generates a voltage signal. The trigger circuit is connected to the voltage division adjusting circuit so as to output a trigger signal. The detection circuit generates a detection signal according to the voltage signal. The control circuit generates an output signal according to the trigger signal and the detection signal to control the first switch circuit and the second switch circuit. The first inverter is connected with the first switching circuit, and the second inverter is connected with the second switching circuit. The discharge circuit is controlled by the first inverter and the second inverter. When static electricity is input to the signal input end, the output signal is converted into a high-voltage level, the discharging circuit is conducted to discharge, and at the moment, a trigger signal generated by the trigger circuit is converted into a low-voltage level, so that the control circuit is controlled to prolong the output time of the output signal to be the high-voltage level.

Description

TECHNICAL FIELD

[0001] The present application relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection device capable of avoiding latch-up effect. BACKGROUND

[0002] In electronic products, electrostatic discharge (ESD) can cause electronic components or electronic systems to be damaged by electrical overstress (EOS), which can cause permanent damage to semiconductor components and computer systems, thereby affecting the circuit function of integrated circuits (ICs) and causing the electronic product to malfunction.

[0003] Among them, after the integrated circuit is packaged into a wafer, it is possible to occur the phenomenon of being damaged by static electricity in the occasions of assembly, testing, storage, transportation, etc. Therefore, the integrated circuits on the market begin to have specifications related to electrostatic discharge, including human body model (HBM), mechanical discharge model (MM), charged discharge model (CDM), egun, surge, EOS, etc. to reproduce the damage phenomenon when electrostatic discharge occurs to test the electrostatic discharge capability. Therefore, the electrostatic discharge element or the electrostatic discharge circuit is used as the protection of the integrated circuit, and the protection capability of the integrated circuit for electrostatic discharge is enhanced to improve the yield. SUMMARY

[0004] The present application provides an electrostatic discharge protection device, which includes a signal input terminal, a voltage dividing adjustment circuit, a trigger circuit, a detection circuit, a control circuit, a first switch circuit, a second switch circuit, a first inverter, a second inverter, and a discharge circuit. The signal input terminal is electrically connected to a voltage input terminal, and the voltage input terminal is fed with a first voltage. The voltage dividing adjustment circuit is electrically connected to the signal input terminal to generate a voltage signal at a voltage dividing node. The trigger circuit is electrically connected to a first node of the voltage dividing adjustment circuit to output a trigger signal. The detection circuit is electrically connected to the voltage dividing node of the voltage dividing adjustment circuit to generate a detection signal according to the voltage signal. The control circuit is electrically connected to the trigger circuit and the detection circuit to generate an output signal according to the trigger signal and the detection signal. The first switch circuit is electrically connected to the control circuit to be controlled by the output signal. The second switch circuit is electrically connected to the control circuit to be controlled by the output signal. The first inverter has a first input terminal and a first output terminal, and is electrically connected between the voltage input terminal and a second input terminal, and the first input terminal is electrically connected to the first switch circuit. The second inverter has a second input terminal and a second output terminal, and is electrically connected between the first output terminal and a ground terminal, and the second input terminal is electrically connected to the second switch circuit. The discharge circuit is electrically connected between the voltage input terminal and the ground terminal, and is controlled by the first output terminal and the second output terminal. When an electrostatic input is input to the signal input terminal, the output signal is changed to a high voltage level, and the discharge circuit is turned on through the first switch circuit and the second switch circuit to discharge the signal input terminal, and the trigger signal generated by the trigger circuit through the first node is changed to a low voltage level to control the control circuit to prolong the output time of the output signal at the high voltage level.

[0005] In an embodiment, the discharge circuit further includes a first discharge transistor and a second discharge transistor, the first discharge transistor and the second discharge transistor are connected in series between the voltage input terminal and the ground terminal, the first discharge transistor is controlled by the voltage of the first output terminal, and the second discharge transistor is controlled by the voltage of the second output terminal.

[0006] In an embodiment, in a normal operation mode, the voltage signal is at a low voltage level, the detection signal is at a high voltage level, the output signal is at a low voltage level, the first switch circuit is turned off to make the first input terminal at a high voltage level, the second switch circuit is turned on to make the second input terminal at a high voltage level, the first output terminal is pulled to a low voltage level through the first inverter, the first discharge transistor is turned off, the second output terminal is pulled to a low voltage level through the second inverter, and the second discharge transistor is turned off.

[0007] In one embodiment, when the signal input is in a discharge mode due to receiving an electrostatic input, the voltage signal is at a high voltage level, the detection signal is at a low voltage level, the output signal is at a high voltage level, the first switch circuit is turned on to make the first input at a low voltage level, the second switch circuit is turned off to make the second input at a low voltage level, the first output is pulled to a high voltage level by the first inverter to turn on the first discharge transistor for discharging, and the second output is pulled to a high voltage level by the second inverter to turn on the second discharge transistor for discharging.

[0008] In one embodiment, the trigger circuit, the detection circuit, the control circuit, the first switch circuit, and the second switch circuit are operated according to a second voltage, and the second voltage is less than the first voltage.

[0009] In one embodiment, the first voltage is 3.3 volts, and the second voltage is 1.8 volts.

[0010] In one embodiment, the first switch circuit further includes a first switch transistor and a second switch transistor, the first switch transistor and the second switch transistor are connected in series and electrically connected between the first input and a ground, the first switch transistor is controlled by the second voltage, and the second switch transistor is controlled by the output signal. The second switch circuit further includes a third switch transistor controlled by the output signal.

[0011] In one embodiment, the detection circuit is a detection inverter, when an electrostatic input is applied to the signal input, the voltage of the voltage signal is higher than a threshold voltage of the detection inverter, the detection signal output by the detection inverter is at a low voltage level, and the output signal generated by the control circuit is at a high voltage level.

[0012] In one embodiment, when the first node is converted from a high voltage level to a low voltage level due to discharging of the signal input, the trigger signal can be maintained at a low voltage level by the trigger circuit until the end of the electrostatic input period.

[0013] In summary, to avoid the latch-up effect, the electrostatic discharge protection device is proposed, which uses the delay characteristics of potential transition to prolong the opening (discharging) time of the electrostatic discharge protection device by the circuit design of the trigger circuit, so that the opening and closing time of the electrostatic discharge protection device can be the same as the electrostatic input period, to maintain a long enough discharging time, and no additional effects are generated. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The circuit schematic diagram of the electrostatic discharge protection device according to one embodiment of the present application.

[0015] Figures 2A to 2GCircuit schematic diagram of various embodiments of a control circuit used in an electrostatic discharge protection device according to the present application.

[0016] Figures 3A to 3E Circuit schematic diagram of various embodiments of a control circuit used in an electrostatic discharge protection device according to the present application. DETAILED DESCRIPTION

[0017] The preferred embodiments are described in detail below with reference to the attached drawing figures, wherein the same or similar components are provided with the same reference numerals, and wherein:

[0018] Figure 1 Circuit schematic diagram of an electrostatic discharge protection device according to an embodiment of the present application, please refer to Figure 1 As shown, the electrostatic discharge protection device 10 includes a signal input terminal 12, a voltage dividing adjustment circuit 14, a trigger circuit 16, a detection circuit 18, a control circuit 20, a first switching circuit 22, a second switching circuit 24, a first inverter 26, a second inverter 28, and a discharge circuit 30.

[0019] In the electrostatic discharge protection device 10, the signal input terminal 12 is electrically connected between a voltage feeding terminal and a ground terminal GND, the signal input terminal 12 can be used to input a power signal or a data signal, and the voltage feeding terminal feeds a first voltage VDD1, in an embodiment, the first voltage VDD1 is 3.3 volts, but the present application is not limited thereto. The voltage dividing adjustment circuit 14 is electrically connected to the signal input terminal 12 and has a voltage dividing node N and a first node A, to generate a voltage signal VS at the voltage dividing node N, in the embodiment, the voltage dividing adjustment circuit 14 includes a plurality of connected transistors, but the present application is not limited thereto. The trigger circuit 16 is electrically connected to the first node A of the voltage dividing adjustment circuit 14 and operates according to a second voltage VDD2, and the second voltage VDD2 is less than the first voltage VDD1, in an embodiment, the second voltage VDD2 is 1.8 volts, so that the trigger circuit 16 outputs a trigger signal EA. The detection circuit 18 is electrically connected between the voltage dividing node N of the voltage dividing adjustment circuit 14 and the control circuit 20, and operates according to the second voltage VDD2, to generate a detection signal DS according to the received voltage signal VS, in an embodiment, the detection circuit 18 is a detection inverter. The control circuit 20 is electrically connected to the trigger circuit 16 and the detection circuit 18, and operates according to the second voltage VDD2, to generate an output signal OS according to the trigger signal EA and the detection signal DS, in an embodiment, the control circuit 20 includes a P-type transistor P1 and two N-type transistors N1, N2 connected in series with each other, but the present application is not limited thereto.

[0020] The first switch circuit 22 is electrically connected between the first input terminal I1 of the first inverter 26 and the ground terminal GND, and is electrically connected to the control circuit 20 and controlled by the control circuit 20 to control the operation of the first switch circuit 22 according to the output signal OS. In an embodiment, the first switch circuit 22 further comprises a first switch transistor TS1 and a second switch transistor TS2, which are connected in series and electrically connected between the first input terminal I1 and the ground terminal GND. The first switch transistor TS1 is controlled by the second voltage VDD2, and the second switch transistor TS2 is controlled by the output signal OS. The second switch circuit 24 is electrically connected between the control circuit 20 and the second input terminal I2 of the second inverter 28, and is controlled by the control circuit 20 to control the operation of the second switch circuit 24 according to the output signal OS. In an embodiment, the second switch circuit 24 further comprises a third switch transistor TS3, which is controlled by the output signal OS output by the control circuit 20. In an embodiment, the first switch transistor TS1 and the second switch transistor TS2 are N-type metal-oxide-semiconductor field-effect transistors (NMOS), and the third switch transistor TS3 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS).

[0021] The first inverter 26 has a first input terminal I1 and a first output terminal O1, and is electrically connected between the voltage input terminal and the second input terminal I2. The first input terminal I1 is electrically connected to the first switch circuit 22. The second inverter 28 has a second input terminal I2 and a second output terminal O2, and is electrically connected between the first output terminal O1 and the ground terminal GND. The second input terminal I2 is electrically connected to the second switch circuit 24. The discharge circuit 30 is electrically connected between the voltage input terminal and the ground terminal GND. The discharge circuit 30 comprises a first discharge transistor TD1 and a second discharge transistor TD2, which are connected in series between the voltage input terminal and the ground terminal GND. The first discharge transistor TD1 is controlled by the voltage of the first output terminal O1, and the second discharge transistor TD2 is controlled by the voltage of the second output terminal O2, so as to directly discharge the signal input terminal 12 when the first discharge transistor TD1 and the second discharge transistor TD2 are turned on. In an embodiment, the first discharge transistor TD1 and the second discharge transistor TD2 are both N-type metal-oxide-semiconductor field-effect transistors (NMOS).

[0022] When an electrostatic input is applied to the signal input terminal 12, the output signal OS changes to a high voltage level. Through the first switch circuit 22 and the second switch circuit 24, the discharge circuit 30 is turned on to discharge the signal input terminal 12. At this time, the trigger signal EA generated by the trigger circuit 16 through the first node A changes to a low voltage level to control the control circuit 20 to extend the output time of the output signal OS to a high voltage level.

[0023] The electrostatic discharge protection device 10 in this case has two operating modes, including a normal operation mode and a discharge mode. These two operating modes will be described in detail below.

[0024] like Figure 1 As shown, when there is no actual static electricity generated or no static electricity input caused by excessive electrical stress (EOS), the input voltage at signal input terminal 12 is normal, and the electrostatic discharge protection device 10 operates in normal operating mode. In normal operating mode, the voltage signal VS generated by the voltage divider adjustment circuit 14 at voltage divider node N is at a low voltage level. The detection signal DS generated by the detection circuit 18 is at a high voltage level, causing the output signal OS generated by the control circuit 20 to be at a low voltage level. The first switching circuit 22 is turned off by the output signal OS, and the first input terminal I1 of the first inverter 26 is at a high voltage level according to the first voltage VDD1. Furthermore, the second switching circuit 24 is turned on by the output signal OS, and the second input terminal I2 is charged according to the second voltage VDD2, causing the second input terminal I2 to be at a high voltage level. The first input terminal I1 is at a high voltage level, and the first output terminal O1 is pulled to a low voltage level through the first inverter 26, so that the first discharge transistor TD1 is turned off. The second input terminal I2 is at a high voltage level, and the second output terminal O2 is pulled to a low voltage level through the second inverter 28, so that the second discharge transistor TD2 is turned off.

[0025] When a momentary high voltage static electricity is inputted, the signal input terminal 12 receives the static electricity input, and the static electricity discharge protection device 10 is in a discharge mode. In the discharge mode, the voltage signal VS generated at the voltage dividing node N by the voltage dividing adjustment circuit 14 is at a high voltage level. The voltage signal VS is inverted to a low voltage level by the detection circuit 18, and the detection signal DS generated by the detection circuit 18 is at a low voltage level, and the output signal OS generated by the control circuit 20 is at a high voltage level. The first switch circuit 22 is turned on by the output signal OS, and the voltage of the first input terminal II is pulled down to a low voltage level, and the second input terminal I2 is at a low voltage level by the second switch circuit 24 being turned off by the output signal OS. The first input terminal I2 is at a low voltage level, and the first output terminal Ol is pulled up to a high voltage level by the first inverter 26, so that the first discharge transistor TD1 is turned on to discharge, and the second input terminal I2 is at a low voltage level, and the second output terminal O2 is pulled up to a high voltage level by the second inverter 28, so that the second discharge transistor TD2 is turned on to discharge. The trigger signal EA is generated from the first node A through the trigger circuit 16. When the static electricity input is generated, the voltage at the first node A is raised, and the trigger signal EA is inverted from a high voltage level to a low voltage level, so that the N-type transistor N2 in the control circuit 20 is turned off, so as to delay the output time of the output signal OS being at a high voltage level. When the first node A is inverted from a high voltage level to a low voltage level by the discharge of the signal input terminal 12, the trigger signal EA can be maintained at a low voltage level due to the characteristics of the trigger circuit 16, until the static electricity input period is over.

[0026] In an embodiment, the trigger circuit 16 is a Schmitt trigger, and has various different embodiments. As shown in FIG. 1, the trigger circuit 16 is composed of three P-type metal oxide semiconductor field effect transistors and one N-type metal oxide semiconductor field effect transistor. As shown in FIG. 2, the trigger circuit 16 is composed of three P-type metal oxide semiconductor field effect transistors, one N-type metal oxide semiconductor field effect transistor, and one resistor. As shown in FIG. 3, the trigger circuit 16 is composed of one P-type metal oxide semiconductor field effect transistor and one N-type metal oxide semiconductor field effect transistor. As shown in FIG. 4, the trigger circuit 16 is composed of three P-type metal oxide semiconductor field effect transistors and two N-type metal oxide semiconductor field effect transistors. As shown in FIG. 5, the trigger circuit 16 is composed of three P-type metal oxide semiconductor field effect transistors, two N-type metal oxide semiconductor field effect transistors, and one resistor. Figure 2A Figure 2B Figure 2C Figure 2D Figure 2E Figure 2F ​​​​​As shown, the trigger circuit 16 consists of three P-type metal-oxide-semiconductor field-effect transistors and three N-type metal-oxide-semiconductor field-effect transistors. Figure 2G As shown, the trigger circuit 16 consists of three P-type metal-oxide-semiconductor field-effect transistors, three N-type metal-oxide-semiconductor field-effect transistors, and two resistors.

[0027] In one embodiment, the control circuit 20, in addition to Figure 1 In addition to the circuit configuration shown, there are various other implementation examples. For example... Figure 3A As shown, the control circuit 20 consists of two P-type metal-oxide-semiconductor field-effect transistors and two N-type metal-oxide-semiconductor field-effect transistors. Figure 3B As shown, the control circuit 20 consists of five P-type metal-oxide-semiconductor field-effect transistors and five N-type metal-oxide-semiconductor field-effect transistors. (As shown...) Figure 3C As shown, the control circuit 20 consists of five P-type metal-oxide-semiconductor field-effect transistors and five N-type metal-oxide-semiconductor field-effect transistors. (As shown...) Figure 3D As shown, the control circuit 20 consists of four P-type metal-oxide-semiconductor field-effect transistors and four N-type metal-oxide-semiconductor field-effect transistors. Figure 3E As shown, the control circuit 20 consists of four P-type metal-oxide-semiconductor field-effect transistors and four N-type metal-oxide-semiconductor field-effect transistors.

[0028] In summary, this case proposes an electrostatic discharge protection device that utilizes the delayed characteristics of potential transition through the circuit design of the trigger circuit to extend the opening (discharge) time of the electrostatic discharge protection device, so that the opening and closing time of the electrostatic discharge protection device can be the same as the electrostatic input cycle, thereby maintaining a sufficiently long discharge time without generating any additional effects.

[0029] The embodiments described above are only for illustrating the technical ideas and features of this case. Their purpose is to enable those skilled in the art to understand the content of this case and implement it accordingly. They should not be used to limit the scope of the patent in this case. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in this case should still be covered within the scope of the patent application in this case.

[0030] [Symbol Explanation]

[0031] 10: Electrostatic discharge protection device

[0032] 12: Signal input terminal

[0033] 14: Voltage divider adjustment circuit

[0034] 16: Trigger circuit

[0035] 18: detection circuit

[0036] 20: control circuit

[0037] 22: first switching circuit

[0038] 24: second switching circuit

[0039] 26: first inverter

[0040] 28: second inverter

[0041] 30: discharge circuit

[0042] A: first node

[0043] DS: detection signal

[0044] EA: trigger signal

[0045] GND: ground

[0046] I1: first input

[0047] I2: second input

[0048] N: dividing node

[0049] N1, N2: N-type transistor

[0050] O1: first output

[0051] O2: second output

[0052] OS: output signal

[0053] P1: P-type transistor

[0054] TD1: first discharge transistor

[0055] TD2: second discharge transistor

[0056] TS1: first switching transistor

[0057] TS2: second switching transistor

[0058] TS3: third switching transistor

[0059] VDD1: first voltage

[0060] VDD2: second voltage

[0061] VS: voltage signal

Claims

1. An electrostatic discharge protection device, comprising: a signal input electrically connected to a voltage feed-in for feeding in a first voltage; a voltage dividing adjustment circuit electrically connected to the signal input for generating a voltage signal at a voltage dividing node; a trigger circuit electrically connected to a first node in the voltage dividing adjustment circuit for outputting a trigger signal; a detection circuit electrically connected to the voltage dividing node of the voltage dividing adjustment circuit for generating a detection signal according to the voltage signal; a control circuit electrically connected to the trigger circuit and the detection circuit for generating an output signal according to the trigger signal and the detection signal; a first switch circuit electrically connected to the control circuit for controlling the first switch circuit according to the output signal; a second switch circuit electrically connected to the control circuit for controlling the second switch circuit according to the output signal; a first inverter having a first input and a first output, and being electrically connected between the voltage feed-in and a second input, and the first input being electrically connected to the first switch circuit; a second inverter having the second input and a second output, and being electrically connected between the first output and a ground, and the second input being electrically connected to the second switch circuit; and a discharge circuit electrically connected between the voltage feed-in and the ground, and being controlled by the first output and the second output; wherein, when an electrostatic input is input to the signal input, the output signal is changed to a high voltage level, and through the first switch circuit and the second switch circuit, the discharge circuit is turned on to discharge the signal input, at this time, the first node is able to change to a low voltage level through the trigger signal generated by the trigger circuit, to control the control circuit to prolong the output time of the output signal at the high voltage level. The discharge circuit further comprises a first discharge transistor and a second discharge transistor, the first discharge transistor and the second discharge transistor are connected in series between the voltage feed-in and the ground, the first discharge transistor is controlled by the voltage of the first output, and the second discharge transistor is controlled by the voltage of the second output.

2. The electrostatic discharge protection device of claim 1, wherein, In a normal operation mode, the voltage signal is at the low voltage level, the detection signal is at the high voltage level, the output signal is at the low voltage level, so that the first switch circuit is closed to make the first input at the high voltage level, and the second switch circuit is turned on to make the second input at the high voltage level, thereby pulling the first output to the low voltage level through the first inverter to make the first discharge transistor closed, and pulling the second output to the low voltage level through the second inverter to make the second discharge transistor closed.

3. The electrostatic discharge protection device of claim 2, wherein, ​ 4. The electrostatic discharge protection device of claim 2, wherein, The signal input end is in a discharge mode due to the static input, the voltage signal is at the high voltage level, the detection signal is at the low voltage level, the output signal is at the high voltage level, the first switch circuit is turned on to make the first input end at the low voltage level, the second switch circuit is turned off to make the second input end at the low voltage level, the first output end is pulled to the high voltage level by the first inverter to make the first discharge transistor conductive for discharging, and the second output end is pulled to the high voltage level by the second inverter to make the second discharge transistor conductive for discharging.

5. The electrostatic discharge protection device of claim 1, wherein, The trigger circuit, the detection circuit, the control circuit, the first switch circuit and the second switch circuit operate according to a second voltage, and the second voltage is less than the first voltage.

6. The electrostatic discharge protection device of claim 5, wherein, The first voltage is 3.3 volts, and the second voltage is 1.8 volts.

7. The electrostatic discharge protection device of claim 5, wherein, The first switch circuit further comprises a first switch transistor and a second switch transistor, the first switch transistor and the second switch transistor are connected in series and electrically connected between the first input end and the ground end, the first switch transistor is controlled by the second voltage, and the second switch transistor is controlled by the output signal; and the second switch circuit further comprises a third switch transistor controlled by the output signal.

8. The electrostatic discharge protection device of claim 7, wherein, The first switch transistor and the second switch transistor are N-type metal oxide semiconductor field effect transistors. The third switch transistor is a P-type metal oxide semiconductor field effect transistor.

9. The electrostatic discharge protection device of claim 1, wherein, The detection circuit is a detection inverter, when the static input is input to the signal input end, the voltage of the voltage signal is higher than the threshold voltage in the detection inverter, the detection signal output by the detection inverter is the low voltage level, and the output signal generated by the control circuit is the high voltage level.

10. The electrostatic discharge protection device of claim 1, wherein, When the first node is converted from the high voltage level to the low voltage level due to the discharge of the signal input end, the trigger signal can continue to maintain the low voltage level until the end of the static input period due to the action of the trigger circuit.

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