Gate drive circuit with switched capacitor circuit for generating negative gate-source voltage pulses

Abstract

An apparatus for driving a MOSFET, comprising: a first gate driver for generating a driving signal for the MOSFET; the switched capacitor circuit is connected to the first gate driver and is used for temporarily generating negative voltage to counteract stray voltage appearing on the first gate driver; and the second gate driver comprises a circuit for driving the switched capacitor. The first gate driver and the second gate driver are powered by the same voltage source and controlled by the same control logic. The device can instantly generate negative voltage to counteract stray voltage generated by a switching device, so that the switching performance is improved.

Description

Technical Field

[0001] This invention relates to electronic circuits, particularly gate drive circuits for transistors. Background Technology

[0002] The bridge-leg structure, consisting of two series-connected switching devices, is widely used in power converters as gate drivers for MOSFETs. During normal operation, the two switching devices alternately switch. However, due to unavoidable delay times, turn-on and turn-off times, the switching devices may partially turn on simultaneously, leading to breakdown. To ensure safe operation, a practical method is to simultaneously turn off both switching devices for a short period before turning either switch on; this time is called the dead time t. d .

[0003] Despite the introduction of t d This can prevent the drive signals generated by the gate drive integrated circuit from overlapping, but the switching of the MOSFET will cause a high dv / dt on the MOSFET and affect the gate voltage caused by the inherent parameters of the MOSFET. When the control switch (i.e., one of the two switching devices) in the bridge arm configuration is turned on, a positive stray voltage will appear on the synchronous switch. If this voltage exceeds the threshold voltage of the MOSFET, the MOSFET will be partially turned on, resulting in a large breakdown current. This may increase the power loss of the converter or even cause device failure. Similarly, when the control switch is turned off, a negative stray voltage will appear. If this voltage exceeds the maximum allowable gate-source voltage of the MOSFET, it will also cause device failure. For detailed analysis, please refer to [1] and [2]. This problem is more serious in wide bandgap devices (such as silicon carbide MOSFETs) because of their high switching speed.

[0004] Numerous studies have been conducted to address the stray voltage problem and maximize the performance of switching devices in bridge arms. Many of the proposed solutions can be categorized into two main approaches. The first approach aims to reduce the magnitude of the stray voltage. Since the stray voltage is primarily caused by displacement current through the gate resistor, it can be reduced by passively lowering the impedance of the gate path, for example, by using a small turn-off gate resistor [3]-[4], connecting a capacitor [4]-[5] or a diode [6]-[7] across the gate resistor. Another active approach is to insert a transistor between the gate and source, which is turned on when a stray voltage occurs [4], [5], [8] and [9]. However, these approaches can only reduce rather than eliminate the stray voltage due to the low impedance path and the non-zero impedance of the gate resistor inside the MOSFET. The second approach is to introduce a negative gate-source voltage during turn-off to ensure that the gate-source voltage remains below the threshold voltage when a stray voltage occurs. These methods include using an additional negative voltage source for the gate driver output [6], [7],

[10] and

[11] , using passive circuitry [5],

[12] and

[13] , using active circuitry [6], [8],

[10] and

[14] -

[17] , or using a charge pump circuit

[14] -

[15] . As shown in Figure 1, a simple approach is to add a negative voltage source VGG_L in the off state to bias the gate-source voltage negatively. However, this circuit may require an additional voltage source to generate the negative voltage. Furthermore, a stable negative voltage may shorten the MOSFET's lifetime

[18] -

[19] . In addition, a stable negative gate-source voltage will increase the forward voltage of the body diode and reduce the permissible negative stray voltage.

[0005] Recently, a multi-stage gate driver technique has been developed [6], [8],

[10] -

[12] and

[16] . This method is based on providing a negative gate-source voltage only for a short period of time before a positive stray voltage appears to prevent false turn-on. The gate-source voltage will then return to zero, thereby reducing stress on the gate oxide layer. Furthermore, the device can withstand negative pulse voltages higher than the static off-state voltage.

[0006] References

[0007] The following references mentioned in this article are indicated by numbers in parentheses. For all purposes, the full contents of these references are hereby included by way of citation.

[0008] [1]J.Wang,H.Chung,and T.Li,"Characterization and experimentalassessment of the Effects of Parasitic Elements on the MOSFET SwitchingPerformance,"IEEE Transactions on Power Electronics,vol.28,no.1,pp.573-590,Jan 2013.

[0009] [2]J.Wang and H.Chung,"Impact of Parasitic Elements on the SpuriousTriggering Pulse in Synchronous Buck Converter,"IEEE Transactions on PowerElectronics,vol.29,no.12,pp.6672-6685,Dec.2014.

[0010] [3]Y.Li,M.Liang,J.Chen,T.Q.Zheng and H.Guo,"ALow Gate Turn-OFFImpedance Driver for Suppressing Crosstalk of SiC MOSFET Based on DifferentDiscrete Packages,"in IEEE Journal ofEmerging and Selected Topics in PowerElectronics,vol.7,no.1,pp.353-365,March 2019.

[0011] [4]K.Yamaguchi,K.Katsura,T.Yamada and Y.Sato,"Comprehensiveevaluation of gate boost driver for SiC-MOSFETs,"2016 IEEE Energy ConversionCongress and Exposition(ECCE),Milwaukee,WI,2016,pp.1-8.

[0012] [5]F.Gao,Q.Zhou,P.Wang and C.Zhang,"AGate Driver of SiC MOSFET forSuppressing the Negative Voltage Spikes in a Bridge Circuit,"in IEEETransactions on Power Electronics,vol.33,no.3,pp.2339-2353,March2018.

[0013] [6]Z.Zhang,J.Dix,F.F.Wang,B.J.Blalock,D.Costinett and L.M.Tolbert,"Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiCDevices,"in IEEE Transactions on Power Electronics,vol.32,no.12,pp.9319-9332,Dec.2017.

[0014] [7]Z.Zhang,Z.Wang,F.Wang,L.M.Tolbert and B.J.Blalock,"Reliability-oriented design of gate driver for SiC devices in voltage source converter,"2015 IEEE International Workshop on Integrated Power Packaging(IWIPP),Chicago,IL,2015,pp.20-23.

[0015] [8]Z.Zhang,F.Wang,L.M.Tolbert and B.J.Blalock,"Active Gate Driver forCrosstalk Suppression of SiC Devices in a Phase-Leg Configuration,"in IEEETransactions on Power Electronics,vol.29,no.4,pp.1986-1997,April2014.

[0016] [9]S.Yin,K.J.Tseng,C.F.Tong and R.Simanjorang,"Design of high-speedgate driver to reduce switching loss and mitigate parasitic effects for SiCMOSFET,"in IET Power Electronics,vol.10,no.10,pp.1183-1189,18 82017.

[0017]

[10] S.Zhao et al.,"Adaptive Multi-Level Active Gate Drivers for SiCPower Devices,"in IEEE Transactions on Power Electronics,vol.35,no.2,pp.1882-1898,Feb.2020.

[0018]

[11] Y.Yang,Y.Wen and Y.Gao,"ANovel Active Gate Driver for ImprovingSwitching Performance of High-Power SiC MOSFET Modules,"in IEEE Transactionson Power Electronics,vol.34,no.8,pp.7775-7787,Aug.2019.

[0019]

[12] Y.Chen,R.Wang,X.Liu and Y.Kang,"Gate-Drive Power Supply WithDecayed Negative Voltage to Solve Crosstalk Problem of GaN Synchronous BuckConverter,"in IEEE Transactions on Power Electronics,vol.36,no.1,pp.6-11,Jan.2021.

[0020]

[13] P.V.Pol,S.L.Patil and S.K.Pandey,"Asimple and novel technique fordriving silicon carbide power MOSFETs with unipolar supply voltage,"2016IEEEInternational Conference on Power Electronics,Drives and Energy Systems(PEDES),Trivandrum,2016,pp.1-6.

[0021]

[14] F.Mo,J.Furuta and K.Kobayashi,"Alow surge voltage and fast speedgate driver for SiC MOSFET with switched capacitor circuit,"2016 IEEE 4thWorkshop on Wide Bandgap Power Devices and Applications(WiPDA),Fayetteville,AR,2016,pp.282-285.

[0022]

[15] H.Gui,J.Sun and L.M.Tolbert,"Charge Pump Gate Drive to ReduceTurn-ON Switching Loss of SiC MOSFETs,"in IEEE Transactions on PowerElectronics,vol.35,no.12,pp.13136-13147,Dec.2020.

[0023]

[16] Q.He,Y.Zhu,H.Zhang,A.Huang,Q.Cai and H.Kim,"A Multilevel GateDriver of SiC mosfets for Mitigating Coupling Noise in Bridge-Leg Converter,"in IEEE Transactions on Electromagnetic Compatibility,vol.61,no.6,pp.1988-1996,Dec.2019.

[0024]

[17] C.Li et al., "High Off-State Impedance Gate Driver of SiC MOSFETs for Crosstalk Voltage Elimination Considering Common-Source Inductance," in IEEE Transactions on Power Electronics, vol.35, no.3, pp.2999-3011, March 2020.

[0025]

[18] A.Maerz, T.Bertelshofer, M.Bakran and M.Helsper, "ANovel Gate DriveConcept to Eliminate Parasitic Turn-on of SiC MOSFET in Low Inductance PowerModules," PCIM Europe 2017; International Exhibition and Conference for PowerElectronics, Intelligent Motion, Renewable Energy and Energy Management,Nuremberg,Germany,2017,pp.1-7.

[0026]

[19] J.Henn et al., "Intelligent Gate Drivers for Future PowerConverters," in IEEE Transactions on Power Electronics, vol.37, no.3, pp.3484-3503, March 2022.

[0027]

[20] "Si827x Data Sheet," Datasheet of SI8275, Rev.A, SILICON LABS, Jun.2022. Summary of the Invention

[0028] Based on the above background, the object of the present invention is to provide an alternative method and apparatus for driving the gate of a transistor (e.g., a SiC MOSFET) to address the deficiencies in the prior art described above.

[0029] Other objects of the invention will become apparent to those skilled in the art from the following description. Therefore, the foregoing statement of objects is not exhaustive and is only intended to illustrate some of the many objects of the invention.

[0030] The present invention provides, in a first aspect, an apparatus for driving a MOSFET, comprising a first gate driver, a switched capacitor circuit, and a second gate driver. The first gate driver generates a drive signal for the MOSFET. The switched capacitor circuit is connected to the first gate driver and temporarily generates a negative voltage to counteract stray voltages appearing on the first gate driver. The second gate driver drives the switched capacitor circuit. The first and second gate drivers are powered by the same voltage source and controlled by the same control logic.

[0031] Preferably, the above-described device further includes a gate resistor. The first gate driver is connected to the gate of the MOSFET through this gate resistor.

[0032] Preferably, the first gate driver includes a first transistor and a second transistor, whose drains are connected together and connected to the MOSFET as the output of the first gate driver. The source of the second transistor is connected to a switched capacitor circuit.

[0033] More preferably, the second gate driver includes a third transistor and a fourth transistor, whose drains are connected together and then connected to a switched capacitor circuit.

[0034] Most preferably, the gates of the first to fourth transistors are all connected to the control logic.

[0035] In another variation, the sources of both the first and third transistors are connected to a voltage source.

[0036] In another variation, the first through fourth transistors are implemented using a gate driver integrated circuit.

[0037] According to another variation of the preferred embodiment, the switched capacitor circuit includes an RC circuit. This RC circuit includes a first resistor and a capacitor connected in parallel.

[0038] Preferably, one end of the RC circuit is connected to the output of the second gate driver, and the other end is connected to the second resistor.

[0039] More preferably, the second gate driver includes a third transistor and a fourth transistor, whose drains are connected together and then connected to an RC circuit. The first end of the second resistor is connected to the RC circuit, and the second end is connected to the source of the fourth transistor.

[0040] More preferably, the first end of the second resistor is further connected to the first gate driver.

[0041] Most preferably, the first gate driver includes a first transistor and a second transistor, whose drains are connected together. A first terminal of the second resistor is connected to the source of the second transistor; the source of the first transistor is connected to a voltage source.

[0042] Therefore, different embodiments of the present invention provide apparatus and methods for providing a negative pulse voltage source adapted to instantaneously generate a negative voltage to counteract stray voltages generated by transistors in a first gate driver and improve switching performance. After the stray voltages are counteracted, the negative pulse voltage returns to zero in the off-state of the transistors in the first gate driver. In one exemplary embodiment, the circuit can be readily implemented using typical gate driver integrated circuits.

[0043] The above summary of the invention is neither intended to define the invention of this application nor to limit the scope of the invention in any way. Attached Figure Description

[0044] The above and further features of the present invention will be clearly described in the following description of embodiments, which are provided by way of example only and together with the following drawings:

[0045] Figure 1 shows a circuit diagram of a gate driver in the prior art with a negative bias voltage.

[0046] Figure 2 shows the internal structure of a typical gate driver IC with dual drivers.

[0047] Figure 3 A circuit diagram of a gate drive circuit according to an embodiment of the present invention is shown.

[0048] Figure 4 Showing Figure 3 Timing diagram of the gate drive circuit.

[0049] Figure 5 Showing the test Figure 3 The circuit diagram of the test circuit for the gate drive circuit.

[0050] Figure 6a Showing Figure 5 The two transistor pairs in the gate drive circuit implemented by the gate drive integrated circuit.

[0051] Figure 6b A gate driver circuit with a conventional gate driver, implemented using a gate driver integrated circuit, is shown for comparative purposes.

[0052] Figure 6c A gate driver circuit with a conventional gate driver, implemented using a gate driver integrated circuit, is shown for comparative purposes.

[0053] Figure 7a The key waveforms of the switching cycle in configuration 1 are shown.

[0054] Figure 7b The key waveforms of the switching cycle in configuration 2 are shown.

[0055] Figure 7c The key waveforms of the switching cycle in configuration 3 are shown.

[0056] Figure 8a The enlarged waveform during the shutdown process in Configuration 1 is displayed.

[0057] Figure 8b The enlarged waveform during the shutdown process in configuration 2 is displayed.

[0058] Figure 8c The enlarged waveform during the shutdown process in configuration 3 is displayed.

[0059] Figure 9a The image shows an amplified waveform during the startup process in Configuration 1.

[0060] Figure 9b The image shows an enlarged waveform during the startup process in configuration 2.

[0061] Figure 9c The image shows an enlarged waveform during the startup process in configuration 3.

[0062] In the accompanying drawings and the various embodiments described herein, the same reference numerals denote similar parts. Detailed Implementation

[0063] Unless otherwise stated, "coupled" or "connected" as used herein and in the claims means an electrical coupling or connection, directly or indirectly, by one or more electrical means. When "direct connection" is described, it means that two circuit components, nodes, or terminals are connected to each other without any intermediate components.

[0064] Embodiments of the present invention provide a switched-capacitor circuit that can provide a negative pulse voltage source. This simple circuit can be easily implemented using a typical gate driver integrated circuit, as shown in Figure 2

[20] . The circuit can instantaneously generate a negative voltage and return to zero during the off state. It can cancel stray voltages and improve switching performance.

[0065] Figure 3A gate drive circuit according to a first embodiment of the present invention is shown, which drives MOSFET 20. For example, MOSFET 20 may be a SiC MOSFET. For example, MOSFET 20 may be one of two series-connected switching devices in a bridge arm configuration. In bridge arm configurations widely used in synchronous buck converters, half-bridge / full-bridge converters, and inverters, there are two complementary switches: a control switch for determining the switching speed and a synchronization switch for zero-voltage switching. For example, MOSFET 20 may serve as either a control switch or a synchronization switch in such a bridge arm configuration.

[0066] Figure 3 The gate drive circuit in the circuit contains four transistors acting as switching devices: Q1, Q2, Q3, and Q4. Q1 and Q3 are P-MOSFETs, while Q2 and Q4 are N-MOSFETs. Transistors Q1 and Q2 form the first gate driver, and transistors Q3 and Q4 form the second gate driver. The gate terminals of all transistors Q1-Q4 are connected together and connected to control logic v1, which is provided, for example, by an MCU (microcontroller). The source terminals of transistors Q1 and Q3 are connected together and connected to a voltage source V. GG_H The positive terminal of transistor Q1 is given, and its source voltage is designated as VDDA. The source voltage of transistor Q3 is called VDDB. The source voltage of transistor Q2 is called VSSA. The source voltage of transistor Q4 is called VSSB.

[0067] The drains of transistors Q1 and Q2 are connected to form the output of the first gate driver, as shown below. Figure 3 As shown in OUTA. OUTA is connected to the gate resistor R. g Connected to the gate terminal of MOSFET 20. The voltage across the source terminal of transistor Q2 is designated as VSSA. The drain terminals of transistors Q3 and Q4 are connected and form the output of the second gate driver, as shown. Figure 3 As shown in OUTB.

[0068] A switched capacitor circuit is connected between the first gate driver and the second gate driver. Specifically, this switched capacitor circuit includes an RC circuit consisting of a resistor R. N and parallel capacitor C N Composition. One end of the RC circuit is connected to OUTB, and the other end is connected to the second resistor R. P Resistance R P One end of the resistor is connected to the source of transistor Q2 in the RC circuit and the first gate driver. P The other end is connected to the source of transistor Q4 and the voltage source V. GG_H The negative electrode and the source electrode of MOSFET 20.

[0069] It should be noted that the first and second gate drivers can be easily implemented using a gate driver IC (integrated circuit) with dual drivers, such as the IC shown in Figure 2. The various pins of the IC shown in Figure 2, including VDDA, VDDB, VSSA, VSSB, OUTA, and OUTB, can be connected to… Figure 3 The pins are defined in the code.

[0070] In description Figure 3 After describing the components and connections in the circuit, the operation of the circuit will be introduced next. The first gate driver consists of transistors Q1 and Q2, forming a conventional driver circuit. It is driven by control logic v1, whose output v g,A This is the main drive voltage, used to control MOSFET 20, and at V DDA and V SSA Switching between them. On the other hand, the second gate driver, consisting of Q3 and Q4, is an auxiliary drive circuit that shares the same control logic v1 as Q1 and Q2. The output drive of the second gate driver is driven by R. N R P and C N The switched capacitor circuit composed of V and SSA Provides a controllable negative voltage source.

[0071] When v1 changes from logical "high" to logical "low", Q1 and Q3 will be activated. g,A The voltage level will change from V SSA Change to V DDA This enables MOSFET 20. g,A The on-state voltage v g,A,ON for:

[0072] v g,A,ON =V DDA (1)

[0073] At the same time, v g,B The voltage level will change from V SSB Become with V DDA The same V DDB Therefore, v g,B The on-state voltage v g,B,ON for:

[0074] v g,B,ON =V DDA (2)

[0075] During conduction, C N Will be charged to R N and R P A given voltage. Assuming the time constant of the switched capacitor circuit is much smaller than the switching period of transistors Q1-Q4, then vCN and v CP The voltage can be expressed as

[0076]

[0077] Where t∈[0 dT],

[0078] When the conduction state ends, capacitor C N Will be fully charged, v CN and v CP The final voltage is expressed as,

[0079]

[0080] When v1 changes from logic "low" to logic "high", transistors Q2 and Q4 will turn on, v g,A The voltage level will change from V DDA Transform into V connected to the midpoint of the switched capacitor network SSA .therefore,

[0081] V g，A (dT + ) = V CP (dT + (7)

[0082] When transistor Q4 is turned on, the C stored in MOSFET 20 gs (Not displayed) and C N The charge on it will be redistributed. At dT, v CN and v CP initial voltage V CN and V CP They can be represented as,

[0083]

[0084] Therefore, in a short period of time, v g,A,OFF A negative voltage will appear on it. In the off state, C... N Will be discharged, v g,A This can be expressed as,

[0085]

[0086] Where t∈[dT T].

[0087] If stray voltage occurs Figure 3 The circuit described herein (hereinafter referred to as "the proposed circuit") can cancel the positive stray voltage generated when the control switch is turned on in the bridge arm configuration. The dead time t for the control switch to turn on... d Typically within tens of nanoseconds. Maximum permissible stray voltage vsp,MAX It can be represented as

[0088]

[0089] Because the time constant of the switched capacitor network is much smaller than the switching period, C... N It will be fully discharged. v ends when the off state is complete. g,A The final value is:

[0090] V g,A,OFF,f =V CP,OFF,f =V cN,OFF，f =0 (11)

[0091] When the control switch is off, the proposed circuit allows for higher negative stray voltages. Its timing diagram is as follows: Figure 4 As shown.

[0092] Next, we will discuss based on Figure 3 Experimental setup and verification of the prototype gate drive circuit. The circuit used to test the proposed circuit is as follows: Figure 5 As shown. The load circuit tested consists only of a SiC MOSFET 120, a load resistor, and a... Figure 3 The driving circuit consists of a typical dual-output gate driver IC (model: Si8275), where V... DDB Set below V DDA This is to prevent IC undervoltage lockout. To evaluate the performance of the proposed circuit in terms of negative voltage generation and switching performance, [the following tests were conducted]... Figures 6a-6c The three configurations shown were tested. Q1, Q2, Q3, and Q4 are implemented using the internal drive circuitry of the gate driver IC. Configuration 1 is the proposed circuit. Configuration 2 uses a conventional gate driver, V DDA =15V, V SSA =0V. Configuration 3 uses a conventional gate driver, V DDA =15V, V SSA = -5V. Table 1 lists the part numbers and component values. The first gate driver voltage V was investigated. g,A Gate-source voltage v gs Drain-source voltage v ds and drain current i d The waveform.

[0093] Table 1: Component Models and Values

[0094]

[0095] Figures 7a-7c This shows the v during several switching cycles of the MOSFET 120. g,A vgs v ds and i d The waveform. Figure 7a , 7b Figures 7 and 7c show the waveforms for configurations 1, 2, and 3, respectively. During conduction, in all configurations, v gs All follow V DDA During shutdown, in configuration 1, v gs There is a momentary negative voltage, then it returns to 0V. In configuration 2, v gs Keep it at 0V. In configuration 3, v gs Maintain at -5V.

[0096] Figures 8a-8c The amplified waveforms of MOSFET 120 when it is turned off are shown in configurations 1-3. The transient and steady-state characteristics when turned off are shown in Table 2. The symbols are named as follows:

[0097] V ds,ON :v ds steady-state conduction value

[0098] t ds,f :v ds The time it takes for the temperature to drop from 90% to 10% of the steady-state value.

[0099] V g,ON :v g steady-state conduction value

[0100] t g,r :v g The rise time (from 10% to 90% of the steady-state value).

[0101] V gs,ON :v gs steady-state conduction value

[0102] t gs,r :v gs The rise time (from 10% to 90% of the steady-state value).

[0103] I d,ON :i d steady-state conduction value

[0104] t d,r :i d The rise time (from 10% to 90% of the steady-state value).

[0105] Table 2: Component Models and Values

[0106]

[0107] In the proposed circuit, v CN It is temporarily negative when closed. SSA It is also negative. Therefore, when MOSFET 120 is off, v gs Drop from 15V to -5V. Although in configurations 1 and 3... gs The fall time is longer, but it is easier to pass the threshold voltage. The proposed circuit has a higher switching speed than configuration 2, and is similar to configuration 3.

[0108] Through observation Figure 8a The turn-off waveform of the proposed circuit shown has a peak negative voltage of -5.8V immediately after the switch is turned off, and a voltage of v after 100ns of turn-off. gs The voltage level is -4.8V. A stray voltage with a maximum value of 4.8V is allowed. This is almost the same as the maximum positive stray voltage allowed when using configuration 3.

[0109] Figures 9a-9c The amplified waveforms of MOSFET 120 when turned on are shown in configurations 1-3. Table 3 shows the transient and steady-state characteristics when turned on. The symbols are named as follows:

[0110] V ds,ON :v ds steady-state conduction value

[0111] t ds,f :v ds The time it takes for the temperature to drop from 90% to 10% of the steady-state value.

[0112] V g,ON :v g steady-state conduction value

[0113] t g,r :v g The rise time (from 10% to 90% of the steady-state value).

[0114] V gs,ON :v gs steady-state conduction value

[0115] t gs,r :v gs The rise time (from 10% to 90% of the steady-state value).

[0116] I d,ON :i d steady-state conduction value

[0117] t d,r :i d The rise time (from 10% to 90% of the steady-state value).

[0118] Table 3: Transient and steady-state characteristics during the start-up period

[0119]

[0120] like Figure 9a As shown, when using the proposed circuit, C at the end of the off state N Complete discharge, V SSA The voltage level is 0. The maximum permissible negative stray voltage is close to configuration 2. Furthermore, when the MOSFET is turned on, v gs The switching speed increases from 0 to 15V, which is higher than that of Configuration 3, but similar to Configuration 2.

[0121] In summary, the proposed circuit can provide a pulsed negative voltage source to cancel positive stray voltages and discharge to 0V to cancel negative stray voltages. Furthermore, it can simultaneously achieve a high turn-on speed (just like V). SSA =0V conventional gate driver) and high turn-off speed (just like V) SSA = -5V conventional gate driver. This results in lower switching losses during turn-on and turn-off compared to using a conventional gate driver (V... SSA =0V or V SSA It has lower switching losses at -5V. Furthermore, this circuit is easy to implement in typical gate driver integrated circuits, and the control signals for the additional transistors are the same as those for conventional gate drivers.

[0122] Figure 3 The proposed circuit shown is a gate drive circuit composed of switched capacitors to provide a negative pulse voltage source. This circuit can generate a negative voltage from a positive voltage source to cancel stray voltages and improve switching performance. Compared to conventional gate drivers, this circuit requires only two transistors, two resistors, and one capacitor. It can be easily implemented using a typical gate driver IC with dual outputs. The proposed circuit has been tested in a 100W switching circuit. Experimental results show that the proposed circuit can generate a pulsed negative voltage from a positive voltage source, which can then cancel positive stray voltages. Furthermore, switching performance is improved compared to conventional gate drivers.

[0123] Embodiments of the present invention have been fully described. While specific embodiments have been mentioned in the description, those skilled in the art will understand that variations in these specific details are possible in implementing the invention. Therefore, the invention should not be construed as being limited to the embodiments set forth herein.

[0124] While the detailed description and specifications of the invention have been set forth in the accompanying drawings and the foregoing description, they should be considered illustrative rather than restrictive, as exemplary embodiments are shown only and the scope of the invention is not limited in any way. It is understood that any feature described herein can be used in conjunction with any embodiment. The illustrative embodiments are not mutually exclusive, nor are other embodiments not described herein. Therefore, the invention also provides embodiments that include combinations of one or more of the illustrative embodiments described above. Modifications and variations can be made to the invention without departing from its spirit and scope; therefore, only the limitations set forth in the appended claims should be applied.

Claims

1. An apparatus for driving a MOSFET, comprising: a first gate driver for generating a driving signal for the MOSFET; a switched capacitor circuit connected to the first gate driver for temporarily generating a negative voltage to offset a stray voltage appearing on the first gate driver; and a second gate driver for driving the switched capacitor circuit; wherein the first gate driver and the second gate driver are powered by a same voltage source and controlled by a same control logic.

2. The apparatus of claim 1, further comprising a gate resistor through which the first gate driver is connected to a gate of the MOSFET.

3. The apparatus of claim 1, wherein the first gate driver comprises a first transistor and a second transistor whose drains are connected together as an output of the first gate driver and connected to the MOSFET; and the source of the second transistor is connected to the switched capacitor circuit.

4. The apparatus of claim 3, wherein the second gate driver comprises a third transistor and a fourth transistor whose drains are connected together and then connected to the switched capacitor circuit.

5. The apparatus of claim 4, wherein the gates of the first through fourth transistors are connected to the control logic.

6. The apparatus of claim 4, wherein the sources of the first and third transistors are connected to the voltage source.

7. The apparatus of claim 4, wherein the first through fourth transistors are implemented by a gate driver integrated circuit.

8. The apparatus of claim 1, wherein the switched capacitor circuit comprises an RC circuit including a first resistor and a capacitor connected in parallel.

9. The apparatus of claim 8, wherein one end of the RC circuit is connected to an output of the second gate driver and the other end is connected to a second resistor.

10. The apparatus of claim 9, wherein the second gate driver comprises a third transistor and a fourth transistor whose drains are connected together and then connected to the RC circuit; and the first end of the second resistor is connected to the RC circuit and the second end is connected to the source of the fourth transistor. The first end of the second resistor is further connected to the first gate driver.

11. The apparatus of claim 10, wherein, 12. The apparatus of claim 11, wherein the first gate driver comprises a first transistor and a second transistor whose drains are connected together; the first end of the second resistor is connected to the source of the second transistor; and the source of the first transistor is connected to the voltage source. ​

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