Sampling system

Abstract

The sampling system includes a sampler circuit, a first stable error canceller circuit, and a second stable error canceller circuit. In a first stage, both the sampler circuit and the first stable error canceller circuit perform a sampling operation, and the second stable error canceller circuit performs a holding operation. In a second stage, the sampler circuit and the second stable error canceller circuit perform charge redistribution, and the first stable error canceller circuit performs a hold operation. In a third stage, both the sampler circuit and the second stable error canceller circuit perform a sampling operation, and the first stable error canceller circuit performs a holding operation. In a fourth stage, the sampler circuit and the first stable error canceller circuit perform charge redistribution, and the second stable error canceller circuit performs a hold operation.

Description

TECHNICAL FIELD

[0001] The present invention relates to sampling an analog input for subsequent processing, and more particularly to a sampling system with settling error cancellation. BACKGROUND

[0002] Polyphase time-interleaved samplers are important building block circuits between continuous-time linear equalizers (CTLE) and analog-to-digital converters (ADC) in high-speed receiver analog front-ends based on mainstream digital signal processors (DSPs). However, when the voltage V I (t1) to be sampled at the current sampling time point t1 is different from the voltage V O (t0) sampled at the previous sampling time point t0, the sampling capacitor needs to be charged / discharged during the sampling of the voltage V I (t1). The voltage V O (t1) sampled at the current sampling time point t1 can deviate from the voltage V I (t1) due to the settling error caused by incomplete settling. For example, when a negative settling error occurs, the voltage V O (t1) held by the sampling capacitor at the end of the current sampling phase will be lower than the voltage V I (t1). For another example, when a positive settling error occurs, the voltage V O (t1) held by the sampling capacitor at the end of the current sampling phase will be higher than the voltage V I (t1). In particular, the settling error caused by the incomplete settling of the voltage V O (t0) can be represented as (1-k)*V O (t0), where k = 1 - e -t / τand τ is the RC time constant of the sampler. The error factor k is closely related to the driving capability of the previous voltage buffer, the effective on-resistance of the switches of the sampler, and the size of the sampling capacitor of the sampler, which also means that the error factor k can be different at different process corners, power supply voltages, and temperatures. A common approach is to use a voltage buffer with strong driving capability (e.g., a source follower), however, a voltage buffer with strong driving capability itself is a power-consuming element, which leads to higher power consumption. Another common approach is to provide a reset stage to clear the currently stored value before a new sampling is performed, however, the reset window is short under high-speed sampling operation, and a large size reset switch is needed. Another common approach is to eliminate the stable error through a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter in a digital signal processor, but at the cost of higher noise / power.

[0003] Therefore, there is a need for a sampling system with an innovative stable error elimination design. SUMMARY

[0004] One of the objectives of the present application is to propose a sampling system with stable error elimination, in which an additional sampling capacitor is introduced to form a stable error elimination circuit based on switched-capacitor.

[0005] In one embodiment of the present invention, a sampling system is disclosed. The sampling system includes a sampler circuit, a first stable error canceller circuit, and a second stable error canceller circuit. The sampler circuit is coupled between an input port and an output port of the sampling system and includes at least one sampling capacitor. The first stable error canceller circuit is coupled between the input port and the output port of the sampling system, wherein the first stable error canceller circuit includes at least one first sampling capacitor. The second stable error canceller circuit is coupled between the input port and the output port of the sampling system, wherein the second stable error canceller circuit includes at least one second sampling capacitor. During a first phase of a stable error cancellation operation, the sampler circuit is configured to sample a voltage input from the input port at the at least one sampling capacitor, the first stable error canceller circuit is configured to sample the voltage input from the input port at the at least one first sampling capacitor, and the second stable error canceller circuit is configured to hold its sample at the at least one second sampling capacitor. During a second phase of the stable error cancellation operation immediately following the first phase, the sampler circuit and the second stable error canceller circuit perform charge redistribution between the at least one sampling capacitor and the at least one second sampling capacitor, and the first stable error canceller circuit is configured to hold its sample at the at least one first sampling capacitor. During a third phase of the stable error cancellation operation immediately following the second phase, the sampler circuit is configured to sample the voltage input from the input port at the at least one sampling capacitor, the second stable error canceller circuit is configured to sample the voltage input from the input port at the at least one second sampling capacitor, and the first stable error canceller circuit is configured to hold its sample at the at least one first sampling capacitor. During a fourth phase of the stable error cancellation operation immediately following the third phase, the sampler circuit and the first stable error canceller circuit perform charge redistribution between the at least one sampling capacitor and the at least one first sampling capacitor, and the second stable error canceller circuit is configured to hold its sample at the at least one second sampling capacitor.

[0006] The present application proposes a stable error cancellation design which uses an extra sampling capacitor to form a switched-capacitor-based stable error canceller circuit at each canceller path to inject the stored information of the current sampling phase to cancel the stable error caused by the incomplete stabilization in the next sampling phase, in particular, the stable error cancellation is achieved by the charge redistribution between the extra sampling capacitor of the canceller path and the original sampling capacitor of the main path, thus, the stable error can be cancelled by adjusting the extra sampling capacitor to a proper capacitance value, for example, the polarity and size of the stable error of the sampler circuit on the main path can be estimated by an online training procedure before enabling the stable error cancellation, for example, the stable error estimation can be performed by using a correlator and a least mean square error loop. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic diagram of a first sampling system with stable error cancellation according to an embodiment of the present application.

[0008] Figure 2 is a waveform diagram of the clock signal for controlling the switches in the sampling system shown in Figure 1

[0009] is a schematic diagram of a second sampling system with stable error cancellation according to an embodiment of the present application. Figure 3

[0010] is a waveform diagram of the clock signal for controlling the switches in the sampling system shown in Figure 4 Figure 3 is a schematic diagram of a third sampling system with stable error cancellation according to an embodiment of the present application.

[0011] Figure 5 is a schematic diagram of a fourth sampling system with stable error cancellation according to an embodiment of the present application.

[0012] Figure 6 is a waveform diagram of the clock signal for controlling the switches in the sampling system shown in

[0013] Figure 7 Figure 6 is a schematic diagram of a fifth sampling system with stable error cancellation according to an embodiment of the present application.

[0014] Figure 8 is a waveform diagram of the clock signal for controlling the switches in the sampling system shown in

[0015] Figure 9 is a waveform diagram of the clock signal for controlling the switches in the sampling system shown in Figure 8 ​​​

[0016] Figure 10 This is a schematic diagram of a sixth sampling system with stable error elimination according to an embodiment of the present invention.

[0017] Figure 11 This is a schematic diagram of a seventh sampling system with stable error elimination according to an embodiment of the present invention.

[0018] [Symbol Explanation]

[0019] 100, 300, 500, 600, 800, 1000, 1100: Sampling system

[0020] 102, 302, 502, 602, 802, 1002, 1102: Sampler circuits

[0021] 104_1, 104_2, 104_3, 104_4, 106_1, 106_2, 106_3, 106_4, 304_1, 304_2, 306_1, 306_2, 604_1, 604_2, 606_1, 606_2: Partial circuit

[0022] 308,808: Negative unity-gain amplifier

[0023] 504, 804, 1004, 1104: First stable error canceller circuit

[0024] 506, 806, 1006, 1106: Second stable error canceller circuit

[0025] N IP Positive input node

[0026] N IN Negative input node

[0027] N OP Positive output node

[0028] N ON Negative output node

[0029] V IP V OP Positive voltage signal

[0030] V IN V ON Negative voltage signal

[0031] LEQ: Linear equalizer

[0032] BUF: Buffer

[0033] ADC: Analog-to-Digital Converter

[0034] CP C N C 11 C 12 C 13 C 14 C 21 C 22 C 23 C 24 C SE Sampling capacitor

[0035] SW P ,SW N ,SW 11 ,SW 12 ,SW 13 ,SW 14 ,SW 15 ,SW 16 ,SW 17 ,SW 18 ,SW 21 ,SW 22 ,SW 23 ,SW 24 ,SW 25 ,SW 26 ,SW 27 ,SW 28 ,SW SE :switch

[0036] CK1,CK1',CK1”,CK2,CK2’,CK2”,CK rank2 CK 1P ',CK 1P CK 2P ',CK 2P CK 1N ',CK 1N CK 2N ',CK 2N Clock signal

[0037] GND: Grounding voltage

[0038] C PAR Parasitic capacitance

[0039] C S C SCP C SCN C SC Capacitance value

[0040] P1: First Stage

[0041] P2: Second Stage

[0042] P3: Third Stage

[0043] P4: Fourth Stage

[0044] N I Single input node

[0045] N O Single output node

[0046] V I V O Single voltage signal

[0047] A I Amplifier input node

[0048] A O Amplifier output node Detailed Implementation

[0049] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" or "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0050] This invention proposes a stabilization error cancellation design that uses additional sampling capacitors to form switched-capacitor-based settling error canceller circuits on each canceller path. These circuits inject memorized information from the current sampling phase to eliminate stabilization errors caused by incomplete instability in the next sampling phase. Specifically, stabilization error cancellation is achieved through charge redistribution between the additional sampling capacitors on the canceller path and the original sampling capacitors on the main path. Therefore, the stabilization error (1-k)*V can be eliminated by adjusting the additional sampling capacitors to an appropriate value. O(t0), for example, before enabling stable error cancellation, the stable error (1-k)*V of the sampler circuit on the main path can be estimated through an online training process. O The polarity and magnitude of (t0) can be determined, for example, by using a correlator and a minimum mean square error loop to estimate the steady-state error. In fact, it is possible to estimate the steady-state error (1-k)*V of the sampler circuit. O Any means of determining the polarity and magnitude of (t0) can be employed. Since this invention is primarily aimed at eliminating stability errors, further descriptions of stability error estimation are omitted here for the sake of brevity.

[0051] Additional sampling capacitance can be implemented using a variable capacitor, and the stability can be adjusted based on the stability error (1-k)*V. O The polarity and / or magnitude of (t0) should be adjusted appropriately. Due to the stability error (1-k)*V O (t0) can be estimated through an online training process, thus stability error elimination can also overcome process, voltage, and temperature variations (PVT variations). In some embodiments, stability error (1-k)*V can also be used. O The polarity of (t0) is used to control the stabilization error canceller circuit based on the switching capacitor. Furthermore, the stabilization error cancellation design proposed in this invention can be embedded into existing multiphase time-interleaved sampling networks, thus easily solving the problem of multiphase sampling clock generation required for the stabilization error canceller circuit based on the switching capacitor in the canceller path.

[0052] The concept of the stabilization error elimination design proposed in this invention is briefly described as follows. The sampling system includes a sampler circuit (located on a main path), a first stabilization error elimination circuit (located on an elimination path), and a second stabilization error elimination circuit (located on another elimination path). The first and second stabilization error elimination circuits perform stabilization error elimination in a time-interleaved manner. For example, the first stabilization error elimination circuit is used to perform stabilization error elimination on the sample at t0, the second stabilization error elimination circuit is used to perform stabilization error elimination on the sample at t1 (t1>t0), the first stabilization error elimination circuit is used to perform stabilization error elimination on the sample at t2 (t2>t1), the second stabilization error elimination circuit is used to perform stabilization error elimination on the sample at t3 (t3>t2), and so on.

[0053] The stabilization error elimination operation can be divided into four stages. During the first stage, each of the sampler circuit and the first stabilization error elimination circuit performs a sampling operation, and the second stabilization error elimination circuit performs a holding operation. Specifically, the sampler circuit samples a voltage input (derived from the input port of the sampling system) across its sampling capacitor, the first stabilization error elimination circuit samples the voltage input (derived from the input port of the sampling system) across its sampling capacitor, and the second stabilization error elimination circuit holds the sampling result across its sampling capacitor.

[0054] During the second phase immediately following the first phase, the sampler circuit and the second stabilizing error canceller circuit perform charge redistribution for stabilizing error cancellation, and the first stabilizing error canceller circuit performs a holding operation. Specifically, the sampler circuit and the second stabilizing error canceller circuit are used to perform charge redistribution between the sampling capacitor of the sampler circuit and the sampling capacitor of the second stabilizing error canceller circuit, and the first stabilizing error canceller circuit is used to hold the sampling result on the sampling capacitor of the first stabilizing error canceller circuit.

[0055] During the third phase immediately following the second phase, each of the sampler circuit and the second stabilizing error canceller circuit performs a sampling operation, and the first stabilizing error canceller circuit performs a holding operation. Specifically, the sampler circuit is used to sample the voltage input (which is obtained from the input port of the sampling system) on the sampling capacitor of the sampler circuit, the second stabilizing error canceller circuit is used to sample the voltage input (which is obtained from the input port of the sampling system) on the sampling capacitor of the second stabilizing error canceller circuit, and the first stabilizing error canceller circuit is used to hold the sampling result on the sampling capacitor of the first stabilizing error canceller circuit.

[0056] During the fourth stage immediately following the third stage, the sampler circuit and the first stabilization error canceller circuit perform charge redistribution for stabilization error cancellation, and the second stabilization error canceller circuit performs a holding operation. Specifically, the sampler circuit and the first stabilization error canceller circuit are used to perform charge redistribution between the sampling capacitor of the sampler circuit and the sampling capacitor of the first stabilization error canceller circuit, and the second stabilization error canceller circuit is used to hold the sampling result on the sampling capacitor of the second stabilization error canceller circuit.

[0057] After the fourth stage is completed, the stabilization error elimination operation will return to the first stage to perform another round of the first, second, third and fourth stages.

[0058] To better understand the technical features of the stable error elimination design proposed in this invention, various sampling systems with stable error elimination are described below with reference to the figures.

[0059] Figure 1 This is a schematic diagram of a first sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 100 includes a sampler circuit 102 located on the main path, a first stable error elimination circuit (comprising multiple partial circuits 104_1, 104_2, 104_3, and 104_4) located on a first eliminater path (labeled "Eliminator Path 1"), and a second stable error elimination circuit (comprising multiple partial circuits 106_1, 106_2, 106_3, and 106_4) located on a second eliminater path (labeled "Eliminator Path 2"). Each of the sampler circuit 102, the first stable error elimination circuit, and the second stable error elimination circuit is coupled between an input port and an output port of the sampling system 100. In this embodiment, the sampling system 100 is a differential operation network; therefore, the input port has a positive input node N. IP and negative input node N IN The differential input port (with parasitic capacitance C) par The output port is a node N with a positive output. OP and negative output node N ON The differential output port receives a voltage input with a positive voltage signal V from the input port. IP (It is driven by a linear equalizer / buffer (LEQ / BUF)) and a negative voltage signal V IN The differential voltage input (driven by another LEQ / BUF) and the voltage output generated from the output port have a positive voltage signal V. OP (which is provided to an ADC through a BUF) and negative voltage signal V ON (It provides a differential voltage output to another ADC through another BUF).

[0060] The sampler circuit 102 includes multiple sampling capacitors C P C N and multiple switches (e.g., transistor switches) SW P SW N Sampling capacitor C P It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C NIt has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C P and C N Having the same capacitance value C S Switch SW P Controlled by clock signal CK1 and coupled to sampling capacitor C P The first end and the positive input node N IP Between. Switch SW N Controlled by clock signal CK1 and coupled to sampling capacitor C N The first end and the negative input node N IN between.

[0061] The first stabilization error elimination circuit includes multiple sampling capacitors (e.g., variable capacitors) C 11 C 12 C 13 C 14 and multiple switches (e.g., transistor switches) SW 11 SW 12 SW 13 SW 14 SW 15 SW 16 SW 17 SW 18 The sampling capacitor C 11 and C 14 Having the same capacitance value C SCP and sampling capacitor C 12 and C 13 Having the same capacitance value C SCN (C SCN ≠C SCP Sampling capacitor C 11 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 12 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 13 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 14 It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND).

[0062] Switch SW 11 From clock signal CK l 'Control, and coupled to the sampling capacitor C' 11 The first end and the positive input node NIP Between. Switch SW 12 Controlled by clock signal CK2' and coupled to sampling capacitor C 11 The first end and the positive output node N OP Between. Switch SW 13 Controlled by clock signal CK1' and coupled to sampling capacitor C 12 The first end and the positive input node N IP Between. Switch SW 14 Controlled by clock signal CK2' and coupled to sampling capacitor C 12 The first end and the negative output node N ON Between. Switch SW 15 Controlled by clock signal CK1' and coupled to sampling capacitor C 13 The first end and the negative input node N IN Between. Switch SW 16 Controlled by clock signal CK2' and coupled to sampling capacitor C 13 The first end and the positive output node N OP Between. Switch SW 17 Controlled by clock signal CK1' and coupled to sampling capacitor C 14 The first end and the negative input node N IN Between. Switch SW 18 Controlled by clock signal CK2' and coupled to sampling capacitor C 14 The first end and the negative output node N ON between.

[0063] The second stabilizing error canceller circuit includes multiple sampling capacitors (e.g., variable capacitors) C 21 C 22 C 23 C 24 and multiple switches (e.g., transistor switches) SW 21 SW 22 SW 23 SW 24 SW 25 SW 26 SW 27 SW 28 The sampling capacitor C 21 and C 24 Having the same capacitance value C SCP and sampling capacitor C 22 and C 23 Having the same capacitance value C SCN (C SCN ≠C SCP Sampling capacitor C 21It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 22 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 23 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 24 It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND).

[0064] Switch SW 21 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 21 The first end and the positive input node N IP Between. Switch SW 22 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 21 The first end and the positive output node N OP Between. Switch SW 23 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 22 The first end and the positive input node N IP Between. Switch SW 24 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 22 The first end and the negative output node N ON Between. Switch SW 25 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 23 The first end and the negative input node N IN Between. Switch SW 26 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 23 The first end and the positive output node N OP Between. Switch SW 27 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 24 The first end and the negative input node N IN Between. Switch SW 28 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 24 The first end and the negative output node N ON between.

[0065] As mentioned above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, resulting in a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ...Figure 2 This is a waveform diagram of a clock signal used to control a switch in a sampling system 100 according to an embodiment of the present invention, wherein... Figure 2 The clock signal CK shown rank2 It is used to control the ADC. During the first stage P1 of the stabilization error elimination operation, switch SW... P SW N SW 11 SW 13 SW 15 SW 17 It is switched on, and the switch SW is turned on / off. 12 SW 14 SW 16 SW 18 SW 21 ~SW 28 It is switched off. During the second phase P2 of the stabilization error elimination operation, switch SW is switched off. 22 SW 24 SW 26 SW 28 It is turned on, and the SW switch is activated. P SW N SW 11 ~SW 18 SW 21 SW 23 SW 25 SW 27 It is turned off. During the third stage P3 of the stabilization error elimination operation, switch SW is turned off. P SW N SW 21 SW 23 SW 25 SW 27 It is turned on, and the SW switch is activated. 22 SW 24 SW 26 SW 28 SW 11 ~SW 18 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 SW 14 SW 16 SW 18 It is turned on, and the SW switch is activated. P SW N SW 21 ~SW 28 SW 11 SW 13 SW 15 SW17 It has been shut down.

[0066] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The sampling circuit 102 on the main path suffers a stable error (1-k)*V with negative polarity. O Under the influence of (t0), the capacitance value C can be adjusted. SCP Set to be greater than the capacitance value C SCN Thus, we obtain (C) SCP -C SCN )>0; In addition, the capacitance value C SCP and C SCN It can be appropriately configured to ensure that a portion of the stored information injected by the activated stabilization error canceller circuit (i.e., one of the first and second stabilization error canceller circuits) can eliminate the stabilization error (1-k)*V. O (t0). The sampling circuit 102 on the main path suffers a stable error (1-k)*V with positive polarity. O In another case where (t0) has an effect, the capacitance value C can be... SCP Set to less than the capacitance value C SCN Thus, we obtain (C) SCP -C SCN )<0; In addition, the capacitance value C SCP and C SCN It can be appropriately configured to ensure that a portion of the stored information injected by the activated stabilization error canceller circuit (i.e., one of the first and second stabilization error canceller circuits) can eliminate the stabilization error (1-k)*V. O (t0). Simply put, due to the stability error of sampling circuit 102, (1-k)*V O The polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The polarity and magnitude of (t0) are used to adjust the capacitance value C. SCP and C SCN By this means, the elimination weight can be set appropriately. The polarity and magnitude.

[0067] Figure 3This is a schematic diagram of a second sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 300 includes a sampler circuit 302 located on the main path, a first stable error elimination circuit (comprising multiple sub-circuits 304_1 and 304_2) located on a first eliminater path (labeled "Eliminator Path 1"), a second stable error elimination circuit (comprising multiple sub-circuits 306_1 and 306_2) located on a second eliminater path (labeled "Eliminator Path 2"), and a negative-unity-gain amplifier 308. Each of the sampling circuit 302, the first stable error elimination circuit, and the second stable error elimination circuit is coupled between an input port and an output port of the sampling system 300. The sampling system 300 is a single-ended computation network; therefore, the input port has a single input node N. I A single-ended input port, and an output port with a single output node N. O The single-ended output port receives a voltage input with a single voltage signal V from the input port. I It has a single-ended voltage input (driven by a LEQ / BUF) and a voltage output from the output port with a single voltage signal V. O (It provides a single-ended voltage output to an ADC via a BUF).

[0068] The negative unity-gain amplifier 308 has amplifier input node A I and amplifier output node A O Where amplifier input node A I Coupled to input node N I The sampler circuit 302 includes a sampling capacitor C. SE and switches (e.g., transistor switches) SW SE Sampling capacitor C SE It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C SE With capacitance value C S Switch SW SE Controlled by clock signal CK1 and coupled to sampling capacitor C SE The first end and the input node N I between.

[0069] The first stable error canceller circuit includes multiple sampling capacitors (e.g., variable capacitors) C 11 C 12 and multiple switches (e.g., transistor switches) SW 11 SW 12 SW 13 SW14 The sampling capacitor C 11 and C 12 Having the same capacitance value C SC Sampling capacitor C 11 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 12 It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND).

[0070] Switch SW 11 From clock signal CK 1P 'Control, and coupled to the sampling capacitor C' 11 The first end and input node N I Between. Switch SW 12 From clock signal CK 2P 'Control, and coupled to the sampling capacitor C' 11 First end and output node N O Between. Switch SW 13 From clock signal CK 1N 'Control, and coupled to the sampling capacitor C' 12 The first terminal and amplifier output node A O Between. Switch SW 14 From clock signal CK 2N 'Control, and coupled to the sampling capacitor C' 12 First end and output node N O between.

[0071] The second stabilizing error canceller circuit includes multiple sampling capacitors (e.g., variable capacitors) C 21 C 22 and multiple switches (e.g., transistor switches) SW 21 SW 22 SW 23 SW 24 The sampling capacitor C 21 and C 22 Having the same capacitance value C SC Sampling capacitor C 21 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 22 It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND).

[0072] Switch SW 21 From clock signal CK 1P "Control, and coupled to the sampling capacitor C"21 The first end and input node N I Between. Switch SW 22 From clock signal CK 2P "Control, and coupled to the sampling capacitor C" 21 First end and output node N O Between. Switch SW 23 From clock signal CK 1N "Control, and coupled to the sampling capacitor C" 22 The first terminal and amplifier output node A O Between. Switch SW 24 From clock signal CK 2N "Control, and coupled to the first terminal of the sampling capacitor C22 and the output node N." O between.

[0073] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, thereby generating a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... Figure 4 This is a waveform diagram of a clock signal used to control a switch in a sampling system 300 according to an embodiment of the present invention, wherein... Figure 4 The clock signal CK shown rank2 It is used to control the ADC.

[0074] When the stable error to be eliminated has negative polarity, it has Figure 4 The clock signal of the waveform shown in sub-diagram (A) can be used by sampling system 300. During the first stage P1 of the stabilization error elimination operation, switch SW SE SW 11 It will turn on, and the switch SW will be activated. 12 ~SW 14 SW 21 ~SW 24 It will be turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 22 It will turn on, and the switch SW will be activated. SE SW 11 ~SW 14 SW 21 SW 23 SW 24 It will be turned off. During the third phase P3 of the stabilization error elimination operation, switch SW... SE SW 21 It is turned on, and the SW switch is activated. 22 ~SW 24 SW 11 ~SW 14It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 Turn on, and switch SW SE SW 21 ~SW 24 SW 11 SW 13 SW 14 It will be shut down.

[0075] In another case where the stable error to be eliminated has a positive polarity, it has the following characteristics: Figure 4 The clock signal of the waveform shown in sub-figure (B) can be used by the sampling system 300. During the first stage P1 of the stabilization error elimination operation, switch SW SE SW 13 It will turn on, and the switch SW will be activated. 11 SW 12 SW 14 SW 21 ~SW 24 It will be turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 24 Turn on, and switch SW SE SW 11 ~SW 14 SW 21 ~SW 23 It will be turned off. During the third phase P3 of the stabilization error elimination operation, switch SW... SE SW 23 It is turned on, and the SW switch is activated. 21 SW 22 SW 24 SW 11 ~SW 14 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 14 It is turned on, and the SW switch is activated. SE SW 21 ~SW 24 SW 11 ~SW 13 It has been shut down.

[0076] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The polarity of the stability error elimination depends on whether the amplifier output of the negative unity-gain amplifier 308 is used (i.e., -V). IThe sampler circuit 302 on the main path suffers a stable error (1-k)*V with negative polarity. O Under the influence of (t0), portions of circuit 304_1 of the first stabilization error canceller circuit and 306_1 of the second stabilization error canceller circuit will be used during the stabilization error cancellation operation. The sampler circuit 302 on the main path suffers a stabilization error (1-k)*V with positive polarity. O In another scenario where (t0) affects the circuit, portions 304_2 of the first stabilizing error canceller circuit and 306_2 of the second stabilizing error canceller circuit are used during the stabilizing error cancellation operation. Additionally, the capacitance value C... SC The stored information injected by the activated stability error canceller circuit (i.e., one of the first and second stability error canceller circuits) is properly configured to eliminate the stability error (1-k)*V. O (t0). Simply put, due to the stability error of sampling circuit 302, (1-k)*V O The polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The capacitance value C is adjusted by the value of (t0). SC By this means, the elimination weight can be set appropriately. Size.

[0077] Figure 5 This is a schematic diagram of a third sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 500 includes a sampler circuit 502 located on the main path, a first stable error eliminater circuit 504 located on a first eliminater path (labeled "Eliminator Path 1"), and a second stable error eliminater circuit 506 located on a second eliminater path (labeled "Eliminator Path 2"). Each of the sampler circuit 502, the first stable error eliminater circuit 504, and the second stable error eliminater circuit 506 is coupled between an input port and an output port of the sampling system 500. In this embodiment, the sampling system 500 is a single-ended computation network; therefore, the input port has a single input node N. I A single-ended input port, and an output port with a single output node N. O The single-ended output port receives a voltage input with a single voltage signal V from the input port. I It has a single-ended voltage input (driven by a LEQ / BUF) and a voltage output from the output port with a single voltage signal V. O(It provides a single-ended voltage output to an ADC via a BUF.) The difference between sampling systems 300 and 500 is that the negative unity-gain amplifier 308 used in sampling system 300 is omitted in sampling system 500. Therefore, the first stabilization error canceller circuit 504 and the second stabilization error canceller circuit 506 can only support the elimination of stabilization errors with negative polarity.

[0078] Sampler circuit 502 includes sampling capacitor C SE and switches (e.g., transistor switches) SW SE Sampling capacitor C SE It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C SE With capacitance value C S Switch SW SE Controlled by clock signal CK1 and coupled to sampling capacitor C SE The first end and the input node N I between.

[0079] The first stabilizing error canceller circuit 504 includes a sampling capacitor (e.g., a variable capacitor) C1 and multiple switches (e.g., transistor switches) SW. 11 SW 12 The sampling capacitor C1 has a capacitance value C SC The sampling capacitor C1 has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Switch SW 11 Controlled by clock signal CK1', and coupled to the first terminal of sampling capacitor C1 and input node N I Between. Switch SW 12 Controlled by clock signal CK2', and coupled to the first terminal of sampling capacitor C1 and output node N. O between.

[0080] The second stabilizing error canceller circuit 506 includes a sampling capacitor (e.g., a variable capacitor) C2 and multiple switches (e.g., transistor switches) SW. 21 SW 22 The sampling capacitor C2 has a capacitance value C SC The sampling capacitor C2 has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Switch SW 21 Controlled by the clock signal CK1”, and coupled to the first terminal of the sampling capacitor C2 and the input node N. I Between. Switch SW22 is controlled by clock signal CK2” and coupled to the first terminal of sampling capacitor C2 and output node N. O between.

[0081] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, resulting in a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... Figure 2 The clock signal of the waveform shown can be used by the sampling system 500. During the first stage P1 of the stabilization error elimination operation, switch SW... SE SW 11 It is turned on, and the SW switch is activated. 12 SW 21 SW 22 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 22 Turn on, and switch SW SE SW 11 SW 12 SW 21 It will be turned off. During the third phase P3 of the stabilization error elimination operation, switch SW... SE SW 21 It is turned on, and the SW switch is activated. 11 SW 12 SW 22 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 Turn on, and switch SW SE SW 11 SW 21 SW 22 closure.

[0082] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. In addition, the capacitance value C SC The stored information injected by the activated stability error eliminator circuit (i.e., one of the first and second stability error eliminator circuits) is properly configured to eliminate the stability error (1-k)*V. O (t0). Simply put, it can be determined based on the stability error to be eliminated: (1-k)*V O The capacitance value C is adjusted by the value of (t0). SC By this means, the elimination weight can be set appropriately. Size.

[0083] Figure 6This is a schematic diagram of a fourth sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 600 includes a sampler circuit 602 located on the main path, a first stable error elimination circuit (comprising multiple component circuits 604_1 and 604_2) located on a first eliminater path (labeled "Eliminator Path 1"), and a second stable error elimination circuit (comprising multiple component circuits 606_1 and 606_2) located on a second eliminater path (labeled "Eliminator Path 2"). Each of the sampler circuit 602, the first stable error elimination circuit, and the second stable error elimination circuit is coupled between an input port and an output port of the sampling system 600. In this embodiment, the sampling system 600 is a differential operation network; therefore, the input port has a positive input node N. IP and negative input node N IN The differential input port has an output port with a positive output node N. OP and negative output node N ON The differential output port receives a voltage input with a positive voltage signal V from the input port. IP (Driven by a LEQ / BUF) and negative voltage signal V IN The differential voltage input (driven by another LEQ / BUF) generates a voltage output with a positive voltage signal V from the output port. OP (which is provided to an ADC through a BUF) and negative voltage signal V ON (It provides a differential voltage output to another ADC through another BUF).

[0084] The sampler circuit 602 includes multiple sampling capacitors C P C N and multiple switches (e.g., transistor switches) SW P SW N Sampling capacitor C P It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C N It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C P and C N Having the same capacitance value C S Switch SW P Controlled by clock signal CK1 and coupled to sampling capacitor C P The first end and the positive input node N IP Between. Switch SW N Controlled by clock signal CK1 and coupled to sampling capacitor C N The first end and the negative input node NIN between.

[0085] The first stable error canceller circuit includes multiple sampling capacitors (e.g., variable capacitors) C 11 C 12 and multiple switches (e.g., transistor switches) SW 11 SW 12 SW 13 SW 14 SW 15 SW 16 The sampling capacitor C 11 and C 12 Having the same capacitance value C SC Sampling capacitor C 11 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 12 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Compared to the first stabilization error canceller circuit used in sampling system 100, the first stabilization error canceller circuit used in sampling system 600 requires less sampling capacitor.

[0086] Switch SW 11 From clock signal CK l 'Control, and coupled to the sampling capacitor C' 11 The first end and the positive input node N IP Between. Switch SW 12 From clock signal CK 2P 'Control, and coupled to the sampling capacitor C' 11 The first end and the positive output node N OP Between. Switch SW 13 From clock signal CK 2N 'Control, and coupled to the sampling capacitor C' 11 The first end and the negative input node N ON Between. Switch SW 14 Controlled by clock signal CK1' and coupled to sampling capacitor C 12 The first end and the negative input node N IN Between. Switch SW 15 From clock signal CK 2P 'Control, and coupled to the sampling capacitor C' 12 The first end and the negative output node N ON Between. Switch SW 16 From clock signal CK 2N 'Control, and coupled to the sampling capacitor C' 12 The first end and the positive output node N OPbetween.

[0087] The second stabilizing error canceller circuit includes multiple sampling capacitors (e.g., variable capacitors) C 21 C 22 and multiple switches (e.g., transistor switches) SW 21 SW 22 SW 23 SW 24 SW 25 SW 26 The sampling capacitor C 21 and C 22 Having the same capacitance value C SC Sampling capacitor C 21 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C 22 It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Compared to the second stabilization error canceller circuit used in sampling system 100, the second stabilization error canceller circuit used in sampling system 600 requires less sampling capacitor.

[0088] Switch SW 21 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 21 The first end and the positive input node N IP Between. Switch SW 22 From clock signal CK 2P "Control, and coupled to the sampling capacitor C" 21 The first end and the positive output node N OP Between. Switch SW 23 From clock signal CK 2N "Control, and coupled to the sampling capacitor C" 21 The first end and the negative input node N ON Between. Switch SW 24 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 22 The first end and the negative input node N IN Between. Switch SW 25 From clock signal CK 2P "Control, and coupled to the sampling capacitor C" 22 The first end and the negative output node N ON Between. Switch SW 26 From clock signal CK 2N "Control, and coupled to the sampling capacitor C" 22 The first end and the positive output node N OP between.

[0089] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, thereby generating a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... Figure 7 This is a waveform diagram of a clock signal used to control a switch in a sampling system 600 according to an embodiment of the present invention, wherein... Figure 7 The clock signal CK shown rank2 It is used to control the ADC.

[0090] When the stable error to be eliminated has negative polarity, it has Figure 7 The clock signal of the waveform shown in sub-diagram (A) can be used by sampling system 600. During the first stage P1 of the stabilization error elimination operation, switch SW P SW N SW 11 SW 14 It is turned on, and the SW switch is activated. 12 SW 13 SW 15 SW 16 SW 21 ~SW 26 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 22 SW 25 It is turned on, and the SW switch is activated. P SW N SW 11 ~SW 16 SW 21 SW 23 SW 24 SW 26 It is turned off. During the third stage P3 of the stabilization error elimination operation, switch SW is turned off. P SW N SW 21 SW 24 It is turned on, and the SW switch is activated. 22 SW 23 SW 25 SW 26 SW 11 ~SW 16 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 SW 15 It is turned on, and the SW switch is activated. P SW N SW 11 SW 13 SW 14 SW16 SW 21 ~SW 26 It has been shut down.

[0091] In another case where the stable error to be eliminated has a positive polarity, it has Figure 7 The clock signal of the waveform shown in sub-diagram (B) can be used by sampling system 600. During the first stage P1 of the stabilization error elimination operation, switch SW P SW N SW 11 SW 14 It is turned on, and the SW switch is activated. 12 SW 13 SW 15 SW 16 SW 21 ~SW 26 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 23 SW 26 Turn on, and switch SW P SW N SW 11 ~SW 16 SW 21 SW 22 SW 24 SW 25 Closed. During the third stage P3 of the stabilization error elimination operation, switch SW... P SW N SW 21 SW 24 It is turned on, and the SW switch is activated. 22 SW 23 SW 25 SW 26 SW 11 ~SW 16 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 13 SW 16 It is turned on, and the SW switch is activated. P SW N SW 11 SW 12 SW 14 SW 15 SW 21 ~SW 26 It has been shut down.

[0092] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The polarity of the stability error elimination depends on the switch selection. The sampler circuit 602 on the main path suffers a stability error of negative polarity (1-k)*V. O Under the influence of (t0), the switch (SW) 12 ,SW 15 ) and (SW 22 ,SW 25 This will be selected to eliminate the stability error (1-k)*V O (t0). The sampler circuit 602 on the main path suffers a stable error (1-k)*V with positive polarity. O In another case of the effect of (t0), the switch (SW) 13 ,SW 16 ) and (SW 23 ,SW 26 This will be selected to eliminate the stability error (1-k)*V O (t0). Additionally, the capacitance value C SC The stored information injected by the activated stability error eliminator circuit (i.e., one of the first and second stability error eliminator circuits) is properly configured to eliminate the stability error (1-k)*V. O (t0). Simply put, due to the stability error of sampling circuit 602 (1-k)*V O The polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The capacitance value C is adjusted by the value of (t0). SC By this means, the elimination weight can be set appropriately. Size.

[0093] Figure 8This is a schematic diagram of a fifth sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 800 includes a sampler circuit 802 located on the main path, a first stable error elimination circuit 804 located on a first eliminater path (labeled "Eliminator Path 1"), a second stable error elimination circuit 806 located on a second eliminater path (labeled "Eliminator Path 2"), and a negative unity-gain amplifier 808. Each of the sampler circuit 802, the first stable error elimination circuit 804, and the second stable error elimination circuit 806 is coupled between an input port and an output port of the sampling system 800. In this embodiment, the sampling system 800 is a single-ended computation network; therefore, the input port has a single input node N. I A single-ended input port, and an output port with a single output node N. O The single-ended output port receives a voltage input with a single voltage signal V from the input port. I A single-ended voltage input (driven by a LEQ / BUF) generates a voltage output with a single voltage signal V from the output port. O (It provides a single-ended voltage output to an ADC via a BUF).

[0094] The negative unity-gain amplifier 808 has amplifier input node A I and amplifier output node A O Where amplifier input node A I Coupled to input node N I The sampler circuit 802 includes a sampling capacitor C. SE and switches (e.g., transistor switches) SW SE Sampling capacitor C SE It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C SE With capacitance value C S Switch SW SE Controlled by clock signal CK1 and coupled to sampling capacitor C SE The first end and the input node N I between.

[0095] The first stabilizing error canceller circuit 804 includes a sampling capacitor (e.g., a variable capacitor) C1 and multiple switches (e.g., transistor switches) SW. 11 SW 12 SW 13 The sampling capacitor C1 has a capacitance value C SC The sampling capacitor C1 has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Switch SW 11From clock signal CK 1P 'Control, and coupled to the first terminal of the sampling capacitor C1 and the input node N' I Between. Switch SW 12 From clock signal CK 1N 'Control, and coupled to the first terminal of the sampling capacitor C1 and the amplifier output node A' O Between. Switch SW 13 Controlled by clock signal CK2', and coupled to the first terminal of sampling capacitor C1 and output node N O between.

[0096] The second stabilizing error canceller circuit 806 includes a sampling capacitor (e.g., a variable capacitor) C2 and multiple switches (e.g., transistor switches) SW. 21 SW 22 SW 23 The sampling capacitor C2 has a capacitance value C SC The sampling capacitor C2 has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Switch SW 21 From clock signal CK 1P "Control, and coupled to the first terminal of the sampling capacitor C2 and the input node N." I Between. Switch SW 22 From clock signal CK 1N "Control, and coupled to the first terminal of the sampling capacitor C2 and the amplifier output node A." O Between. Switch SW 23 Controlled by the clock signal CK2”, and coupled to the first terminal of the sampling capacitor C2 and the output node N O between.

[0097] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, thereby generating a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... Figure 9 This is a waveform diagram of a clock signal used to control a switch in a sampling system 800 according to an embodiment of the present invention, wherein... Figure 9 The clock signal CK shown rank2 It is used to control the ADC.

[0098] When the stable error to be eliminated has negative polarity, it has Figure 9 The clock signal of the waveform shown in sub-diagram (A) can be used by sampling system 800. During the first stage P1 of the stabilization error elimination operation, switch SW SE SW 11 Turn on, and switch SW12 SW 13 SW 21 ~SW 23 Closed. During the second phase P2 of the error elimination operation, switch SW is turned off. 23 Turn on, and switch SW SE SW 11 ~SW 13 SW 21 SW 22 Closed. During the third stage P3 of the stabilization error elimination operation, switch SW... SE SW 21 It is turned on, and the SW switch is activated. 11 ~SW 13 SW 22 SW 23 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 13 Turn on, and switch SW SE SW 21 ~SW 23 SW 11 SW 12 closure.

[0099] In another case where the stable error to be eliminated has a positive polarity, it has the following characteristics: Figure 9 The clock signal of the waveform shown in sub-diagram (B) can be used by sampling system 800. During the first stage P1 of the stabilization error elimination operation, switch SW SE SW 12 It will turn on, and the switch SW will be activated. 11 SW 13 SW 21 ~SW 23 It will be turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 23 Turn on, and switch SW SE SW 11 ~SW 13 SW 21 SW 22 Closed. During the third stage P3 of the stabilization error elimination operation, switch SW... SE SW 22 It is turned on, and the SW switch is activated. 21 SW 23 SW 11 ~SW 13 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 13 Turn on, and switch SW SE SW 11 SW 12SW 21 ~SW 23 closure.

[0100] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The polarity of the stability error elimination depends on whether the amplifier output of the negative unity-gain amplifier 808 is used (i.e., -V). I The sampler circuit 802 on the main path suffers a stable error (1-k)*V with negative polarity. O Under the influence of (t0), switch SW 11 SW 21 It will be used during the sampling phase. The sampler circuit 802 on the main path suffers a stable error of positive polarity (1-k)*V. O In another case of the effect of (t0), switch SW 12 SW 22 It will be used during the sampling phase. Additionally, the capacitance value C... SC The stored information injected by the activated stability error eliminator circuit (i.e., one of the first and second stability error eliminator circuits) is properly configured to eliminate the stability error (1-k)*V. O (t0). Simply put, due to the stability error of the 802 sampling circuit (1-k)*V O The polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The capacitance value C is adjusted by the value of (t0). SC By this means, the elimination weight can be set appropriately. Size.

[0101] Figure 10 This is a schematic diagram of a sixth sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 1000 includes a sampler circuit 1002 located on the main path, a first stable error eliminater circuit 1004 located on a first eliminater path (labeled "Eliminator Path 1"), and a second stable error eliminater circuit 1006 located on a second eliminater path (labeled "Eliminator Path 2"). Each of the sampler circuit 1002, the first stable error eliminater circuit 1004, and the second stable error eliminater circuit 1006 is coupled between an input port and an output port of the sampling system 1000. The sampling system 1000 is a differential operation network; therefore, the input port has a positive input node N.IP and negative input node N IN The differential input port has an output port with a positive output node N. OP and negative output node N ON The differential output port receives a voltage input with a positive voltage signal V from the input port. IP (It is driven by a LEQ / BUF) and a negative voltage signal V IN The differential voltage input (driven by another LEQ / BUF) generates a voltage output with a positive voltage signal V from the output port. OP (which is provided to an ADC through a BUF) and negative voltage signal V ON (It provides a differential voltage output to another ADC through another BUF).

[0102] Sampler circuit 1002 includes multiple sampling capacitors C P C N and multiple switches (e.g., transistor switches) SW P SW N Sampling capacitor C P It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C N It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C P and C N Having the same capacitance value C S Switch SW P Controlled by clock signal CK1 and coupled to sampling capacitor C P The first end and the positive input node N IP Between. Switch SW N Controlled by clock signal CK1 and coupled to sampling capacitor C N The first end and the negative input node N IN between.

[0103] The first stabilizing error canceller circuit 1004 includes a sampling capacitor (e.g., a variable capacitor) C1 and multiple switches (e.g., transistor switches) SW. 11 SW 12 SW 13 SW 14 SW 15 SW 16 The sampling capacitor C1 has a capacitance value C. SCIt has a first end (top plate) and a second end (bottom plate). Compared to the first stabilizing error canceller circuit used in the sampling system 600, the first stabilizing error canceller circuit used in the sampling system 1000 requires fewer sampling capacitors.

[0104] Switch SW 11 From clock signal CK l 'Control, and coupled to the first terminal of the sampling capacitor C1 and the positive input node N' IP Between. Switch SW 12 From clock signal CK 2P 'Control, and coupled to the first terminal of the sampling capacitor C1 and the positive output node N' OP Between. Switch SW 13 From clock signal CK 2N 'Control, and coupled to the first terminal of the sampling capacitor C1 and the negative input node N' ON Between. Switch SW 14 Controlled by clock signal CK1', and coupled to the second terminal of sampling capacitor C1 and negative input node N. IN Between. Switch SW 15 From clock signal CK 2P 'Control, and coupled to the second terminal of the sampling capacitor C1 and the negative output node N' ON Between. Switch SW 16 From clock signal CK 2N 'Control, and coupled to the second terminal of the sampling capacitor C1 and the positive output node N' OP between.

[0105] The second stabilizing error canceller circuit 1006 includes a sampling capacitor (e.g., a variable capacitor) C2 and multiple switches (e.g., transistor switches) SW. 21 SW 22 SW 23 SW 24 SW 25 SW 26 It has a capacitance value of C. SC The sampling capacitor C2 includes a first terminal (top plate) and a second terminal (bottom plate). Compared to the second stabilization error canceller circuit used in sampling system 600, the second stabilization error canceller circuit used in sampling system 1000 requires fewer sampling capacitors.

[0106] Switch SW 21 Controlled by the clock signal CK1”, and coupled to the first terminal of the sampling capacitor C2 and the negative input node N. IN Between. Switch SW 22 From clock signal CK 2P "Control, and coupled to the first terminal of the sampling capacitor C2 and the negative output node N." ONBetween. Switch SW 23 From clock signal CK 2N "Control, and coupled to the first terminal of the sampling capacitor C2 and the positive output node N." OP Between. Switch SW 24 Controlled by the clock signal CK1”, and coupled to the second terminal of the sampling capacitor C2 and the positive input node N. IP Between. Switch SW 25 From clock signal CK 2P "Control, and coupled to the second terminal of the sampling capacitor C2 and the positive output node N." OP Between. Switch SW 26 Subject to clock signal CK 2N "Control, and coupled to the second terminal of the sampling capacitor C2 and the negative output node N." ON between.

[0107] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, resulting in a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... When the stabilization error to be eliminated has a negative polarity, it has... Figure 7 The clock signal of the waveform shown in sub-diagram (A) can be used by sampling system 1000. During the first stage P1 of the stabilization error elimination operation, switch SW P SW N SW 11 SW 14 It is turned on, and the SW switch is activated. 12 SW 13 SW 15 SW 16 SW 21 ~SW 26 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 22 SW 25 It is turned on, and the SW switch is activated. P SW N SW 11 ~SW 16 SW 21 SW 23 SW 24 SW 26 It is turned off. During the third stage P3 of the stabilization error elimination operation, switch SW is turned off. P SW N SW 21 SW 24 It is turned on, and the SW switch is activated. 22 SW 23 SW25 SW 26 SW 11 ~SW 16 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 SW 15 It is turned on, and the SW switch is activated. P SW N SW 11 SW 13 SW 14 SW 16 SW 21 ~SW 26 It has been shut down.

[0108] In another case where the stable error to be eliminated has a positive polarity, it has the following characteristics: Figure 7 The clock signal of the waveform shown in sub-diagram (B) can be used by sampling system 1000. During the first stage P1 of the stabilization error elimination operation, switch SW P SW N SW 11 SW 14 It is turned on, and the SW switch is activated. 12 SW 13 SW 15 SW 16 SW 21 ~SW 26 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 23 SW 26 Turn on, and switch SW P SW N SW 11 ~SW 16 SW 21 SW 22 SW 24 SW 25 Closed. During the third stage P3 of the stabilization error elimination operation, switch SW... P SW N SW 21 SW 24 It is turned on, and the SW switch is activated. 22 SW 23 SW 25 SW 26 SW 11 ~SW 16 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 13 SW 16 It is turned on, and the SW switch is activated. P SWN SW 11 SW 12 SW 14 SW 15 SW 21 ~SW 26 It has been shut down.

[0109] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The polarity of the stability error elimination depends on the switch selection. The sampler circuit 1002 on the main path suffers a stability error (1-k)*V with negative polarity. O Under the influence of (t0), the switch (SW) 12 ,SW 15 ) and (SW 22 ,SW 25 The sampler circuit 1002 on the main path is selected for stabilization error elimination. It suffers a stabilization error (1-k)*V with positive polarity. O In another case of the effect of (t0), the switch (SW) 13 ,SW 16 ) and (SW 23 ,SW 26 This will be selected for stabilizing error elimination. Additionally, the capacitance value C... SC The system is properly configured to ensure that a portion of the stored information injected by the activated stability error canceller circuit (i.e., one of the first and second stability error canceller circuits) can eliminate the stability error. Simply put, due to the stability error (1-k)*V of the sampling circuit 1002... O The polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The capacitance value C is adjusted by the value of (t0). SC By this means, the elimination weight can be set appropriately. Size.

[0110] Figure 11This is a schematic diagram of a seventh sampling system with stable error elimination according to an embodiment of the present invention. The sampling system 1100 includes a sampler circuit 1102 located on the main path, a first stable error eliminater circuit 1104 located on a first eliminater path (labeled "Eliminator Path 1"), and a second stable error eliminater circuit 1106 located on a second eliminater path (labeled "Eliminator Path 2"). Each of the sampler circuit 1102, the first stable error eliminater circuit 1104, and the second stable error eliminater circuit 1106 is coupled between an input port and an output port of the sampling system 1100. The sampling system 1100 is a differential operation network; therefore, the input port has a positive input node N. IP and negative input node N IN The differential input port has an output port with a positive output node N. OP and negative output node N ON The differential output port receives a voltage input from the input port, which is a positive voltage signal V. IP (It is driven by a LEQ / BUF) and a negative voltage signal V IN The differential voltage input (driven by another LEQ / BUF) generates a voltage output with a positive voltage signal V from the output port. OP (which is provided to an ADC through a BUF) and negative voltage signal V ON (It provides a differential voltage output to another ADC through another BUF).

[0111] Sampler circuit 1102 includes multiple sampling capacitors C P C N and multiple switches (e.g., transistor switches) SW P SW N Sampling capacitor C P It has a first terminal (top plate) and a second terminal (bottom plate), wherein the second terminal is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C N It has a first end (top plate) and a second end (bottom plate), wherein the second end is coupled to a reference voltage (e.g., ground voltage GND). Sampling capacitor C P and C N Having the same capacitance value C S Switch SW P Controlled by clock signal CK1 and coupled to sampling capacitor C P The first end and the positive input node N IP Between. Switch SW N Controlled by clock signal CK1 and coupled to sampling capacitor C N The first end and the negative input node N IN between.

[0112] The first stabilizing error canceller circuit 1104 includes multiple sampling capacitors (e.g., variable capacitors) C 11 C 12 and multiple switches (e.g., transistor switches) SW 11 SW 12 SW 13 SW 14 SW 15 SW 16 SW 17 SW 18 The sampling capacitor C 11 The capacitance value is C SCP Sampling capacitor C 12 The capacitance value is C SCN (C SCN ≠C SCP Sampling capacitor C 11 and C 12 Each of them has a first end (top plate) and a second end (bottom plate). Compared to the first stabilizing error canceller circuit used in sampling system 100, the first stabilizing error canceller circuit used in sampling system 1100 requires less sampling capacitor.

[0113] Switch SW 11 From clock signal CK l 'Control, and coupled to the sampling capacitor C' 11 The first end and the positive input node N IP Between. Switch SW 12 Controlled by clock signal CK2' and coupled to sampling capacitor C 11 The first end and the positive output node N OP Between. Switch SW 13 Controlled by clock signal CK1' and coupled to sampling capacitor C 11 The second end and the negative input node N IN Between. Switch SW 14 Controlled by clock signal CK2' and coupled to sampling capacitor C 11 The second end and the negative output node N ON Between. Switch SW 15 Controlled by clock signal CK1' and coupled to sampling capacitor C 12 The first end and the positive input node N IP Between. Switch SW 16 Controlled by clock signal CK2' and coupled to sampling capacitor C 12 The first end and the negative output node N ON Between. Switch SW 17 Controlled by clock signal CK1' and coupled to sampling capacitor C 12The second end and the negative input node N IN Between. Switch SW 18 Controlled by clock signal CK2' and coupled to sampling capacitor C 12 The second end and the positive output node N OP between.

[0114] The second stabilizing error canceller circuit 1106 includes multiple sampling capacitors (e.g., variable capacitors) C 21 C 22 and multiple switches (e.g., transistor switches) SW 21 SW 22 SW 23 SW 24 SW 25 SW 26 SW 27 SW 28 The sampling capacitor C 21 The capacitance value is C SCP and sampling capacitor C 22 The capacitance value is C SCN (C SCN ≠C SCP Sampling capacitor C 21 and C 22 Each of them has a first end (top plate) and a second end (bottom plate). Compared to the second stabilization error canceller circuit used in sampling system 100, the second stabilization error canceller circuit used in sampling system 1100 requires less sampling capacitor.

[0115] Switch SW 21 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 21 The first end and the positive input node N IP Between. Switch SW 22 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 21 The first end and the positive output node N OP Between. Switch SW 23 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 21 The second end and the negative input node N IN Between. Switch SW 24 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 21 The second end and the negative output node N ON Between. Switch SW 25 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 22 The first end and the positive input node N IP Between. Switch SW 26Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 22 The first end and the negative output node N ON Between. Switch SW 27 Controlled by the clock signal CK1”, and coupled to the sampling capacitor C 22 The second end and the negative input node N IN Between. Switch SW 28 Controlled by the clock signal CK2”, and coupled to the sampling capacitor C 22 The second end and the positive output node N OP between.

[0116] As described above, the stabilization error elimination operation can be divided into four stages: P1, P2, P3, and P4. Specifically, stages P1, P2, P3, and P4 are activated sequentially and cyclically, resulting in a sequence of ... → P1 → P2 → P3 → P4 → P1 → P2 → P3 → P4 → ... Figure 2 The clock signal of the waveform shown can be used by the sampling system 1100. During the first stage P1 of the stabilization error elimination operation, switch SW... P SW N SW 11 SW 13 SW 15 SW 17 It is turned on, and the SW switch is activated. 12 SW 14 SW 16 SW 18 SW 21 ~SW 28 It is turned off. During the second phase P2 of the stabilization error elimination operation, switch SW... 22 SW 24 SW 26 SW 28 It is turned on, and the SW switch is activated. P SW N SW 11 ~SW 18 SW 21 SW 23 SW 25 SW 27 It is turned off. During the third stage P3 of the stabilization error elimination operation, switch SW is turned off. P SW N SW 21 SW 23 SW 25 SW 27 It is turned on, and the SW switch is activated. 22 SW 24 SW 26 SW28 SW 11 ~SW 18 It is turned off. During the fourth stage P4 of the stabilization error elimination operation, switch SW... 12 SW 14 SW 16 SW 18 It is turned on, and the SW switch is activated. P SW N SW 21 ~SW 28 SW 11 SW 13 SW 15 SW 17 It has been shut down.

[0117] Based on the stored information obtained in the previous stage P3 (or P1), stabilization error elimination can be achieved in stage P2 (or P4) through charge redistribution. Therefore, the percentage of stored information obtained in the previous sampling stage P3 (or P1) that should be applied to eliminate the stabilization error occurring in the current sampling stage P2 (or P4) depends on the elimination weight. The sampling circuit 1102 in the main path suffers a stable error (1-k)*V with negative polarity. O Under the influence of (t0), the capacitance value C can be adjusted. SCP Set to be greater than the capacitance value C SCN This leads to (C) SCP -C SCN )>0; In addition, the capacitance value C SCP C SCN The stored information injected by the activated stability error canceller circuit (i.e., one of the first and second stability error canceller circuits) is correctly configured to eliminate the stability error (1-k)*V. O (t0). The sampling circuit 1102 in the main path suffers a stable error (1-k)*V with positive polarity. O In another case where (t0) has an effect, the capacitance value C can be... SCP Set to less than the capacitance value C SCN This leads to (C) SCP -C SCN )<0; In addition, the capacitance value C SCP C SCN The stored information injected by the activated stability error canceller circuit (i.e., one of the first and second stability error canceller circuits) is correctly configured to eliminate the stability error (1-k)*V. O (t0). Simply put, due to the stability error (1-k)*V of the sampling circuit 1102... OThe polarity and magnitude of (t0) can be estimated through the online training process, and therefore can be determined based on the stability error (1-k)*V to be eliminated. O The polarity and magnitude of (t0) are used to adjust the capacitance value C. SCP and C SCN By this means, the elimination weight can be set appropriately. The polarity and magnitude.

[0118] Please note that compared to Figure 3 , Figure 5 , Figure 6 , Figure 8 and Figure 10 The embodiment shown, Figure 1 and Figure 11 The illustrated embodiment will be affected by eliminating the weighted numerator (C) SCP -C SCN It can be set to less than C. SC It has higher error elimination accuracy due to its numerical value.

[0119] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A sampling system, comprising: a sampler circuit coupled between an input port and an output port of the sampling system, wherein the sampler circuit comprises at least one sampling capacitor; a first stable error canceller circuit coupled between the input port and the output port of the sampling system, wherein the first stable error canceller circuit comprises at least one first sampling capacitor; and a second stable error canceller circuit coupled between the input port and the output port of the sampling system, wherein the second stable error canceller circuit comprises at least one second sampling capacitor; wherein during a first phase of a stable error cancellation operation, the sampler circuit is to sample a voltage input from the input port at the at least one sampling capacitor, the first stable error canceller circuit is to sample the voltage input from the input port at the at least one first sampling capacitor, and the second stable error canceller circuit is to hold its sampling result at the at least one second sampling capacitor; during a second phase of the stable error cancellation operation immediately after the first phase, the sampler circuit and the second stable error canceller circuit are to perform charge redistribution between the at least one sampling capacitor and the at least one second sampling capacitor, and the first stable error canceller circuit is to hold its sampling result at the at least one first sampling capacitor; during a third phase of the stable error cancellation operation immediately after the second phase, the sampler circuit is to sample the voltage input from the input port at the at least one sampling capacitor, the second stable error canceller circuit is to sample the voltage input from the input port at the at least one second sampling capacitor, and the first stable error canceller circuit is to hold its sampling result at the at least one first sampling capacitor; and during a fourth phase of the stable error cancellation operation immediately after the third phase, the sampler circuit and the first stable error canceller circuit are to perform charge redistribution between the at least one sampling capacitor and the at least one first sampling capacitor, and the second stable error canceller circuit is to hold its sampling result at the at least one second sampling capacitor.

2. The sampling system of claim 1, wherein the input port is a differential input port having a positive input node and a negative input node, the output port is a differential output port having a positive output node and a negative output node, and the voltage input is a differential voltage input having a positive voltage signal and a negative voltage signal.

3. The sampling system of claim 2, wherein the at least one first sampling capacitor comprises a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; and the first stable error canceller circuit comprises: the first capacitor having a first end and a second end, wherein the second end of the first capacitor is coupled to a reference voltage; the second capacitor having a first end and a second end, wherein the second end of the second capacitor is coupled to the reference voltage; the third capacitor has a first end and a second end, wherein the second end of the third capacitor is coupled to the reference voltage; the fourth capacitor has a first end and a second end, wherein the second end of the fourth capacitor is coupled to the reference voltage; a first switch coupled between the first end of the first capacitor and the positive input node; a second switch coupled between the first end of the first capacitor and the positive output node; a third switch coupled between the first end of the second capacitor and the positive input node; a fourth switch coupled between the first end of the second capacitor and the negative output node; a fifth switch coupled between the first end of the third capacitor and the negative input node; a sixth switch coupled between the first end of the third capacitor and the positive output node; a seventh switch coupled between the first end of the fourth capacitor and the negative input node; and an eighth switch coupled between the first end of the fourth capacitor and the negative output node.

4. The sampling system of claim 3, wherein during the first phase of the settling error cancellation operation, the first, third, fifth, and seventh switches are turned on, and the second, fourth, sixth, and eighth switches are turned off; during the second and third phases of the settling error cancellation operation, the first through eighth switches are all turned off; and during the fourth phase of the settling error cancellation operation, the first, third, fifth, and seventh switches are turned off, and the second, fourth, sixth, and eighth switches are turned on.

5. The sampling system of claim 2, wherein the at least one first sampling capacitor comprises a first capacitor and a second capacitor; and the first settling error canceller circuit comprises: the first capacitor has a first end and a second end, wherein the second end of the first capacitor is coupled to a reference voltage; the second capacitor has a first end and a second end, wherein the second end of the second capacitor is coupled to the reference voltage; a first switch coupled between the first end of the first capacitor and the positive input node; a second switch coupled between the first end of the first capacitor and the positive output node; a third switch coupled between the first end of the first capacitor and the negative output node; a fourth switch coupled between the first end of the second capacitor and the negative input node; a fifth switch coupled between the first end of the second capacitor and the negative output node; and a sixth switch coupled between the first end of the second capacitor and the positive output node.

6. The sampling system of claim 5, wherein during the first phase of the settling error cancellation operation, the first switch and the fourth switch are turned on, and the second, third, fifth, and sixth switches are turned off; during the second and third phases of the settling error cancellation operation, the first through sixth switches are all turned off; and during the fourth phase of the settling error cancellation operation, the second switch and the fifth switch are turned on, and the first, third, fourth, and sixth switches are turned off. ​ ​ 7. The sampling system of claim 5, wherein during the first phase of the settling error cancellation operation, the first switch and the fourth switch are open, and the second, third, fifth, and sixth switches are closed; during the second and third phases of the settling error cancellation operation, the first through sixth switches are all closed; and during the fourth phase of the settling error cancellation operation, the third switch and the sixth switch are open, and the first, second, fourth, and fifth switches are closed.

8. The sampling system of claim 2, wherein the at least one first sampling capacitor comprises a capacitor; and the first settling error canceller circuit comprises: the capacitor having a first terminal and a second terminal; a first switch coupled between the first terminal of the capacitor and the positive input node; a second switch coupled between the first terminal of the capacitor and the positive output node; a third switch coupled between the second terminal of the capacitor and the negative input node; a fourth switch coupled between the second terminal of the capacitor and the negative output node; a fifth switch coupled between the first terminal of the capacitor and the negative output node; and a sixth switch coupled between the second terminal of the capacitor and the positive output node.

9. The sampling system of claim 8, wherein during the first phase of the settling error cancellation operation, the first switch and the fourth switch are open, and the second, third, fifth, and sixth switches are closed; during the second and third phases of the settling error cancellation operation, the first through sixth switches are all closed; and during the fourth phase of the settling error cancellation operation, the second switch and the fifth switch are open, and the first, third, fourth, and sixth switches are closed.

10. The sampling system of claim 8, wherein during the first phase of the settling error cancellation operation, the first switch and the fourth switch are open, and the second, third, fifth, and sixth switches are closed; during the second and third phases of the settling error cancellation operation, the first through sixth switches are all closed; and during the fourth phase of the settling error cancellation operation, the third switch and the sixth switch are open, and the first, second, fourth, and fifth switches are closed.

11. The sampling system of claim 2, wherein the at least one first sampling capacitor comprises a first capacitor and a second capacitor; and the first settling error canceller circuit comprises: the first capacitor having a first terminal and a second terminal; the second capacitor having a first terminal and a second terminal; a first switch coupled between the first terminal of the first capacitor and the positive input node; a second switch coupled between the first terminal of the first capacitor and the positive output node; a third switch coupled between the second terminal of the first capacitor and the negative input node; a fourth switch coupled between the second terminal of the first capacitor and the negative output node; a fifth switch coupled between the first terminal of the second capacitor and the positive input node; and a sixth switch coupled between the second terminal of the second capacitor and the positive output node. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a sixth switch coupled between the first terminal of the second capacitor and the negative output node; a seventh switch coupled between the second terminal of the second capacitor and the negative input node; and an eighth switch coupled between the second terminal of the second capacitor and the positive output node.

12. The sampling system of claim 11, wherein during the first phase of the settling error cancellation operation, the first, third, fifth, and seventh switches are turned on, and the second, fourth, sixth, and eighth switches are turned off; during the second and third phases of the settling error cancellation operation, the first through eighth switches are all turned off; and during the fourth phase of the settling error cancellation operation, the first, third, fifth, and seventh switches are turned off, and the second, fourth, sixth, and eighth switches are turned on.

13. The sampling system of claim 1, wherein the input port is a single-ended input port having a single input node, the output port is a single-ended output port having a single output node, and the voltage input is a single-ended voltage input having a single voltage signal.

14. The sampling system of claim 13, wherein the at least one first sampling capacitor comprises a first capacitor and a second capacitor; the sampling system further comprises a negative unity gain amplifier having an amplifier input node and an amplifier output node, wherein the amplifier input node is coupled to the single input node; and the first settling error cancellation circuit comprises: the first capacitor having a first terminal and a second terminal, wherein the second terminal of the first capacitor is coupled to a reference voltage; the second capacitor having a first terminal and a second terminal, wherein the second terminal of the second capacitor is coupled to the reference voltage; a first switch coupled between the first terminal of the first capacitor and the single input node; a second switch coupled between the first terminal of the first capacitor and the single output node; a third switch coupled between the first terminal of the second capacitor and the amplifier output node; a fourth switch coupled between the first terminal of the second capacitor and the single output node.

15. The sampling system of claim 14, wherein during the first phase of the settling error cancellation operation, the first switch is turned on, and the second through fourth switches are turned off; during the second and third phases of the settling error cancellation operation, the first through fourth switches are all turned off; and during the fourth phase of the settling error cancellation operation, the second switch is turned on, and the first, third, and fourth switches are turned off.

16. The sampling system of claim 14, wherein during the first phase of the settling error cancellation operation, the third switch is turned on, and the first, second, and fourth switches are turned off; during the second and third phases of the settling error cancellation operation, the first through fourth switches are all turned off; and during the fourth phase of the settling error cancellation operation, the fourth switch is turned on, and the first through third switches are turned off.

17. The sampling system of claim 13, wherein the at least one first sampling capacitor comprises a capacitor; and the first stable error canceller circuit comprises: the capacitor having a first terminal and a second terminal, wherein the second terminal of the capacitor is coupled to a reference voltage; a first switch coupled between the first terminal of the capacitor and the single input node; and a second switch coupled between the first terminal of the capacitor and the single output node.

18. The sampling system of claim 17, wherein during the first phase of the stable error cancellation operation, the first switch is turned on and the second switch is turned off; during the second and third phases of the stable error cancellation operation, the first and second switches are both turned off; and during the fourth phase of the stable error cancellation operation, the second switch is turned on and the first switch is turned off.

19. The sampling system of claim 13, wherein the at least one first sampling capacitor comprises a capacitor; the sampling system further comprises a negative unity gain amplifier having an amplifier input node and an amplifier output node, wherein the amplifier input node is coupled to the single input node; and the first stable error canceller circuit comprises: the capacitor having a first terminal and a second terminal, wherein the second terminal of the capacitor is coupled to a reference voltage; a first switch coupled between the first terminal of the capacitor and the single input node; a second switch coupled between the first terminal of the capacitor and the amplifier output node; and a third switch coupled between the first terminal of the capacitor and the single output node.

20. The sampling system of claim 19, wherein during the first phase of the stable error cancellation operation, the first switch is turned on and the second and third switches are turned off; during the second and third phases of the stable error cancellation operation, the first, second, and third switches are all turned off; and during the fourth phase of the stable error cancellation operation, the third switch is turned on and the first and second switches are turned off.

21. The sampling system of claim 19, wherein during the first phase of the stable error cancellation operation, the second switch is turned on and the first and third switches are turned off; during the second and third phases of the stable error cancellation operation, the first, second, and third switches are all turned off; and during the fourth phase of the stable error cancellation operation, the third switch is turned on and the first and second switches are turned off.

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