Analog-to-digital converter and implementation method thereof

Abstract

The invention discloses an analog-to-digital converter and an implementation method thereof, and relates to the technical field of analog-to-digital converters, the analog-to-digital converter comprises a complementary dynamic comparison module, a control module and a digital-to-analog conversion module; wherein the complementary dynamic comparison module comprises a complementary dynamic pre-amplification circuit, a first pre-amplification latch circuit, a second pre-amplification latch circuit and a pre-amplification reset switch circuit; the pre-amplification reset switch circuit, the first pre-amplification latch circuit and the second pre-amplification latch circuit are connected with the complementary dynamic pre-amplification circuit; the first pre-amplification latch circuit, the second pre-amplification latch circuit and the complementary dynamic pre-amplification circuit are connected with the control module; the digital-to-analog conversion module is connected with the first pre-amplification latch circuit; and the digital-to-analog conversion module is connected with the second pre-amplification latch circuit.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital converter technology, and in particular to an analog-to-digital converter and its implementation method. Background Technology

[0002] To achieve high speed, low-precision SAR ADCs typically use relatively small values ​​for the DAC capacitor. Therefore, the backlash during comparisons in the comparator module leads to significant changes in the input common-mode voltage within the comparator module. Furthermore, loop-expanded SAR ADCs use multiple comparator modules; each comparison lowers the input common-mode voltage, resulting in cumulative drops and ultimately significant variations. After the SAR is operating normally, the input common-mode voltage of the comparator module differs considerably from that during normal operation. Since the offset voltage of the comparator module is related to its input common-mode voltage, these variations cause the offset value obtained during offset calibration to differ from the actual offset value during comparator operation, thus affecting the accuracy of the comparator offset calibration. Therefore, these are technical problems that still need to be addressed in this field. Summary of the Invention

[0003] In view of this, embodiments of this application provide an analog-to-digital converter and its implementation method to improve the calibration accuracy of a loop-deployed SAR ADC.

[0004] One aspect of this application provides an analog-to-digital converter, including:

[0005] The system includes a complementary dynamic comparison module, a control module, and a digital-to-analog conversion module; wherein the complementary dynamic comparison module includes a complementary dynamic pre-amplification circuit, a first pre-amplification latch circuit, a second pre-amplification latch circuit, and a pre-amplification reset switch circuit.

[0006] The pre-amplification reset switch circuit, the first pre-amplification latch circuit, and the second pre-amplification latch circuit are connected to the complementary dynamic pre-amplification circuit; the first pre-amplification latch circuit, the second pre-amplification latch circuit, and the complementary dynamic pre-amplification circuit are connected to the control module; the digital-to-analog conversion module is connected to the first pre-amplification latch circuit; and the digital-to-analog conversion module is connected to the second pre-amplification latch circuit.

[0007] In some embodiments, the complementary dynamic preamplifier circuit includes:

[0008] A first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the gate of the first NMOS transistor is connected to a first input terminal; the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor; the gate of the second NMOS transistor is connected to a second input terminal; the gate of the second NMOS transistor is connected to the gate of the second PMOS transistor; the source of the first NMOS transistor, the source of the second NMOS transistor, and the drain of the third NMOS transistor are connected; the gate of the third NMOS transistor is connected to the control module; the source of the third NMOS transistor is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the drain of the first NMOS transistor is connected to a first output terminal; the drain of the second NMOS transistor is connected to a second output terminal; the source of the first PMOS transistor, the source of the second PMOS transistor, and the drain of the third PMOS transistor are connected; the gate of the third PMOS transistor is connected to the control module; the source of the third PMOS transistor is connected to a power supply.

[0009] In some embodiments, the first pre-amplified latch circuit includes:

[0010] The fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor;

[0011] The gate of the fourth PMOS transistor is connected to the second output terminal; the gate of the fifth PMOS transistor is connected to the first output terminal; the drain of the fourth PMOS transistor and the drain of the eighth NMOS transistor are connected to the source of the sixth PMOS transistor; the drain of the fifth PMOS transistor and the drain of the ninth NMOS transistor are connected to the source of the seventh PMOS transistor; the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected to the drain of the eighth PMOS transistor; the gate of the eighth PMOS transistor is connected to the control module; the source of the eighth PMOS transistor is connected to the power supply.

[0012] The gate of the sixth PMOS transistor, the drain of the seventh PMOS transistor, the gate of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the drain of the sixth NMOS transistor are connected; the gate of the seventh PMOS transistor, the drain of the sixth PMOS transistor, the gate of the fifth NMOS transistor, the drain of the fourth NMOS transistor, and the drain of the seventh NMOS transistor are connected.

[0013] The gate of the sixth NMOS transistor is connected to the gate of the eighth NMOS transistor; the gate of the sixth NMOS transistor is connected to the control module; the gate of the seventh NMOS transistor is connected to the gate of the ninth NMOS transistor; the gate of the seventh NMOS transistor is connected to the control module.

[0014] The sources of the fourth, fifth, sixth, seventh, eighth, and ninth NMOS transistors are all grounded.

[0015] In some embodiments, the second pre-amplified latch circuit includes:

[0016] Ninth PMOS transistor, tenth PMOS transistor, eleventh PMOS transistor, twelfth PMOS transistor, thirteenth PMOS transistor, fourteenth PMOS transistor, tenth NMOS transistor, eleventh NMOS transistor, twelfth NMOS transistor, thirteenth NMOS transistor, and fourteenth NMOS transistor;

[0017] The sources of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, and the fourteenth PMOS transistor are all grounded.

[0018] The gate of the tenth NMOS transistor is connected to the second output terminal; the gate of the eleventh NMOS transistor is connected to the first output terminal.

[0019] The drain of the tenth NMOS transistor, the source of the twelfth NMOS transistor, and the drain of the thirteenth PMOS transistor are connected; the drain of the eleventh NMOS transistor, the source of the thirteenth NMOS transistor, and the drain of the fourteenth PMOS transistor are connected.

[0020] The source of the tenth NMOS transistor, the source of the eleventh NMOS transistor, and the drain of the fourteenth NMOS transistor are connected; the gate of the fourteenth NMOS transistor is connected to the control module; the source of the fourteenth NMOS transistor is grounded.

[0021] The gate of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor, the gate of the ninth PMOS transistor, the drain of the tenth PMOS transistor, and the drain of the twelfth PMOS transistor are connected.

[0022] The gate of the thirteenth NMOS transistor, the drain of the twelfth NMOS transistor, the gate of the tenth PMOS transistor, the drain of the ninth PMOS transistor, and the drain of the eleventh PMOS transistor are connected.

[0023] The gate of the eleventh PMOS transistor is connected to the gate of the thirteenth PMOS transistor; the gate of the eleventh PMOS transistor is connected to the control module; the gate of the twelfth PMOS transistor is connected to the gate of the fourteenth PMOS transistor; and the gate of the twelfth PMOS transistor is connected to the control module.

[0024] In some embodiments, the pre-amplified reset switch circuit includes:

[0025] A fifteenth PMOS transistor, a sixteenth PMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor; the gates of the fifteenth PMOS transistor and the sixteenth PMOS transistor are connected to the digital-to-analog converter module; the gates of the fifteenth NMOS transistor and the sixteenth NMOS transistor are connected to the digital-to-analog converter module; the sources of the fifteenth PMOS transistor and the sixteenth PMOS transistor are connected to a power supply; the drains of the sixteenth NMOS transistor and the sixteenth PMOS transistor are connected; the drain of the fifteenth PMOS transistor and the drain of the fifteenth NMOS transistor are connected; the drain of the sixteenth PMOS transistor is connected to the second output terminal; the drain of the fifteenth PMOS transistor is connected to the first output terminal; the sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor are both grounded.

[0026] In some embodiments, the digital-to-analog conversion module includes:

[0027] A first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; the capacitance value of the first capacitor is A, the capacitance value of the second capacitor is B, the capacitance value of the third capacitor is C, the capacitance value of the fourth capacitor is D, the capacitance value of the fifth capacitor is E, and the capacitance value of the sixth capacitor is F; the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor satisfy the following relationship: 2A=B, 2B=C, 2C=D, 2D=E, 2E=F.

[0028] In some embodiments, the capacitance value of the first capacitor is 1.2fF.

[0029] In some embodiments, the number of the first capacitors is eight.

[0030] In some embodiments, the number of the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are all four.

[0031] Another aspect of this application embodiment provides a method for implementing an analog-to-digital converter, the method comprising:

[0032] The first output voltage of the complementary dynamic preamplifier circuit is reset to VDD by the preamplifier reset switch circuit, and after the reset is completed, the control module is started to output a first clock signal and a second clock signal. The first clock signal is a control signal to control the dynamic complementary preamplifier to start comparison, and the second clock signal is a control signal to control the first preamplifier latch circuit or the second preamplifier latch circuit.

[0033] When the first clock signal is a high-level signal and the second clock signal is a low-level signal controlling the first pre-amplification latch circuit, the first pre-amplification latch circuit outputs a first comparison result, and the digital-to-analog converter module converts the first comparison result into the output signal of the analog-to-digital converter.

[0034] When the first clock signal is a low-level signal and the second clock signal is a high-level signal controlling the second pre-amplification latch circuit, the second pre-amplification latch circuit outputs a first comparison result, and the digital-to-analog converter module converts the first comparison result into the output signal of the analog-to-digital converter.

[0035] This application includes at least the following beneficial effects:

[0036] This application can alternately use complementary dynamic pre-amplified NMOS and PMOS terminals and their corresponding first pre-amplified latch circuit and second pre-amplified latch circuit to cancel out the backlash generated by the two, eliminate the common-mode voltage change caused by each comparison, so that the comparator input common-mode voltage is approximately equal to that during calibration and operation, thereby improving calibration accuracy. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of an analog-to-digital converter provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the complementary dynamic comparison module of the analog-to-digital converter provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the logic signals of the analog-to-digital converter during operation, provided in an embodiment of this application.

[0041] Figure 4 A flowchart illustrating the implementation method of the analog-to-digital converter provided in this application embodiment;

[0042] Figure 5 This is a schematic diagram of the digital-to-analog conversion module of the analog-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] Reference Figure 1 as well as Figure 2 This application provides an analog-to-digital converter. The converter may include: a complementary dynamic comparison module 1, a control module 2, and a digital-to-analog conversion module 3; wherein, the complementary dynamic comparison module 1 includes a complementary dynamic pre-amplification circuit 11, a first pre-amplification latch circuit 12, a second pre-amplification latch circuit 13, and a pre-amplification reset switch circuit 14.

[0045] The pre-amplification reset switch circuit 14, the first pre-amplification latch circuit 12, and the second pre-amplification latch circuit 13 are connected to the complementary dynamic pre-amplification circuit 11; the first pre-amplification latch circuit 12, the second pre-amplification latch circuit 13, and the complementary dynamic pre-amplification circuit 11 are connected to the control module 2; the N terminal of the digital-to-analog converter module 3 is connected to the first pre-amplification latch circuit 12; and the P terminal of the digital-to-analog converter module 3 is connected to the second pre-amplification latch circuit 13.

[0046] In some embodiments, the complementary dynamic pre-amplifier circuit 11 includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M5, a first PMOS transistor M3, a second PMOS transistor M4, and a third PMOS transistor M6; the gate of the first NMOS transistor M1 is connected to the first input terminal Vip; the gate of the first NMOS transistor M1 is connected to the gate of the first PMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the second input terminal Vin; the gate of the second NMOS transistor M2 is connected to the gate of the second PMOS transistor M4; the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are connected to the drain of the third NMOS transistor M5; the third NMOS transistor M5... The gate of the third NMOS transistor M5 is connected to the output signal Clk_preamp of the control module 2; the source of the third NMOS transistor M5 is grounded; the drain of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M3; the drain of the second NMOS transistor M2 is connected to the drain of the second PMOS transistor M4; the drain of the first NMOS transistor M1 is connected to the first output terminal Dn; the drain of the second NMOS transistor M2 is connected to the second output terminal Dp; the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are connected to the drain of the third PMOS transistor M6; the gate of the third PMOS transistor M6 is connected to the output signal Clk_preamp of the control module 2; and the source of the third PMOS transistor M6 is connected to the power supply.

[0047] In some embodiments, the first pre-amplification latch circuit 12 includes: a fourth PMOS transistor M7, a fifth PMOS transistor M8, a sixth PMOS transistor M9, a seventh PMOS transistor M10, an eighth PMOS transistor M13, a fourth NMOS transistor M11, a fifth NMOS transistor M12, a sixth NMOS transistor M15, a seventh NMOS transistor M17, an eighth NMOS transistor M14, and a ninth NMOS transistor M16.

[0048] The gate of the fourth PMOS transistor M7 is connected to the second output terminal Dp; the gate of the fifth PMOS transistor M8 is connected to the first output terminal Dn; the drain of the fourth PMOS transistor M7 and the drain of the eighth NMOS transistor M14 are connected to the source of the sixth PMOS transistor M9; the drain of the fifth PMOS transistor M8 and the drain of the ninth NMOS transistor M16 are connected to the source of the seventh PMOS transistor M10; the source of the fourth PMOS transistor M7 and the source of the fifth PMOS transistor M8 are connected to the drain of the eighth PMOS transistor M13; the gate of the eighth PMOS transistor M13 is connected to the control module 2; the source of the eighth PMOS transistor M13 is connected to the power supply.

[0049] The gate of the sixth PMOS transistor M9, the drain of the seventh PMOS transistor M10, the gate of the fourth NMOS transistor M11, the drain of the fifth NMOS transistor M12, and the drain of the sixth NMOS transistor M15 are connected; the gate of the seventh PMOS transistor M10, the drain of the sixth PMOS transistor M9, the gate of the fifth NMOS transistor M12, the drain of the fourth NMOS transistor M11, and the drain of the seventh NMOS transistor M17 are connected.

[0050] The gate of the sixth NMOS transistor M15 is connected to the gate of the eighth NMOS transistor M14; the gate of the sixth NMOS transistor M15 is connected to the output signal Clk_latchn of the control module 2; the gate of the seventh NMOS transistor M17 is connected to the gate of the ninth NMOS transistor M16; the gate of the seventh NMOS transistor M17 is connected to the output signal Clk_latchn of the control module 2.

[0051] The sources of the fourth NMOS transistor M11, the fifth NMOS transistor M12, the sixth NMOS transistor M15, the seventh NMOS transistor M17, the eighth NMOS transistor M14, and the ninth NMOS transistor M16 are all grounded.

[0052] In some embodiments, the second pre-amplification latch circuit 13 includes: a ninth PMOS transistor M23, a tenth PMOS transistor M24, an eleventh PMOS transistor M27, a twelfth PMOS transistor M25, a thirteenth PMOS transistor M28, a fourteenth PMOS transistor M26, a tenth NMOS transistor M18, an eleventh NMOS transistor M19, a twelfth NMOS transistor M22, a thirteenth NMOS transistor M21, and a fourteenth NMOS transistor M29.

[0053] The sources of the ninth PMOS transistor M23, the tenth PMOS transistor M24, the eleventh PMOS transistor M27, the twelfth PMOS transistor M25, the thirteenth PMOS transistor M28, and the fourteenth PMOS transistor M26 are all grounded.

[0054] The gate of the tenth NMOS transistor M18 is connected to the second output terminal Dp; the gate of the eleventh NMOS transistor M19 is connected to the first output terminal Dn.

[0055] The drain of the tenth NMOS transistor M18, the source of the twelfth NMOS transistor M22, and the drain of the thirteenth PMOS transistor M28 are connected; the drain of the eleventh NMOS transistor M19, the source of the thirteenth NMOS transistor M21, and the drain of the fourteenth PMOS transistor M26 are connected.

[0056] The source of the tenth NMOS transistor M18 and the source of the eleventh NMOS transistor M19 are connected to the drain of the fourteenth NMOS transistor M29; the gate of the fourteenth NMOS transistor M29 is connected to the control module 2; the source of the fourteenth NMOS transistor M29 is grounded.

[0057] The gate of the twelfth NMOS transistor M22, the drain of the thirteenth NMOS transistor M21, the gate of the ninth PMOS transistor M23, the drain of the tenth PMOS transistor M24, and the drain of the twelfth PMOS transistor M25 are connected.

[0058] The gate of the thirteenth NMOS transistor M21, the drain of the twelfth NMOS transistor M22, the gate of the tenth PMOS transistor M24, the drain of the ninth PMOS transistor M23, and the drain of the eleventh PMOS transistor M27 are connected.

[0059] The gate of the eleventh PMOS transistor M27 is connected to the gate of the thirteenth PMOS transistor M28; the gate of the eleventh PMOS transistor M27 is connected to the output signal Clk_latchp of control module 2; the gate of the twelfth PMOS transistor M25 is connected to the gate of the fourteenth PMOS transistor M26; the gate of the twelfth PMOS transistor M25 is connected to the output signal Clk_latchp of control module 2.

[0060] In some embodiments, the pre-amplification reset switch circuit 14 includes: a fifteenth PMOS transistor M32, a sixteenth PMOS transistor M33, a fifteenth NMOS transistor M30, and a sixteenth NMOS transistor M31; the gates of the fifteenth PMOS transistor M32 and the sixteenth PMOS transistor M33 are connected to the digital-to-analog converter module 3; the gates of the fifteenth NMOS transistor M30 and the sixteenth NMOS transistor M31 are connected to the digital-to-analog converter module 3.

[0061] The source of the fifteenth PMOS transistor M32 and the source of the sixteenth PMOS transistor M33 are connected to the power supply; the drain of the sixteenth NMOS transistor M31 is connected to the drain of the sixteenth PMOS transistor M33; the drain of the fifteenth PMOS transistor M32 is connected to the drain of the fifteenth NMOS transistor M30; the drain of the sixteenth PMOS transistor M33 is connected to the second output terminal Dp; the drain of the fifteenth PMOS transistor M32 is connected to the first output terminal Dn; the source of the fifteenth NMOS transistor M30 and the source of the sixteenth NMOS transistor M31 are both grounded.

[0062] In some embodiments, refer to Figure 5The digital-to-analog conversion module 3 includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The capacitance value of the first capacitor is A, the capacitance value of the second capacitor is B, the capacitance value of the third capacitor is C, the capacitance value of the fourth capacitor is D, the capacitance value of the fifth capacitor is E, and the capacitance value of the sixth capacitor is F. The capacitance values ​​of the first, second, third, fourth, and fifth capacitors satisfy the following relationships: 2A=B, 2B=C, 2C=D, 2D=E, 2E=F. Specifically, in the figure, the capacitance value of the first capacitor is Cu, the capacitance value of the second capacitor is 2Cu, the capacitance value of the third capacitor is 4Cu, the capacitance value of the fourth capacitor is 8Cu, the capacitance value of the fifth capacitor is 16Cu, and the capacitance value of the sixth capacitor is 32Cu, where Cu is a unit capacitance and its capacitance value is fixed.

[0063] In some embodiments, the capacitance value of the first capacitor is 1.2fF.

[0064] In some embodiments, the number of first capacitors is eight.

[0065] In some embodiments, the number of the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are all four.

[0066] In addition, refer to Figure 4 This application also provides a method for implementing an analog-to-digital converter. The implementation method may include steps S101 and S102, or S101 and S103.

[0067] S101. The first output voltage of the complementary dynamic preamplifier circuit is reset to VDD through the preamplifier reset switch circuit, and after the reset is completed, the control module is started to output the first clock signal and the second clock signal. The first clock signal is a control signal to control the dynamic complementary preamplifier to start comparison, and the second clock signal is a control signal to control the first preamplifier latch circuit or the second preamplifier latch circuit.

[0068] S102. When the first clock signal is a high-level signal and the second clock signal is a low-level signal controlling the first pre-amplification latch circuit, the first pre-amplification latch circuit outputs the first comparison result, and the digital-to-analog converter module converts the first comparison result into the output signal of the analog-to-digital converter.

[0069] S103. When the first clock signal is a low-level signal and the second clock signal is a high-level signal controlling the second pre-amplification latch circuit, the second pre-amplification latch circuit outputs the first comparison result, and the digital-to-analog converter module converts the first comparison result into the output signal of the analog-to-digital converter.

[0070] Specifically, firstly, the comparator can adopt the complementary dynamic amplifier design shown in Figure 1, with the preamplifier using a P-N complementary design, and two different types of latches connected after the preamplifier.

[0071] Then, taking the NMOS input terminal working first as an example, the working principle of this comparator will be explained:

[0072] Before the comparator starts working, the preamplifier output node is reset to VDD. When the comparator starts working, Clk_preamp is set high and Clk_latchn is set low. Dn and Dp begin to discharge, and the difference in discharge rate is determined by the difference between Vip and Vin. When Vgs of the input pair transistors M7 and M8 of the latch corresponding to the NMOS input preamplifier is greater than the threshold voltage, the latch begins to regenerate and obtain the comparison result. Then, rstn is used with an additional switch to discharge any possible residual charge, preparing for the PMOS input preamplifier to work. When the PMOS terminal is working, Clk_preamp is set low and Clk_latchp is set high. Dn and Dp begin to charge, and the difference in charging rate is determined by the difference between Vip and Vin. When Vgs of the input pair transistors M21 and M22 of the latch corresponding to the PMOS input preamplifier is greater than the threshold voltage, the latch begins to regenerate and obtain the comparison result.

[0073] The capacitor DAC in this embodiment is shown in Figure 5, with a unit capacitance value Cu of 1.2fF. This embodiment employs a split capacitor switching scheme to ensure a constant common-mode voltage. Specifically, each capacitor is split into two identical capacitors. During the reset phase, the two capacitor base plates are reset to 1 and 0 respectively. Taking the first switching as an example, if the comparator result is 1, the output voltage of the capacitor DAC needs to be reduced by 0.5 times the reference voltage. Therefore, the capacitor with a base plate of 1 at the P terminal is switched to 0, while the capacitor with a base plate voltage of 0 at the N terminal is switched to 1. At this time, the P terminal changes by -0.25 times the reference voltage, and the N terminal changes by +0.25 times the reference voltage. The common-mode voltage remains unchanged, while the differential-mode voltage decreases by 0.5 times the reference voltage. Subsequent comparisons follow the same pattern to complete successive approximations.

[0074] In this embodiment, the last two bits of the capacitor DAC have the same capacitance value, resulting in one bit of redundancy. This reduces the impact of DAC setup error and thus reduces DAC setup time, which is beneficial for high-speed design.

[0075] This embodiment uses loop-expanded SAR logic, employing eight asynchronously triggered comparators to complete the successive comparator operation. Each latch drives a 1-bit capacitor DAC. The eight comparators consist of four complementary dynamic preamplifiers, four N-type latches, and four P-type latches.

[0076] The timing diagram of the loop-expanded SAR logic is shown in Figure 3. Because the complementary dynamic preamplifier may have residual charge after operation, a reset is required after its completion. Therefore, the same preamplifier cannot be used continuously. A discontinuous triggering mode for the same preamplifier is designed. The specific triggering sequence is shown in Figure 3: N1, P2, N3, P4, N2, P3, N4, P1. Identical numerical labels indicate the use of the same complementary dynamic preamplifier. After the final comparison, calibration is triggered.

[0077] During calibration, a pair of calibration tubes are connected in parallel to the pre-amplified input tubes. Based on the calibration measurement results, the discrete charge pump is controlled to adjust the gate voltage of the calibration tubes to form negative feedback, thereby achieving accurate calibration of the comparator misalignment.

[0078] Reference Figure 1 , Figure 2 as well as Figure 3 The specific working process is as follows: Clk is triggered when the falling edge of Clks arrives. <1> Rising edge, En <7> Valid. The NMOS input of the first comparator is active, and the comparison result is obtained. Then, based on the comparison result, the most significant bit of the capacitor DAC is switched to update the comparator input voltage, completing one SAR cycle. Meanwhile, Valid <7> The signal is valid, and after a specific delay to ensure that the DAC is established, Clk is triggered. <2> Falling edge, En <6> Valid. The PMOS terminal of the second comparator is activated, and the comparison result is obtained. This process continues for a total of 8 SAR cycles, completing the analog-to-digital conversion. The triggering sequence of the 8 latches is shown below. Figure 3 The numbers are N1, P2, N3, P4, N2, P3, N4, and P1. If the numbers are the same, it means that the same complementary dynamic preamplifier is used.

[0079] When the NMOS terminal of the comparator is working, Figure 2 M5 and M13 are turned on, while M6 and M29 are turned off. Nodes Dp and Dn discharge according to the comparator input voltage. As the voltage of nodes Dp and Dn decreases, M7 and M8 are turned on in sequence, controlled by the comparator input voltage. At this time, the latch composed of M9-M12 begins to regenerate, and latchn_outn and latchn_outp will be pulled to 0 or 1 respectively.

[0080] When the PMOS terminal of the comparator is working, Figure 2 M6 and M29 are turned on, while M5 and M13 are turned off. Nodes Dp and Dn are charged according to the comparator input voltage. As the voltage of nodes Dp and Dn rises, M18 and M19 are turned on in sequence, controlled by the comparator input voltage. At this time, the latch composed of M21-M14 begins to regenerate, and latchp_outn and latchp_outp will be pulled to 0 or 1 respectively.

[0081] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0082] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the described functions and / or features may be integrated into a single physical system and / or software module, or one or more functions and / or features may be implemented in a separate physical system or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the system disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0083] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, system, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, system, or device). For the purposes of this specification, "computer-readable medium" can mean any system that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, system, or device.

[0084] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0086] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. An analog-to-digital converter, characterized by The analog-to-digital converter comprises: a complementary dynamic comparison module, a control module, and a digital-to-analog conversion module; wherein the complementary dynamic comparison module comprises a complementary dynamic preamplification circuit, a first preamplification latch circuit, a second preamplification latch circuit, and a preamplification reset switch circuit; the preamplification reset switch circuit, the first preamplification latch circuit, and the second preamplification latch circuit are connected with the complementary dynamic preamplification circuit; the first preamplification latch circuit, the second preamplification latch circuit, and the complementary dynamic preamplification circuit are connected with the control module; the digital-to-analog conversion module is connected with the first preamplification latch circuit; and the digital-to-analog conversion module is connected with the second preamplification latch circuit.

2. An analog-to-digital converter according to claim 1, characterized in that The complementary dynamic preamplification circuit comprises: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; a gate of the first NMOS transistor is connected with a first input end; a gate of the first NMOS transistor is connected with a gate of the first PMOS transistor; a gate of the second NMOS transistor is connected with a second input end; a gate of the second NMOS transistor is connected with a gate of the second PMOS transistor; a source of the first NMOS transistor, a source of the second NMOS transistor, and a drain of the third NMOS transistor are connected; a gate of the third NMOS transistor is connected with the control module; a source of the third NMOS transistor is grounded; a drain of the first NMOS transistor is connected with a drain of the first PMOS transistor; a drain of the second NMOS transistor is connected with a drain of the second PMOS transistor; the drain of the first NMOS transistor is connected with a first output end; the drain of the second NMOS transistor is connected with a second output end; a source of the first PMOS transistor, a source of the second PMOS transistor, and a drain of the third PMOS transistor are connected; a gate of the third PMOS transistor is connected with the control module; and a source of the third PMOS transistor is connected with a power supply.

3. An analog-to-digital converter according to claim 2, characterized in that The first preamplification latch circuit comprises: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; a gate of the fourth PMOS transistor is connected with the second output end; a gate of the fifth PMOS transistor is connected with the first output end; a drain of the fourth PMOS transistor, a drain of the eighth NMOS transistor, and a source of the sixth PMOS transistor are connected; a drain of the fifth PMOS transistor, a drain of the ninth NMOS transistor, and a source of the seventh PMOS transistor are connected; a source of the fourth PMOS transistor, a source of the fifth PMOS transistor, and a drain of the eighth PMOS transistor are connected; a gate of the eighth PMOS transistor is connected with the control module; and a source of the eighth PMOS transistor is connected with a power supply. The gate of the sixth PMOS tube, the drain of the seventh PMOS tube, the gate of the fourth NMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are connected; the gate of the seventh PMOS tube, the drain of the sixth PMOS tube, the gate of the fifth NMOS tube, the drain of the fourth NMOS tube and the drain of the seventh NMOS tube are connected; The gate of the sixth NMOS tube is connected with the gate of the eighth NMOS tube; the gate of the sixth NMOS tube is connected with the control module; the gate of the seventh NMOS tube is connected with the gate of the ninth NMOS tube; the gate of the seventh NMOS tube is connected with the control module; The source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube, the source of the seventh NMOS tube, the source of the eighth NMOS tube and the source of the ninth NMOS tube are grounded.

4. An analog-to-digital converter according to claim 2, wherein The second pre-amplification latch circuit comprises: a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube; The source of the ninth PMOS tube, the source of the tenth PMOS tube, the source of the eleventh PMOS tube, the source of the twelfth PMOS tube, the source of the thirteenth PMOS tube and the source of the fourteenth PMOS tube are grounded; The gate of the tenth NMOS tube is connected with the second output end; the gate of the eleventh NMOS tube is connected with the first output end; The drain of the tenth NMOS tube, the source of the twelfth NMOS tube and the drain of the thirteenth PMOS tube are connected; the drain of the eleventh NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth PMOS tube are connected; The source of the tenth NMOS tube, the source of the eleventh NMOS tube and the drain of the fourteenth NMOS tube are connected; the gate of the fourteenth NMOS tube is connected with the control module; the source of the fourteenth NMOS tube is grounded; The gate of the twelfth NMOS tube, the drain of the thirteenth NMOS tube, the gate of the ninth PMOS tube, the drain of the tenth PMOS tube and the drain of the twelfth PMOS tube are connected; The gate of the thirteenth NMOS tube, the drain of the twelfth NMOS tube, the gate of the tenth PMOS tube, the drain of the ninth PMOS tube and the drain of the eleventh PMOS tube are connected; The gate of the eleventh PMOS tube is connected with the gate of the thirteenth PMOS tube; the gate of the eleventh PMOS tube is connected with the control module; the gate of the twelfth PMOS tube is connected with the gate of the fourteenth PMOS tube; the gate of the twelfth PMOS tube is connected with the control module.

5. An analog-to-digital converter according to claim 2, wherein The pre-amplification reset switch circuit comprises: a fifteenth PMOS transistor, a sixteenth PMOS transistor, a fifteenth NMOS transistor and a sixteenth NMOS transistor; a gate of the fifteenth PMOS transistor and a gate of the sixteenth PMOS transistor are connected with the digital-to-analog conversion module; a gate of the fifteenth NMOS transistor and a gate of the sixteenth NMOS transistor are connected with the digital-to-analog conversion module; a source of the fifteenth PMOS transistor and a source of the sixteenth PMOS transistor are connected with a power supply; a drain of the sixteenth NMOS transistor is connected with a drain of the sixteenth PMOS transistor; a drain of the fifteenth PMOS transistor is connected with a drain of the fifteenth NMOS transistor; the drain of the sixteenth PMOS transistor is connected with the second output end; the drain of the fifteenth PMOS transistor is connected with the first output end; the source of the fifteenth NMOS transistor and the source of the sixteenth NMOS transistor are both grounded.

6. An analog-to-digital converter according to claim 1, wherein the digital-to-analog conversion module comprises: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; a capacitance value of the first capacitor is A, a capacitance value of the second capacitor is B, a capacitance value of the third capacitor is C, a capacitance value of the fourth capacitor is D, a capacitance value of the fifth capacitor is E, and a capacitance value of the sixth capacitor is F; the capacitance values between the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor satisfy the relationship: 2A=B, 2B=C, 2C=D, 2D=E and 2E=F.

7. An analog-to-digital converter according to any one of claims 6, characterized in that The capacitance value of the first capacitor is 1.2 fF.

8. An analog-to-digital converter according to any one of claims 6, characterized in that The number of the first capacitors is 8.

9. An analog-to-digital converter according to any one of claims 6, characterized in that, The number of the second capacitors, the third capacitors, the fourth capacitors, the fifth capacitors and the sixth capacitors is all 4.

10. An analog-to-digital converter implementation method, characterized by, The method comprises: resetting the first output voltage of the complementary dynamic preamplification circuit to VDD through a preamplification reset switch circuit, and starting the control module to output a first clock signal and a second clock signal after the resetting is completed, wherein the first clock signal is a control signal for controlling the dynamic complementary preamplifier to start comparison, and the second clock signal is a control signal for controlling the first preamplification latch circuit or the second preamplification latch circuit; when the first clock signal is a high-level signal and the second clock signal is a low-level signal for controlling the first preamplification latch circuit, the first preamplification latch circuit outputs a first comparison result, and the digital-to-analog conversion module converts the first comparison result into an output signal of the analog-to-digital converter; when the first clock signal is a low-level signal and the second clock signal is a high-level signal for controlling the second preamplification latch circuit, the second preamplification latch circuit outputs a first comparison result, and the digital-to-analog conversion module converts the first comparison result into an output signal of the analog-to-digital converter.

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