Antenna device

Abstract

An apparatus comprising: an antenna pin coupled to a pair of antenna inductors; and a first set of differential input-output pins coupled to the first pair of inductors. The first pair of inductors is configured to be magnetically coupled with the pair of antenna inductors for transmission of signaling. The apparatus additionally includes a functional switch including a second set of differential input-output pins coupled to a second pair of inductors. The functional switch includes a first switch between the second pair of inductors. The second pair of inductors is configured to be magnetically coupled with the pair of antenna inductors for receiving signaling. The functional switch includes a third set of differential input-output pins coupled to a third pair of inductors. The functional switch includes a second switch between the third pair of inductors. The third pair of inductors is configured to be magnetically coupled with the pair of antenna inductors for receiving signaling.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a device and in particular to a device configured to receive a signal for transmission from an input and provide the received signal to an output and capable of transmitting and receiving signaling or signals using the same pin. The present disclosure also relates to a device comprising a transmit / receive switch. BACKGROUND

[0002] Devices capable of transmitting and receiving signaling or signals using the same pin can be beneficial in a range of applications, for example in radar signaling, where a signal is transmitted and subsequently detected from a reflection from an object. In some examples, the device can transmit and receive ultra-wideband (UWB) signals, but any other suitable signaling bandwidth can also be used. SUMMARY

[0003] According to a first aspect of the present disclosure, there is provided a device, the device comprising:

[0004] an antenna pin for coupling to an antenna, the antenna pin coupled to at least a first antenna inductor in series with a second antenna inductor, wherein the second antenna inductor is further coupled to a first reference pin configured to provide a first reference voltage;

[0005] a first set of differential input-output pins comprising a first input-output pin and a second input-output pin, wherein the first input-output pin is coupled to a first inductor in series with a second inductor, and wherein the second inductor is further coupled to the second input-output pin, wherein the device further comprises a first power supply terminal coupled between the first inductor and the second inductor to receive a first power supply voltage, wherein

[0006] the first inductor is configured to be magnetically coupled with the first antenna inductor and the second inductor is configured to be magnetically coupled with the second antenna inductor for transmitting signaling received from the antenna at the first set of differential input-output pins when the antenna is coupled to the antenna pin; and

[0007] a function switch comprising:

[0008] a second set of differential input-output pins comprising a third input-output pin and a fourth input-output pin, wherein the third input-output pin is coupled to a third inductor in series with a fourth inductor, and wherein the fourth inductor is further coupled to the fourth input-output pin, and wherein the function switch comprises a first switch between the third inductor and the fourth inductor, wherein

[0009] The third inductor is configured to be magnetically coupled to the first antenna inductor, and the fourth inductor is configured to be magnetically coupled to the second antenna inductor, for providing signaling received from the antenna pins to the second set of differential input-output pins;

[0010] The third set of differential input-output pins includes a fifth input-output pin and a sixth input-output pin. The fifth input-output pin is coupled to a fifth inductor connected in series with the sixth inductor, and the sixth inductor is further coupled to the sixth input-output pin. The function switch includes a second switch between the fifth and sixth inductors.

[0011] The fifth inductor is configured to be magnetically coupled to the first antenna inductor, and the sixth inductor is configured to be magnetically coupled to the second antenna inductor, for providing signaling received from the antenna pins to the third set of differential input-output pins.

[0012] In one or more embodiments, the device includes a receiver amplifier arrangement. In one or more embodiments, the second set of differential input-output pins and the third set of differential input-output pins are configured to be connected to the receiver amplifier arrangement, which is configured to receive the signaling received from the antenna via the antenna pins. The receiver amplifier arrangement may include a first portion formed by at least one pair of PMOS transistors and a second portion formed by at least one pair of NMOS transistors.

[0013] In one or more embodiments,

[0014] The second set of differential input-output pins is connected to the first portion of the receiver amplifier arrangement; and in one or more embodiments,

[0015] The third set of differential input-output pins is connected to the second portion of the receiver amplifier arrangement.

[0016] In one or more embodiments,

[0017] The first switch is connected to a second power supply terminal, which is configured to receive a second power supply voltage, such that when the first switch is closed, the third inductor and the fourth inductor receive the second power supply voltage, and when the first switch is open, the third inductor is not connected to the fourth inductor; and in one or more embodiments,

[0018] The second switch is connected to a second reference terminal, which is configured to receive a second reference voltage such that when the second switch is closed, the fifth inductor and the sixth inductor receive the second reference voltage, and when the second switch is open, the fifth inductor is not connected to the sixth inductor.

[0019] In one or more embodiments, the device is configured to operate in a transmission mode and a reception mode, wherein:

[0020] When the device is in the transmission mode, the first switch and the second switch can be configured to be open, and the device can be configured to receive signaling for transmission from the first set of differential input-output pins; and

[0021] When the device is in the receive mode, the first switch and the second switch can be configured to be closed, and the device can be configured to provide signaling received via the antenna pins to the second set of differential input-output pins and the third set of differential input-output pins, such that the second set of differential input-output pins and the third set of differential input-output pins can be configured to provide the signaling as a differential signal to the receiver amplifier arrangement.

[0022] In one or more embodiments:

[0023] The first switch includes a plurality of transistors configured to provide an off or non-conducting state and a closed or on state for individually controlling the impedance between the third inductor and the fourth inductor; and in one or more embodiments,

[0024] The second switch includes a plurality of transistors configured to provide an open or non-conducting state and a closed or on state for individually controlling the impedance between the fifth inductor and the sixth inductor.

[0025] In one or more embodiments, the device is configured to operate in a fast stabilization mode, wherein when the device is in the fast stabilization mode:

[0026] While the device provides signaling to the antenna:

[0027] One or more of the plurality of transistors in the first switch can be configured to be off;

[0028] One or more of the plurality of transistors in the first switch can be configured to be closed;

[0029] One or more of the plurality of transistors in the second switch can be configured to be off; and

[0030] One or more of the plurality of transistors in the second switch can be configured to be closed.

[0031] In one or more embodiments, the device is configured to operate in a fast stabilization mode while the device receives signaling from the antenna:

[0032] All of the plurality of transistors in the first switch can be configured to be closed; and

[0033] All of the plurality of transistors in the second switch can be configured to be closed.

[0034] It should be understood that fast stabilization is a conceptual name for a pattern in which multiple transistors have the states described herein, which in some cases can resolve signal interruptions that occur more quickly during function switch switching, signaling to the receiver amplifier arrangement, and signaling received from the first set of differential input-output pins for transmission.

[0035] In one or more embodiments:

[0036] The first switch includes:

[0037] A plurality of first PMOS transistors are connected in series to form a chain, such that the source terminal of one first PMOS transistor in the chain is connected to the drain terminal of an adjacent first PMOS transistor.

[0038] The source terminal of the first first PMOS transistor in the chain can be connected to the third inductor, and the drain terminal of the last first PMOS transistor in the chain can be connected to the fourth inductor.

[0039] The gate terminal of each of the first PMOS transistors can be connected to the first terminal of a corresponding resistor, and the second terminal of the corresponding resistor can be connected to the first switch control terminal.

[0040] In one or more embodiments:

[0041] The first switch includes:

[0042] Multiple second PMOS transistors, among which

[0043] The source terminal of each second PMOS transistor can be connected to the second power supply terminal, and the drain terminal of each second PMOS transistor can be connected to the source terminal of a first PMOS transistor and the drain terminal of its adjacent first PMOS transistor, such that a second PMOS transistor can be connected between each pair of first PMOS transistors.

[0044] In one or more examples, the gate terminal of each second PMOS transistor may be connected to the first switch control terminal.

[0045] In one or more embodiments:

[0046] The second switch includes:

[0047] A plurality of first NMOS transistors are connected in series to form a chain, such that the source terminal of one first NMOS transistor can be connected to the drain terminal of an adjacent first NMOS transistor.

[0048] The source terminal of the first first NMOS transistor in the chain can be connected to the fifth inductor, and the drain terminal of the last first NMOS transistor in the chain can be connected to the sixth inductor.

[0049] The gate terminal of each of the first PMOS transistors in the first NMOS transistors can be connected to the first terminal of a corresponding resistor, and the second terminal of the corresponding resistor can be connected to the second switch control terminal.

[0050] In one or more embodiments:

[0051] The second switch includes:

[0052] Multiple second NMOS transistors, among which

[0053] The source terminal of each second NMOS transistor can be connected to the second reference terminal, and the drain terminal of each second NMOS transistor can be connected to the source terminal of a first NMOS transistor and the drain terminal of its adjacent first NMOS transistor, such that a second NMOS transistor can be connected between each pair of first NMOS transistors.

[0054] In one or more examples, the gate terminal of each second NMOS transistor can be connected to the second switch control terminal.

[0055] In one or more embodiments:

[0056] When the device is in the transmission mode, the first switch is turned off, such that one or more signals provided to the first switch control terminal are configured to disable the plurality of first PMOS transistors and the plurality of second PMOS transistors, and the second switch is turned off, such that one or more signals provided to the second switch control terminal are configured to disable the plurality of first NMOS transistors and the plurality of second NMOS transistors.

[0057] In one or more embodiments:

[0058] When the device is in the receiving mode, the first switch is closed such that one or more signals provided to the first switch control terminal are configured to turn on the plurality of first PMOS transistors and the plurality of second PMOS transistors, and the second switch is closed such that one or more signals provided to the second switch control terminal are configured to turn on the plurality of first NMOS transistors and the plurality of second NMOS transistors.

[0059] In one or more embodiments:

[0060] The plurality of first PMOS transistors may include three first PMOS transistors;

[0061] The plurality of second PMOS transistors may include two second PMOS transistors;

[0062] The plurality of first NMOS transistors may include three first NMOS transistors; and

[0063] The plurality of second NMOS transistors may include two second NMOS transistors.

[0064] In one or more embodiments:

[0065] The first switch includes:

[0066] A plurality of first PMOS transistors are connected in series to form a chain, such that the source terminal of one first PMOS transistor can be connected to the drain terminal of the adjacent first PMOS transistor.

[0067] The source terminal of the first first PMOS transistor in the plurality of first PMOS transistors may be connected to the third inductor, and the drain terminal of the last first PMOS transistor in the chain may be connected to the fourth inductor.

[0068] The gate terminals of the first and last first PMOS transistors in the chain can be connected to the first terminal of a corresponding resistor, and the second terminal of the corresponding resistor can be connected to a first switch control terminal, and the gate terminal of each other first PMOS transistor can be connected to a first switch blanking control terminal.

[0069] In one or more embodiments:

[0070] The first switch includes:

[0071] Multiple second PMOS transistors, among which

[0072] The source terminal of each second PMOS transistor can be connected to the second power supply terminal, and the drain terminal of each second PMOS transistor can be connected to the source terminal of a first PMOS transistor and the drain terminal of its adjacent first PMOS transistor, such that a second PMOS transistor can be connected between each pair of first PMOS transistors.

[0073] In one or more examples, the gate of each second PMOS transistor may be connected to the first switch blanking control terminal.

[0074] In one or more embodiments:

[0075] The second switch includes:

[0076] A plurality of first NMOS transistors are connected in series to form a chain, such that the source terminal of one first NMOS transistor can be connected to the drain terminal of an adjacent series-connected NMOS transistor.

[0077] The source terminal of the first first NMOS transistor in the plurality of first NMOS transistors may be connected to the fifth inductor, and the drain terminal of the last first NMOS transistor in the chain may be connected to the sixth inductor.

[0078] The gate terminals of the first and last first NMOS transistors in the chain can be connected to the first terminal of a corresponding resistor, and the second terminal of the corresponding resistor can be connected to a second switch control terminal, and the gate terminal of each other first NMOS transistor can be connected to a second switch blanking control terminal.

[0079] In one or more embodiments:

[0080] The second switch includes:

[0081] Multiple second NMOS transistors, among which

[0082] The source terminal of each second NMOS transistor can be connected to the second reference terminal, and the drain terminal of each second NMOS transistor can be connected to the source terminal of a first NMOS transistor and the drain terminal of its adjacent first NMOS transistor, such that a second NMOS transistor can be connected between each pair of first NMOS transistors.

[0083] In one or more examples, the gate terminal of each second NMOS transistor can be connected to the second switch blanking control terminal.

[0084] In one or more embodiments:

[0085] When the device is in the transmission mode:

[0086] The first switch can be turned off, such that one or more signals provided to the control terminal of the first switch are configured to de-conduct the first first PMOS transistor and the last first PMOS transistor in the chain. One or more signals provided to the blanking control terminal of the first switch can be configured to de-conduct each of the other first PMOS transistors and the plurality of second PMOS transistors.

[0087] In one or more examples, the second switch can be turned off, such that one or more signals provided to the control terminal of the second switch can be configured to de-conduct the first first NMOS transistor and the last first NMOS transistor in the chain. One or more signals provided to the blanking control terminal of the second switch can be configured to de-conduct each of the other first NMOS transistors and the plurality of second NMOS transistors.

[0088] In one or more embodiments:

[0089] When the device is in the receiving mode:

[0090] The first switch can be turned off, such that one or more signals provided to the control terminal of the first switch can be configured to turn on the first first PMOS transistor of the plurality of first PMOS transistors and the last first PMOS transistor in the chain. One or more signals provided to the blanking control terminal of the first switch can be configured to turn on each of the other first PMOS transistors of the plurality of first PMOS transistors and the plurality of second PMOS transistors.

[0091] The second switch can be turned off, such that one or more signals provided to the control terminal of the second switch can be configured to turn on the first first NMOS transistor and the last first NMOS transistor in the chain. One or more signals provided to the blanking control terminal of the second switch can be configured to turn on each of the other first NMOS transistors and the plurality of parallel NMOS transistors.

[0092] In one or more embodiments:

[0093] When the device is in the fast stabilization mode:

[0094] One or more signals provided to the first switch blanking control terminal and the second switch blanking control terminal can be configured to de-conduct one or more of the first PMOS transistors in the chain (excluding the first and last first PMOS transistors), one or more of the first NMOS transistors in the chain (excluding the first and last first NMOS transistors), and the second PMOS transistor and the second NMOS transistor, while the device provides signaling to the antenna. One or more signals provided to the first switch control terminal and the second switch control terminal can be configured to convert the first and last first PMOS transistors in the chain, as well as the first and last first NMOS transistors in the chain, while the device provides signaling to the antenna.

[0095] In one or more embodiments:

[0096] When the device is in the fast stabilization mode:

[0097] One or more signals provided to the first switch blanking control terminal and the second switch blanking control terminal can be configured to turn on one or more of the first PMOS transistors in the chain, excluding the first first PMOS transistor and the last first PMOS transistor, one or more of the first NMOS transistors in the chain, excluding the first first NMOS transistor and the last first NMOS transistor, and the second PMOS transistor and the second NMOS transistor, simultaneously when the device receives signaling from the antenna. One or more signals provided to the first switch control terminal and the second switch control terminal can be configured to turn on the first first PMOS transistor and the last first PMOS transistor in the chain, as well as the first first NMOS transistor and the last first NMOS transistor in the chain, simultaneously when the device receives signaling from the antenna.

[0098] In one or more embodiments, the receiver amplifier arrangement further includes:

[0099] A plurality of capacitors are configured to at least partially eliminate noise within the receiver amplifier arrangement;

[0100] A second plurality of capacitors are configured to at least partially eliminate noise within the receiver amplifier arrangement;

[0101] One or more blanking power supply voltage terminals, the one or more blanking power supply voltage terminals being configured to provide one or more blanking power supply voltages.

[0102] During the fast stabilization mode, when the device receives signaling from the antenna, the receiver amplifier arrangement can be configured to provide one or more blanking power supply voltages to the first plurality of capacitors and the second plurality of capacitors.

[0103] In one or more embodiments:

[0104] The first PMOS transistor in the pair of PMOS transistors includes:

[0105] The source terminal is coupled to the third differential input-output pin;

[0106] The drain terminal is coupled to the first output terminal;

[0107] The gate terminal is coupled to a first terminal of a first portion of a first capacitor. The second terminal of the first portion of the first capacitor can be coupled to a fourth differential input-output pin.

[0108] In one or more embodiments:

[0109] The second PMOS transistor in the pair of PMOS transistors includes:

[0110] The source terminal is coupled to the fourth differential input-output pin;

[0111] The drain terminal is coupled to the second output terminal;

[0112] The gate terminal is coupled to a first terminal of the first portion of the second capacitor. The second terminal of the first portion of the second capacitor can be coupled to the third differential input-output pin.

[0113] In one or more embodiments:

[0114] The receiver amplifier arrangement further includes a pair of output transistors, wherein:

[0115] The first output transistor in the pair of output transistors includes:

[0116] The first channel terminal is coupled to the first output terminal;

[0117] A second channel terminal, the second channel terminal being coupled to the drain terminal of the first PMOS transistor in the pair of PMOS transistors and the drain terminal of the first NMOS transistor in the pair of NMOS transistors; and

[0118] The control terminal is connected to the power supply terminal of the receiver amplifier.

[0119] In one or more embodiments:

[0120] The receiver amplifier arrangement further includes a pair of output transistors, wherein:

[0121] The second output transistor in the pair of output transistors includes:

[0122] The first channel terminal is coupled to the second output terminal;

[0123] A second channel terminal, the second channel terminal being coupled to the drain terminal of the second PMOS transistor in the pair of PMOS transistors and the drain terminal of the second NMOS transistor in the pair of NMOS transistors; and

[0124] The control terminal is connected to the power supply terminal of the receiver amplifier.

[0125] In one or more embodiments, the pair of output transistors is a pair of output NMOS transistors.

[0126] In one or more embodiments:

[0127] The first part of the low-noise amplifier circuit also includes:

[0128] A first portion blanking power supply voltage terminal, configured to provide a first portion blanking power supply voltage; and

[0129] The first partial blanking transistor has a drain terminal connected to the first partial blanking power supply voltage terminal, a source terminal connected to the first terminal of the first partial first capacitor and the first terminal of the first partial second capacitor, and a gate terminal connected to the first partial blanking control terminal.

[0130] In one or more embodiments:

[0131] The first NMOS transistor in the pair of NMOS transistors includes:

[0132] The source terminal is coupled to the fifth differential input-output pin;

[0133] The drain terminal is coupled to the first output terminal;

[0134] The gate terminal is coupled to a first terminal of the second portion of the first capacitor. The second terminal of the second portion of the first capacitor can be coupled to a sixth differential input-output pin.

[0135] In one or more embodiments:

[0136] The second PMOS transistor in the pair of PMOS transistors includes:

[0137] The source terminal is coupled to the sixth differential input-output pin;

[0138] The drain terminal is coupled to the second output terminal;

[0139] The gate terminal is coupled to the first terminal of the second portion of the second capacitor. The second terminal of the second portion of the first capacitor can be coupled to the fifth differential input-output pin.

[0140] In one or more embodiments:

[0141] The second part of the low-noise amplifier circuit further includes: a second part blanking power supply voltage terminal, the second part blanking power supply voltage terminal being configured to provide a second part blanking power supply voltage; and

[0142] The second blanking transistor has a drain terminal connected to the fourth power supply voltage terminal, a source terminal connected to the first terminal of the second part first capacitor and the first terminal of the second part second capacitor, and a gate terminal connected to the second blanking control terminal.

[0143] In one or more embodiments:

[0144] When the device is in the transmission mode, one or more signals provided to the first partial blanking control terminal and the second partial blanking control terminal can be configured to disable the first partial blanking transistor and the second partial blanking transistor.

[0145] In one or more embodiments:

[0146] When the device is in the receiving mode, one or more signals provided to the first partial blanking control terminal and the second partial blanking control terminal can be configured to turn on the first partial blanking transistor and the second partial blanking transistor.

[0147] In one or more embodiments:

[0148] When the device is in the fast stabilization mode:

[0149] One or more signals provided to the first partial blanking control terminal and the second partial blanking control terminal can be configured to de-conduct the first partial blanking transistor and the second partial blanking transistor while the device provides signaling to the antenna, so that the charge on the first partial first capacitor and the first partial second capacitor, as well as the charge on the second partial first capacitor and the second partial second capacitor, remains unchanged.

[0150] In one or more embodiments:

[0151] When the device is in the fast stabilization mode:

[0152] One or more signals provided to the first partial blanking control terminal and the second partial blanking control terminal can be configured to turn on the first partial blanking transistor and the second partial blanking transistor while the receiver amplifier is receiving signaling from the antenna pin.

[0153] While this disclosure is adaptable to various modifications and alternatives, its details have been shown by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0154] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the present or future claims. Various example embodiments are also illustrated by the following figures and detailed description. A more complete understanding of the various example embodiments can be gained from the following detailed description taken in conjunction with the accompanying figures. Attached Figure Description

[0155] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0156] Figure 1 An example device according to an embodiment of the present disclosure is shown;

[0157] Figure 2 An example amplifier arrangement and an example function switch are shown according to embodiments of the present disclosure;

[0158] Figure 3 An example first switch configured to operate in both a transmission mode and a reception mode according to an embodiment of the present disclosure is shown;

[0159] Figure 4 An example second switch configured to operate in both a transmission mode and a reception mode according to an embodiment of the present disclosure is shown;

[0160] Figure 5 An example first switch configured to operate in a transmit mode, a receive mode, and a fast stabilization mode according to another embodiment of the present disclosure is shown;

[0161] Figure 6 An example second switch, configured to operate in transmit mode, receive mode, and fast stabilization mode according to another embodiment of the present disclosure, is shown.

[0162] Figure 7 A second portion of an example amplifier arrangement configured to operate in transmit mode, receive mode, and fast stabilization mode according to embodiments of the present disclosure is shown; and

[0163] Figure 8 A first portion of an example LNA circuit configured to operate in a fast stabilization mode according to an embodiment of the present disclosure is shown. Detailed Implementation

[0164] Figure 1An example device 100 according to an embodiment of the present disclosure is shown. Device 100 includes an antenna pin 101 series-coupled to a first antenna inductor 102A and a second antenna inductor 102B, wherein the second antenna inductor 102B is configured to be additionally coupled via its other end to a first reference terminal 103, the first reference terminal 103 being configured to provide a first reference voltage. The first reference voltage may be ground or any other suitable reference voltage. The device also includes a first set of differential input-output pins including a first input-output pin 104A and a second input-output pin 104B, wherein the first input-output pin 104A is coupled to the first inductor 105A in series with a second inductor 105B, and the second inductor 105B is additionally coupled to the second input-output pin 104B. The device further includes a first power supply terminal 106 between inductors 105A and 105B to receive the first power supply voltage. A first inductor 105A is configured to be magnetically coupled to a first antenna inductor 102A, and a second inductor 105B is configured to be magnetically coupled to a second antenna inductor 102B. In this embodiment, antenna pin 101 is connected to or at least configured to be connected to antenna 101A, which is configured to transmit and receive signals.

[0165] The device also includes a function switch 160, the state of which is controlled based on whether the device operates in transmit mode or receive mode. Function switch 160 can be coupled to a second set of differential input-output pins, including a third input-output pin 107A and a fourth input-output pin 107B. The third input-output pin 107A can be coupled to a first terminal of a third inductor 108A. The second terminal of the third inductor 108A is coupled to a first terminal of a fourth inductor 108B, such that the inductors are connected in series. The second terminal of the fourth inductor 108B is coupled to the fourth input-output pin 107B. A first switch 120 is located between the third inductor 108A and the fourth inductor 108B, such that the first switch 120 is coupled between the second terminal of the third inductor 108A and the first terminal of the fourth inductor 108B. A third inductor 107A is configured to be magnetically coupled to a first antenna inductor 102A, and a fourth inductor 107B is configured to be magnetically coupled to a second antenna inductor 102B. In the current example, a function switch 160 is coupled to a third set of differential input-output pins, which includes a fifth input-output pin 109A and a sixth input-output pin 109B. The fifth input-output pin 109A can be coupled to a first terminal of a fifth inductor 110A. The second terminal of the fifth inductor 110A can be coupled to a first terminal of the sixth inductor 110B, such that the inductors are connected in series. The second terminal of the sixth inductor 110B is coupled to the sixth input-output pin 109B. A second switch 130 is located between the second terminal of the fifth inductor 110A and the first terminal of the sixth inductor 110B, such that they are coupled in series via the second switch 130. The fifth inductor 110A is configured to be magnetically coupled to the first antenna inductor 102A, and the sixth inductor 110B is configured to be magnetically coupled to the second antenna inductor 102B. In this way, the second and third sets of differential input-output pins are configured to provide signaling received from the antenna 101A as differential signals to the receivers coupled to the second and third sets of differential input-output pins.

[0166] As previously described, antenna pin 101 is connected to antenna 101A, which is configured to transmit and receive signals. To facilitate this, in this embodiment, a first set of differential input-output pins 104A, 104B is connected to or intended for connection to a transmitter configured to transmit signals using antenna 101A. In this embodiment, a second set of differential input-output pins 107A, 107B and a third set of differential input-output pins 109A, 109B are connected to or intended for connection to a receiver configured to receive signals from antenna 101A. It should be understood that any other suitable circuit architecture configured to transmit and receive signals from a single-pin antenna is possible.

[0167] In this embodiment, the transmitter includes a power amplifier circuit 111. The power amplifier circuit 111 can be configured to amplify a signal for transmission through antenna 101A. In some embodiments, the receiver includes a receiver amplifier arrangement. In this embodiment, the receiver amplifier arrangement includes an LNA circuit 140. The LNA circuit 140 can be configured to amplify the signal received from antenna 101A while maintaining the signal-to-noise ratio of the signal. The LNA circuit 140 can be a differential complementary (PMOS and NMOS) current-multiplexed common-gate LNA. The LNA circuit 140 can be configured to provide both a PMOS-based amplification path and an NMOS-based amplification path, which can reduce current consumption without degrading RF performance.

[0168] In some embodiments, device 100 can be configured to operate in both a transmission mode and a reception mode. In these embodiments, the transmission mode and reception mode are implemented by controlling a first switch 120 and a second switch 130. In transmission mode, device 100 is configured to transmit signals using antenna pin 101. In reception mode, device 100 is configured to receive signals from antenna pin 101. The use of both transmission and reception modes allows device 100 to block transmitted signals from the receiver when necessary, which can reduce interference, prevent damage to sensitive components, and improve the power efficiency of device 100.

[0169] In transmission mode, the first switch 120 and the second switch 130 are open, resulting in high impedance between the third inductor 108A and the fourth inductor 108B, and also high impedance between the fifth inductor 110A and the sixth inductor 110B. This high impedance reduces the cross-coupling effect of the third inductor 108A, the fourth inductor 108B, the fifth inductor 110A, and the sixth inductor 110B on the first inductor 105A and the second inductor 105B when the transmitter is transmitting a signal. In this way, the power amplifier circuit 111 can amplify the signal used for transmission more effectively, which can produce a stronger transmitted signal or achieve the same output power with less current consumption. Additionally, the high impedance provided by the first switch 120 and the second switch 130 also reduces the strength of the transmitted signal unintentionally received by the receiver. Because less power is coupled to the LNA circuit 140, potential damage to the LNA circuit 140 and any other connected circuitry due to excessive signal strength is reduced.

[0170] In receive mode, the first switch 120 and the second switch 130 are closed, resulting in low impedance between the third inductor 108A and the fourth inductor 108B, and also low impedance between the fifth inductor 110A and the sixth inductor 110B. In this way, the receiver can effectively receive signals from antenna pin 101. The transmitter is inactive during receive mode and is therefore unaffected by the operation of the first switch 120 and the second switch 130.

[0171] In some embodiments, the LNA circuit 140 includes a first portion and a second portion. Reference will be made below. Figure 2 Let's discuss an example LNA circuit 140. In these embodiments, a second set of differential input-output pins 107A, 107B are connected to a first portion of the LNA circuit 140, and a third set of differential input-output pins 109A, 109B are connected to a second portion of the LNA circuit 140, but the reverse is also possible.

[0172] Figure 2 An example LNA circuit 240 and a function switch 260 according to an embodiment of the present disclosure are shown. In this example, the LNA circuit 240 includes a first portion shown in the upper half of the figure, and the LNA circuit 240 includes a second portion shown in the lower half of the figure. The first portion includes a pair of PMOS transistors 242A and 242B, and the second portion includes a pair of NMOS transistors 244A and 244B.

[0173] In this embodiment, the first PMOS transistor 242A of the pair of PMOS transistors in the first part includes: a source terminal coupled to the third differential input-output pin 207A, a drain terminal coupled to the first output terminal 247, and a gate terminal coupled to the first terminal of the first portion of the first capacitor 241B. The second terminal of the first portion of the first capacitor 241B is coupled to the fourth differential input-output pin 207B. The cross-coupled first portion of the first capacitor 241B and the first portion of the second capacitor 241A are configured to eliminate noise within the LNA circuit 240. The connection provided by the first portion of the first transistor 241B from the gate terminal of the first PMOS transistor 242A to the drain terminal of the second PMOS transistor 242B ensures that any noise present on the first PMOS transistor 242A will also be present in the current path to the second differential output terminal 248. The presence of this noise in the two differential output current paths has the effect that the noise is canceled when the output of the LNA circuit 240 is differentially obtained. Similarly, the connection provided by the second transistor 241A in the first part, from the gate of the second PMOS transistor 242B to the drain of the first PMOS transistor 242A, ensures that any noise present in the second PMOS transistor 242B will also be present in the current path to the first differential output 247. This noise existing in both differential output current paths ensures that the noise is canceled out when the output of the LNA circuit 240 is differentially obtained.

[0174] Similarly, in this embodiment, the second PMOS transistor 242B of the pair of PMOS transistors includes: a source terminal coupled to the fourth differential input-output pin 207B, a drain terminal coupled to the second output terminal 248, and a gate terminal coupled to the first terminal of the first portion of the second capacitor 241A. The second terminal of the first portion of the second capacitor 241A is coupled to the third differential input-output pin 207A.

[0175] The pair of NMOS transistors 244A and 244B in the second part are arranged in a similar manner to the pair of PMOS transistors 242A and 242B in the first part. Specifically, the first NMOS transistor 244A in the pair of NMOS transistors in the second part includes: a source terminal coupled to the fifth differential input-output pin 209A, a drain terminal coupled to the first output terminal 247, and a gate terminal coupled to the first terminal of the first capacitor 243B in the second part. The second terminal of the first capacitor 243B in the second part is coupled to the sixth differential input-output pin 209B.

[0176] The second NMOS transistor 244B of the pair of NMOS transistors includes a source terminal coupled to the sixth differential input-output pin 209B, a drain terminal coupled to the second output terminal 248, and a gate terminal coupled to the first terminal of the second portion of the second capacitor 243A. The second terminal of the second portion of the second capacitor 243A is coupled to the fifth differential input-output pin 209A. The second portion of the first capacitor 243B and the second portion of the second capacitor 243A are configured to eliminate noise within the LNA circuit 240 in the same manner as the first portion of the first capacitor 241B and the first portion of the second capacitor 241A described above.

[0177] Example LNA circuit 240 also includes a pair of output NMOS transistors 245A and 245B. In other examples, LNA circuit 240 may include a pair of output PMOS transistors instead of NMOS transistors. The source terminal of each of the output NMOS transistors 245A and 245B is connected to the drain terminal of one of the PMOS transistors 242A and 242B and one of the NMOS transistors 244A and 244B. That is, in this example, the source terminal of the first output NMOS transistor 245A is connected to the drain terminal of the first PMOS transistor 242A and the drain terminal of the first NMOS transistor 244A. Correspondingly, in this example, the source terminal of the second output NMOS transistor 245B is connected to the drain terminal of the second PMOS transistor 242B and the drain terminal of the second NMOS transistor 244B. The gate terminal of each of the output NMOS transistors 245A and 245B is connected to an LNA power supply terminal 246, which is configured to provide an LNA power supply voltage. The drain terminal of each output NMOS transistor 245A, 245B is connected to either the first output voltage terminal 247 or the second output voltage terminal 248. In this example, the first output terminal 247 is negative and the second output terminal 248 is positive. However, in other examples, depending on the circuit topology, the first output terminal 247 can be positive and the second output terminal 248 can be negative.

[0178] Outside of the receiver amplifier arrangement or LNA circuit 240 shown in the embodiment. Figure 2A functional switch 260 (split in half) is also shown, comprising a first switch 220 and a second switch 230. In this embodiment, the first switch 220 is configured to connect a third inductor 208A and a fourth inductor 208B to a second power supply terminal 221 configured to receive a second power supply voltage, or the first switch is open. In this way, when the first switch 220 is closed (i.e., when the first switch 220 has low impedance), the third inductor 208A and the fourth inductor 208B receive the second power supply voltage. When the first switch 220 is open (i.e., when the first switch 220 has high impedance), the third inductor 208A is not connected to the fourth inductor 208B. Similarly, the second switch 230 is configured to connect a fifth inductor 210A and a sixth inductor 210B to a second reference terminal 231 configured to receive a second reference voltage, or the second switch 230 is open. When the second switch 230 is closed (i.e., the second switch 230 has low impedance), the fifth inductor 210A and the sixth inductor 210B receive the second reference voltage. When the second switch 230 is open (i.e., when the second switch 230 has high impedance), the fifth inductor 210A is not connected to the sixth inductor 210B.

[0179] about Figure 1 and 2 The device under discussion is configured to operate in both a transmit mode and a receive mode. When device 100 is in transmit mode, the first switch 220 and the second switch 230 are configured to be open, and the transmitter is configured to transmit one or more signals from antenna 101A. In this way, the transmitted signal from antenna 101A is not received by LNA circuit 240, and therefore the transmitted signal is unlikely to cause damage to LNA circuit 240 or any other circuit connected to it. When device 100 is in receive mode, the first switch 220 and the second switch 230 are configured to be closed, and the receiver is configured to receive one or more signals from antenna 101A. In this way, the receiver can effectively perform its role.

[0180] Figure 3An example first switch 320 (an example of first switches 120, 220) according to an embodiment of the present disclosure is shown. The first switch 320 includes a plurality of transistors 322A, 322B, 322C, 322D, 322E. When the device is in transmit mode, all transistors 322A, 322B, 322C, 322D, 322E are configured to be non-conductive. When the device is in receive mode, all transistors 322A, 322B, 322C, 322D, 322E are configured to be conductive. In this embodiment, the first switch 320 includes a plurality of first PMOS transistors 322A, 322B, 322C connected in series in a chain, such that the source terminal of one first PMOS transistor 322A, 322B, 322C is connected to the drain terminal of an adjacent first PMOS transistor 322A, 322B, 322C. In this example, the plurality of first PMOS transistors 322A, 322B, and 322C includes three first PMOS transistors 322A, 322B, and 322C, but other numbers of first PMOS transistors are also possible. Therefore, in this example, the drain of the first transistor 322A in the chain is connected to the source of the second transistor 322B, and the drain of the second transistor 322B is connected to the source of the last transistor 322C in the chain. It should be understood that additional first transistors can be coupled in this manner if present.

[0181] The source terminal of the first transistor 322A in the chain of first PMOS transistors is connected to the third inductors 108A and 208A. The drain terminal of the last first PMOS transistor 322C in the chain is connected to the fourth inductors 108B and 208B. It should be understood that, in other examples, the third inductor may alternatively be connected to the drain terminal of the last first PMOS transistor in the chain, and the fourth inductor may alternatively be connected to the source terminal of the first first PMOS transistor in the chain of first PMOS transistors. The gate terminal of each of the first PMOS transistors 322A, 322B, and 322C is connected to the first terminal of the corresponding resistor 323A, 323B, and 323C. The second terminal of each corresponding resistor 323A, 323B, and 323C is connected to the first switch control terminals 324A, 324B, and 324C.

[0182] The first switch 320 also includes a plurality of second PMOS transistors 325D, 325E, wherein the source terminal of each second PMOS transistor 325D, 325E is connected to the second power supply terminal 321. The drain terminal of each second PMOS transistor 325D, 325E is connected to the source terminal of a corresponding first PMOS transistor 323A, 323B, 323C and the drain terminal of its adjacent first PMOS transistor 323A, 323B, 323C. In this way, one second PMOS transistor 325D, 325E is connected between each pair of first PMOS transistors 323A, 323B, 323C. In this example, the plurality of second PMOS transistors 325D, 325E includes two second PMOS transistors 325D, 325E, but other numbers of second PMOS transistors are also possible. In this example, the drain of the first transistor 325D in the second PMOS transistor is connected to the drain of the first transistor 322A in the first PMOS transistor and the source of the second transistor 322B in the first PMOS transistor. The drain of the second transistor 325E in the second PMOS transistor is connected to the drain of the second transistor 322B in the first PMOS transistor and the source of the last transistor 322C in the first PMOS transistor. The gate of each of the second PMOS transistors 325D and 325E is connected to the first switch control terminals 324E and 324D.

[0183] The first switch control terminals 324A, 324B, 324C, 324D, and 324E associated with each transistor of the first switch 320 can be controlled independently or together with each of the other first switch control terminals 324A, 324B, 324C, 324D, and 324E. In this example, all of the first switch control terminals 324A, 324B, 324C, 324D, and 324E are controlled together.

[0184] When the device is in transmit mode, the first switch 320 is open, causing one or more signals provided to the first switch control terminals 324A, 324B, 324C, 324D, and 324E to de-energize a plurality of first PMOS transistors 322A, 322B, and 322C and a plurality of second PMOS transistors 325D and 325E. When the device is in receive mode, the first switch 320 is closed, causing one or more signals provided to the first switch control terminals 324A, 324B, 324C, 324D, and 324E to energize a plurality of first PMOS transistors 322A, 322B, and 322C and a plurality of second PMOS transistors 325D and 325E. One or more signals may be provided to the second switch control terminals 324A, 324B, 324C, 324D, and 324E by a controller (not shown) or any other suitable component. The controller may be the same controller used to control the transmission and / or reception of the signals.

[0185] Figure 4 An example second switch 430 (an example of second switches 130, 230) according to an embodiment of the present disclosure is shown. The second switch 430 includes a plurality of transistors 432A, 432B, 432C, 432D, 432E. When the device is in transmit mode, all transistors 432A, 432B, 432C, 432D, 432E are configured to be non-conductive. When the device is in receive mode, all transistors 432A, 432B, 432C, 432D, 432E are configured to be conductive. Similar to the first switch, in this embodiment, the second switch 430 includes a plurality of first NMOS transistors 432A, 432B, and 432C, which are connected in series to form a chain, such that the source terminal of one first NMOS transistor 432A, 432B, or 432C is connected to the drain terminal of an adjacent first NMOS transistor 432A, 432B, or 432C. In this example, the plurality of first NMOS transistors 432A, 432B, and 432C includes three first NMOS transistors 432A, 432B, and 432C, but other numbers of first NMOS transistors are also possible. Therefore, in this example, the drain terminal of the first first NMOS transistor 432A is connected to the source terminal of the second first NMOS transistor 432B, and the drain terminal of the second first NMOS transistor 432B is connected to the source terminal of the last first NMOS transistor 432C.

[0186] The source terminal of the first transistor 432A in the chain of first NMOS transistors is connected to the fifth inductors 110A and 210A. The drain terminal of the last transistor 432C in the chain of first NMOS transistors is connected to the sixth inductors 110B and 210B. It should be understood that, in other examples, the fifth inductor 110A may alternatively be connected to the drain terminal of the last first NMOS transistor in the chain, and the sixth inductor may alternatively be connected to the source terminal of the first first NMOS transistor in the chain of first NMOS transistors. The gate terminal of each of the first NMOS transistors 432A, 432B, and 432C is connected to the first terminal of the corresponding resistor 433A, 433B, and 433C. The second terminal of each corresponding resistor 433A, 433B, and 433C is connected to the second switch control terminals 434A, 434B, and 434C.

[0187] The second switch 430 also includes a plurality of second NMOS transistors 435D, 435E, wherein the source terminal of each second NMOS transistor 435D, 435E is connected to the second reference terminal 431, and the drain terminal of each second NMOS transistor 435D, 435E is connected to the source terminal of a first NMOS transistor 433A, 433B, 433C and the drain terminal of its adjacent first NMOS transistor 433A, 433B, 433C. In this manner, one second NMOS transistor 435D, 435E is connected between each pair of first NMOS transistors 433A, 433B, 433C. In this example, the plurality of second NMOS transistors 435D, 435E includes two second NMOS transistors 435D, 435E, but other numbers of second NMOS transistors are also possible. Therefore, in this example, the drain terminal of the first transistor 435D in the second NMOS transistor is connected to the drain terminal of the first transistor 432A in the first NMOS transistor and the source terminal of the second transistor 432B in the first NMOS transistor. The drain terminal of the second transistor 435E in the second NMOS transistor is connected to the drain terminal of the second transistor 432B in the first NMOS transistor and the source terminal of the last transistor 432C in the first NMOS transistor. The gate terminal of each of the second NMOS transistors 435D and 435E is connected to the second switch control terminals 434E and 434D.

[0188] The second switch control terminals 434A, 434B, 434C, 434D, and 434E, individually shown as associated with each transistor of the second switch 430, can be controlled independently or together with each of the other second switch control terminals 434A, 434B, 434C, 434D, and 434E. In this example, all of the second switch control terminals 434A, 434B, 434C, 434D, and 434E are controlled together. When the device is in transmit mode, the second switch 430 is open, such that one or more signals provided to the second switch control terminals 434A, 434B, 434C, 434D, and 434E are configured to de-energize the plurality of first NMOS transistors 432A, 432B, and 432C and the plurality of second NMOS transistors 435D and 435E. When the device is in receive mode, the second switch 430 is closed, causing one or more signals provided to the second switch control terminals 434A, 434B, 434C, 434D, and 434E to be configured to turn on a plurality of first NMOS transistors 432A, 432B, and 432C and a plurality of second NMOS transistors 435D and 435E. One or more signals may be provided to the second switch control terminals 434A, 434B, 434C, 434D, and 434E by a controller (not shown) or any other suitable component. The controller may be the same controller used to control the transmission and / or reception of the control signals.

[0189] In some examples, in addition to receive and transmit modes, the device can also be configured to operate in a fast stabilization mode. The device can be configured to operate in fast stabilization mode when the transmitter is configured to transmit a signal from the antenna, and the receiver is configured to receive a signal from the antenna within a short time period from the start of transmission. For example, the received signal could be a reflection of a signal transmitted from the antenna. To facilitate this mode without risk of damage to any components, first switch 220 and second switch 230 are controlled such that first switch 220 and second switch 230 are configured to open when the transmitter transmits a signal from the antenna, and first switch 220 and second switch 230 are configured to close when the receiver receives a signal from the antenna. As mentioned above, the time between signal transmission and reception may be too short, making the time required for switching between transmit and receive modes too long for the device to receive a signal. For example, if the transmitted signal is a radar signal and if the target is close to the antenna, a reflection from the target may be received very shortly after transmission. Therefore, it is advantageous for the function switches to switch quickly with low interference to the receiver amplifier arrangement.

[0190] The following text is about Figures 5-7The described embodiments are capable of “blank” LNA circuitry 140 for a very short period of time, thereby allowing the transmitter to transmit at high power and the receiver to subsequently receive with high sensitivity without damaging the LNA circuitry or saturating the receiver chain. Specifically, the function switch is controlled in a manner that “blanks” the receiver amplifier arrangements (e.g., LNA circuitry 140, 240) with low interruption at the bias point of the receiver amplifier arrangements 140, 240 during transmission.

[0191] Figure 5 An example first switch 520 configured to operate in a transmit mode, a receive mode, and a fast stabilization mode according to embodiments of the present disclosure is shown. The first switch 520 includes a plurality of transistors 522A, 522B, 522C, 522D, and 522E. When the device is in transmit mode, all transistors 522A, 522B, 522C, 522D, and 522E are configured to be non-conductive. When the device is in receive mode, all transistors 522A, 522B, 522C, 522D, and 522E are configured to be conductive. When the device is in fast stabilization mode, some transistors 522A, 522B, 522C, 522D, and 522E are configured to be conductive, and some transistors 522A, 522B, 522C, 522D, and 522E are configured to be non-conductive.

[0192] As can be clearly seen from the figure, the first switch 520 used for operation in the fast stabilization mode in this embodiment is very similar to the reference stylist. Figure 3 The first switch is described. However, in Figure 3In the first switch, where the gate of each of the plurality of first PMOS transistors is connected to the first terminal of a corresponding resistor (and the second terminal of the corresponding resistor is connected to the first switch control terminal), in this embodiment, only the gates of the first transistor 522A and the last transistor 522C of the plurality of first PMOS transistors in the chain are connected to the first terminals of corresponding resistors 523A and 523C (and the second terminals of the corresponding resistors are connected to the first switch control terminals 524A and 524C). The gate of each other first PMOS transistor (in this example, the second transistor 522B of the first PMOS transistors) is connected to the first switch blanking control terminal 526B. The gates of each second PMOS transistor 525D and 525E are connected to the first switch blanking control terminals 526D and 526E. The absence of a corresponding resistor between the first PMOS transistor 522B, which is not the first or last transistor in the chain, and the first switch blanking control terminal 526B increases the stabilization speed of the first switch 520 and thus helps to facilitate the rapid stabilization mode of the device. This is because the stabilization time is proportional to the resistance. By eliminating the relatively large resistor between the first PMOS transistor 522B (which is neither the first nor the last transistor in the chain) and the first switch blanking control terminal, only parasitic resistance is retained in this path, and thus a faster settling time has been found. In this example, the plurality of first PMOS transistors 522A, 522B, 522C includes three first PMOS transistors 522A, 522B, 522C, and the plurality of second PMOS transistors 525D, 525E includes two second PMOS transistors 525D, 525E, but other numbers of transistors are also possible.

[0193] When the device is in transmission mode, the first switch 520 is open, causing one or more signals provided to the first switch control terminal to de-conduct the first transistor 522A and the last first PMOS transistor 522C in the chain of multiple first PMOS transistors. One or more signals provided to the first switch blanking control terminal are configured to de-conduct each of the other first PMOS transistors in the multiple series PMOS transistors (in this example, the second transistor 522B in the first PMOS transistors) and the multiple second PMOS transistors 525D, 525E.

[0194] When the device is in receive mode, the first switch 520 is closed, such that one or more signals provided to the first switch control terminals 524A and 524C are configured to turn on the first transistor 522A and the last first PMOS transistor 522C in the chain of multiple first PMOS transistors. One or more signals provided to the first switch blanking control terminal are configured to turn on each of the other first PMOS transistors in the multiple series PMOS transistors (in this example, the second transistor 522B in the first PMOS transistors) and the multiple second PMOS transistors 525D and 525E.

[0195] When the device is in fast stabilization mode, one or more signals provided to the first switch blanking control terminals 526B, 526D, and 526E are configured to de-conduct all first PMOS transistors in the chain except for the first and last transistors in the first PMOS transistor chain (in this example, the second transistor 522B in the first PMOS transistor chain) and the second PMOS transistors 525D and 525E. One or more signals provided to the first switch control terminals 524A and 524C are also configured to conduct the first transistor 522A and the last transistor 522C in the first PMOS transistor chain when the transmitter is transmitting signals from the antenna. One or more signals provided to the first switch blanking control terminals 526B, 526D, and 526E are configured to conduct all first PMOS transistors in the chain except for the first and last transistors in the first PMOS transistor chain (in this example, the second transistor 522B in the first PMOS transistor chain) and the second PMOS transistors 525D and 525E while the receiver amplifier is receiving signals from the antenna. One or more signals provided to the first switch control terminals 524A and 524C are also configured to turn on the first transistor 522A and the last transistor 522C of the first PMOS transistors in the chain when the transmitter receives a signal from the antenna. In other words, the first switch blanking control terminals 526B, 526D, and 526E are dynamically controlled for LNA blanking. The first switch control terminals 524A and 524C and the first switch blanking control terminals 526B, 526D, and 526E can be controlled by a controller (not shown) or any other suitable component. The controller can be the same controller used to control the transmission and / or reception of control signals.

[0196] Figure 6An example second switch 630, configured to operate in a transmit mode, a receive mode, and a fast stabilization mode according to embodiments of the present disclosure, is shown. The second switch 630 includes a plurality of transistors 632A, 632B, 632C, 632D, and 632E. When the device is in transmit mode, all transistors 632A, 632B, 632C, 632D, and 632E are configured to be non-conductive. When the device is in receive mode, all transistors 632A, 632B, 632C, 632D, and 632E are configured to be conductive. When the device is in fast stabilization mode, some transistors 632A, 632B, 632C, 632D, and 632E are configured to be conductive, and some transistors 632A, 632B, 632C, 632D, and 632E are configured to be non-conductive.

[0197] As can be clearly seen from the figure, the second switch 630 used for operation in the fast stabilization mode in this embodiment is very similar to the reference stylist. Figure 4 The second switch described. However, in Figure 4 In the second switch, where the gate of each of the plurality of first NMOS transistors is connected to the first terminal of a corresponding resistor (and the second terminal of the corresponding resistor is connected to the second switch control terminal), in this embodiment, only the gates of the first transistor 632A and the last transistor 632C of the plurality of first NMOS transistors in the chain are connected to the first terminals of corresponding resistors 633A and 633C (and the second terminals of the corresponding resistors are connected to the second switch control terminals 634A and 634C). The gate of each other first NMOS transistor (in this example, the second transistor 632B of the first NMOS transistors) is connected to the second switch blanking control terminal 636B. The gates of each second NMOS transistor 635D and 635E are connected to the second switch blanking control terminals 636D and 636E. The absence of a corresponding resistor between the first NMOS transistor 632B, which is not the first or last transistor in the chain, and the second switch blanking control terminal 636B improves the stabilization speed of the second switch 630 and thus helps to facilitate the rapid stabilization mode of the device. Similar to... Figure 5 The example first switch shown in this example includes three first NMOS transistors 632A, 632B, and 632C, and two second NMOS transistors 635D and 635E, but other numbers of transistors are also possible.

[0198] When the device is in transmission mode, the second switch 630 is open, causing one or more signals provided to the second switch control terminal to de-conduct the first transistor 632A and the last transistor 632C of the plurality of first NMOS transistors in the chain. One or more signals provided to the second switch blanking control terminal are configured to de-conduct each of the other first NMOS transistors (in this example, the second transistor 632B of the first NMOS transistors) and the plurality of second NMOS transistors 635D, 635E.

[0199] When the device is in receive mode, the second switch 630 is closed, causing one or more signals provided to the second switch control terminals 634A and 634C to turn on the first transistor 632A and the last transistor 632C of the plurality of first NMOS transistors in the chain. One or more signals provided to the second switch blanking control terminal are configured to turn on each of the other first NMOS transistors in the plurality of series NMOS transistors (in this example, the second transistor 632B of the first NMOS transistors) and the plurality of second NMOS transistors 635D and 635E.

[0200] When the device is in fast stabilization mode, one or more signals provided to the second switch blanking control terminals 636B, 636D, and 636E are configured to de-conduct all first NMOS transistors in the chain, except for the first and last transistors in the first NMOS transistor chain (in this example, the second transistor 632B in the first NMOS transistor chain) and the second NMOS transistors 635D and 635E. One or more signals provided to the second switch control terminals 634A and 634C are also configured to conduct the first transistor 632A and the last transistor 632C in the first NMOS transistor chain when the transmitter is transmitting signals from the antenna. One or more signals provided to the second switch blanking control terminals 636B, 636D, and 636E are configured to conduct all first NMOS transistors in the chain, except for the first and last transistors in the first NMOS transistor chain (in this example, the second transistor 632B in the first NMOS transistor chain) and the second NMOS transistors 635D and 635E, when the receiver is receiving signals from the antenna. One or more signals provided to the second switch control terminals 634A and 634C are also configured to turn on the first transistor 632A and the last transistor 632C in the chain of first NMOS transistors when the transmitter receives a signal from the antenna. In other words, the second switch blanking control terminals 636B, 636D, and 636E are dynamically controlled for LNA blanking.

[0201] Figure 7 A second portion of an example LNA circuit 740 configured to operate in a fast stabilization mode according to an embodiment of this disclosure is shown. (Except for reference...) Figure 2 In addition to the described components, a second portion of the LNA circuit 740 includes a second partial blanking power supply voltage terminal 749 configured to provide a second partial blanking power supply voltage. In one or more embodiments, the second partial blanking power supply voltage is equal to the LNA power supply voltage. The second portion of the LNA circuit 740 also includes a second partial blanking transistor 750 having a drain terminal connected to the second partial blanking power supply voltage terminal 749, a source terminal connected to a first terminal of the second partial first capacitor 743B and a first terminal of the second partial second capacitor 743A, and a gate terminal connected to a second partial blanking control terminal 751. That is, the source terminal of the second partial blanking transistor 750 is connected to the gate terminals of two of the pair of NMOS transistors 744A, 744B. In this example, the second portion of the example LNA circuit 740 also includes a pair of resistors 752A, 752B. A first terminal of the first resistor 752A is connected to the source terminal of the second partial blanking transistor 750, and a second terminal of the first resistor 752A is connected to a second terminal of the second partial first capacitor 743B. The first terminal of the second resistor 752B in the pair of resistors is connected to the source terminal of the second partial blanking transistor 750, and the second terminal of the second resistor 752A is connected to the second terminal of the second partial second capacitor 743A. In this way, the pair of resistors 752A and 752B are also connected between the gate terminals of the pair of NMOS transistors 744A and 744B. The pair of resistors 752A and 752B provides a DC path for the LNA, which defines the operating point of the pair of NMOS transistors 744A and 744B.

[0202] In this example, the first part of the LNA circuit 740 includes a corresponding set of features. Figure 8 A first portion of an example LNA circuit 840 configured to operate in a fast-stabilization mode according to an embodiment of the present disclosure is shown.

[0203] Besides reference Figure 2In addition to the described components, a first portion of the LNA circuit 840 includes a first partial blanking power supply voltage terminal 853 configured to provide a first partial blanking power supply voltage. In one or more embodiments, the first partial blanking power supply voltage is equal to the LNA power supply voltage. The first portion of the LNA circuit 840 also includes a first partial blanking transistor 854 having a drain terminal connected to the first partial blanking power supply voltage terminal 853, a source terminal connected to a first terminal of a first partial capacitor 841B and a first terminal of a first partial capacitor 841A, and a gate terminal connected to a first partial blanking control terminal 855. That is, the source terminal of the first partial blanking transistor 854 is connected to the gate terminals of two of the pair of PMOS transistors 842A, 842B. In this example, the first portion of the example LNA circuit 840 also includes a pair of resistors 856A, 856B. A first terminal of the first resistor 856A is connected to the source terminal of the first partial blanking transistor 854, and a second terminal of the first resistor 856A is connected to a second terminal of the first partial capacitor 841B. The first terminal of the second resistor 856B in the pair of resistors is connected to the source terminal of the first partial blanking transistor 854, and the second terminal of the second resistor 752A is connected to the second terminal of the first partial second capacitor 841A. In this way, the pair of resistors 856A and 856B are also connected between the gate terminals of the pair of PMOS transistors 842A and 842B. The pair of resistors 856A and 856B provides a DC path for the LNA, which defines the operating point of the pair of PMOS transistors 842A and 842B.

[0204] When the device is in transmit mode, one or more signals provided to the first partial blanking control terminal 855 and the second partial blanking control terminal 751 are configured to de-energize the first partial blanking transistor 854 and the second partial blanking transistor 750. In this way, the LNA blanking-related components in the LNA circuit 740 do not affect the ability of the LNA circuit 740 to operate normally in transmit mode.

[0205] When the device is in receive mode, one or more signals provided to the first partial blanking control terminal 855 and the second partial blanking control terminal 751 are configured to turn on the first partial blanking transistor 854 and the second partial blanking transistor 750. In this way, the LNA blanking-related components in the LNA circuit 740 do not affect the ability of the LNA circuit 740 to operate normally in receive mode.

[0206] When the device is in fast stabilization mode, while the device provides signaling to the antenna, the receiver amplifier arrangement 740 is configured to de-conduct the first partial blanking transistor 854 and the second partial blanking transistor 750, so that the charge on the first plurality of capacitors 841A, 841B and the second plurality of capacitors 743A, 743B remains unchanged / undisturbed, thereby maintaining the bias point of the LNA circuit. In this way, the receiver amplifier arrangement 740 can return to a state where the receiver amplifier arrangement 740 can receive signaling from the amplifier more quickly.

[0207] More specifically, when the device is in fast stabilization mode: one or more signals provided to the first partial blanking control terminal 855 and the second partial blanking control terminal 751 are configured to de-conduct the first partial blanking transistor 854 and the second partial blanking transistor 750 while the transmitter is transmitting a signal from the antenna, such that the charges on the first partial capacitor 841B and the first partial capacitor 841A, as well as the charges on the second partial capacitor 743B and the second partial capacitor 743A, remain unchanged. One or more signals provided to the first partial blanking control terminal 855 and the second partial blanking control terminal 751 are configured to turn on the first partial blanking transistor 854 and the second partial blanking transistor 750 while the receiver is receiving a signal from the antenna. In this example, one or more signals provided to the first partial blanking control terminal and the second partial blanking control terminal 751 are configured to turn on the first partial blanking transistor and the second partial blanking transistor 750, while one or more signals provided to the first switch blanking control terminal and the second switch blanking control terminal are configured to turn on the corresponding transistors of the switch blanking control terminals. In this way, the LNA circuit 740 is able to receive signaling from the antenna.

[0208] Advantageously, because the charges on the first and second cross-coupling capacitors 743A and 743B remain constant during the temporary LNA blanking period used for transmission, rapid stabilization can be achieved, allowing the LNA circuit 740 to reconnect and begin receiving reflected signals much faster than in other cases. This reduction in switching time reduces the "dead zone" of undetectable reflections, where the term "dead zone" refers to a situation where a reflecting object is too close to the antenna for the device to switch between transmit and receive modes quickly enough. In this way, the "dead zone" defines the area where the radar antenna cannot detect reflections.

[0209] The instructions and / or flowchart steps in the above figures can be performed in any order unless a specific order is explicitly specified. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context of the detailed description provided herein.

[0210] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor can refer to a single component or multiple components.

[0211] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transient machine-readable or computer-usable storage media. Such one or more computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple manufactured components. One or more non-transient machine-readable or computer-usable media as defined herein do not include signals, but such one or more media are capable of receiving and processing information from signals and / or other transient media.

[0212] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, Internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0213] In one example, one or more instructions or steps discussed in this article are automated. The terms automated or automatic (and similar variations) mean using computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0214] It should be understood that any components that are to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, another component may be placed between the two components that are said to be coupled.

[0215] In this specification, exemplary embodiments have been presented according to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of details, can be practiced. The appended claims are intended to cover all possible exemplary embodiments.

Claims

1. An apparatus, comprising: comprises: an antenna pin for coupling to an antenna, the antenna pin coupled to at least a first antenna inductor in series with a second antenna inductor, wherein the second antenna inductor is otherwise coupled to a first reference pin configured to provide a first reference voltage; a first set of differential input-output pins comprising a first input-output pin and a second input-output pin, wherein the first input-output pin is coupled to a first inductor in series with a second inductor, and wherein the second inductor is otherwise coupled to the second input-output pin, wherein the device otherwise comprises a first power supply terminal coupled between the first inductor and the second inductor to receive a first power supply voltage, wherein the first inductor is configured to be magnetically coupled with the first antenna inductor and the second inductor is configured to be magnetically coupled with the second antenna inductor for transmitting signaling received from the antenna at the first set of differential input-output pins when the antenna is coupled to the antenna pin; and a function switch comprising: a second set of differential input-output pins comprising a third input-output pin and a fourth input-output pin, wherein the third input-output pin is coupled to a third inductor in series with a fourth inductor, and wherein the fourth inductor is otherwise coupled to the fourth input-output pin, and wherein the function switch comprises a first switch between the third inductor and the fourth inductor, wherein the third inductor is configured to be magnetically coupled with the first antenna inductor and the fourth inductor is configured to be magnetically coupled with the second antenna inductor for providing signaling received from the antenna pin to the second set of differential input-output pins; a third set of differential input-output pins comprising a fifth input-output pin and a sixth input-output pin, wherein the fifth input-output pin is coupled to a fifth inductor in series with a sixth inductor, and wherein the sixth inductor is otherwise coupled to the sixth input-output pin, and wherein the function switch comprises a second switch between the fifth inductor and the sixth inductor, wherein the fifth inductor is configured to be magnetically coupled with the first antenna inductor and the sixth inductor is configured to be magnetically coupled with the second antenna inductor for providing signaling received from the antenna pin to the third set of differential input-output pins.

2. The apparatus of claim 1, wherein, comprises a receiver amplifier arrangement, wherein the second set of differential input-output pins and the third set of differential input-output pins are configured to be connected to the receiver amplifier arrangement, the receiver amplifier arrangement configured to receive the signaling received from the antenna via the antenna pin, wherein the receiver amplifier arrangement comprises a first portion formed by at least one pair of PMOS transistors and a second portion formed by at least one pair of NMOS transistors.

3. The device of claim 2, wherein: the second set of differential input-output pins are connected to the first portion of the receiver amplifier arrangement; and the third set of differential input-output pins are connected to the second portion of the receiver amplifier arrangement.

4. The device of any preceding claim, wherein: the first switch is connected to a second supply terminal configured to receive a second supply voltage, such that when the first switch is closed, the third inductor and the fourth inductor receive the second supply voltage, and when the first switch is open, the third inductor is not connected to the fourth inductor; and the second switch is connected to a second reference terminal configured to receive a second reference voltage, such that when the second switch is closed, the fifth inductor and the sixth inductor receive the second reference voltage, and when the second switch is open, the fifth inductor is not connected to the sixth inductor.

5. The apparatus of any preceding claim, wherein, the device is configured to operate in a transmission mode and a reception mode, wherein: when the device is in the transmission mode, the first switch and the second switch are configured to be open, and the device is configured to receive signaling for transmission from the first set of differential input-output pins; and when the device is in the reception mode, the first switch and the second switch are configured to be closed, and the device is configured to provide signaling received via the antenna pin to the second set of differential input-output pins and third set of differential input-output pins, such that the second set of differential input-output pins and the third set of differential input-output pins are configured to provide the signaling as differential signals to a receiver amplifier arrangement.

6. The device of any preceding claim, wherein: the first switch comprises: a plurality of first PMOS transistors connected in series in a chain, such that a source terminal of a first PMOS transistor in the chain is connected to a drain terminal of an adjacent first PMOS transistor, wherein a first first PMOS transistor in the plurality of first PMOS transistors in the chain has the source terminal connected to the third inductor, and a last first PMOS transistor in the chain has the drain terminal connected to the fourth inductor, and a gate terminal of each of the first PMOS transistors is connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a first switch control terminal; and a plurality of second PMOS transistors, wherein a source terminal of each second PMOS transistor is connected to the second supply terminal, and a drain terminal of each second PMOS transistor is connected to the source terminal of a first PMOS transistor and the drain terminal of its adjacent first PMOS transistor, such that one second PMOS transistor is connected between each pair of first PMOS transistors, and a gate terminal of each second PMOS transistor is connected to a second switch control terminal. a gate terminal of each of the first PMOS transistors is connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a first switch control terminal, and each other first PMOS transistor has a gate terminal connected to a first switch blanking control terminal; and the second switch comprises: a plurality of first NMOS transistors connected in series into a chain such that a source terminal of one first NMOS transistor is connected to a drain terminal of an adjacent first NMOS transistor, wherein the source terminal of a first first NMOS transistor in the chain is connected to the fifth inductor, and the drain terminal of a last first NMOS transistor in the chain is connected to the sixth inductor, and a gate terminal of each of the first NMOS transistors is connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a second switch control terminal; and a plurality of second NMOS transistors, wherein a source terminal of each second NMOS transistor is connected to the second reference terminal, and a drain terminal of each second NMOS transistor is connected to the source terminal of one first NMOS transistor and the drain terminal of its adjacent first NMOS transistor, such that one second NMOS transistor is connected between each pair of first NMOS transistors, and a gate terminal of each second NMOS transistor is connected to a second switch control terminal.

7. The apparatus of any one of claims 1 to 5, wherein: the first switch comprises: a plurality of first PMOS transistors connected in series into a chain such that a source terminal of one first PMOS transistor is connected to a drain terminal of an adjacent first PMOS transistor, wherein the source terminal of a first first PMOS transistor in the chain is connected to the third inductor, and the drain terminal of a last first PMOS transistor in the chain is connected to the fourth inductor, and a gate terminal of the first first PMOS transistor in the chain and a gate terminal of the last first PMOS transistor are connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a first switch control terminal, and a gate terminal of each other first PMOS transistor is connected to a first switch blanking control terminal; and a plurality of second PMOS transistors, wherein a source terminal of each second PMOS transistor is connected to the second supply terminal, and a drain terminal of each second PMOS transistor is connected to the source terminal of one first PMOS transistor and the drain terminal of its adjacent first PMOS transistor, such that one second PMOS transistor is connected between each pair of first PMOS transistors, and a gate terminal of each second PMOS transistor is connected to a first switch blanking control terminal. the second switch comprises: a plurality of first NMOS transistors connected in series into a chain such that a source terminal of one first NMOS transistor is connected to a drain terminal of an adjacent first NMOS transistor, wherein a gate terminal of each of the first NMOS transistors is connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a second switch control terminal; and a plurality of second NMOS transistors, wherein a source terminal of each second NMOS transistor is connected to the second reference terminal, and a drain terminal of each second NMOS transistor is connected to the source terminal of one first NMOS transistor and the drain terminal of its adjacent first NMOS transistor, such that one second NMOS transistor is connected between each pair of first NMOS transistors, and a gate terminal of each second NMOS transistor is connected to a second switch control terminal. the source terminal of a first one of the plurality of first NMOS transistors is connected to the fifth inductor, and the drain terminal of a last one of the plurality of first NMOS transistors in the chain is connected to the sixth inductor, and the gate terminal of the first one of the plurality of first NMOS transistors in the chain and the gate terminal of the last one of the plurality of first NMOS transistors are connected to a first terminal of a respective resistor, and wherein a second terminal of the respective resistor is connected to a second switch control terminal, and the gate terminal of each other first NMOS transistor is connected to a second switch blanking control terminal; and a plurality of second NMOS transistors, wherein the source terminal of each second NMOS transistor is connected to the second reference terminal, and the drain terminal of each second NMOS transistor is connected to the source terminal of one first NMOS transistor and the drain terminal of its adjacent first NMOS transistor, such that one second NMOS transistor is connected between each pair of first NMOS transistors, and the gate terminal of each second NMOS transistor is connected to a second switch blanking control terminal.

8. The device of claim 7, wherein: when the device is in the transmit mode: the first switch is open such that one or more signals provided to the first switch control terminal are configured to render the first one of the plurality of first PMOS transistors in the chain and the last one of the plurality of first PMOS transistors in the chain non-conductive, and one or more signals provided to the first switch blanking control terminal are configured to render each other first PMOS transistor of the plurality of first PMOS transistors and the plurality of second PMOS transistors non-conductive; and the second switch is open such that one or more signals provided to the second switch control terminal are configured to render the first one of the plurality of first NMOS transistors in the chain and the last one of the plurality of first NMOS transistors in the chain non-conductive, and one or more signals provided to the second switch blanking control terminal are configured to render each other first NMOS transistor of the plurality of first NMOS transistors and the plurality of second NMOS transistors non-conductive; and when the device is in the receive mode: the first switch is open such that one or more signals provided to the first switch control terminal are configured to render the first one of the plurality of first PMOS transistors in the chain and the last one of the plurality of first PMOS transistors in the chain conductive, and one or more signals provided to the first switch blanking control terminal are configured to render each other first PMOS transistor of the plurality of first PMOS transistors and the plurality of second PMOS transistors conductive; and ​ ​ The second switch is open such that one or more signals provided to the second switch control terminal are configured to turn on the first one of the plurality of first NMOS transistors in the chain and the last one of the plurality of first NMOS transistors in the chain, and one or more signals provided to the second switch blanking control terminal are configured to turn on each other first NMOS transistor of the plurality of first NMOS transistors and the plurality of parallel NMOS transistors; when the device is in the fast settling mode: one or more signals provided to the first switch blanking control terminal and the second switch blanking control terminal are configured to turn off one or more of the first PMOS transistors in the chain other than the first one and the last one, one or more of the first NMOS transistors in the chain other than the first one and the last one, the second PMOS transistor, and the second NMOS transistor, and one or more signals provided to the first switch control terminal and the second switch control terminal are configured to turn on the first one and the last one of the first PMOS transistors in the chain and the first one and the last one of the first NMOS transistors in the chain while the device is providing signaling to the antenna, and one or more signals provided to the first switch blanking control terminal and the second switch blanking control terminal are configured to turn off one or more of the first PMOS transistors in the chain other than the first one and the last one, one or more of the first NMOS transistors in the chain other than the first one and the last one, the second PMOS transistor, and the second NMOS transistor, and one or more signals provided to the first switch control terminal and the second switch control terminal are configured to turn on the first one and the last one of the first PMOS transistors in the chain and the first one and the last one of the first NMOS transistors in the chain while the device is providing signaling to the antenna, and 9. The apparatus of claim 2 or claim 3, wherein, The receiver amplifier arrangement additionally includes: a first plurality of capacitors configured to at least partially cancel noise within the receiver amplifier arrangement; a second plurality of capacitors configured to at least partially cancel noise within the receiver amplifier arrangement; one or more blanking power supply voltage terminals configured to provide one or more blanking power supply voltages; wherein one or more blanking power supply voltage terminals configured to provide one or more blanking power supply voltages; wherein During the fast settling mode, when the device receives signaling from the antenna, the receiver amplifier arrangement is configured to provide the one or more blanking supply voltages to the first plurality of capacitors and the second plurality of capacitors.

10. The device of claim 2 or claim 3, wherein: a first PMOS transistor of the pair of PMOS transistors includes: a source terminal coupled to a third differential input-output pin; a drain terminal coupled to a first output terminal; a gate terminal coupled to a first terminal of a first portion first capacitor, wherein a second terminal of the first portion first capacitor is coupled to a fourth differential input-output pin; a second PMOS transistor of the pair of PMOS transistors includes: a source terminal coupled to the fourth differential input-output pin; a drain terminal coupled to a second output terminal; a gate terminal coupled to a first terminal of a first portion second capacitor, wherein a second terminal of the first portion second capacitor is coupled to the third differential input-output pin; the first portion of the low noise amplifier circuit further includes: a first portion blanking supply voltage terminal configured to provide a first portion blanking supply voltage; and a first portion blanking transistor having a drain terminal connected to the first portion blanking supply voltage terminal, a source terminal connected to the first terminal of the first portion first capacitor and the first terminal of the first portion second capacitor, and a gate terminal connected to a first portion blanking control terminal; a first NMOS transistor of the pair of NMOS transistors includes: a source terminal coupled to a fifth differential input-output pin; a drain terminal coupled to the first output terminal; a gate terminal coupled to a first terminal of a second portion first capacitor, wherein a second terminal of the second portion first capacitor is coupled to a sixth differential input-output pin; a second NMOS transistor of the pair of NMOS transistors includes: a source terminal coupled to the sixth differential input-output pin; a drain terminal coupled to the second output terminal; a gate terminal coupled to a first terminal of a second portion second capacitor, wherein a second terminal of the second portion first capacitor is coupled to the fifth differential input-output pin; the second portion of the low noise amplifier circuit further includes: a second portion blanking supply voltage terminal configured to provide a second portion blanking supply voltage; and a second portion blanking transistor having a drain terminal connected to the fourth supply voltage terminal, a source terminal connected to the first terminal of the second portion first capacitor and the first terminal of the second portion second capacitor, and a gate terminal connected to a second portion blanking control terminal.

Images