Communication physical link multi-protocol sharing method during parallel operation of energy storage converters

Abstract

The invention discloses a communication physical link multi-protocol sharing method during parallel operation of energy storage converters. The method is based on two general physical links, and efficient sharing of multiple protocols is achieved through the steps of hardware standardization integration, protocol intelligent adaptation, automatic switching of a drive circuit and the links, protocol signal two-way transmission, real-time state monitoring and the like. A unified adaptation platform is built on the hardware level, a multi-protocol special drive circuit and a high-performance MCU are integrated, the protocol level supports dynamic switching and parallel work of multiple protocols such as CAN, I2C, RS485, RJ45 and carrier synchronization signals, and scene changes can be responded without changing hardware. And during operation, through a full-dimension state monitoring and redundancy protection mechanism, transmission stability and rapid fault recovery are guaranteed. Redundant configuration of a special link and a driving circuit is reduced, the space utilization rate of a circuit board and the flexibility of the system are improved, and the diversified communication requirements of large-scale parallel connection of the energy storage converter can be quickly met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of energy storage converter communication, in particular to a method for multiprotocol sharing of physical communication links in parallel operation of energy storage converters. BACKGROUND

[0002] Parallel operation of energy storage converters (PCS) is a configuration mode for large-scale application of new energy storage systems, and its stable operation relies on the coordinated support of multiple communication protocols. Different communication scenarios have significant differences in protocol function requirements. For example, control instruction transmission relies on protocols with strong anti-interference capability, long-distance data interaction requires protocols suitable for long-distance transmission, high-speed state monitoring data requires high-bandwidth protocols, and multi-unit synchronous operation requires a dedicated synchronization signal transmission mechanism.

[0003] Currently, the communication design of energy storage converter parallel systems generally adopts the traditional mode of one-to-one correspondence between protocols, links, and driving circuits. Each communication protocol requires a dedicated physical link and supporting driving components. CAN protocol requires a dedicated CAN transceiver and independent wiring, RS485 protocol relies on a dedicated differential transmission link and driving circuit, RJ45 Ethernet communication requires a separate Ethernet controller and network cable, and carrier synchronization signal requires a dedicated synchronization transmission line. This traditional design has the following problems:

[0004] (1) Serious waste of hardware resources, multiple independent physical links result in a significant increase in cable usage, and the repeated deployment of supporting driving circuits not only increases hardware costs but also occupies more circuit board space, while the utilization rate of each link in actual operation is generally low.

[0005] (2) Insufficient system flexibility, the fixed binding of protocols and links makes the communication mode unable to be dynamically adjusted according to actual operation requirements. When the communication protocol needs to be changed due to scene switching, the hardware link needs to be redeployed or modified.

[0006] (3) Limited scalability, when adding a new communication protocol, the physical link layout and driving circuit adaptation scheme need to be redesigned, which cannot quickly respond to system upgrade requirements. Maintenance difficulty and cost are high, and the parallel deployment of multiple links increases the complexity of cable wiring and fault troubleshooting, reducing the overall reliability of the system.

[0007] Therefore, how to realize efficient sharing of multiple communication protocols in the parallel operation scenario of energy storage converters, reduce the redundant configuration of physical links and hardware components, and improve the flexibility, scalability, and cost-effectiveness of system communication has become a problem that needs to be solved in the current industry. SUMMARY

[0008] To address the issues of hardware redundancy and insufficient flexibility in existing technologies, this invention proposes a method for sharing multiple protocols in the physical communication link when energy storage converters are operating in parallel, through innovative hardware design and protocol adaptation mechanisms.

[0009] The beneficial effects of this invention are as follows:

[0010] (1) This method only requires two general physical links to realize the shared transmission of multiple protocols such as CAN, I2C, RS485, RJ45 and carrier synchronization line, without the need to deploy dedicated links and driver circuits for each protocol. Compared with the traditional one-protocol-one-link design, it reduces the redundant configuration of redundant cables, dedicated transceivers and supporting circuits, reduces the hardware component occupancy by more than 40%, significantly improves the board space utilization, and avoids the resource waste problem of long-term low-load operation of a single protocol link.

[0011] (2) The system supports dynamic switching and parallel operation of protocols without requiring changes to hardware connections. When the parallel operation scenario of the energy storage converter changes, the protocol and link can be re-matched simply by issuing configuration commands through the host computer. For example, switching from "CAN control command transmission" to "RJ45 high-speed status monitoring", or realizing a parallel mode where link A transmits CAN control signals and link B transmits I2C sensor data. The switching process is short and can quickly respond to the communication needs of different operating stages.

[0012] (4) The system has a built-in full-dimensional status monitoring and redundancy protection mechanism. It collects data such as the signal strength of the physical link, the transmission bit error rate, the working temperature of the drive circuit, and the power supply status in real time. Once an abnormality such as link interruption, drive failure or bit error rate exceeding the threshold is detected, it can immediately trigger an audible and visual alarm and record the log. At the same time, it automatically switches to the backup protocol or redundant link, and the fault recovery time is short.

[0013] In summary, this invention, through a design with fewer links and multiple protocols, achieves an optimized balance between cost and reliability while improving resource utilization and flexibility, providing an efficient and economical communication solution for the large-scale parallel application of energy storage converters. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating the method steps of an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the method in an embodiment of the present invention;

[0016] Figure 3 This is a wiring diagram of the method according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This embodiment, based on two common physical links, achieves flexible sharing of multiple protocols such as CAN, I2C, RS485, RJ45, and carrier synchronization signals through hardware standardization integration, intelligent protocol adaptation, and closed-loop status monitoring. The solution can achieve dynamic protocol switching without hardware modifications, ensuring the stability, efficiency, and scalability of multi-unit parallel communication. Figure 1 The specific steps are as follows:

[0019] S1 hardware standardization integration and initialization configuration. For example... Figure 2 As shown, a unified hardware foundation for adapting to multiple protocols is built, and the deployment and parameter configuration from the link to the core control module are completed. The initialization verification ensures that the hardware system meets the electrical and mechanical requirements for multi-protocol transmission.

[0020] S11 general physical link deployment. For example... Figure 3 As shown, two independent physical links are planned, namely Link A and Link B, each configured with an independent RX receiving line and TX transmitting line. The links can use AWG22-24 shielded twisted-pair cable with an internal aluminum foil + braided double-layer shielding structure, a signal level adaptation range covering 0 to 5V, and a transmission rate supporting 0 to 1Mbps. The link characteristics must meet industrial-grade electromagnetic compatibility requirements, resisting electrostatic interference, electromagnetic radiation interference, and conducted interference, providing a stable physical carrier for multi-protocol signal transmission.

[0021] The S12 unit integrates internal circuitry. Each energy storage converter unit's circuit board integrates physical interface circuitry and function selection circuitry. The physical interface circuitry employs industrial-grade protection design, supporting IP67 waterproof and dustproof standards, and is equipped with surge, overvoltage, and overcurrent protection components. The core of the function selection circuitry consists of a high-precision switch matrix and multi-protocol dedicated drive circuitry. The dedicated drive circuitry includes a CAN drive circuit, an RS485 / I2C dual-mode drive circuit, an RJ45 PHY Ethernet drive circuit, and a carrier synchronization drive circuit. Each drive circuit has reserved standardized signal interfaces, and the modular design facilitates maintenance and replacement.

[0022] S13 MCU Core Function Configuration. A 32-bit high-performance microcontroller supporting GPIO multi-function multiplexing is selected, and its communication port expansion and DMA data transfer functions are enabled. The MCU's GPIO ports are soldered to the control terminals of the function selection circuit using gold-plated pads. The GPIO output level is configured to a standard 3.3V logic level, with an output current capability of no less than 20mA. The MCU's CAN, RS485, I2C, Ethernet, and synchronous control ports are enabled, and basic parameter initialization is completed: CAN baud rate is set to 500Kbps, supporting standard and extended frames; RS485 baud rate is set to 9600bps, with 8 data bits, 1 stop bit, and no parity; I2C clock frequency is set to 100KHz, supporting multi-master mode; the Ethernet port is configured in 10 / 100Mbps adaptive mode.

[0023] S14 Parallel Communication Topology Construction. All converter unit physical interface circuit ports are interconnected via industrial-grade RJ45 connectors or dedicated waterproof plugs. All units in Link A have their RX terminals connected to the same bus, and their TX terminals connected to the same bus; Link B uses the same interconnection method, forming a multi-unit, dual-link star parallel communication topology. 120Ω terminating resistors are installed at both ends of the bus to reduce signal reflection interference. After connection, mechanical stability testing is performed to ensure that the plug insertion and extraction force meets industrial standards, and that the contact resistance change under vibration does not exceed 50mΩ.

[0024] S15 System Initialization Verification. After MCU startup, the initialization verification process is automatically executed, sequentially checking the continuity status of the physical link, the power supply voltage of the drive circuit, and the signal integrity of the communication port. When verifying the physical link, a test pulse signal is sent and the reflected wave is detected to determine if there is a short circuit or open circuit. When verifying the drive circuit, the power supply voltage of each drive module is checked to ensure it is within the range of 3.3V ± 0.1V. When verifying the communication port, a self-loop test verifies that the data transmission and reception functions are normal. The verification results are fed back through the MCU's status indicator lights. After all items pass the verification, the system enters standby mode to await protocol configuration commands.

[0025] S2 Protocol Requirements Analysis and Control Command Issuance. Based on the actual scenario of parallel operation of energy storage converters, the protocol type, link allocation, and transmission parameters are clearly defined. Configuration issuance is completed through a standardized command process to ensure the accuracy and timeliness of command transmission.

[0026] S21 Communication Scenario Requirements Analysis. This section comprehensively analyzes the communication requirements of the current parallel operation scenario, including data types, transmission priorities, bandwidth requirements, transmission distance, and synchronization accuracy. Data types are categorized into four types: control commands, status monitoring data, sensor data, and synchronization signals. Transmission priorities are divided into three levels: Level 1 for emergency control commands, Level 2 for status monitoring data, and Level 3 for routine sensor data. Bandwidth requirements are determined based on data volume; large data transmissions require a minimum of 100Mbps, while small data transmissions can be as low as 9600bps. Transmission distance is determined based on the deployment scenario; short-distance scenarios do not exceed 10m, while long-distance scenarios support up to 1200m. Synchronization accuracy requires the phase error of the carrier synchronization signal to not exceed 1μs.

[0027] S22 Protocol and Link Allocation Strategy. An allocation strategy is developed based on requirements analysis, supporting either independent operation of a single protocol or parallel operation of two protocols. First-priority data preferentially uses CAN or RS485 protocols, leveraging their strong anti-interference characteristics to ensure transmission reliability. Second-priority large-volume data uses RJ45 Ethernet protocol to meet high-bandwidth transmission requirements. Third-priority short-range sensor data uses I2C protocol to simplify the communication architecture. Link allocation follows load balancing principles to avoid long-term high-load operation of a single link. When operating in parallel, two links carry different types of protocol data respectively, ensuring transmission efficiency.

[0028] S23 Configuration Command Generation and Encapsulation. Configuration parameters are input via host computer monitoring software or by calling pre-set scenario-based parameter templates. Configuration parameters include the target protocol type, corresponding link number, transmission rate, data frame format, verification method, and synchronization accuracy requirements. After generation, the command is encapsulated in a standardized format, including a command header, parameter segment, checksum segment, and command trailer. The command header uses a fixed identifier field for MCU identification, and the checksum segment uses the CRC32 algorithm to calculate the checksum value, ensuring that the command is not tampered with or corrupted during transmission.

[0029] S24 Command Verification and Encrypted Transmission. The host computer sends the encapsulated command to the MCU of the main converter unit through a pre-connected communication channel. After receiving the command, the MCU first verifies the validity of the command header identifier, and then verifies the integrity of the parameter segment using the CRC32 algorithm. If the verification fails, the MCU sends a retransmission request to the host computer; if the verification succeeds, the command is decrypted, and the core configuration parameters can be extracted using the AES-128 encryption algorithm. The encrypted transmission mechanism prevents the command from being illegally intercepted or tampered with, ensuring the security of the configuration process.

[0030] S25 Instruction Parsing and Control Signal Generation. The MCU parses the decrypted instructions using its built-in parsing algorithm, clarifying the correspondence between the link and protocol, and the transmission parameter requirements. Based on the parsing results, it generates link selection signals and protocol control signals. These signals use a binary encoding format, where the high 4 bits identify the link number and the low 4 bits identify the protocol type. After the control signals are generated, they are stored in the MCU's dedicated buffer, awaiting distribution to the function selection circuit. The signal transmission delay is strictly controlled to within 10μs.

[0031] The S3 drive circuit and link automatically switch. The function selection circuit responds to the MCU control signal, completes link conduction, drive circuit matching and parameter adaptation, establishes a stable link, drive circuit and protocol transmission path, and ensures no signal conflict during the switching process.

[0032] S31 Link Selection Signal Reception and Decoding. The switch matrix of the function selection circuit receives control signals from the MCU and parses the link number and protocol type information in the signals using a built-in decoding module. The decoding process employs hardware decoding to ensure fast response, with a decoding delay not exceeding 5μs. After decoding, the switch matrix locks the target link and protocol, preparing for subsequent path switching.

[0033] S32 Link On / Off Control and Collision Prevention. The switch matrix executes link on / off operations based on the decoding results, employing a disconnect-then-on switching mechanism. Before switching, the currently potentially ongoing path is disconnected to avoid signal collisions between the two links. After the disconnection operation is completed, the target link is connected only after a 2μs delay. The on / off process is implemented through internal relays. The relay contacts are made of silver alloy to reduce contact resistance and ensure that the signal transmission loss after the link is connected does not exceed 0.5dB.

[0034] The S33 driver circuit features precise matching and connection. The switch matrix establishes a physical connection between the conductive link and the corresponding dedicated driver circuit based on the protocol type. When the CAN protocol is selected, the CAN driver circuit is activated; when the I2C protocol is selected, the I2C channel of the RS485 / I2C dual-mode driver circuit is activated; when the RS485 protocol is selected, the RS485 channel of the dual-mode driver circuit is activated; when the RJ45 protocol is selected, the RJ45 PHY Ethernet driver circuit is activated; and when a carrier synchronization signal is selected, the carrier synchronization driver circuit is activated. The driver circuit connections use standardized interfaces to ensure the stability and consistency of signal transmission.

[0035] The S34 driver circuit features adaptive parameter configuration. Upon power-on, the driver circuit automatically initiates a parameter adaptation process, adjusting operating parameters according to the electrical characteristics of the target protocol. The CAN driver circuit adjusts the differential signal amplification factor to 20-40dB to adapt to signal attenuation requirements over different transmission distances; the RS485 driver circuit configures the differential output voltage to 2-6V to meet anti-interference requirements for long-distance transmission; the I2C driver circuit adjusts the rise and fall times of the clock signal to ensure signal integrity at 100kHz or 400kHz clock frequencies; the RJ45 PHY driver circuit is configured in Ethernet rate negotiation mode, automatically matching 10 / 100 / 1000Mbps transmission rates; and the carrier synchronization driver circuit adjusts the PWM signal output amplitude and duty cycle to adapt to the transmission requirements of synchronization signals.

[0036] S35 Driver Circuit Self-Test and Readiness Feedback. After parameter configuration, the driver circuit initiates a comprehensive self-test process, checking key indicators such as power supply status, signal interface connections, amplifier module performance, and filter circuit effectiveness. During the self-test, if an anomaly is detected, a fault signal is sent to the MCU, triggering an alarm mechanism. If the self-test passes, the driver circuit sends a readiness signal to the MCU, indicating that the link, driver circuit, and protocol path have been established and data transmission can begin. The self-test process takes no more than 20μs, ensuring rapid system response.

[0037] S4 protocol signal adaptation and bidirectional transmission execution. Based on the established transmission path, it completes data protocol encapsulation, signal processing, bidirectional transmission, and synchronization calibration to ensure the accuracy, integrity, and synchronization of data transmission.

[0038] S41 Transmitter Data Protocol Encapsulation. The MCU of the transmitter converter encapsulates the data to be transmitted into standard data frames according to the target protocol specification. CAN protocol data frames include an 11-bit or 29-bit ID field, an 8-byte data segment, a 16-bit cyclic redundancy check segment, and an ACK acknowledgement segment; I2C protocol data frames include a 7-bit slave address field, a 1-bit read / write control bit, a data byte segment, and a stop bit; RS485 protocol data frames include a start bit, 8 data bits, a 1-bit stop bit, and an optional parity bit; RJ45 Ethernet protocol data is encapsulated as TCP / UDP packets, including an IP address field, a port number field, a data segment, and a check field; the carrier synchronization signal is encapsulated as a standard PWM pulse signal, including a synchronization start identifier, a timing calibration field, and a pulse sequence.

[0039] S42 Transmitter Signal Conversion and Optimization. After packaging, the MCU converts the data frame into a corresponding electrical signal and transmits it to the matching driver circuit. The driver circuit amplifies, shapes, and filters the electrical signal. Amplification increases the signal amplitude to the protocol-required range, shaping corrects signal distortion, and filtering uses a low-pass filter to remove high-frequency noise. The processed signal is transmitted to the TX line of the physical link through the output of the driver circuit. The signal rise and fall times are controlled within the protocol's allowable range to avoid interference caused by signal overshoot.

[0040] S43 Link Transmission and Interference Suppression. The optimized signal is transmitted through a physical link. The shielded twisted-pair cable of the link suppresses electromagnetic interference, and the double-layer shielding structure reduces the impact of external electromagnetic radiation on the signal while preventing internal signal radiation from interfering with other devices. During transmission, the transmission distance is controlled according to the protocol type: CAN protocol transmission distance is limited to 1000m, RS485 protocol transmission distance is up to 1200m, I2C protocol transmission distance is limited to 10m, and RJ45 Ethernet protocol transmission distance is limited to 100m. For long-distance transmission scenarios, signal repeaters can be added in the middle of the link to ensure that the signal strength meets the reception requirements.

[0041] S44 Receiver Signal Demodulation and Restoration. After receiving the signal transmitted via the link, the physical interface circuit of the receiver converter transmits it to the corresponding drive circuit. The drive circuit demodulates, denoises, and equalizes the received signal. The demodulation process converts the analog signal into a digital signal. The denoising process uses an adaptive noise suppression algorithm to filter out residual noise. The equalization process compensates for amplitude attenuation and phase shift during signal transmission. After processing, the drive circuit transmits the restored standard digital signal to the corresponding communication port of the local MCU, ensuring signal integrity.

[0042] S45 Data Integrity Verification and Parsing. After receiving the digital signal, the receiving MCU performs data integrity verification according to the corresponding protocol specifications. The CAN protocol verifies the cyclic redundancy check value and ACK response status; the I2C protocol verifies the slave address matching; the RS485 protocol verifies the correctness of the check bits; and the RJ45 Ethernet protocol verifies the TCP / UDP checksum field. If the verification passes, the MCU parses the core information in the data frame, extracting control commands, status data, or synchronization signals. If the verification fails, the MCU sends a data retransmission request to the host computer to ensure the accuracy of data transmission.

[0043] S46 Carrier Synchronization Signal Timing Calibration. If a carrier synchronization signal is transmitted, the receiving MCU initiates the timing calibration process after receiving the PWM synchronization signal. The start marker of the synchronization signal is captured by a built-in high-precision timer. The phase difference between the local waveform transmission timing and the synchronization signal is compared, and a PID algorithm is used to dynamically adjust the output frequency and phase of the local oscillator. The calibration process tracks the phase deviation in real time to ensure that the output waveforms of multiple parallel converters are phase-consistent, with the phase error controlled within 1μs, meeting the synchronization requirements for parallel operation.

[0044] S5 provides real-time status monitoring and dynamic adaptation. It continuously monitors key status indicators of the link, drive circuits, and data transmission, supports dynamic protocol switching and intelligent anomaly handling, and ensures the continuity, reliability, and adaptability of the communication system.

[0045] The S51 provides real-time acquisition of comprehensive status data. The MCU's built-in status monitoring module collects key data at a frequency of 10ms / time, covering three main categories of indicators. Link status indicators include signal strength, bit error rate, bus load rate, link impedance, and shielding integrity; driver circuit status indicators include supply voltage, operating temperature, module operating current, amplification factor, and filtering effect; data transmission status indicators include transmission delay time, retransmission count, data frame loss rate, and synchronization phase deviation. The collected data is stored in the MCU's circular buffer, forming a real-time status dataset.

[0046] S52 Status Data Evaluation and Threshold Judgment. The MCU performs real-time evaluation of the collected status data, comparing various indicators with preset thresholds. Signal strength thresholds are set according to protocol type: no less than 0.5V for CAN protocol, no less than 2V for RS485 protocol, and no less than 0.8V for I2C protocol. The transmission bit error rate threshold is set to 0.5%; exceeding this value indicates a link anomaly. The driver circuit operating temperature threshold is set to -40℃ to 85℃; exceeding this range indicates a temperature anomaly. The synchronization phase deviation threshold is set to 1μs; exceeding this value initiates the calibration process. Evaluation results are categorized into three levels: normal, warning, and abnormal, each triggering different processing mechanisms.

[0047] S53 Protocol Dynamic Switching and Parameter Update. When communication requirements change, no hardware modifications are needed; only steps S2 to S4 need to be repeated. The host computer issues a new protocol configuration command, which the MCU parses and generates a switching signal. The function selection circuit automatically re-matches the link and drive circuit. During the switching process, the MCU first pauses the current data transmission, completes the path switching and parameter adaptation, and then resumes transmission. The total switching time does not exceed 100ms, and it does not affect the normal operation of the parallel energy storage converter system. After the switching is completed, the MCU updates the threshold parameters of the status monitoring module to adapt to the operating requirements of the new protocol.

[0048] S54 Anomaly Classification and Redundancy Switching. If the status monitoring module detects an anomaly, it performs classified processing according to the anomaly level. For warning-level anomalies, such as a bit error rate reaching 0.3% or a drive circuit temperature reaching 75℃, the MCU sends a warning message to the host computer and simultaneously adjusts relevant parameters for optimization. For general anomalies, such as link signal interruption, drive circuit failure, or a bit error rate exceeding 0.5%, the MCU immediately triggers an audible and visual alarm mechanism, recording the anomaly occurrence time, anomaly type, and relevant status data to the log. Simultaneously, a redundancy switching strategy is automatically initiated: switching to the RS485 protocol in case of CAN link failure, and switching to a backup link in case of RJ45 link failure, ensuring uninterrupted communication and a fault recovery time of no more than 500ms.

[0049] S55 Historical Data Tracking and Optimization Iteration. The MCU periodically uploads status monitoring logs and anomaly handling records to the host computer, which then establishes a historical database for storage and analysis. By analyzing historical data, it identifies link performance degradation trends, high-incidence periods of driver circuit failures, and scenarios with frequent protocol switching, providing data support for system optimization. Based on the analysis results, protocol allocation strategies can be adjusted, driver circuit parameters optimized, or hardware configuration upgraded to achieve continuous iterative improvement in system communication performance.

[0050] Through the above steps, this embodiment of the invention completes an innovative hardware design and protocol adaptation mechanism, realizing a method for sharing multiple protocols in the physical communication link when energy storage converters are operating in parallel.

[0051] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for multiprotocol sharing of physical communication links when energy storage converters operate in parallel, characterized in that, Comprise the following steps: S1: hardware standardization integration and initialization configuration, build a unified hardware foundation for adapting multiple protocols, complete link deployment, circuit integration, MCU configuration, topology construction and system verification; S2: protocol requirement analysis and control instruction issuing, analyze the communication requirements of energy storage converter parallel operation, develop protocol and link allocation strategy, generate and encrypt configuration instructions; the configuration instructions include protocol type, link number and configuration parameters; S3: drive circuit and link switching, the function selection circuit receives and decodes the control signal, adopts the first break and then on mechanism to turn on the target link, matches the corresponding special drive circuit and adapts the configuration parameters, completes the transmission path establishment; S4: protocol signal adaptation and bidirectional transmission execution, the sending end encapsulates the data frame and optimizes the electrical signal, the received end demodulates and restores the signal after transmission through the link, checks the data integrity, and increases timing calibration if it is a carrier synchronous signal; S5: real-time state monitoring and dynamic adaptive adjustment, periodically collect the state of link, drive circuit and data transmission, evaluate state indicators and handle exceptions in stages, implement protocol dynamic switching and historical data tracing optimization.

2. The method of claim 1, wherein the communication physical link multiplexing method is used in parallel operation of the energy storage converter. The S1 comprises the following steps: S11: general physical link deployment, plan two independent physical links, each link is configured with independent RX receiving line and TX transmission line meeting electromagnetic compatibility requirements; S12: unit circuit integration, each energy storage converter unit circuit board integrates physical interface circuit, function selection circuit and multi-protocol special drive circuit supporting waterproof and dustproof standards; the function selection circuit includes a switch matrix; the multi-protocol special drive includes CAN drive, RS485 I2C dual-mode drive, RJ45 PHY drive and carrier synchronous drive; S13: MCU function configuration, select a microcontroller supporting GPIO multi-function multiplexing, configure GPIO output standard logic level and output current amplitude, enable CAN, RS485, I2C, Ethernet and synchronous control ports and initialize parameters; S14: parallel communication topology construction, interconnect the corresponding ports of all converter unit physical interface circuits through connectors, form a double-link star topology, and install terminal matching resistors at both ends of the bus; S15: system initialization verification, MCU detects link conduction state, drive circuit power voltage and communication port signal integrity, the verification result is fed back through the status indicator light, and the system enters standby state after verification; 3. The method of claim 1, wherein the communication physical link multiplexing method is used in parallel operation of the energy storage converter. The S2 comprises the following steps: S21: communication scenario requirement analysis, sort out data types, divide three transmission priority levels, determine bandwidth, transmission distance and synchronization signal phase error requirements; the data types include control instructions, state monitoring data, sensor data and synchronization signals; S22: protocol and link allocation strategy, first level transmission priority data selects CAN or RS485 protocol, second level transmission priority large data selects RJ45 Ethernet protocol, third level transmission priority short distance sensor data selects I2C protocol, link allocation adopts load balancing principle, and single protocol works independently or double protocols work in parallel; S23: configuration instruction generation and packaging, input parameters or call preset templates through the host computer, and the instruction is packaged in the format of "instruction header, parameter section, verification section, instruction tail". The instruction header includes a fixed identification field for MCU identification; S24: instruction verification and encrypted transmission, the host computer sends the instruction to the main converter unit MCU, the MCU verifies the validity of the instruction header and checks the parameter section, and after successful verification, the parameters are extracted using a decryption algorithm; S25: instruction analysis and control signal generation, MCU analyzes the instruction and generates a binary coded control signal, which includes link number and protocol type.

4. The method of claim 1, wherein the communication physical link multiplexing method is used in parallel operation of the energy storage converter. The S3 includes the following steps: S31: link selection signal receiving and decoding, the switch matrix of the function selection circuit receives the control signal, and the link number and protocol type are analyzed through the decoding module; S32: link conduction and anti-collision control, the switch matrix first disconnects the current path, and then conducts the target link through the contact relay after a short delay. The signal transmission loss is checked to be lower than the threshold value; S33: drive circuit matching and connection, connect the corresponding drive circuit according to the protocol type: CAN protocol connects CAN drive circuit, I2C and RS485 protocol connects double-mode drive circuit corresponding channel, RJ45 protocol connects RJ45 PHY drive circuit, and carrier synchronous signal connects carrier synchronous drive circuit; S34: drive circuit parameter adaptive configuration, CAN drive circuit adjusts the differential signal amplification multiple to 20-40dB, RS485 drive circuit configures differential output voltage 2-6V, I2C drive circuit adjusts clock signal edge time, RJ45 PHY drive circuit configures rate negotiation mode, and carrier synchronous drive circuit adjusts PWM signal amplitude and duty cycle; S35: drive circuit self-checking and ready feedback, the drive circuit detects the states of power supply, interface, amplification module and filter circuit, and sends a fault signal if abnormal, or sends a ready signal if normal.

5. The method of claim 1, wherein the method is used in parallel operation of the energy storage converter, and the physical link is a communication physical link. The S4 includes the following steps: S41: sending end data protocol packaging, package data according to protocol specification: CAN protocol frame contains ID, data section, cyclic redundancy check section and ACK response section, I2C protocol frame contains slave address, read / write control bit and data section, RS485 protocol frame contains start bit, data bit, stop bit and optional check bit, RJ45 protocol is packaged as TCP UDP data packet, and carrier synchronous signal is packaged as PWM pulse signal; S42: sending end signal conversion and optimization, MCU converts data frame into electrical signal and transmits it to the drive circuit, the drive circuit amplifies, shapes and filters the signal, and the control signal edge time is within the protocol allowed range; S43: link transmission and interference suppression, the signal is transmitted through shielded twisted pair, the transmission distance of CAN protocol is less than 1000m, the transmission distance of RS485 protocol is less than 1200m, the transmission distance of I2C protocol is less than 10m, the transmission distance of RJ45 protocol is less than 100m, and a signal repeater is added for long-distance transmission; S44: signal demodulation and restoration at the receiving end, the receiving end drive circuit demodulates, denoises and equalizes the signal, and converts the analog signal into digital signal and transmits it to the local MCU; S45: Data integrity check and analysis, MCU checks data according to protocol: CAN verifies cyclic redundancy check value and ACK, I2C verifies slave address, RS485 verifies check bit, RJ45 verifies TCP UDP check field, and parses information after passing the check, and requests retransmission if it fails; S46: Carrier synchronization signal timing calibration, the receiving end MCU captures the PWM synchronization signal start identifier through the timer, and adjusts the local oscillator parameters by using the PID algorithm to make the phase error less than the threshold value.

6. The method of claim 1, wherein the method is used in parallel operation of the energy storage converter, and the physical link is a communication physical link. The S5 comprises the following steps: S51: Real-time acquisition of state data, the MCU acquires the link state, the driving circuit state and the data transmission state at a preset frequency, and stores the data in a ring buffer; the link state includes signal strength and bit error rate; the driving circuit state includes power supply voltage and temperature; the data transmission state includes delay and retransmission times; S52: State data evaluation and threshold judgment, compare the state indicators with the preset threshold; the evaluation results include normal, early warning and abnormal; S53: Protocol dynamic switching and parameter updating, the host computer issues new instructions when the scene changes, repeats steps S2 to S4 to complete switching, and updates the monitoring threshold after switching; S54: Abnormal hierarchical processing and redundant switching, send early warning information and optimize parameters when early warning, trigger sound and light alarm and record logs when abnormal, and automatically switch to backup protocol or link; S55: Historical data tracing and optimization iteration, the MCU regularly uploads the state logs and abnormal records to the host computer, the host computer establishes a database analysis, and optimizes the protocol allocation and driving parameters.

7. The method of claim 2, wherein the communication physical link multiplexing method is used in parallel operation of the energy storage converter. The general physical link adopts a shielded twisted pair, the signal level adaptation range is 0 to 5V, the transmission rate supports 0 to 1Mbps, and 120Ω terminal matching resistors are arranged at both ends of the bus.

8. The method of claim 1, wherein the method is used in parallel operation of the energy storage converter, and the physical link is a communication physical link. The check of the configuration instruction uses a cyclic redundancy check algorithm, the encrypted transmission of the configuration instruction uses a symmetric encryption algorithm, and the link number and protocol type are identified through binary coded control signals after the instruction is decrypted.

9. The method for sharing multiple protocols in the physical communication link when energy storage converters are operating in parallel according to claim 2, characterized in that, The RX ends of the two independent physical links are connected to the same bus, and the TX ends are connected to the same bus.

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