Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device may include a highly integrated memory cell. The method of manufacturing the semiconductor device may include: forming a first mold stack and a first bonding layer on a substrate; forming a second mold stack and a second bonding layer on the sacrificial substrate; overturning the sacrificial substrate and bonding the first bonding layer and the second bonding layer; removing the sacrificial substrate; and forming a plurality of vertically stacked memory cells in the first mold stack and the second mold stack.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0117590, filed on August 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices including three-dimensional (3D) memory cells, and methods of manufacturing the semiconductor device. Background Technology

[0004] Recently, in response to the trend of increasing the capacity and miniaturization of storage devices, a three-dimensional (3D) storage device in which multiple storage cells are stacked has been proposed. In-depth research is currently underway to improve the structure and performance of 3D storage devices. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices including highly integrated memory cells and methods for manufacturing such semiconductor devices.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, which may include: forming a first mode stack and a first bonding layer on a substrate; forming a second mode stack and a second bonding layer on a sacrificial substrate; flipping the sacrificial substrate and bonding the first bonding layer and the second bonding layer; removing the sacrificial substrate; and forming a plurality of vertically stacked memory cells in the first mode stack and the second mode stack.

[0007] According to one embodiment of this disclosure, a semiconductor device may include: a lower-level array stack of first memory cells; an upper-level array stack of second memory cells; a bonding structure between the lower-level array stack and the upper-level array stack; and a vertical wire penetrating the bonding structure and coupled to both the first memory cell and the second memory cell.

[0008] According to one embodiment of this disclosure, a semiconductor device may include: a lower-level array stack, wherein first memory cells are stacked vertically; an upper-level array stack, wherein second memory cells are stacked vertically; a bonding structure between the lower-level array stack and the upper-level array stack; a bit line that penetrates the bonding structure and is coupled to both the first and second memory cells; and a common electrode that penetrates the bonding structure and is coupled to both the first and second memory cells.

[0009] According to one embodiment of the present disclosure, a semiconductor device may include a stacked structure of a lower-level array stack, a bonding structure, and an upper-level array stack, wherein both the lower-level array stack and the upper-level array stack may include a three-dimensional array of vertically stacked memory cells, and the three-dimensional array may include horizontally oriented switching elements, vertically oriented first wires, and horizontally oriented data storage elements.

[0010] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a first mold stack including multiple mold layers on a substrate; forming a first bonding layer on the first mold stack; forming a second mold stack including multiple mold layers on a sacrificial substrate; forming a second bonding layer on the second mold stack; performing a wafer bonding process using the first bonding layer and the second bonding layer to form a mold stack with high stacking including the first mold stack and the second mold stack; removing the sacrificial substrate; and forming memory cells with high stacking in the mold stack with high stacking.

[0011] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a first mode stack including a first mode layer and a second mode layer epitaxially grown on a substrate; forming a first bonding layer on the first mode stack; forming a second mode stack including the first mode layer and the second mode layer epitaxially grown on a sacrificial substrate; forming a second bonding layer on the second mode stack; bonding the first bonding layer and the second bonding layer to form a mode stack with high stacking including the first mode stack and the second mode stack; and removing the sacrificial substrate. The method may further include forming memory cells with high stacking in the mode stack with high stacking.

[0012] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a first structure including a first mode stack and a first bonding layer on a substrate; forming a second structure including a second mode stack and a second bonding layer on a sacrificial substrate; flipping the second structure and positioning the flipped second structure on the first structure such that the first bonding layer and the second bonding layer are adjacent to each other; bonding the first bonding layer and the second bonding layer; removing the sacrificial substrate after bonding the first bonding layer and the second bonding layer; and forming a plurality of vertically stacked memory cells in the first mode stack and the second mode stack. Forming the vertically stacked memory cells may include replacing the first mode stack with memory cells to form a lower-level array stack of memory cells; and replacing the second mode stack with memory cells to form an upper-level array stack of memory cells. Attached Figure Description

[0013] Figure 1A This is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure.

[0014] Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell.

[0015] Figure 2 This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 3 This is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4A It is along Figure 3 The diagram shows a cross-sectional view of the semiconductor device taken by line A-A'.

[0018] Figure 4B It is along Figure 3 The diagram shows a cross-sectional view of the semiconductor device taken by line B-B'.

[0019] Figures 5 to 27 Various views of a semiconductor device formed using a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0020] Figure 28 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 29A and Figure 29B This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 30A and Figure 30B Various views of a stacked assembly according to embodiments of this disclosure are shown. Detailed Implementation

[0023] This document describes various embodiments of the present disclosure with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structures in the figures may be modified due to manufacturing processes and / or tolerances. Embodiments of the present disclosure are not limited to the specific structures shown in the embodiments and figures, but may include other embodiments or modifications to the embodiments, including any structural changes resulting from manufacturing process requirements. Therefore, the areas shown in the figures are schematic, and the shapes of the areas shown are intended to illustrate specific structures of element regions and are not intended to limit the scope of embodiments of the present disclosure.

[0024] The following embodiments relate to three-dimensional (3D) memory cells, wherein the memory cells are stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0025] According to the following embodiments, a three-dimensional (3D) memory cell array with high stacking can be formed by combining epitaxial growth of semiconductor layers and wafer bonding processes.

[0026] Figure 1A This is a schematic perspective view showing a storage unit MC according to an embodiment of the present disclosure. Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell MC.

[0027] refer to Figure 1A and Figure 1B The storage unit MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0028] The first conductor BL may be oriented perpendicularly to a first direction D1. The first conductor BL may include a bit line. The first conductor BL may be referred to as a "vertical conductor," "vertically oriented bit line," "vertically extended bit line," or "pillar bit line." The first conductor BL may contain a conductive material. The first conductor BL may contain a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL may contain polycrystalline silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductor BL may contain polycrystalline silicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL may contain a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are stacked sequentially.

[0029] A switching element TR has the function of controlling the voltage or current supplied to a data storage element CAP during data write and read operations. The switching element TR may include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL may include a horizontal conductor or a horizontal word line, and the nanosheet HL may include an active layer. The switching element TR may include a transistor, in which case the second conductor WL may serve as a gate electrode. The switching element TR may also be referred to as a "nanosheet transistor," an "access element," or a "select element." The second conductor WL may be referred to as a "horizontal gate electrode" or a "horizontal word line."

[0030] The nanosheet HL can extend along a second direction D2 intersecting the first direction D1. The second conductor WL can extend along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductor WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as a "horizontal layer".

[0031] The nanosheet HL may include a channel CH, a first doped region SR between the channel CH and a first conductive line BL, and a second doped region DR between the channel CH and a data storage element CAP. The first doped region SR may be electrically coupled to the first conductive line BL via a first conductive node BLC and an ohmic contact layer BLO. The second doped region DR may be electrically coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 may be greater than the height of the first doped region SR and the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 may be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 may be equal to each other.

[0032] The nanosheet HL may comprise a first region NS and a second region WS that are horizontally adjacent to each other in a second direction D2. More specifically, the second region WS may extend from one end of the first region NS toward the second contact node SNC. The second region WS may have a thickness that gradually increases from the first region NS toward the data storage element CAP along the second direction D2 between the first region NS and the data storage element CAP. The average vertical height or thickness of the second region WS in the first direction D1 may be greater than that of the first region NS. Hereinafter, the first region NS will be referred to as a "narrow sheet" and the second region WS will be referred to as a "wide sheet".

[0033] The narrow sheet NS can have a flat plate shape. The wide sheet WS can have a fan-shaped shape. The wide sheet WS can have a thickness that gradually increases along the second direction D2. The narrow sheet NS can be referred to as a "flat sheet", and the wide sheet WS can be referred to as a "fan-shaped sheet". The boundary between the narrow sheet NS and the wide sheet WS can have curvature.

[0034] The first doped region SR and the channel CH can be disposed in the narrow wafer NS. The second doped region DR can be disposed in the wide wafer WS. The channel CH formed in the narrow wafer NS can be called a "narrow channel" or a "flat channel". The side of the wide wafer WS facing the data storage element CAP and the side of the second doped region DR in contact with the narrow wafer NS can both have a flat shape.

[0035] In some embodiments, a portion of the second doped region DR may extend to be disposed in a narrow wafer NS (not shown). In such embodiments, the second doped region DR may include a thick portion disposed in a wide wafer WS and a thin portion disposed in a narrow wafer NS.

[0036] The horizontal length of the wide stripe WS in the second direction D2 can be less than that of the narrow stripe NS. For example, the horizontal length of the wide stripe WS in the second direction D2 can be less than 1 / 2 or 1 / 3 of the horizontal length of the narrow stripe NS. The narrow stripe NS can be called a "long stripe", and the wide stripe WS can be called a "short stripe".

[0037] The nanosheet HL may comprise a semiconductor material. For example, the nanosheet HL may comprise polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. In some embodiments, the nanosheet HL may comprise an oxide semiconductor material. For example, the oxide semiconductor material may comprise indium gallium zinc oxide (IGZO), indium tin zinc oxide (InSnZnO), or zinc tin oxide (ZnSnO), or combinations thereof. In some embodiments, the nanosheet HL may comprise a conductive metal oxide. In some embodiments, the nanosheet HL may comprise a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), or molybdenum diselenide (MoSe2).

[0038] When the nanosheet HL is formed from an oxide semiconductor material, the channel CH can also be formed from an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The nanosheet HL can also be called an "active layer" or a "thin body".

[0039] The first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. For example, the first doped region SR and the second doped region DR may be doped with N-type or P-type conductive impurities. The first doped region SR and the second doped region DR may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be electrically coupled to a first conductor BL. The second doped region DR may be electrically coupled to a data storage element CAP. The first and second doped regions SR and DR may be referred to as the "first and second source / drain regions".

[0040] The nanosheet HL can be horizontally oriented in the second direction D2, with its first end electrically coupled to the first wire BL and its second end electrically coupled to the data storage element CAP.

[0041] The second conductor WL may have a gate-all-around (GAA) structure that surrounds the nanosheet HL and extends along the third direction D3. A nanosheet dielectric layer GD may be formed between the nanosheet HL and the second conductor WL. The nanosheet dielectric layer GD may surround a portion of the nanosheet HL, such as the channel CH of the nanosheet HL. The second conductor WL may surround the nanosheet HL on the nanosheet dielectric layer GD. The switching element TR may include a GAA transistor.

[0042] The second conductive line WL may comprise a metal-based material, a semiconductor material, or a combination thereof. The second conductive line WL may comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the second conductive line WL may comprise a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line WL may comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. The second conductive line WL may comprise a stack of low work function materials and high work function materials.

[0043] A nanosheet dielectric layer GD can be disposed between the nanosheet HL and the second conductive line WL. The nanosheet dielectric layer GD can be referred to as a "gate dielectric layer" or a "channel-side dielectric layer". The nanosheet dielectric layer GD may comprise silicon oxide, silicon nitride, metal oxides, metal nitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The nanosheet dielectric layer GD may comprise SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet dielectric layer GD can be formed by depositing a nanosheet dielectric material and thermally oxidizing the nanosheet HL. In some embodiments, the nanosheet dielectric layer GD can be deposited on the nanosheet HL or formed by thermal oxidation of the nanosheet HL.

[0044] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally positioned from the switching element TR along a second direction D2. The data storage element CAP may include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from the nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally positioned along the second direction D2. The first electrode SN may include an internal space and multiple outer surfaces, and the internal space of the first electrode SN may include multiple inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically along a first direction D1, and the horizontal outer surfaces of the first electrode SN may extend horizontally along either the second direction D2 or a third direction D3. The internal space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed within the internal space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically coupled to a second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be coupled to the common plate PL. The first electrode SN can be referred to as the "storage node".

[0045] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, and the first electrode SN having this three-dimensional structure may have a three-dimensional structure horizontally oriented along a second direction D2. As an example of the three-dimensional structure, the first electrode SN may be cylindrical. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically coupled to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN may be disposed on the cylindrical inner surface and the cylindrical outer surface of the first electrode SN. In one embodiment, the first electrode SN may have a semi-cylindrical shape. Specifically, a semi-cylindrical shape may refer to a structure in which the second electrode PN partially covers the outer surface of the first electrode SN.

[0046] In some embodiments, the first electrode SN may be concave, cylindrical, or cylindrical. Cylindrical may refer to a structure that combines cylindrical and cylindrical shapes.

[0047] The first electrode SN and the second electrode PN may comprise metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN) stacks, or combinations thereof. The second electrode PN may also comprise a combination of metal-based materials and silicon-based materials. For example, the second electrode PN may be a titanium nitride / silicon germanium / tungsten nitride stack. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be used as an interstitial filling material to fill the interior of the first electrode SN, titanium nitride (TiN) can be used as the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material. In some embodiments, the second electrode PN may comprise a titanium nitride / tungsten / polycrystalline silicon (TiN / W / Poly-Si) stack.

[0048] The dielectric layer DE can be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer DE may comprise silicon oxide, silicon nitride, high-k materials, perovskite materials, or combinations thereof. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). In some embodiments, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0049] The dielectric layer DE can be formed from a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure comprising zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack can have a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). A ZAZ stack can have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. Both ZA and ZAZ stacks can be referred to as "zirconia (ZrO2) substrates". In some embodiments, the dielectric layer DE can be formed of hafnium (Hf)-based oxides. The dielectric layer DE can have a stacked structure comprising hafnium oxide (HfO2). The dielectric layer DE can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and oxide are stacked on top of hafnium oxide (HfO2). The structure consists of sequentially stacked hafnium (HfO2). Both HA and HAH stacks can be referred to as "hafnium oxide (HfO2) base layers." In ZA, ZAZ, HA, and HAH stacks, the band gap energy of alumina (Al2O3) can be greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of alumina (Al2O3) can be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can comprise a stack of high-k materials and high-bandgap materials with band gap energies greater than those of the high-k materials. Besides alumina (Al2O3), the dielectric layer DE can... The dielectric layer DE incorporates silicon oxide (SiO2) as a high bandgap material. Because the dielectric layer DE contains a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. In some embodiments, the dielectric layer DE may include a stacked structure of alternating high-k and high-bandgap materials. For example, the dielectric layer DE may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, or HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks. Stacked, HAHAH(HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacked, HZAZH(HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stacked, ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2) / HfO2 / ZrO2) stacked, HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2) stacked, or AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stacked.In the above stacked structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0050] In some embodiments, the dielectric layer DE may comprise a high-k material and a high-bandgap material, and the dielectric layer DE may have a laminated structure in which a plurality of high-k materials and a plurality of high-bandgap materials are stacked, or a hybrid structure in which high-k materials and high-bandgap materials are mixed.

[0051] In some embodiments, the dielectric layer DE may comprise a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may comprise HfZrO.

[0052] In some embodiments, the dielectric layer DE may comprise a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0053] In some embodiments, an interface control layer may also be formed between the first electrode SN and the dielectric layer DE to reduce leakage current. The interface control layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0054] Data storage element CAP may include a three-dimensional capacitor. Data storage element CAP may include a metal-insulator-metal (MIM) capacitor. Data storage element CAP may be replaced with other data storage materials. For example, data storage materials may be thyristors, phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0055] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductor BL and the nanosheet HL. The first contact node BLC may contain a metal-based material or a semiconductor material. For example, the first contact node BLC may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may contain doped polycrystalline silicon, and the first doped region SR may contain impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may contain a metal-based material or a semiconductor material. For example, the second contact node SNC may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may contain doped silicon, and the second doped region DR may contain impurities diffused from the second contact node SNC. The height of the first contact node BLC in the first direction D1 may be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 may be greater than the height of the channel CH in the first direction D1.

[0056] In some embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node SNC can be a doped silicon epitaxial layer.

[0057] In some embodiments, the first contact node BLC can be selectively grown from a narrow NS of the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node BLC can be a doped silicon epitaxial layer.

[0058] The first contact node BLC can be a narrow-side contact node, and the second contact node SNC can be a wide-side contact node.

[0059] The nanosheet HL may include a first edge and a second edge. The first edge may refer to the portion of the first doped region SR that is electrically coupled to the first wire BL, while the second edge may refer to the portion of the second doped region DR that is electrically coupled to the first electrode SN of the data storage element CAP.

[0060] The memory cell MC may further include an ohmic contact layer BLO between the first contact node BLC and the first conductive line BL. The ohmic contact layer BLO may contain metal silicide. In some embodiments, the memory cell MC may further include an ohmic contact layer formed between the second contact node SNC and the first electrode SN of the data storage element CAP. The first conductive line BL, the ohmic contact layer BLO, the first contact node BLC, and the first doped region SR may be electrically coupled to each other. The second doped region DR, the second contact node SNC, and the first electrode SN of the data storage element CAP may be electrically coupled to each other.

[0061] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductive line WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductive line BL and the second conductive line WL. The first spacer SP1 and the second spacer SP2 may extend in the third direction D3 and surround the nanosheet HL. That is, the first spacer SP1 and the second spacer SP2 may surround the nanosheet HL and be disposed on the two sidewalls of the second conductive line WL.

[0062] The first spacer SP1 and the second spacer SP2 may have a double-pad structure or a single-pad structure. For example, the first spacer SP1 may have a single-pad structure, and the second spacer SP2 may have a double-pad structure, wherein the double-pad structure of the second spacer SP2 may include a stack of the first pad L1 and the second pad L2. The first spacer SP1 and the second spacer SP2 may contain a dielectric material. The first spacer SP1 and the second spacer SP2 may contain silicon oxide, silicon nitride, or a combination thereof. The first pad L1 of the second spacer SP2 may contain silicon nitride, and the second pad L2 of the second spacer SP2 may contain silicon oxide.

[0063] The first conductor BL may include multiple horizontal extensions BLE1, BLE2, and BLE3. The horizontal extensions BLE1, BLE2, and BLE3 may extend along a second direction D2. The horizontal extensions BLE1, BLE2, and BLE3 may include an inner horizontal extension BLE2 and outer horizontal extensions BLE1 and BLE3. The inner horizontal extension BLE2 of the first conductor BL may be disposed in a recess defined in the first pad L1 of the second spacer SP2 and disposed perpendicularly adjacent to it. Therefore, the inner horizontal extension BLE2 of the first conductor BL may be electrically coupled to the ohmic contact layer BLO.

[0064] The outer horizontal extensions BLE1 and BLE3 of the first conductor BL can extend to be disposed on one side of the second spacer SP2. Therefore, the outer horizontal extensions BLE1 and BLE3 can contact the first pad L1 and the second pad L2 of the second spacer SP2. In some embodiments, the outer horizontal extensions BLE1 and BLE3 of the first conductor BL can be omitted.

[0065] Figure 2 This is a schematic perspective view showing a semiconductor device 100 according to an embodiment of the present disclosure.

[0066] refer to Figure 2 The semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MCs vertically stacked along a first direction D1. The memory cell array MCA may include a plurality of memory cells MCs horizontally arranged along a second direction D2. The memory cell array MCA may include a plurality of memory cells MCs horizontally arranged along a third direction D3.

[0067] Each memory cell MC may include a first conductor BL, a switching element TR, and a data storage element CAP, wherein the switching element TR may include a second conductor WL, a nanosheet dielectric layer GD, and a nanosheet HL. The memory cell MC may also include a first contact node BLC, an ohmic contact layer BLO, and a second contact node SNC. The memory cell MC can be connected to... Figure 1A and Figure 1BThe memory cells MC shown are the same. (See reference...) Figure 1A and Figure 1B The second conductor WL may have a gate all-around (GAA) structure.

[0068] Although not shown, the storage unit MC may include a reference. Figure 1B The first and second spacers are described. The first and second spacers may be disposed on both sides of the second conductor WL and extend along a third direction D3. The first and second spacers may extend along the third direction D3 and surround the nanosheet HL, similar to the second conductor WL.

[0069] The memory cell array MCA may include a column array AR1 of memory cells MC and a row array AR2 of memory cells MC. The column array AR1 may include a plurality of memory cells MC stacked vertically along a first direction D1. The memory cells MC in the column array AR1 may share a first conductor BL. The row array AR2 may include a plurality of memory cells MC arranged horizontally along a third direction D3. The memory cells MC in the row array AR2 may share a second conductor WL. The second conductor WL of the memory cell array MCA may have a structure in which a plurality of surrounds and a plurality of surround-merging portions are merged together. Each surround-merging portion may be disposed in the gap between nanosheets HL, wherein a nanosheet dielectric layer GD is formed.

[0070] The array AR1 may include nanosheets HL arranged vertically along a first direction D1, a first wire BL coupled to the vertically arranged nanosheets HL, and each second wire WL surrounding a different vertically arranged nanosheet HL.

[0071] The row array AR2 may include nanosheets HL arranged horizontally along the third direction D3, with first wires BL all coupled to one of the different horizontally arranged nanosheets HL, and second wires WL surrounding the horizontally arranged nanosheets HL.

[0072] The first direction D1 can be vertical, and the third direction D3 can be horizontal. The memory cell array MCA may also include a horizontal hierarchical array AR3, which may include multiple memory cells MC arranged at the same horizontal level along the second direction D2. Adjacent memory cells MC in the horizontal hierarchical array AR3 may share a first conductor BL.

[0073] A memory cell array (MCA) may include a first sub-cell array (MCA1) and a second sub-cell array (MCA2). Both the first sub-cell array (MCA1) and the second sub-cell array (MCA2) may include a three-dimensional array of memory cells (MC). The first sub-cell array (MCA1) and the second sub-cell array (MCA2) may share a first conductor (BL). The first conductor (BL) may include a first vertical conductor (BLA) and a second vertical conductor (BLB), and the bottom of the first vertical conductor (BLA) and the bottom of the second vertical conductor (BLB) may be merged together. The first conductor (BL) may have a U-shaped shape due to the combination of the first vertical conductor (BLA) and the second vertical conductor (BLB). The memory cells (MC) of the first sub-cell array (MCA1) may share the first vertical conductor (BLA), and the memory cells (MC) of the second sub-cell array (MCA2) may share the second vertical conductor (BLB). Thus, adjacent first sub-cell arrays (MCA1) and second sub-cell arrays (MCA2) may have a mirror structure sharing the first conductor (BL). From a top view, the first vertical conductor (BLA) and the second vertical conductor (BLB) may have a rectangular shape.

[0074] Figure 3 This is a schematic plan view illustrating a semiconductor device 200 according to an embodiment of the present disclosure. Figure 4A It is along Figure 3 The cross-sectional view of semiconductor device 200 taken by line A-A' is shown. Figure 4B It is along Figure 3 The cross-sectional view of semiconductor device 200 taken by line B-B' is shown.

[0075] Figures 3 to 4B The memory cell array MCA of the semiconductor device 200 shown can be similar to Figure 2 The storage cell array MCA shown is illustrated, and the storage cells MC of the storage cell array MCA can be similar to... Figure 1A and Figure 1B The storage unit MC is shown below. Refer to [reference] below. Figure 1A , Figure 1B and Figure 2 Provide a detailed description of the overlapping components.

[0076] refer to Figure 3 , Figure 4A and Figure 4BThe semiconductor device 200 may include a memory cell array (MCA) above a lower structure LS. The memory cell array (MCA) may include a lower-level array stack (MCA10), an upper-level array stack (MCA20), and a bonding structure (BOX). The upper-level array stack (MCA20) may include a first array stack (MCA21) and a second array stack (DMCA). The second array stack (DMCA) may be disposed between the first array stack (MCA21) and the lower-level array stack (MCA10). The second array stack (DMCA) and the bonding structure (BOX) may be in contact with each other. The second array stack (DMCA) may also refer to the bottom of the upper-level array stack (MCA20).

[0077] A bonding structure BOX can be disposed between the upper-level array stack MCA20 and the lower-level array stack MCA10. The upper-level array stack MCA20 and the lower-level array stack MCA10 can be bonded to each other through the bonding structure BOX. The bonding structure BOX may include a stack of a first bonding layer BO1 and a second bonding layer BO2. The first bonding layer BO1 and the second bonding layer BO2 can be bonded by a wafer bonding process. The first bonding layer BO1 can be disposed on the lower-level array stack MCA10, and the second bonding layer BO2 can be disposed below the upper-level array stack MCA20. The first bonding layer BO1 and the second bonding layer BO2 may contain SiO2, SiN, SiCN, SiCO, SiCON, or combinations thereof.

[0078] Both the lower-level array stack MCA10 and the upper-level array stack MCA20 can include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC can include a column array and a row array of memory cells MC. The column array of memory cells MC can include a plurality of memory cells MC stacked along a first direction D1, and the row array of memory cells MC can include a plurality of memory cells MC horizontally arranged along a second direction D2. The row array of memory cells MC can include a plurality of memory cells MC horizontally arranged along a third direction D3. Both the lower-level array stack MCA10 and the upper-level array stack MCA20 can include sub-memory cell arrays arranged adjacent to each other along the second direction D2. Each sub-memory cell array can have a mirror structure, wherein two memory cells MC share a common electrode PL. In some embodiments, the lower-level array stack MCA10 and the upper-level array stack MCA20 of the semiconductor device 200 can also include sub-memory cell arrays with a mirror structure, wherein two memory cells MC share a first conductor BL. When the column array of memory cells MC repeats along the third direction D3, a row array of memory cells MC can be configured.

[0079] The storage cells MC of the storage cell array MCA may include a first storage cell MC10, a second storage cell MC20, and a third storage cell MC21. The first storage cell MC10 and the second storage cell MC20 may have the same components. The third storage cell MC21 may have a similar configuration to the first storage cell MC10 and the second storage cell MC20.

[0080] Return to reference Figure 4A The lower-level array stack MCA10 may include a three-dimensional array of first storage cells MC10, and the upper-level array stack MCA20's first array stack MCA21 may include a three-dimensional array of second storage cells MC20. The upper-level array stack MCA20's second array stack DMCA may include a third storage cell MC21.

[0081] The height of the second array stack DMCA of the upper-level array stack MCA20 can be less than that of the first array stack MCA21. The number of second memory cells MC20 of the first array stack MCA21 can be greater than the number of third memory cells MC21 of the second array stack DMCA. The second memory cells MC20 of the first array stack MCA21 and the third memory cells MC21 of the second array stack DMCA can have different shapes.

[0082] Both the first memory cell MC10 and the second memory cell MC20 may include a first conductor BL, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL, a nanosheet dielectric layer GD, and a nanosheet HL. Both the first memory cell MC10 and the second memory cell MC20 may also include a first contact node BLC, an ohmic contact layer BLO, and a second contact node SNC. Both the first memory cell MC10 and the second memory cell MC20 may also include a first spacer SP1 and a second spacer SP2. The first spacer SP1 and the second spacer SP2 may be disposed on both sides of each second conductor WL. The first spacer SP1 and the second spacer SP2 may extend along a third direction D3 and surround the nanosheet HL, similar to the second conductor WL.

[0083] The upper and lower surfaces of each second conductor WL in the lower-level array stack MCA10 and the upper-level array stack MCA20 may include multiple shallow pits. That is, the upper and lower surfaces of the second conductor WL may not have a flat shape, but may have a non-flat shape due to the multiple shallow pits.

[0084] The lower-level array stack MCA10 may include a first inter-cell dielectric layer IL1 disposed between first memory cells MC10 disposed along a third direction D3. The lower-level array stack MCA10 may include a second inter-cell dielectric layer IL2 disposed between the first memory cells MC10 stacked along a first direction D1. The upper-level array stack MCA20 may include a first inter-cell dielectric layer IL1 disposed between second memory cells MC20 disposed along a third direction D3. The upper-level array stack MCA20 may include a second inter-cell dielectric layer IL2 disposed between the second memory cells MC20 stacked along a first direction D1.

[0085] The first inter-cell dielectric layer IL1 can be disposed between data storage elements CAP along a third direction D3. The second inter-cell dielectric layer IL2 can be disposed between second conductors WL along a first direction D1. Each second inter-cell dielectric layer IL2 may include multiple protrusions. The protrusions of the second inter-cell dielectric layer IL2 may be portions that fill shallow pits in the second conductors WL. The upper and lower surfaces of the second inter-cell dielectric layer IL2 may have non-planar shapes due to the multiple protrusions. Both the uppermost and lowermost second inter-cell dielectric layers IL2 may include combinations of flat and non-flat shapes.

[0086] A third inter-cell dielectric layer IL3 may be formed between data storage elements CAP stacked along the first direction D1. The third inter-cell dielectric layer IL3 may comprise silicon oxide. The third inter-cell dielectric layer IL3 may be disposed along the first direction D1 between the first electrodes SN of the data storage elements CAP.

[0087] The dielectric layers IL1, IL2, and IL3 between the first to third units can each contain silicon oxide, silicon carbide, air gaps, air gap embedded oxides, or combinations thereof.

[0088] The first inter-unit dielectric layer IL1 can be called the "vertical inter-unit dielectric layer". The second inter-unit dielectric layer IL2 can be called the "first inter-unit horizontal dielectric layer", and the third inter-unit dielectric layer IL3 can be called the "second inter-unit horizontal dielectric layer".

[0089] Both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include a plurality of second conductors WL stacked perpendicularly along a first direction D1. Both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include a plurality of nanosheets HL stacked perpendicularly along the first direction D1. Both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include a plurality of data storage elements CAP stacked perpendicularly along the first direction D1. Both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include a plurality of first conductors BL spaced apart along a third direction D3. The lower-level array stack MCA10 may include a lower-level horizontal electrode WLL, and the second array stack DMCA of the upper-level array stack MCA20 may include an upper-level horizontal electrode WLU. The upper-level horizontal electrode WLU and the lower-level horizontal electrode WLL may not surround the nanosheets HL. Both the upper-level horizontal electrode WLU and the lower-level horizontal electrode WLL may have a non-circling shape. The second memory cell MC20 of the first array stack MCA21 may include a second conductor WL, each second conductor WL having a gate all around (GAA) structure, while the third memory cell MC21 of the second array stack DMCA may include an upper-level horizontal electrode WLU having a non-Gate all around shape.

[0090] A first bottom protective layer BT1 may be formed below the first conductor BL, and a second bottom protective layer BT2 may be formed below the common electrode PL. Both the first bottom protective layer BT1 and the second bottom protective layer BT2 may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof. A bottom liner BTL and a nanosheet dielectric layer GD may be formed between the first bottom protective layer BT1 and the underlying structure LS.

[0091] Multiple hard mask layers HM1 and HM2 can be placed on top of the uppermost second conductor WL.

[0092] A first spacer SP1 may be disposed between the second conductor WL and the first electrode SN of the data storage element, and a second spacer SP2 may be disposed between the second conductor WL and the first conductor BL. The second spacer SP2 may be disposed on the upper and lower surfaces of each second inter-cell dielectric layer IL2. The first spacer SP1 may be formed on a first side of the second conductor WL, and the second spacer SP2 may be formed on a second side of the second conductor WL. The first spacer SP1 may cover one side of the second inter-cell dielectric layer IL2. One side of the second inter-cell dielectric layer IL2 may have a spherical shape, and the first spacer SP1 may have a cup-shaped shape, for example... Shape. The first spacer SP1 can cover the spherical shape of the second inter-unit dielectric layer IL2.

[0093] A first spacer SP1 may be disposed between the second conductive wire WL and the second doped region DR. A second spacer SP2 may be disposed between the first conductive wire BL and the second conductive wire WL. The first spacer SP1 and the second spacer SP2 may extend along a third direction D3 and surround the nanosheet HL. That is, the first spacer SP1 and the second spacer SP2 may be disposed on the two sidewalls of the second conductive wire WL and surround the nanosheet HL.

[0094] Both the first spacer SP1 and the second spacer SP2 can have a double-pad structure or a single-pad structure. For example, the first spacer SP1 can have a single-pad structure, and the second spacer SP2 can have a double-pad structure. The double-pad structure of the second spacer SP2 may include... Figure 1B The first spacer L1 and the second spacer L2. Both the first spacer SP1 and the second spacer SP2 may contain dielectric material. The first spacer SP1 and the second spacer SP2 may contain silicon oxide, silicon nitride, silicon carbide, an air gap, or a combination thereof.

[0095] Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can share a second conductor WL. Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can be coupled to different first conductors BL. Switching elements TR stacked along the first direction D1 can share a first conductor BL. Switching elements TR arranged horizontally along the third direction D3 can share a second conductor WL.

[0096] The third inter-cell dielectric layer IL3 can be disposed between the first electrodes SN of the data storage element CAP along the third direction D3. The first electrodes SN stacked along the first direction D1 can be isolated from each other by the third inter-cell dielectric layer IL3. The second electrode PN of the data storage element CAP can be coupled to the common plate PL. The lower-level array stack MCA10 and the upper-level array stack MCA20 can share the common plate PL.

[0097] The third storage cell MC21 of the second array stacked DMCA of the upper-level array stacked MCA20 can be referred to as a "dummy cell". Each third storage cell MC21 of the second array stacked DMCA can include an upper-level horizontal electrode WLU with a single structure. Each third storage cell MC21 of the second array stacked DMCA can include a horizontally arranged bottom first doped region SRD, a bottom channel CHD, and a bottom second doped region DRD. The horizontally arranged bottom first doped region SRD, bottom channel CHD, and bottom second doped region DRD can form the substrate DHL of the upper-level array stacked MCA20. The vertical height or thickness of the substrate DHL can be greater than the vertical height or thickness of each nanosheet HL. The bottom first doped region SRD can be coupled to the first conductor BL and the first contact node BLC, and the bottom second doped region DRD can be coupled to the second contact node SNC and the data storage element CAP.

[0098] In some embodiments, the second array stack DMCA may include a stack of dummy cells.

[0099] In some embodiments, the second array stack DMCA may refer to a portion of the first array stack MCA21. In this case, the second storage unit MC20 of the first array stack MCA21 and the third storage unit MC21 of the second array stack DMCA may have the same configuration.

[0100] The lower-level array stack MCA10 and the upper-level array stack MCA20 can share the first conductor BL and the common electrode plate PL.

[0101] The lower structure LS can be positioned below the level of the memory cell array MCA. The lower structure LS can be made of any material suitable for semiconductor processing. The lower structure LS may contain at least one of conductive, dielectric, and semiconductor materials. Various materials can be formed on the lower structure LS.

[0102] In one embodiment, the underlying structure LS may include a semiconductor substrate. The underlying structure LS may be formed of a silicon-containing material. The underlying structure LS may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. The underlying structure LS may include another semiconductor material, such as germanium. The underlying structure LS may include a group III / V semiconductor substrate, such as a compound semiconductor substrate like gallium arsenide (GaAs). The underlying structure LS may include a silicon-on-insulator (SOI) substrate. The underlying structure LS may be referred to as the "substrate".

[0103] In some embodiments, the lower structure LS may include a metal wiring structure, a dielectric structure, a conductive structure, a bonding pad structure, and another memory or peripheral circuitry portion. For example, the lower structure LS may include a structure in which the peripheral circuitry portion, the metal wiring structure, and the bonding pad structure are stacked sequentially. The peripheral circuitry portion of the memory cell array (MCA) and the lower structure LS may be bonded by wafer bonding. Wafer bonding may include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof. The peripheral circuitry portion of the lower structure LS may be located below the level of the memory cell array (MCA). This may be referred to as a "lower-cell PERI (PUC) structure" or a "peri-cell-on-cell (COP) structure".

[0104] The peripheral circuitry of the lower structure LS may include at least one control circuit for driving the memory cell array MCA. The at least one control circuit in the peripheral circuitry may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit in the peripheral circuitry may include an address decoder circuit, a read circuit, or a write circuit. The at least one control circuit in the peripheral circuitry may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, or a fin-channel transistor (FinFET).

[0105] For example, the peripheral circuitry may include a sub-word line driver and a sense amplifier. A second conductor WL may be coupled to the sub-word line driver. A first conductor BL may be coupled to the sense amplifier.

[0106] In some embodiments, the lower structure LS may include a semiconductor substrate, and the memory cell array MCA may be disposed on the lower structure LS, and the peripheral circuitry may be disposed on the memory cell array MCA. This may be referred to as a "PERI on-cell (POC) structure" or a "PERI lower cell (CUP) structure".

[0107] In some embodiments, the memory cell array (MCA) may include DRAM, embedded DRAM, NAND, FeRAM, STTRAM, PCRAM, or ReRAM.

[0108] Refer again Figure 3 A support layer BLF may be formed between the first conductors BL. The support layer BLF may extend vertically along a first direction D1 and horizontally along a third direction D3. The first conductors BL arranged adjacent to each other in the second direction D2 may be isolated by the support layer BLF. The first conductors BL arranged adjacent to each other in the third direction D3 may be isolated by the support layer BLF and a second spacer SP2. The support layer BLF may contain a dielectric material. The support layer BLF may contain silicon oxide, silicon nitride, an air gap, or a combination thereof. The support layer BLF may be referred to as a "vertical dielectric layer".

[0109] For reference Figures 3 to 4BThe semiconductor device 200 may include a stacked structure of a lower-level array stack MCA10, a bonding structure BOX, and an upper-level array stack MCA20. Both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include a three-dimensional array of vertically stacked memory cells MC. This three-dimensional array may include horizontally oriented switching elements TR, vertically oriented first conductive lines BL, and horizontally oriented data storage elements CAP. The horizontally oriented switching element TR may include a nanosheet HL and a horizontally oriented second conductive line WL. The nanosheet HL may include a first doped region SR, a second doped region DR, and a channel CH between the first doped region SR and the second doped region DR. The horizontally oriented second conductive line WL may have a gate-all-around (GAA) structure, and the GAA structure of the horizontally oriented second conductive line WL may surround all surfaces of the channel CH of the nanosheet HL. The horizontally oriented second conductive line WL may surround the channel CH of the nanosheet HL at the same horizontal level. The horizontally oriented data storage element CAP may include a horizontally oriented first electrode SN, and the first electrode SN may be electrically coupled to the second doped region DR. The data storage element CAP may further include a second electrode PN and a dielectric layer DE between the first electrode SN and the second electrode PN. A vertically oriented first conductor BL may be electrically coupled to a first doped region SR. A horizontally oriented second conductor WL may be spaced from the channel CH by a nanosheet dielectric layer GD. Nanosheets HL may be formed horizontally in a vertical stack.

[0110] From another perspective, reference Figure 4B Semiconductor device 200 may include a stacked structure of a lower-level array stack MCA10, a bonding structure BOX, and an upper-level array stack MCA20. The lower-level array stack MCA10 and the upper-level array stack MCA20 may include a vertical stack in which a second inter-unit dielectric layer IL2 and nanosheets HL are alternately stacked. A first conductor BL is coupled to a first edge of the nanosheet HL and is vertically oriented along the stacking direction (i.e., first direction D1). A second conductor WL includes an inner surface facing the nanosheet HL and an outer surface facing the second inter-unit dielectric layer IL2 and is horizontally oriented along a direction intersecting the stacking direction (i.e., third direction D3). A nanosheet dielectric layer GD is formed between the inner surface of the second conductor WL and the nanosheet HL, and between the outer surface of the second conductor WL and the second inter-unit dielectric layer IL2. Data storage elements CAP are all coupled to different second edges of the nanosheet HL. The nanosheet HL may include a first doped region SR, a second doped region DR, and a channel CH between the first doped region SR and the second doped region DR. The second conductor WL can have a gate all around (GAA) structure, and the gate all around (GAA) structure of the horizontally oriented second conductor WL can surround all surfaces of the channel CH.

[0111] From another perspective, the semiconductor device 200 may include a stacked structure of a lower-level array stack MCA10, a bonding structure BOX, and an upper-level array stack MCA20, and both the lower-level array stack MCA10 and the upper-level array stack MCA20 may include horizontally arranged nanosheets HL and a second wire WL surrounding the horizontally arranged nanosheets HL.

[0112] according to Figures 3 to 4B The lower-level array stack MCA10 and the upper-level array stack MCA20 can be coupled to each other via a bonding structure BOX. The number of layers of memory cells MC, MC10, and MC20 can be increased through the bonding structure BOX.

[0113] Figures 5 to 27 A semiconductor device formed using a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Hereinafter, Figures 5 to 27 The first, second, and third directions in the reference can correspond to the reference. Figures 3 to 4B The first direction D1, the second direction D2, and the third direction D3 are described.

[0114] like Figure 5 As shown, a first-mode stack SB10 may be formed on a substrate 11. The substrate 11 may be made of any material suitable for semiconductor processing. The substrate 11 may contain at least one of a conductive material, a dielectric material, and a semiconductor material. The substrate 11 may contain silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. The substrate 11 may contain other semiconductor materials, such as germanium. The substrate 11 may contain a group III / V semiconductor substrate, such as a compound semiconductor substrate like gallium arsenide (GaAs).

[0115] The first module stack SB10 may include an alternating stack of a first module layer 12 and a second module layer 13. The first module layer 12 may be stacked alternately with the second module layer 13, and the first module layer 12 and the second module layer 13 may be epitaxially grown multiple times to form the first module stack SB10.

[0116] The first template layer 12 and the second template layer 13 can be made of different semiconductor materials. The first template layer 12 may contain silicon germanium or single-crystal silicon germanium. The second template layer 13 may contain single-crystal silicon. The first template layer 12 and the second template layer 13 can be formed by an epitaxial growth process. The bottommost first template layer 12 can act as a seed layer in the epitaxial growth process. The first template layer 12 may be thinner than the second template layer 13. The first template layer 12 may include a first epitaxial growth layer, and the second template layer 13 may include a second epitaxial growth layer.

[0117] In one embodiment, in the first mode stack SB10, multiple monocrystalline silicon-germanium layers can be stacked alternately with multiple monocrystalline silicon layers. For example, the first mode layer 12 can be a monocrystalline silicon-germanium layer, and the second mode layer 13 can be a monocrystalline silicon layer. The stacking of monocrystalline silicon-germanium layers / monocrystalline silicon layers (SiGe / Si stacking) can be performed multiple times. The first mode layer 12 can be referred to as a "sacrificial layer," and the second mode layer 13 can be referred to as a "nanosheet target layer" or a "recessed target layer."

[0118] The first-mode stack SB10 can be referred to as "vertical stacking". The first-mode stack SB10 can be formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystal silicon-germanium layer, and the nanosheet target layer can be a single-crystal silicon layer.

[0119] The thickness ratio of the first mode layer 12 and the second mode layer 13 in the first mode stack SB10 can vary depending on the design. For example, the thickness of the first mode layer 12 can be approximately 5 to 20 nm, and the thickness of the second mode layer 13 can be approximately 50 to 80 nm. Various variations of the first mode layer 12 and the second mode layer 13 in the first mode stack SB10 can vary depending on the design. In some embodiments, a triple stack including first mode layer 12 / second mode layer 13 / first mode layer 12 can be defined at the bottommost and / or topmost part of the first mode stack SB10. The thickness of the second mode layer 13 in the triple stack can be less than that of the second mode layer 13 in the first mode stack SB10. The topmost layer of the first mode stack SB10 can be the first mode layer 12.

[0120] The first-mode stack SB10 can be replaced with the reference through subsequent processes. Figure 4A The lower-level array stack described is MCA10.

[0121] The first bonding layer 14A may be formed on the first mode stack SB10. The first bonding layer 14A may contain a dielectric material, such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first bonding layer 14A may contain SiO2, SiN, SiCN, SiCO, SiCON, or a combination thereof. The first mode stack SB10, the substrate 11, and the first bonding layer 14A may also be referred to as a first structure.

[0122] In some embodiments, an anti-warping layer BSO may be formed on the back side of substrate 11. The anti-warping layer BSO may be made of any material suitable for preventing warping of substrate 11 during subsequent wafer bonding processes. For example, the anti-warping layer BSO may comprise silicon oxide. The anti-warping layer BSO can control stress during the epitaxial growth process of the first mold layer 12 and the second mold layer 13.

[0123] like Figure 6As shown, a second-mode stack SB11 may be formed on a sacrificial substrate 11A. The sacrificial substrate 11A may be made of any material suitable for semiconductor processing. The sacrificial substrate 11A may contain at least one of a conductive material, a dielectric material, and a semiconductor material. The sacrificial substrate 11A may contain silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. The sacrificial substrate 11A may contain other semiconductor materials, such as germanium. The sacrificial substrate 11A may contain a group III / V semiconductor substrate, such as a compound semiconductor substrate like gallium arsenide (GaAs). The sacrificial substrate 11A and substrate 11 may be made of the same material. The sacrificial substrate 11A may be thinner than substrate 11.

[0124] The second-mode stack SB11, like the first-mode stack SB10, comprises alternating stacks of a first-mode layer 12 and a second-mode layer 13. The first-mode layer 12 and the second-mode layer 13 may be alternately stacked on the sacrificial substrate 11A. The first-mode layer 12 and the second-mode layer 13 may be epitaxially grown multiple times to form the second-mode stack SB11. The first-mode layer 12 and the second-mode layer 13 may be made of different semiconductor materials. For example, in one embodiment, the first-mode layer 12 may comprise silicon germanium or single-crystal silicon germanium, while the second-mode layer 13 may comprise single-crystal silicon. The first-mode layer 12 and the second-mode layer 13 may be formed by an epitaxial growth process. The uppermost layer of the second-mode stack SB11 may be one of the second-mode layers 13. The thickness ratio of the first-mode layer 12 and the second-mode layer 13 in the second-mode stack SB11 may vary depending on the design. For example, the thickness of each first-mode layer 12 may be approximately 5 to 20 nm, and the thickness of each second-mode layer 13 may be approximately 50 to 80 nm. Various variations of the first module layer 12 and the second module layer 13 in the second module stack SB11 can be made according to the design. In some embodiments, a triple stack including the first module layer 12 / the second module layer 13 / the first module layer 12 can be defined at the bottommost and / or topmost part of the second module stack SB11. The second module layer 13 of the triple stack can have a smaller thickness than the second module layer 13 of the second module stack SB11.

[0125] The second-mode stack SB11 can be replaced with the reference one through subsequent processes. Figure 4A The upper-level array stacked MCA20 is described.

[0126] The second bonding layer 14B may be formed on the second mode stack SB11. The second bonding layer 14B may contain a dielectric material, such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. The second mode stack SB11, the sacrificial substrate 11A, and the second bonding structure 14B may also be referred to as the second structure.

[0127] For example, the second bonding layer 14B may comprise SiO2, SiN, SiCN, SiCO, SiCON, or a combination thereof. The first bonding layer 14A and the second bonding layer 14B may be made of the same material. The first bonding layer 14A and the second bonding layer 14B may have the same thickness. The first bonding layer 14A and the second bonding layer 14B may be non-epitaxial grown materials. The first bonding layer 14A and the second bonding layer 14B may be formed by deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0128] In some embodiments, an anti-warping layer BSO may be formed on the back side of the sacrificial substrate 11A. The anti-warping layer BSO may be a material used to prevent the sacrificial substrate 11A from warping during subsequent wafer bonding processes. The anti-warping layer BSO may comprise silicon oxide. The anti-warping layer BSO may also control stress during the epitaxial growth process of the first mold layer 12 and the second mold layer 13.

[0129] according to Figure 5 and Figure 6 The substrate 11 can be referred to as the "first wafer" or "donor wafer", while the sacrificial substrate 11A can be referred to as the "second wafer" or "support wafer".

[0130] That is, the first mode stack SB10 can be formed on the first wafer, while the second mode stack SB11 can be formed on the second wafer.

[0131] When multiple silicon and silicon-germanium layers are alternately stacked and epitaxially grown to a thickness not less than a certain value due to stress caused by lattice mismatch between the silicon and silicon-germanium layers, dislocations can occur in the alternating stacking. Dislocations can impair channel characteristics, thereby reducing the reliability of memory cells.

[0132] Since the first mode stack SB10 and the second mode stack SB11 are formed on different wafers in two separate wafers in the embodiments of this disclosure, a stacked structure with a higher stacking density can be stably formed compared to forming the mode stack on a single wafer. Furthermore, since the first mode stack SB10 and the second mode stack SB11 are formed on different wafers in two separate wafers, a dislocation-free epitaxial growth structure can be formed.

[0133] The first-mode stack SB10 may have a "first dislocation-free epitaxial growth structure", and the second-mode stack SB11 may have a "second dislocation-free epitaxial growth structure". The first dislocation-free epitaxial growth structure and the second dislocation-free epitaxial growth structure may be stacks in which single-crystal silicon layers and single-crystal silicon-germanium layers are alternately stacked and epitaxially grown.

[0134] In one embodiment, a Si / SiGe alternating stack with high stacking density and no dislocations can be fabricated by sequentially performing a process of alternatingly stacking Si / SiGe stacks on two wafers, a process of forming a bonding layer, and a process of performing wafer bonding.

[0135] like Figure 7 As shown, the first bonding layer 14A and the second bonding layer 14B can be bonded to form a high-stack structure including a first mode stack SB10 and a second mode stack SB11. For example, the sacrificial substrate 11A can be flipped so that the second bonding layer 14B is at the bottom. The process of flipping the sacrificial substrate 11A on which the second bonding layer 14B is formed can be called "wafer flipping" or "substrate flipping". In one embodiment, the second structure can be flipped and positioned on the first structure such that the first bonding layer 14A and the second bonding layer 14B are adjacent to each other.

[0136] Then, the first bonding layer 14A and the second bonding layer 14B can be bonded together, for example, by any suitable wafer bonding process BP. For example, the first bonding layer 14A and the second bonding layer 14B can be bonded by oxide-oxide bonding. Alternatively, as an example, the wafer bonding process BP can include fusion bonding. Fusion bonding can be referred to as "direct bonding". Fusion bonding can employ chemical bonding of the first bonding layer 14A and the second bonding layer 14B. Specifically, the first bonding layer 14A and the second bonding layer 14B can be fusion bonded to provide a Si-O-Si bond connection between the first mode stack SB1 and the second mode stack SB11.

[0137] In some embodiments, the anti-warping layer BSO can prevent warping of the sacrificial substrate 11A and substrate 11 during the wafer bonding process BP.

[0138] Subsequently, the edges of the substrate 11 and the sacrificial substrate 11A bonded by the wafer bonding process BP can be trimmed.

[0139] like Figure 8 As shown, the sacrificial substrate 11A can be removed. Removing the sacrificial substrate 11A may include: grinding a portion of the sacrificial substrate 11A, and then performing a wet etching process on the remaining portion of the sacrificial substrate 11A. During the wet etching process, the topmost first mode layer 12 of the second mode stack SB11 can be used as an etch stop layer.

[0140] In some embodiments, the anti-warping layer BSO on the sacrificial substrate 11A may be removed before removing the sacrificial substrate 11A. The anti-warping layer BSO disposed on the back side of the substrate 11 can be retained in subsequent processes. Hereinafter, the reference numerals for the anti-warping layer BSO disposed on the back side of the substrate 11 are omitted.

[0141] according to Figure 7 and Figure 8By performing wafer bonding process BP, a mode stack SB can be formed on substrate 11. The mode stack SB may include a dislocation-free epitaxial growth structure and a bonding structure BOX. The dislocation-free epitaxial growth structure may include a first mode stack SB10 and a second mode stack SB11, and the bonding structure BOX may include a first bonding layer 14A and a second bonding layer 14B.

[0142] A first mode stack SB10, a first bonding layer 14A, a second bonding layer 14B, a second mode stack SB11, and a sacrificial substrate 11A can be sequentially stacked on a substrate 11 using a wafer bonding process (BP). The first mode stack SB10, the first bonding layer 14A, the second bonding layer 14B, and the second mode stack SB11 can be a single mode stack SB. The first mode stack SB10, the bonding structure BOX, and the second mode stack SB11 can be sequentially stacked within the mode stack SB. The bonding structure BOX can be positioned between the first mode stack SB10 and the second mode stack SB11. Both the first mode stack SB10 and the second mode stack SB11 can include multiple first mode layers 12 and multiple second mode layers 13. The uppermost first mode layer 12 of the first mode stack SB10 and the lowermost second mode layer 13 of the second mode stack SB11 can directly contact the bonding structure BOX. The first mode stack SB10 and the second mode stack SB11 can be physically and / or chemically discontinuous through the bonding structure BOX.

[0143] The mode stack SB can include a dislocation-free epitaxial growth structure. The first mode stack SB10 can be a first dislocation-free epitaxial growth structure, and the second mode stack SB11 can be a second dislocation-free epitaxial growth structure. Both the first and second dislocation-free epitaxial growth structures can be stacks in which single-crystal silicon layers and single-crystal silicon-germanium layers are alternately stacked and epitaxially grown. That is, both the first and second dislocation-free epitaxial growth structures can be referred to as "Si / SiGe mode stacks".

[0144] The mold stack SB may include a plurality of first mold layers 12 and a plurality of second mold layers 13. The first bonding layer 14A and the second bonding layer 14B of the mold stack SB can be used to distribute stress between the first mold layers 12 and the second mold layers 13. The first bonding layer 14A and the second bonding layer 14B may be referred to as "stress distribution layers".

[0145] The thickness ratio of the first module layer 12 and the second module layer 13 in the module stack SB can vary depending on the design. For example, the thickness of each first module layer 12 can be about 10 nm, and the thickness of each second module layer 13 can be about 70 nm. In some embodiments, the thickness of each first module layer 12 can be about 15 nm, and the thickness of each second module layer 13 can be about 65 nm.

[0146] The number of first mode layers 12 and second mode layers 13 in the first mode stack SB10 and the second mode stack SB11 can vary depending on the design. When using wafer bonding process BP, the critical thickness of the Si / SiGe stack in the mode stack SB can be increased by approximately two times. For example, based on Si / SiGe (70nm / 10nm) stacks, a dislocation-free stack of 139 layers can be achieved, while when using wafer bonding process BP, the number of layers can be 278.

[0147] In some embodiments, a silicon-germanium barrier layer may be pre-formed on the sacrificial substrate 11A before the formation of the second-mode stack SB11. The silicon-germanium barrier layer can serve as a barrier layer during subsequent removal of the sacrificial substrate 11A. The thickness of the silicon-germanium barrier layer may be from 10 nm to 30 nm.

[0148] In some embodiments, silicon oxide may be formed as an anti-warping layer BSO to control stress during the epitaxial growth process forming the first mode stack SB10 and the second mode stack SB11. The silicon oxide of the anti-warping layer BSO may be formed on the back side of the substrate 11 and the sacrificial substrate 11A before or after the wafer bonding process BP.

[0149] according to Figures 5 to 8 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure may include: forming a first mode stack SB10 including a first mode layer 12 and a second mode layer 13 epitaxially grown on a substrate 11; forming a first bonding layer 14A on the first mode stack SB10; forming a second mode stack SB11 including the first mode layer 12 and the second mode layer 13 epitaxially grown on a sacrificial substrate 11A; forming a second bonding layer 14B on the second mode stack SB11; bonding the first bonding layer 14A and the second bonding layer 14B to form a mode stack SB with high stacking including the first mode stack SB10 and the second mode stack SB11; and removing the sacrificial substrate 11A. The mode stack SB with high stacking may include a high stacking structure of the first mode layer 12 and the second mode layer 13.

[0150] Subsequently, a series of processes can be performed on the high-stacked slab to form a structure including a reference slab. Figures 2 to 4B The memory cell array MCA is described as a high-stacked memory cell array MC with a lower-level array stack and an upper-level array stack. For example, the first mode stack SB10 can be replaced by the lower-level array stack MCA10, and the second mode stack SB11 can be replaced by the upper-level array stack MCA20. As will be described later, the second mode layer 13 of the mode stack SB can be transformed into nanosheets, each nanosheet comprising narrow and wide sheets, through a selective recessing process. The first mode layer 12 of the mode stack SB can be removed.

[0151] like Figure 9As shown, multiple sacrificial linear openings 15 and 16 can be formed in the die stack SB. The sacrificial linear openings 15 and 16 may include a first sacrificial linear opening 15 and a second sacrificial linear opening 16. From the top view, the first sacrificial linear opening 15 and the second sacrificial linear opening 16 may be linear openings extending along a third direction D3.

[0152] like Figure 10 As shown, linear sacrificial layers 15L and 16L can be formed to fill the first sacrificial linear opening 15 and the second sacrificial linear opening 16, respectively. Linear sacrificial layers 15L and 16L may include the first linear sacrificial layer 15L and the second linear sacrificial layer 16L. From a top view, the first linear sacrificial layer 15L and the second linear sacrificial layer 16L may have a linear shape extending along a third direction D3. Both the first linear sacrificial layer 15L and the second linear sacrificial layer 16L may extend perpendicularly along a first direction D1. From a top view, both the first linear sacrificial layer 15L and the second linear sacrificial layer 16L may have a rectangular cross-section. In some embodiments, both the first linear sacrificial layer 15L and the second linear sacrificial layer 16L may have a circular or elliptical cross-section. The first linear sacrificial layer 15L and the second linear sacrificial layer 16L may be made of the same material. For example, the first linear sacrificial layer 15L and the second linear sacrificial layer 16L may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or combinations thereof.

[0153] like Figure 11 As shown, in the first linear sacrificial layer 15L and the second linear sacrificial layer 16L, the first linear sacrificial layer 15L can be selectively removed to form a first linear opening 18. The bottom of the first linear opening 18 can extend inside the substrate 11. From a top view, the first linear opening 18 can have a line shape extending along a third direction D3 and be horizontally spaced from the adjacent second linear sacrificial layer 16L along a second direction D2 at a regular spacing.

[0154] Subsequently, the first mold layer 12 can be selectively recessed through the first linear opening 18, leaving only the remaining portion 12A. To selectively recess the first mold layer 12, the difference in etching selectivity between the first mold layer 12 and the second mold layer 13 can be utilized. The first mold layer 12 can be removed using either a wet etching process or a dry etching process. For example, when the first mold layer 12 comprises a silicon-germanium layer and the second mold layer 13 comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer. The remaining portion 12A of the first mold layer 12 can each retain its original thickness.

[0155] like Figure 12As shown, a portion (first portion) of each second mold layer 13 can be selectively recessed to form a vesicle 13P. The selective recessing of the second mold layer 13 can be performed from the first linear opening 18 along the second direction D2. The second mold layer 13 can be recessed using a wet or dry etching process. The original body portion 13A and the vesicle 13P can be formed by the partial recessing of each second mold layer 13. The original body portion 13A can maintain its original thickness T1, while the vesicle 13P can have a thickness T2 less than the original thickness T1. The horizontal length of the original body portion 13A in the second direction D2 can be the same as or different from the horizontal length of the vesicle 13P in the second direction D2; the combination of the original body portion 13A and the vesicle 13P can be referred to as a “preliminary nanosheet.” The vesicle 13P can be referred to as a “flat sheet” or a “protruding vesicle.” As described above, the first portion of the second mold layer 13 can be selectively recessed to form a preliminary nanosheet comprising the original body portion 13A and the vesicle 13P.

[0156] The recessed process used to form the narrow wafer 13P can be referred to as a "thinning process" or "trimming process" for the second module layer 13. To form the narrow wafer 13P, the upper surface, lower surface, and side surfaces of the second module layer 13 can be recessed. The narrow wafer 13P can be referred to as a "thin active layer." The narrow wafer 13P may include a monocrystalline silicon layer. The recessed process used to form the narrow wafer 13P can use, for example, Hot SC-1 (HSC1). HSC1 may contain a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. Using HSC1, the second module layer 13 can be selectively etched.

[0157] Narrow sheets 13P can be formed by a localized recessing process of the second mold layer 13 as described above, and inter-sheet recesses 19 can be formed between the vertically arranged narrow sheets 13P. Both the upper and lower surfaces of the narrow sheets 13P can be flat surfaces. The boundary portion between the original body portion 13A and the narrow sheets 13P can be vertical or curved. Each first mold layer 12A can be disposed between the vertically stacked original body portions 13A. The horizontal arrangement of the narrow sheets 13P can be formed along a third direction D3. The vertical arrangement of the narrow sheets 13P can be formed along a first direction D1. The inter-sheet recesses 19 can be referred to as "vertical gaps" between the vertically arranged narrow sheets 13P.

[0158] In the 13P narrow film, the narrow film (i.e., the film 13D) above the bonding structure BOX can be thicker than other 13P narrow films.

[0159] like Figure 13 As shown, a nanosheet dielectric layer 20 can be formed on the exposed portion of the narrow strip 13P. The nanosheet dielectric layer 20 can be used as a "gate dielectric layer".

[0160] The nanosheet dielectric layer 20 can be formed by oxidizing the surface of the narrow strip 13P. In some embodiments, the nanosheet dielectric layer 20 can be formed by a process of depositing silicon oxide and a process of oxidizing the surface of the narrow strip 13P. The nanosheet dielectric layer 20 may comprise silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 20 may comprise SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 20 may be conformally formed on the surface of the narrow strip 13P. The nanosheet dielectric layer 20 may extend to form on the exposed surfaces of the first mold layer 12A and the original body portion 13A. The nanosheet dielectric layer 20 may be formed on the exposed surfaces of the substrate 11 and the film 13D. The nanosheet dielectric layer 20 can be formed on a portion of the first bonding layer 14A and a portion of the second bonding layer 14B of the bonded structure BOX.

[0161] like Figure 14 As shown, a first spacer layer 21A may be formed on the nanosheet dielectric layer 20. The first spacer layer 21A may contain silicon nitride. The first spacer layer 21A may surround and cover the narrow strip 13P on the nanosheet dielectric layer 20. The first spacer layer 21A may be thicker than the nanosheet dielectric layer 20.

[0162] A first inter-unit horizontal dielectric material 22A may be formed on the first spacer layer 21A. The first inter-unit horizontal dielectric material 22A may comprise silicon oxide. The first spacer layer 21A and the first inter-unit horizontal dielectric material 22A may fill the inter-nanosheet recess 19 between the nanosheets 13P. The first spacer layer 21A and the first inter-unit horizontal dielectric material 22A may partially fill the first linear opening 18.

[0163] like Figure 15 As shown, a portion of the first inter-unit horizontal dielectric material 22A can be cut through the first linear opening 18. Therefore, the first inter-unit horizontal dielectric material can be retained as a plurality of first inter-unit horizontal dielectric material layers 22, as indicated by the reference numeral "22".

[0164] Subsequently, the first spacer layer 21A can be selectively recessed through the first linear opening 18 to form the first spacer 21. With the formation of the first spacer 21, a linear surrounding recess 23 can be formed on the nanosheet dielectric layer 20, surrounding the narrow strip 13P. A horizontal dielectric layer 22 between each first unit can be disposed between the vertically arranged linear surrounding recesses 23. The first spacer 21 can surround the narrow strip 13P at the same horizontal level along a third direction D3.

[0165] like Figure 16As shown, a horizontal guide 24 can be formed to fill the linear surrounding recess 23. The horizontal guide 24 can extend horizontally along the third direction D3. The horizontal guide 24 can correspond to a reference. Figures 2 to 4B The second conductor WL is described.

[0166] Forming the horizontal conductive line 24 may include: depositing a conductive material on the nanosheet dielectric layer 20 to fill the linear surrounding recess 23; and performing a horizontal etch-back process on the conductive material. The horizontal etch-back process on the conductive material may be performed from the first linear opening 18 along the second direction D2. The horizontal conductive line 24 may simultaneously surround a narrow strip 13P at the same horizontal level. The horizontal conductive line 24 may comprise a metal, a metal-based material, a semiconductor material, or a combination thereof.

[0167] The horizontal conductor 24 may comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the horizontal conductor 24 may comprise a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The horizontal conductor 24 may comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or lower, while the P-type work function material may have a high work function of 4.5 eV or higher. A horizontal dielectric layer 22 between each first unit may be disposed between the plurality of horizontal conductors 24 along a first direction D1. The horizontal conductor 24 surrounding the narrow strip 13P may be referred to as a “gate all-around (GAA) electrode.” The narrow strip 13P may be referred to as a “nanopie channel,” a “nanowire,” or a “nanowire channel.”

[0168] The lower-level horizontal electrode 24L can be formed on the surface of the substrate 11. The upper-level horizontal electrode 24U can be formed on the film 13D. Both the lower-level horizontal electrode 24L and the upper-level horizontal electrode 24U can have a non-circular shape.

[0169] like Figure 17 As shown, a second spacer 25 may be formed on the side of each horizontal conductor 24. The second spacer 25 may be formed by depositing and etching spacer material. The etching of the spacer material may include an etch-back process. The etch-back process of the spacer material may be performed from the first linear opening 18 along the second direction D2. The second spacer 25 may comprise silicon oxide, silicon nitride, silicon carbide, embedded air gap, or a combination thereof. Simultaneously or subsequently, a bottom pad 25D may be formed on the side of the lower-level horizontal electrode 24L. The bottom pad 25D and the second spacer 25 may be made of the same material. The second spacer 25 may extend along a third direction D3. The second spacer 25 may surround a narrow strip 13P of the same horizontal level disposed along the third direction D3.

[0170] Subsequently, a deposition and etch-back process for the first bottom protective layer 26 can be performed. The first bottom protective layer 26 may contain a dielectric material such as spin-on dielectric (SOD). The first bottom protective layer 26 may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0171] After the first bottom protective layer 26 is formed, a portion of the nanosheet dielectric layer 20 can be cut to expose one side of each narrow strip 13P.

[0172] like Figure 18 As shown, one side of each narrow strip 13P and a portion of the nanosheet dielectric layer 20 may be horizontally recessed in the second direction D2 to form a nanosheet-level recess 27 through the recess of the narrow strip 13P. The nanosheet-level recess 27 may be a side recess disposed in the second spacer 25.

[0173] like Figure 19 As shown, a first contact node 28 can be formed to fill the nanosheet-level recess 27. Forming the first contact node 28 may include depositing a conductive material to fill the nanosheet-level recess 27 and performing a row etch-back process on the conductive material. The first contact node 28 may comprise a semiconductor material. The first contact node 28 may comprise doped polysilicon having an N-type dopant. The first contact node 28 can fill the nanosheet-level recess 27 formed between the second spacers 25.

[0174] A first doped region 29 may be formed on one side of each narrow wafer 13P. A thermal processing process may be performed to form the first doped region 29 by diffusing dopant from the first contact node 28. Simultaneously with the formation of the first doped region 29, a bottom first doped region 29D may be formed in the substrate 13D.

[0175] Another method for forming the first contact node 28 may include selective epitaxial growth (SEG) of doped semiconductor material.

[0176] like Figure 20 As shown, a vertical conductor 30 can be formed on the first contact node 28. Before forming the vertical conductor 30, an ohmic contact layer can be formed on the first contact node 28. Ohmic contact layer reference. Figure 1A and Figure 1B The ohmic contact layer BLO shown is described.

[0177] The vertical conductor 30 can be coupled together with the vertically positioned narrow strip 13P and the first contact node 28. The vertical conductor 30 can correspond to... Figure 1A , Figure 1B , Figure 2 , Figure 3 and Figure 4A The first conductor BL is shown in the diagram. The vertical conductor 30 may include a reference. Figure 1A and Figure 1BThe description includes multiple horizontal extensions, BLE1, BLE2, and BLE3.

[0178] The vertical conductor 30 may comprise a metallic base material. The vertical conductor 30 may comprise titanium nitride, tungsten, or a combination thereof.

[0179] Forming the vertical conductor 30 may include a deposition and etching process of the vertical conductor material. The vertical conductor 30 may extend vertically along a first direction D1. Vertical conductors 30 arranged adjacent to each other along a second direction D2 may be coupled to each other. That is, narrow strips 13P arranged adjacent to each other in the second direction D2 may share the vertical conductor 30. The vertical conductor 30 may be U-shaped.

[0180] A support member 31 or a support layer may be formed on the vertical conductor 30. The support member 31 may extend vertically along a first direction D1 and horizontally along a third direction D3. The vertical conductors 30 arranged adjacent to each other in the third direction D3 may be isolated by the support member 31. The support member 31 may contain a dielectric material. The support member 31 may contain silicon oxide, silicon nitride, an air gap, or a combination thereof. The support member 31 may be an isolation layer between the vertical conductors 30 arranged adjacent to each other in the third direction D3. The support member 31 may be referred to as a "vertical dielectric layer". The support member 31 may fill the first linear opening 18.

[0181] like Figure 21 As shown, a second hard mask layer 32 may be formed on the first hard mask layer 17, the vertical conductor 30, and the support member 31. The second hard mask layer 32 may include linear openings.

[0182] The second hard mask layer 32 can be used as a barrier layer to remove the second linear sacrificial layer 16L. This forms the second linear opening 33.

[0183] After the second linear opening 33 is formed, the first mold layer 12A can be selectively removed along the second direction D2 through the second linear opening 33. To selectively remove the first mold layer 12A, the difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be utilized. The first mold layer 12A can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a monocrystalline silicon layer, an etchant or etching gas selective relative to the monocrystalline silicon layer can be used to etch the silicon-germanium layer. When the first mold layer 12A is removed, the upper and lower surfaces of the original body portion 13A can be exposed.

[0184] like Figure 22 As shown, the original body portion 13A can be selectively recessed using a wet or dry etching process. The vertical thickness of the original body portion 13A can be reduced, as indicated by the reference numeral "13S". Hereinafter, the original body portion 13A will be referred to as the "recessed portion 13S".

[0185] An interbody recess 13R can be formed between the vertically set concave portions 13S.

[0186] like Figure 23 As shown, a second inter-unit horizontal dielectric layer 34 can be formed to fill the inter-unit recess 13R. The second inter-unit horizontal dielectric layer 34 may contain silicon oxide.

[0187] After forming the second inter-unit horizontal dielectric layer 34, a second bottom protective layer 33T may be formed at the bottom of the second linear opening 33. The second bottom protective layer 33T may include a material with etch selectivity relative to the substrate 11. The second bottom protective layer 33T may contain a dielectric material. The second bottom protective layer 33T may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0188] After forming the second bottom protective layer 33T, a storage opening 35 and a wide plate 13E can be formed by selectively recessing the recessed portion 13S. The storage opening 35 may be referred to as a "capacitor opening". The wide plate 13E may refer to the remaining recessed portion 13S after recessing. The average vertical height of the wide plate 13E in the first direction D1 may be greater than the average vertical height of the narrow plate 13P. The thickness of the wide plate 13E may gradually increase in the second direction D2. The horizontal length of the wide plate 13E in the second direction D2 may be less than the horizontal length of the narrow plate 13P. Each wide plate 13E may have a fan-shaped shape. The wide plate 13E may be referred to as a "fan-shaped plate", while the narrow plate 13P may be referred to as a "flat plate".

[0189] To form the wafer 13E, the concave portion 13S can be etched isotropically or anisotropically. One side of each wafer 13E, i.e., the side exposed by the storage opening 35, can have a flat shape. One side of the wafer 13E can have various shapes. For example, one side of the wafer 13E can have a rounded concave shape, a rounded convex shape, an angular concave shape, or an angular convex shape.

[0190] The second bottom protective layer 33T and the bottommost second inter-unit horizontal dielectric layer 34 can prevent the loss of substrate 11 during the recess process of recess portion 13S.

[0191] Each storage opening 35 can be disposed between the second cell horizontal dielectric layers 34 along the first direction D1.

[0192] When forming the wide film 13E, a portion of the negative 13D may be horizontally recessed.

[0193] In some embodiments, the horizontal recess of the recessed portion 13S used to form the wide sheet 13E may stop at the boundary region between the narrow sheet 13P and the wide sheet 13E.

[0194] Each narrow 13P and each wide 13E can form a nanosheet HL.

[0195] The first spacer 21 can surround a wide strip 13E of the same horizontal level on the third direction D3, and the second spacer 25 can surround a narrow strip 13P of the same horizontal level on the third direction D3.

[0196] like Figure 24 As shown, a pre-cleaning process can be performed on the surface of the wide sheet 13E.

[0197] A second contact node 36 may be formed on the wafer 13E. The formation of the second contact node 36 may include selective epitaxial growth (SEG). For example, semiconductor material may be grown from the side of the wafer 13E by selective epitaxial growth (SEG). The second contact node 36 may contain SEG Si. Since the wafer 13E contains monocrystalline silicon, a silicon layer may be epitaxially grown along the crystal surface of the side of the wafer 13E.

[0198] The second contact node 36 may contain a dopant. When a silicon layer is grown using selective epitaxial growth (SEG), the dopant can be doped in situ. Therefore, the second contact node 36 may be a doped epitaxial layer. The second contact node 36 may contain an N-type dopant. The N-type dopant may include phosphorus, arsenic, antimony, or combinations thereof. The second contact node 36 may include a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., doped SEG SiP. In some embodiments, the second contact node 36 may be formed by a deposition and etch-back process of doped polysilicon.

[0199] Each second contact node 36 may be disposed between the horizontal dielectric layers 34 of the vertically stacked second cells. The second contact node 36 may correspond to Figure 4B The second contact node SNC is shown.

[0200] A second doped region 37 can be formed in the wide wafer 13E. A thermal processing process can be performed to form the second doped region 37, so that the dopant can diffuse from the second contact node 36. Simultaneously with the formation of the second doped region 37, a bottom second doped region 37D can be formed in the substrate 13D.

[0201] The channel 38 may be defined between each first doped region 29 and each second doped region 37. The horizontal arrangement of the first doped region 29, the channel 38, and the second doped region 37 can form a nanosheet HL. The bottom channel 38D may be defined between each bottom first doped region 29D and each bottom second doped region 37D. The horizontal arrangement of the bottom first doped region 29D, the bottom channel 38D, and the bottom second doped region 37D can be formed in the substrate 13D.

[0202] Each nanosheet HL may include a first doped region 29, a second doped region 37, and a channel 38. The first doped region 29 and the channel 38 may be formed in each narrow wafer 13P, while the second doped region 37 may be formed in each wide wafer 13E. A portion of the second doped region 37 may extend into the narrow wafer 13P. One side of the second doped region 37 of the nanosheet HL may be coupled to the channel 38, and the other side of the second doped region 37 of the nanosheet HL may be coupled to a second contact node 36.

[0203] The first spacer 21 may surround the second doped region 37 at the same horizontal level on the third direction D3, and the second spacer 25 may surround the first doped region 29 at the same horizontal level on the third direction D3. The horizontal conductor 24 may surround the channel 38 at the same horizontal level along the third direction D3.

[0204] In some embodiments, an ohmic contact layer comprising metal silicide may also be formed after the second contact node 36 is formed.

[0205] As described above, the second module layer 13 of the module stack SB may include nanosheets HL formed by a subsequent selective recess process, each nanosheet HL may include narrow wafers 13P and wide wafers 13E. A first doped region 29 and a channel 38 may be formed in the narrow wafer 13P, and a second doped region 37 may be formed in the wide wafer 13E.

[0206] like Figure 25 As shown, the first electrode 39 of the data storage element can be formed on the second contact node 36. Each first electrode 39 can have a horizontally oriented cylindrical shape. Each first electrode 39 can be disposed in a different storage opening 35. First electrodes 39 disposed adjacent to each other in the second direction D2 can be spaced apart from each other by a second linear opening 33. First electrodes 39 disposed adjacent to each other in the first direction D1 can be spaced apart from each other by a second inter-cell horizontal dielectric layer 34. Forming the first electrode 39 may include depositing a metallic material, an interstitial sacrificial material, and an insulating metallic material in the vertical / horizontal directions. The sacrificial material may comprise oxide or polysilicon.

[0207] Each first electrode 39 may include an internal space and multiple outer surfaces. The internal space of the first electrode 39 may include multiple inner surfaces. The outer surfaces of the first electrode 39 may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode 39 may extend vertically along a first direction D1, and the horizontal outer surfaces of the first electrode 39 may extend horizontally along a second direction D2 or a third direction D3. The internal space of the first electrode 39 may be three-dimensional, and the first electrode 39 may be cylindrical.

[0208] In the outer surface of the first electrode 39, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 36.

[0209] The first electrode 39 may comprise a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 39 may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or a combination thereof.

[0210] like Figure 26 As shown, a portion of the second inter-cell horizontal dielectric layer 34 may be horizontally recessed (refer to reference numeral "34R"). Therefore, the outer wall of the first electrode 39 may be partially exposed. The first electrode 39 may have a semi-cylindrical shape. The depth of the horizontal recess in the second inter-cell horizontal dielectric layer 34 may be a depth that does not expose the second contact node 36. The semi-cylindrical shape of each first electrode 39 may include a cylindrical inner surface and a semi-cylindrical outer surface.

[0211] like Figure 27 As shown, a dielectric layer 40 and a second electrode 41 can be sequentially formed on the first electrode 39. The first electrode 39, the dielectric layer 40, and the second electrode 41 can form a data storage element CAP. The second electrode 41 of the data storage element CAP can be merged together to form a common electrode PL.

[0212] The dielectric layer 40 and the second electrode 41 may be disposed on the cylindrical inner surface of the first electrode 39. A portion of the dielectric layer 40 and a portion of the second electrode 41 may extend to be disposed on the semi-cylindrical outer surface of the first electrode 39. The second electrode 41 may extend perpendicularly along the first direction D1.

[0213] The dielectric layer 40 may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 40 may comprise silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 40 may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Dielectric layer 40 may include ZA (ZrO2 / Al2O3) stacks, ZAZ (ZrO2 / Al2O3 / ZrO2) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HA (HfO2 / Al2O3) stacks, HAH (HfO2 / Al2O3 / HfO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (... Stacked structures include HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2, HZAZH(HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2), ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2), or AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3).

[0214] The second electrode 41 may comprise a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the second electrode 41 may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or a combination thereof. The second electrode 41 may also comprise a combination of a metal-based material and a silicon-based material. For example, titanium nitride, tungsten, and polycrystalline silicon may be stacked sequentially in the second electrode 41.

[0215] In some embodiments, an interface control layer may be formed between the first electrode 39 and the dielectric layer 40 to mitigate leakage current. The interface control layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 41 and the dielectric layer 40.

[0216] In some embodiments, this can be omitted. Figure 26 The second unit inter-unit horizontal dielectric layer 34 is shown as a recess. Thereafter, as... Figure 27 As shown, a dielectric layer 40 and a second electrode 41 can be formed. Therefore, a data storage element CAP including a concave first electrode 39 can be formed.

[0217] refer to Figures 5 to 27 A method for manufacturing a semiconductor device according to one embodiment may include: forming a first mold stack SB10 on a substrate 11 in which a first mold layer 12 and a second mold layer 13 are alternately stacked; forming a first bonding layer 14A on the first mold stack SB10; forming a second mold stack SB11 on a sacrificial substrate 11A in which the first mold layer 12 and the second mold layer 13 are alternately stacked; forming a second bonding layer 14B on the second mold stack SB11; and flipping the sacrificial substrate 11A on which the second mold stack SB11 is formed to bond the first bonding layer 14B. A bonding layer 14A and a second bonding layer 14B are formed, a sacrificial substrate 11A is removed, a narrow strip 13P and an original body portion 13A are formed by selectively recessing the second layer 13 of the first mode stack SB10 and the second mode stack SB11, a horizontal conductor 24 is formed around the narrow strip 13P, a vertical conductor 30 is formed that is coupled to one side of the narrow strip 13P, a wide strip 13E is formed by selectively recessing the original body portion 13A, and data storage elements CAP are formed that are coupled to different wide strips 13E respectively.

[0218] According to the above embodiments, since the first mode stack SB10 and the second mode stack SB11, including the first mode layer 12 and the second mode layer 13 of epitaxial growth, are bonded by wafer bonding when forming a three-dimensional array of memory cells, a dislocation-free epitaxial growth structure with high stacking density can be formed, thereby increasing the number of layers of memory cells.

[0219] Figure 28 This is a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of the present disclosure.

[0220] like Figure 28As shown, the semiconductor device 300 may include three memory cell array stacks MCA11, MCA12, and MCA13, and three bonding structure BOXes. Each bonding structure BOX may be disposed between the memory cell array stacks MCA11, MCA12, and MCA13. The memory cell array stacks MCA11, MCA12, and MCA13 may share a vertical conductor BL. The vertical conductor BL may pass through the bonding structure BOX. The memory cell array stacks MCA11, MCA12, and MCA13 may include a first memory cell array stack MCA11, a second memory cell array stack MCA12, and a third memory cell array stack MCA13. The first to third memory cell array stacks MCA11, MCA12, and MCA13 may each include a three-dimensional memory cell array.

[0221] Each bonded structure BOX may have a dual structure of a first bonded dielectric layer BO1 and a second bonded dielectric layer BO2. The first bonded dielectric layer BO1 and the second bonded dielectric layer BO2 may contain SiO2, SiN, SiCN, SiCO, SiCON or a combination thereof.

[0222] In some embodiments, the semiconductor device 300 may have at least four or more memory cell arrays stacked vertically by a bonding structure BOX.

[0223] Figure 29A and Figure 29B This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0224] like Figure 29A As shown, a semiconductor device COP may include a memory cell array (MCA), a peripheral circuitry section (PERI), and a bonding interface (BS). The bonding interface BS may be disposed between the memory cell array (MCA) and the peripheral circuitry section (PERI). In the semiconductor device COP, the memory cell array (MCA) may be disposed at a higher level than the peripheral circuitry section (PERI). The semiconductor device COP may be referred to as a "peri (PUC) structure under a cell array." The memory cell array (MCA) may include a substrate (on which back-side grinding is performed) and a memory cell array. For example, as shown in the reference... Figure 27 After forming the data storage element CAP, the substrate 11 can be flipped by wafer flipping, and then the substrate 11 can be partially back-side ground.

[0225] like Figure 29BAs shown, a semiconductor device POC may include a memory cell array (MCA), a peripheral circuitry section (PERI), and a bonding interface (BS). The bonding interface BS may be disposed between the memory cell array (MCA) and the peripheral circuitry section (PERI). In the semiconductor device POC, the memory cell array (MCA) may be disposed at a lower level than the peripheral circuitry section (PERI). The semiconductor device POC may be referred to as a "Peri-Under-Cell Array (CUP) structure." The formation of the peripheral circuitry section (PERI) may include forming multiple control circuits on the peripheral circuitry substrate and forming multi-level interconnects on the control circuits.

[0226] exist Figure 29A and Figure 29B In this context, the memory cell array (MCA) may include Figure 28 The semiconductor device 300 shown. That is, Figure 29A and Figure 29B The illustrated memory cell array (MCA) may include at least one or more of the memory cell array stacks MCA11, MCA12, and MCA13, and at least one or more of the bonding structures (BOX). In some embodiments, Figure 29A and Figure 29B The memory cell array (MCA) shown may include a lower-level array stack (MCA10), a bonding structure (BOX), and an upper-level array stack (MCA20), as shown in the reference. Figure 4A As stated above.

[0227] exist Figure 29A and Figure 29B In this context, the bonding interface BS may include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof. Hybrid bonding may refer to a combination of pad bonding and oxide-oxide bonding. Pad bonding may include forming cell bonding pads for a memory cell array, forming peripheral circuit bonding pads for peripheral circuit portions, performing wafer flipping to make the cell bonding pads and peripheral circuit bonding pads face each other, and performing wafer bonding.

[0228] Figure 29A The semiconductor device COP shown can perform wafer flipping on the substrate on which the memory cell array is formed after the cell bonding pads and peripheral circuit bonding pads are formed, so that the cell bonding pads and peripheral circuit bonding pads face each other. Figure 29B The semiconductor device POC shown can be wafer flipped after forming the unit bonding pads and peripheral circuit bonding pads, so that the unit bonding pads and peripheral circuit bonding pads face each other.

[0229] Figure 30A and Figure 30B Various views of a stacked assembly according to one embodiment of the present disclosure are shown.

[0230] like Figure 30A As shown, the stacked assembly 400 may include a component of semiconductor dies. For example, the stacked assembly 400 may include a first semiconductor die BSD and a plurality of second semiconductor dies 401. The first semiconductor die BSD may include logic circuitry. Each of the second semiconductor dies 401 may include a stack of memory cell arrays according to the above embodiments. Each of the second semiconductor dies 401 may include a reference... Figure 28 The storage cell array stacks MCA11, MCA12 and MCA13, and the bonding structure BOX, contain at least one or more of the following:

[0231] The second semiconductor die 401 may include a structure in which the memory cell array is stacked and the peripheral circuit portion is stacked, for example Figure 29A The semiconductor device shown has COP or Figure 29B The semiconductor device proof of concept (POC) is shown. The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 401. The second semiconductor die 401 may be chip-level or wafer-level.

[0232] The second semiconductor die 401 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 401 can be electrically coupled to each other through the bonding interface (CBS). The second semiconductor die 401 can be referred to as a "core die", "semiconductor chip", or "memory chip".

[0233] Bonding interfaces (CBS) may include microbump bonding, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0234] like Figure 30B As shown, the stacked assembly 500 may include a component of semiconductor dies. For example, the stacked assembly 500 may include a first semiconductor die BSD, a plurality of second semiconductor dies 501, and a plurality of third semiconductor dies 502. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 501 and each third semiconductor die 502 may include a stack of memory cell arrays according to the above embodiments. The second semiconductor dies 501 and the third semiconductor dies 502 may have different structures. For example, each second semiconductor die 501 and each third semiconductor die 502 may include a reference. Figure 28 The storage cell array stacks MCA11, MCA12 and MCA13, and the bonding structure BOX, contain at least one or more of the following:

[0235] Each second semiconductor die 501 may include Figure 29A The semiconductor device COP shown includes a memory cell array stacked on top of a peripheral circuitry portion. Each third semiconductor die 502 may include... Figure 29B The semiconductor device POC shown has its peripheral circuitry stacked on top of the memory cell array.

[0236] In some embodiments, each second semiconductor die 501 may include Figure 29B The semiconductor device POC shown includes peripheral circuitry stacked on top of a memory cell array, and each third semiconductor die 502 may include... Figure 29A The semiconductor device COP shown has a memory cell array stacked on top of the peripheral circuitry.

[0237] The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 501 and the third semiconductor die 502. The second semiconductor die 501 and the third semiconductor die 502 may be chip-level or wafer-level.

[0238] The second semiconductor die 501 and the third semiconductor die 502 are electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 501 are electrically coupled to each other through the bonding interface (CBS). The second semiconductor die 501 and the third semiconductor die 502 may be referred to as "core dies," "semiconductor chips," or "memory chips."

[0239] Bonding interfaces (CBS) may include microbump bonding, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0240] Figure 30A and Figure 30B The stacked components 400 and 500 shown can be high-bandwidth memories.

[0241] According to various embodiments of this disclosure, since the stacked molds are bonded by wafer bonding when forming a three-dimensional array of memory cells, a dislocation-free epitaxial growth structure can be formed, thereby increasing the number of layers of memory cells.

[0242] According to various embodiments of this disclosure, a high-stack dislocation-free silicon / silicon-germanium layer stack can be formed by wafer bonding.

[0243] While embodiments of this disclosure have been described and illustrated in conjunction with specific examples and accompanying drawings, the disclosed embodiments are not intended to limit this disclosure. Furthermore, it should be noted that those skilled in the art, based on their understanding of this disclosure, can implement the embodiments through various means such as substitution, alteration, and modification without departing from the spirit and / or scope of this disclosure and its appended claims. Moreover, these embodiments can be combined to form other embodiments.

Claims

1. A method of fabricating a semiconductor device, the method comprising: forming a first die stack and a first bonding layer on a substrate; forming a second die stack and a second bonding layer on a sacrificial substrate; inverting the sacrificial substrate and bonding the first bonding layer and the second bonding layer; removing the sacrificial substrate; and forming a plurality of vertically stacked memory cells in the first die stack and the second die stack. forming the vertically stacked memory cells comprises:

2. The method of claim 1, wherein, replacing the first die stack with the memory cells and forming a lower tier array stack of the memory cells; and replacing the second die stack with the memory cells and forming an upper tier array stack of the memory cells. the first bonding layer and the second bonding layer each comprise a dielectric material.

3. The method of claim 1, wherein, the first bonding layer and the second bonding layer each comprise SiO2, SiN, SiCN, SiCO, SiCON, or a combination thereof.

4. The method of claim 1, wherein, the substrate and the sacrificial substrate each comprise single crystalline silicon.

5. The method of claim 1, wherein, in each of the first die stack and the second die stack, a first semiconductor layer is alternately stacked with a second semiconductor layer such that the first semiconductor layer and the second semiconductor layer are epitaxially grown.

6. The method of claim 1, wherein, in each of the first die stack and the second die stack, the first semiconductor layer comprises silicon germanium and the second semiconductor layer comprises single crystalline silicon.

7. The method of claim 5, wherein, the first die stack and the second die stack each include a stack of dislocation free epitaxial growth layers.

8. The method of claim 1, wherein, forming the plurality of vertically stacked memory cells comprises:

9. The method of claim 1, wherein, forming a nanosheet; forming a horizontal wire encircling the nanosheet; forming a vertical wire coupled to one side of each of the nanosheets; and forming a data storage element coupled to another side of each of the nanosheets.

10. A semiconductor device, comprising: a lower tier array stack of first memory cells; an upper tier array stack of second memory cells; a bonding structure between the lower tier array stack and the upper tier array stack; and a vertical wire through the bonding structure and commonly coupled to the first memory cells and the second memory cells. the bonding structure comprises a dielectric material. the bonding structure comprises SiO2, SiN, SiCN, SiCO, SiCON, or a combination thereof.

11. The semiconductor device of claim 10, wherein, the bonding structure includes a double bonding layer.

12. The semiconductor device of claim 10, wherein, the bonding structure includes an oxide-oxide bond.

13. The semiconductor device of claim 10, wherein, the first memory cells and the second memory cells are vertically stacked, and 14. The semiconductor device of claim 10, wherein, wherein the first memory cells and the second memory cells each include:

15. The semiconductor device of claim 10, wherein, a nanosheet horizontally oriented; a vertical wire coupled to one side of the nanosheet; a horizontal wire encircling the nanosheet; and a data storage element coupled to another side of the nanosheet. the data storage element includes: a first electrode coupled to the nanosheet; 16. The semiconductor device of claim 15, wherein, a dielectric layer on the first electrode; and a second electrode on the dielectric layer.

17. A method of fabricating a semiconductor device, the method comprising: forming a first structure including a first die stack and a first bonding layer on a substrate; forming a second structure including a second die stack and a second bonding layer on a sacrificial substrate; ​ ​ turning over the second structure and positioning the turned over second structure on the first structure such that the first bonding layer and the second bonding layer are adjacent to each other; bonding the first bonding layer and the second bonding layer; removing the sacrificial substrate after bonding the first bonding layer and the second bonding layer; and forming a plurality of vertically stacked memory cells in the first and second die stacks.

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