Semiconductor device and manufacturing method thereof

Abstract

Embodiments of the present disclosure relate to a semiconductor device including a highly integrated memory cell and a method of manufacturing the semiconductor device, the semiconductor device may include: a plurality of nanosheets vertically stacked; a first wire commonly coupled to a first edge of the nanosheet, the first wire being vertically oriented; a plurality of data storage elements, each data storage element coupled to a second edge of the nanosheet; a plurality of second conductive lines, each second conductive line surrounding the nanosheets and oriented horizontally; and a plurality of inter-cell dielectric layers disposed between the second conductive lines, each inter-cell dielectric layer including an air gap.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0118377, filed on September 2, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including a three-dimensional (3D) memory cell and a method of manufacturing the same. Background Technology

[0004] Recently, in order to address the trend of large capacity and miniaturization of storage devices, a three-dimensional (3D) storage device in which multiple storage cells are stacked has been proposed. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices including highly integrated memory cells, and methods of manufacturing such semiconductor devices.

[0006] According to one embodiment of the present disclosure, a semiconductor device may include: a plurality of vertically stacked nanosheets; a first wire that is commonly coupled to a first edge of the nanosheets and is vertically oriented; a plurality of data storage elements that are each coupled to a second edge of the nanosheets; a plurality of second wires that surround the nanosheets and are horizontally oriented; and a plurality of inter-unit dielectric layers disposed between the second wires and each inter-unit dielectric layer including an air gap.

[0007] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device may include: forming a vertically stacked and spaced-apart nanosheet target layer on a substrate; trimming a first portion of the nanosheet target layer and forming a flat sheet; forming a first spacer layer defining an interior space in the upper and lower portions of the flat sheet; forming an air gap target layer that fills the interior space; forming a release barrier layer at the entrance of the interior space and a release path between the release barrier layers; removing the air gap target layer through the release path and forming an initial air gap; forming an air gap forming layer that fills the initial air gap and embeds the air gap in the air gap forming layer; horizontally recessing the first spacer layer to form a first spacer covering the sides of the air gap forming layer and surrounding recesses exposing the upper and lower portions of the flat sheet; and forming horizontal wires that fill the surrounding recesses and are located between the air gap forming layers.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a target layer of nanosheets that are vertically stacked and spaced apart from each other in a first direction on a substrate; trimming a first portion of the target layer of nanosheets and forming a narrow strip extending along a second direction intersecting the first direction; forming an initial air gap between the narrow strips stacked in the first direction; forming an air gap forming layer that fills the initial air gap and has air gap embeddings in the air gap forming layer; forming surrounding recesses between the air gap forming layers that expose the narrow strips in a third-direction upward direction intersecting the first and second directions; and forming horizontal wires that fill the surrounding recesses in a third-direction upward direction and are disposed between the air gap forming layers.

[0009] These and other features and advantages of the embodiments of this disclosure will be better understood by those skilled in the art through the following accompanying drawings and detailed description. Attached Figure Description

[0010] Figure 1A This is a schematic perspective view illustrating a storage unit according to an embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A A schematic cross-sectional view of the storage cell shown.

[0012] Figure 2A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2B yes Figure 2A A schematic perspective view of the memory cell array shown.

[0014] Figure 2C yes Figure 2B The equivalent circuit diagram of the column array shown is shown.

[0015] Figure 2D yes Figure 2B The equivalent circuit diagram of the row array shown is shown.

[0016] Figure 3 This is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4A It is along Figure 3 The image shows a cross-sectional view of the semiconductor device taken by line A-A'.

[0018] Figure 4B It is along Figure 3 The cross-sectional view of the semiconductor device shown is taken by line B-B'.

[0019] Figures 5A to 26BVarious views of a semiconductor device formed using a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0020] Figure 27 and Figure 28 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 29 and Figure 30 A stacked assembly according to an embodiment of the present disclosure is shown. Detailed Implementation

[0022] This document describes various embodiments of the present disclosure with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structures in the figures may be modified due to manufacturing processes and / or tolerances. Embodiments of this disclosure are not limited to the specific structures shown in the embodiments and figures, but may include other embodiments or modifications to the embodiments, including any structural changes that may arise due to manufacturing process requirements. Therefore, the areas shown in the figures are schematic in nature, and the shapes of the areas shown in the figures are intended to illustrate specific structures of element regions and are not intended to limit the scope of embodiments of this disclosure.

[0023] The following embodiments relate to three-dimensional (3D) memory cells, wherein the memory cells are stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0024] Figure 1A This is a schematic perspective view illustrating a storage unit MC according to an embodiment of the present disclosure. Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell MC.

[0025] Reference Figure 1A and Figure 1B The storage unit MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0026] The first conductor BL may be oriented perpendicularly along a first direction D1. The first conductor BL may include a bit line. The first conductor BL may be referred to as a "vertical conductor," "vertically oriented bit line," "vertically extended bit line," or "pillar bit line." The first conductor BL may include a conductive material. The first conductor BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductor BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked.

[0027] A switching element TR controls the voltage or current supply to a data storage element CAP during a data write or read operation. The switching element TR may include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL may include a horizontal conductor or a horizontal word line, and the nanosheet HL may include an active layer. The switching element TR may include a transistor, in which case the second conductor WL may serve as a gate electrode. The switching element TR may also be referred to as a "nanosheet transistor," an "access element," or a "select element." The second conductor WL may be referred to as a "horizontal gate electrode" or a "horizontal word line."

[0028] The nanosheet HL can extend along a second direction D2 intersecting the first direction D1. The second conductor WL can extend along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductor WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as a "horizontal layer".

[0029] The nanosheet HL may include a channel CH, a first doped region SR between the channel CH and a first conductive line BL, and a second doped region DR between the channel CH and a data storage element CAP. The first doped region SR may be electrically coupled to the first conductive line BL, and the second doped region DR may be electrically coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 may be greater than the heights of the first doped region SR and the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 may be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 may be equal to each other.

[0030] The nanosheet HL may include a first region NS and a second region WS that are horizontally arranged adjacent to each other in a second direction D2. The second region WS may extend continuously from the first region NS without any gaps. The second region WS may have a thickness that gradually increases from the first region NS toward the data storage element CAP in the second direction D2. The average vertical height or thickness of the second region WS in the first direction D1 may be greater than the average vertical height or thickness of the first region NS. Hereinafter, the first region NS is referred to as a "narrow sheet", and the second region WS is referred to as a "wide sheet".

[0031] The narrow sheet NS can have a flat plate shape. The wide sheet WS can have a fan-shaped shape. The wide sheet WS can have a thickness that gradually increases in the second direction D2. The narrow sheet NS can be called a "flat sheet", while the wide sheet WS can be called a "fan-shaped sheet". The boundary between the narrow sheet NS and the wide sheet WS can have curvature.

[0032] The first doped region SR and the channel CH can be disposed in the narrow wafer NS, while the second doped region DR can be disposed in the wide wafer WS. The channel CH formed in the narrow wafer NS can be referred to as a "narrow channel" or a "flat channel". One side of the contact data storage element CAP of the wide wafer WS and one side of the second doped region DR can both have a flat side shape.

[0033] In some embodiments, a portion of the second doped region DR may extend to be disposed in the narrow wafer NS. The second doped region DR may include a thick portion disposed in the wide wafer WS and a thin portion disposed in the narrow wafer NS.

[0034] The horizontal length of the wide slice WS in the second direction D2 can be less than the horizontal length of the narrow slice NS. Therefore, the narrow slice NS can be called a "long slice", while the wide slice WS can be called a "short slice".

[0035] Nanosheets HL may include semiconductor materials. For example, nanosheets HL may include polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. In some embodiments, nanosheets HL may include oxide semiconductor materials. For example, oxide semiconductor materials may include indium gallium zinc oxide (IGZO), InSnZnO, ZnSnO, or combinations thereof. In some embodiments, nanosheets HL may include conductive metal oxides. In some embodiments, nanosheets HL may include two-dimensional materials, such as at least one of molybdenum disulfide (MoS2), tungsten disulfide (WS2), or molybdenum diselenide (MoSe2).

[0036] When the nanosheet HL is formed from an oxide semiconductor material, the channel CH can also be formed from an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The nanosheet HL can also be referred to as an "active layer" or "thin body".

[0037] The first doped region SR and the second doped region DR can be doped with impurities of the same conductivity type. The first doped region SR and the second doped region DR can be doped with either N-type or P-type conductive impurities. The first doped region SR and the second doped region DR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR can be electrically coupled to a first conductive line BL, while the second doped region DR can be electrically coupled to a data storage element CAP. The first doped region SR and the second doped region DR can be referred to as the "first source / drain region" and the "second source / drain region".

[0038] The nanosheet HL can be horizontally oriented from the first wire BL along the second direction D2.

[0039] The second conductor WL can have a gate-all-around (GAA) structure. For example, the second conductor WL can surround the nanosheet HL and extend along a third direction D3. A nanosheet dielectric layer GD can be formed between the nanosheet HL and the second conductor WL. The nanosheet dielectric layer GD can surround a portion of the nanosheet HL, such as the channel CH of the nanosheet HL. The second conductor WL can surround the nanosheet HL on the nanosheet dielectric layer GD. The switching element TR can include a GAA transistor.

[0040] The second conductor WL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductor WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the second conductor WL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductor WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. The second conductor WL may include a stack of low work function materials and high work function materials.

[0041] A nanosheet dielectric layer (GD) can be disposed between the nanosheet HL and the second conductive line WL. The nanosheet dielectric layer GD can be referred to as a "gate dielectric layer" or a "channel-side dielectric layer." The nanosheet dielectric layer GD can include silicon oxide, silicon nitride, metal oxides, metal nitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The nanosheet dielectric layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet dielectric layer GD can be formed by a combination of deposition of the nanosheet dielectric material and thermal oxidation of the nanosheet HL. In some embodiments, the nanosheet dielectric layer GD can be deposited on the nanosheet HL or formed by thermal oxidation of the nanosheet HL.

[0042] The data storage element CAP may include a storage element for storing data. The data storage element CAP may be, for example, a capacitor. The data storage element CAP may be horizontally disposed along a second direction D2, starting from a switching element TR. The data storage element CAP may include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally along the second direction D2, starting from a nanosheet HL. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed along the second direction D2. The first electrode SN may include an internal space and multiple outer surfaces, and the internal space of the first electrode SN may include multiple inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically along a first direction D1, while the horizontal outer surfaces of the first electrode SN may extend horizontally along the second direction D2 or a third direction D3. The internal space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed on the dielectric layer DE within the internal space of the first electrode SN. Some outer surfaces of the first electrode SN may be electrically coupled to a second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be coupled to the common board PL. The first electrode SN can be referred to as the "storage node".

[0043] The data storage element CAP can have a three-dimensional structure. The first electrode SN can also have a three-dimensional structure, and this three-dimensional structure can be horizontally oriented along a second direction D2. As an example of the three-dimensional structure, the first electrode SN can be cylindrical. The cylindrical shape of the first electrode SN can include an inner surface and an outer surface. Some of the outer surfaces of the first electrode SN can be electrically coupled to the second doped region DR of the nanosheet HL. The dielectric layer DE and the second electrode PN can be disposed on the inner and outer surfaces of the first electrode SN. In one embodiment, the first electrode SN can have a semi-cylindrical shape. Specifically, the semi-cylindrical shape can refer to a structure in which the second electrode PN partially covers the outer surface of the first electrode SN.

[0044] In some embodiments, the first electrode SN may be concave, cylindrical, or cylindrical. A cylindrical shape may refer to a structure that combines cylindrical and cylindrical shapes.

[0045] The first electrode SN and the second electrode PN can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode PN can also include a combination of metal-based materials and silicon-based materials. For example, the second electrode PN can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be an interstitial filling material filling the interior of the first electrode SN, titanium nitride (TiN) can be the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material. In some embodiments, the second electrode PN may comprise a titanium nitride / tungsten / polycrystalline silicon (TiN / W / Poly-Si) stack.

[0046] The dielectric layer (DE) can be referred to as a "capacitor dielectric layer" or a "storage layer." The dielectric layer (DE) may include silicon oxide, silicon nitride, high-k materials, perovskite materials, or combinations thereof. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). In some embodiments, the dielectric layer (DE) may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0047] The dielectric layer DE can be formed of zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure comprising zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack can have a structure where alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). A ZAZ stack can have a structure where zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. Both ZA and ZAZ stacks can be referred to as a "zirconia (ZrO2) base layer." In some embodiments, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure comprising hafnium oxide (HfO2). The dielectric layer DE can include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. HA stacks can have a structure where alumina (Al₂O₃) is stacked on hafnium oxide (HfO₂). HAH stacks can have a structure where hafnium oxide (HfO₂), alumina (Al₂O₃), and hafnium oxide (HfO₂) are stacked sequentially. Both HA and HAH stacks can be referred to as a "hafnium oxide (HfO₂) base layer." In ZA, ZAZ, HA, and HAH stacks, the band gap energy of alumina (Al₂O₃) can be higher than that of zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). The dielectric constant of alumina (Al₂O₃) can be lower than that of zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, the dielectric layer DE can include a stack of high-k materials and high-bandgap materials, where the band gap energy of the high-bandgap material is greater than that of the high-k material. The dielectric layer DE can include silicon oxide (SiO₂) as a high-bandgap material other than alumina (Al₂O₃). Because the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. In some embodiments, the dielectric layer DE may include a stacked structure in which high-k materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, etc. HZAZH(HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stacking, ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2) stacking, HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2) stacking, or AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2) stacking 2 / HfO2 / Al2O3) stack. In the above stacked structure, the alumina (Al2O3) layer can be thinner than the zirconium oxide (ZrO2) layer and the hafnium oxide (HfO2) layer.

[0048] In some embodiments, the dielectric layer DE may include a high-k material and a high-bandgap material, and the dielectric layer DE may have a laminated structure in which multiple high-k materials and multiple high-bandgap materials are stacked, or a hybrid structure in which high-k materials and high-bandgap materials are mixed.

[0049] In some embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0050] In some embodiments, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0051] In some embodiments, an interface control layer (not shown) may also be formed between the first electrode SN and the dielectric layer DE to mitigate leakage current. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or combinations thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0052] Data storage element CAP can include a three-dimensional capacitor. Data storage element CAP can include a metal-insulator-metal (MIM) capacitor. Data storage element CAP can be replaced with another data storage material. For example, the data storage material can be a thyristor, phase change material, magnetic tunnel junction (MTJ), or variable resistance material.

[0053] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductive line BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC in the first direction D1 may be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 may be greater than the height of the channel CH in the first direction D1.

[0054] In some embodiments, the second contact node SNC can be selectively grown from the wide sheet WS of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node SNC can be a doped silicon epitaxial layer.

[0055] In some embodiments, the first contact node BLC may also be selectively grown from the narrow NS of the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node BLC can be a doped silicon epitaxial layer.

[0056] The first contact node BLC can be a narrow-side contact node, while the second contact node SNC can be a wide-side contact node.

[0057] The nanosheet HL may include a first edge and a second edge. The first edge may refer to the portion of the first doped region SR that is electrically coupled to the first wire BL, while the second edge may refer to the portion of the second doped region DR that is electrically coupled to the first electrode SN of the data storage element CAP.

[0058] The memory cell MC may further include an ohmic contact layer BLO between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may include a metal silicide. In some embodiments, the memory cell MC may further include an ohmic contact layer formed between the second contact node SNC and the first electrode SN of the data storage element CAP. The first conductor BL, the ohmic contact layer BLO, the first contact node BLC, and the first doped region SR may be electrically coupled to each other. The second doped region DR, the second contact node SNC, and the first electrode SN of the data storage element CAP may be electrically coupled to each other.

[0059] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductive line WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductive line BL and the second conductive line WL. The first spacer SP1 and the second spacer SP2 may extend in the third direction D3 and surround the nanosheet HL. That is, the first spacer SP1 and the second spacer SP2 may surround the nanosheet HL and be disposed on the two sidewalls of the second conductive line WL.

[0060] The first spacer SP1 and the second spacer SP2 can have a double-pad structure or a single-pad structure. For example, the first spacer SP1 can have a single-pad structure, and the second spacer SP2 can have a double-pad structure, and the double-pad structure of the second spacer SP2 can include a stack of the first pad L1 and the second pad L2. The first spacer SP1 and the second spacer SP2 can include a dielectric material. The first spacer SP1 and the second spacer SP2 can include silicon oxide, silicon nitride, or a combination thereof. The first pad L1 of the second spacer SP2 can include silicon nitride, while the second pad L2 of the second spacer SP2 can include silicon oxide.

[0061] The first conductor BL may include multiple horizontal extensions BLE1, BLE2, and BLE3. The horizontal extensions BLE1, BLE2, and BLE3 may extend along a second direction D2. The horizontal extensions BLE1, BLE2, and BLE3 may include an inner horizontal extension BLE2 and outer horizontal extensions BLE1 and BLE3. The inner horizontal extension BLE2 of the first conductor BL may be disposed in a recess defined in the first pad L1 of a second spacer SP2 that is perpendicularly adjacent to each other. Therefore, the inner horizontal extension BLE2 of the first conductor BL can be electrically coupled to the ohmic contact layer BLO.

[0062] The outer horizontal extensions BLE1 and BLE3 of the first conductor BL can extend to be disposed on one side of the second spacer SP2. Therefore, the outer horizontal extensions BLE1 and BLE3 can contact the first pad L1 and the second pad L2 of the second spacer SP2. In some embodiments, the outer horizontal extensions BLE1 and BLE3 of the first conductor BL can be omitted.

[0063] Figure 2A This is a schematic perspective view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2B yes Figure 2A A schematic 3D view of the memory cell array MCA shown. Figure 2C yes Figure 2B The equivalent circuit diagram of the column array AR1 shown is shown. Figure 2D yes Figure 2B The equivalent circuit diagram of the row array AR2 is shown.

[0064] refer to Figures 2A to 2D The semiconductor device 100 may include multiple planes T-1, T-2, and TN constituting a vertical stack 100V. Each of the planes T-1, T-2, and TN may include multiple memory cells MC. The vertical stack 100V may include a memory cell array MCA, and the memory cell array MCA may include a three-dimensional array of memory cells MC. (See above reference...) Figure 1A and 1B The detailed components of the storage unit MC are described.

[0065] The storage cell array MCA may include multiple storage cells MC stacked vertically along a first direction D1, multiple storage cells MC horizontally arranged along a second direction D2, and multiple storage cells MC horizontally arranged along a third direction D3.

[0066] Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductive line WL, a nanosheet dielectric layer GD, and a nanosheet HL extending between a first doped region SR and a second doped region DR. The memory cell MC may also include a first contact node BLC, an ohmic contact layer BLO, and a second contact node SNC. The memory cell MC can be connected to… Figure 1A and Figure 1B The memory cells MC shown are the same. See reference... Figure 1A and 1B The second conductor WL may have a gate all-around (GAA) structure.

[0067] Although not shown, the storage unit MC may include a reference. Figure 1BThe first and second spacers are described. The first and second spacers may be disposed on both sides of each second conductor WL and extend along a third direction D3. The first and second spacers may extend along a third direction D3 and surround the nanosheet HL, similar to the second conductor WL.

[0068] The memory cell array MCA may include a column array AR1 of memory cells MC and a row array AR2 of memory cells MC. The column array AR1 may include multiple memory cells MC stacked vertically along a first direction D1. The memory cells MC in the column array AR1 may share a first conductor BL. The row array AR2 may include multiple memory cells MC horizontally arranged along a third direction D3. The memory cells MC in the row array AR2 may share a second conductor WL.

[0069] The array AR1 may include nanosheets HL arranged vertically along a first direction D1, wherein a first wire BL is coupled to the vertically arranged nanosheets HL, and a second wire WL surrounds the vertically arranged nanosheets HL.

[0070] The row array AR2 may include nanosheets HL arranged horizontally along a third direction D3, wherein a first wire BL is coupled to the horizontally arranged nanosheets HL, and a second wire WL surrounds the horizontally arranged nanosheets HL.

[0071] The first direction D1 can be vertical, and the third direction D3 can be horizontal. The memory cell array MCA may also include a horizontal layer array AR3, which may include multiple memory cells MC arranged on the same horizontal layer along the second direction D2. Adjacent memory cells MC in the horizontal layer array AR3 may share a first conductor BL.

[0072] A memory cell array (MCA) may include a first sub-cell array (MCA1) and a second sub-cell array (MCA2). Both the first sub-cell array (MCA1) and the second sub-cell array (MCA2) may include a three-dimensional array of memory cells (MC). The first sub-cell array (MCA1) and the second sub-cell array (MCA2) may share a first conductor (BL). The first conductor (BL) may include a first vertical conductor (BLA) and a second vertical conductor (BLB). The bottom of the first vertical conductor (BLA) and the bottom of the second vertical conductor (BLB) may merge to form a U-shape. Therefore, the first conductor (BL) may have a U-shape formed by merging the first vertical conductor (BLA) and the second vertical conductor (BLB). The memory cells (MC) of the first sub-cell array (MCA1) may share the first vertical conductor (BLA), while the memory cells (MC) of the second sub-cell array (MCA2) may share the second vertical conductor (BLB). Thus, adjacent first sub-cell arrays (MCA1) and second sub-cell arrays (MCA2) may have a mirror-shaped structure sharing the first conductor (BL). From a top view, both the first vertical conductor (BLA) and the second vertical conductor (BLB) may have a rectangular shape.

[0073] The lower structure (LS) can be disposed below the memory cell array (MCA). The lower structure LS may include a semiconductor substrate, metal interconnect structures, dielectric structures, conductive structures, bonding pad structures, and another memory or peripheral circuitry portion. For example, the lower structure LS may include a structure in which peripheral circuitry portions, metal interconnect structures, and bonding pad structures are sequentially stacked. The peripheral circuitry portions of the memory cell array (MCA) and the lower structure LS can be bonded together via wafer bonding.

[0074] The peripheral circuitry of the lower structure (LS) can be positioned below the level of the memory cell array (MCA). This can be referred to as a "PERI upper cell (COP) structure". The peripheral circuitry may include at least one control circuit for driving the memory cell array (MCA). The at least one control circuit of the peripheral circuitry may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit of the peripheral circuitry may include an address decoder circuit, a read circuit, or a write circuit. The at least one control circuit of the peripheral circuitry may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, or a fin-channel transistor (FinFET).

[0075] For example, the peripheral circuitry may include a sub-word line driver and a sense amplifier. A first conductor BL may be coupled to the sense amplifier, while a second conductor WL may be coupled to the sub-word line driver.

[0076] In some embodiments, the peripheral circuitry may be positioned at a level higher than the memory cell array (MCA). This may be referred to as a "PERI (POC) structure on cell".

[0077] In some embodiments, the memory cell array (MCA) may include DRAM, embedded DRAM, NAND, FeRAM, STTRAM, PCRAM, or ReRAM.

[0078] Figure 3 This is a schematic plan view showing a semiconductor device 200 according to an embodiment of the present disclosure. Figure 4A For along Figure 3 The cross-sectional view of semiconductor device 200 taken by line A-A' shown is shown. Figure 4B For along Figure 3 The cross-sectional view of semiconductor device 200 taken by line B-B' shown is illustrated.

[0079] Figures 3 to 4B The memory cell array MCA of the semiconductor device 200 shown can be connected with... Figures 2A to 2D The storage cell array MCA shown is similar, and the storage cell MC of the storage cell array MCA can be the same as... Figure 1A and Figure 1B The memory cell MC shown is similar. (As mentioned above...) Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C and Figure 2D A detailed description of the overlapping components is provided.

[0080] refer to Figure 3 , Figure 4A and Figure 4B The semiconductor device 200 may include a memory cell array MCA, and a lower structure LS may be disposed below the memory cell array MCA. The memory cell array MCA may include a three-dimensional array of memory cells MC1 and MC2. The memory cell array MCA may include a first sub-cell array MCA1 and a second sub-cell array MCA2. The memory cell array MCA may include first conductors BL, and each first conductor BL may include a first vertical conductor BLA and a second vertical conductor BLB. The bottom of the first vertical conductor BLA and the bottom of the second vertical conductor BLB may be merged together. Each first conductor BL may have a U-shape formed by merging the first vertical conductor BLA and the second vertical conductor BLB.

[0081] The first sub-cell array MCA1 may include a three-dimensional array of first memory cells MC1. Each first memory cell MC1 may include a first vertical conductor BLA, a switching element TR, and a data storage element CAP, and the switching element TR may include a second conductor WL and a nanosheet HL extending between a first doped region SR and a second doped region DR. The nanosheet HL may include the first doped region SR, the second doped region DR, and a channel CH. The second conductor WL may surround the nanosheet HL, which is disposed at the same horizontal level on a third direction D3. The second conductor WL may surround the channel CH of the nanosheet HL, which is disposed at the same horizontal level on a third direction D3. The first doped region SR of the nanosheet HL may be electrically coupled to the first vertical conductor BLA. The data storage element CAP may include a first electrode SN, a dielectric layer DE, and a second electrode PN. The second electrodes PN of the data storage element CAP may be merged together to form a common plate PL. The second doped region DR of the nanosheet HL may be electrically coupled to the first electrode SN of the data storage element CAP.

[0082] The second sub-cell array MCA2 may include a three-dimensional array of second memory cells MC2. Each second memory cell MC2 may include a second vertical conductor BLB, a switching element TR, and a data storage element CAP, and the switching element TR may include a nanosheet HL extending between a first doped region SR and a second doped region DR and a second conductor WL. The nanosheet HL may include a first doped region SR, a second doped region DR, and a channel CH. The second conductor WL may surround the nanosheet HL, which is disposed at the same horizontal level on a third-direction D3. The first doped region SR of the nanosheet HL may be electrically coupled to the second vertical conductor BLB. The second conductor WL may surround the channel CH of the nanosheet HL, which is disposed at the same horizontal level on a third-direction D3. The data storage element CAP may include a first electrode SN, a dielectric layer DE, and a second electrode PN. The second electrodes PN of the data storage element CAP may be merged together to form a common plate PL. The second doped region DR of the nanosheet HL may be electrically coupled to the first electrode SN of the data storage element CAP.

[0083] The first storage unit MC1 and the second storage unit MC2 can have the same as the reference. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C and Figure 2D The storage unit MC described has the same configuration.

[0084] The first vertical conductor BLA and the second vertical conductor BLB of the first sub-cell array MCA1 and the second sub-cell array MCA2 can extend vertically along the first direction D1, the nanosheet HL can extend along the second direction D2, and the second conductor WL can extend horizontally along the third direction D3.

[0085] The first storage cell MC1 of the first sub-cell array MCA1, which is vertically stacked in the first direction D1, can share the first vertical conductor BLA, while the second storage cell MC2 of the second sub-cell array MCA2, which is vertically stacked in the first direction D1, can share the second vertical conductor BLB.

[0086] Each of the first storage cell MC1 and the second storage cell MC2 in the first sub-cell array MCA1 and the second sub-cell array MCA2 may further include a first contact node BLC, an ohmic contact layer BLO, and a second contact node SNC.

[0087] The first contact node BLC may be disposed between each of the first conductor BLA and the second conductor BLB and the nanosheet HL. The first contact node BLC may comprise a metal-based material or a semiconductor material. For example, the first contact node BLC may comprise titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may comprise doped polycrystalline silicon, and the first doped region SR may comprise impurities diffused from the first contact node BLC.

[0088] The second contact node SNC can be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC can include a metal-based material or a semiconductor material. For example, the second contact node SNC can include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC can include doped polycrystalline silicon, and the second doped region DR can include impurities diffused from the second contact node SNC.

[0089] The height of the first contact node BLC in the first direction D1 can be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 can be greater than the height of the channel CH in the first direction D1.

[0090] The ohmic contact layer BLO can be formed between each of the first vertical conductor BLA and the second vertical conductor BLB and the first contact node BLC. The ohmic contact layer BLO may include metal silicide.

[0091] Each of the storage cells MC1 and MC2 may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 and the second spacer SP2 may be disposed on opposite sides of the second conductor WL. Similar to the second conductor WL, the first spacer SP1 and the second spacer SP2 may extend in a third direction D3 and surround the nanosheet HL. The first spacer SP1 and the second spacer SP2 may extend in a third direction D3 and surround the nanosheet HL at the same horizontal height. The first spacer SP1 may have a vertically extending integral structure.

[0092] The first spacer SP1 and the second spacer SP2 can both have a double-pad structure or a single-pad structure. For example, the first spacer SP1 can have a single-pad structure, and the second spacer SP2 can have a double-pad structure, and the double-pad structure of the second spacer SP2 can include a stack of the first pad L1 and the second pad L2. The first spacer SP1 and the second spacer SP2 can include a dielectric material. The first spacer SP1 and the second spacer SP2 can include silicon oxide, silicon nitride, or a combination thereof. The first pad L1 of the second spacer SP2 can include silicon nitride, while the second pad L2 of the second spacer SP2 can include silicon oxide.

[0093] The upper and lower surfaces of each second conductor WL may include multiple shallow concave surfaces. That is, the upper and lower surfaces of each second conductor WL may not have a flat shape, but may have a non-flat shape due to multiple shallow concavities.

[0094] A first inter-cell dielectric layer IL1 can be formed between memory cells MC disposed on a third direction D3. A second inter-cell dielectric layer IL2 can be formed between memory cells MC stacked on a first direction D1. The first inter-cell dielectric layer IL1 can be disposed between data storage elements CAP along the third direction D3. The second inter-cell dielectric layer IL2 can be disposed between second conductors WL along the first direction D1. The second inter-cell dielectric layer IL2 may include multiple protrusions. The protrusions of the second inter-cell dielectric layer IL2 may be portions filled in shallow concave surfaces of the second conductors WL. The upper and lower surfaces of each second inter-cell dielectric layer IL2 may not have a flat shape, but may have a non-flat shape due to the multiple protrusions. In the second inter-cell dielectric layers IL2, the uppermost second inter-cell dielectric layer IL2 and the lowermost second inter-cell dielectric layer IL2 may include a combination of flat and non-flat shapes. A third inter-cell dielectric layer IL3 can be formed between data storage elements CAP stacked on the first direction D1. The third inter-cell dielectric layer IL3 may include silicon oxide. The third inter-cell dielectric layer IL3 can be disposed between the first electrodes SN of the data storage element CAP along the first direction D1. The first spacer SP1 can cover one side of each second inter-cell dielectric layer IL2. The first spacer SP1 can have a cup shape, for example... shape.

[0095] The dielectric layers IL1, IL2, and IL3 between the first to third units may include silicon oxide, silicon carbide, air gap, air gap embedded oxide, or a combination thereof.

[0096] The first inter-cell dielectric layer IL1 can be called the "vertical inter-cell dielectric layer". The second inter-cell dielectric layer IL2 can be called the "first inter-cell horizontal dielectric layer", and the third inter-cell dielectric layer IL3 can be called the "second inter-cell horizontal dielectric layer".

[0097] Each second inter-cell dielectric layer IL2 may include an air gap AG. The second inter-cell dielectric layer IL2 may include a release barrier layer SDL and an air gap forming layer AGC, with the air gap AG embedded within the air gap forming layer AGC. The release barrier layer SDL may include silicon carbide (SiOC). The air gap forming layer AGC may include silicon oxide. The release barrier layer SDL may be a material selectively deposited on the surface of the first spacer SP1. The air gap forming layer AGC may be silicon oxide embedded within the air gap AG. The air gap AG reduces the parasitic capacitance between the second conductors WL stacked along the first direction D1, thus reducing the RC (resistance-capacitance) delay. As the RC delay decreases, the cell matrix size increases, thereby increasing the cell density.

[0098] The memory cell array MCA may include a plurality of second conductors WL stacked perpendicularly along a first direction D1. The memory cell array MCA may include a plurality of nanosheets HL stacked perpendicularly along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP stacked perpendicularly along the first direction D1. The memory cell array MCA may include a plurality of first vertical conductors BLA and second vertical conductors BLB spaced apart on a third direction D3.

[0099] Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can share a second conductor WL. Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can be coupled to different first conductors BL. Switching elements TR stacked along the first direction D1 can share a first conductor BL. Switching elements TR arranged horizontally along the third direction D3 can share a second conductor WL.

[0100] The memory cell array (MCA) may include dummy second conductors WLU and WLL, which are respectively positioned at a level above the uppermost second conductor WL and a level below the lowermost second conductor WL. Both dummy second conductors WLU and WLL may have a horizontally extending linear shape.

[0101] The memory cell array MCA may include a stack of multiple hard mask layers HM1, HM2, HM3 and HM4 positioned at a level above the topmost second conductor WL.

[0102] The memory cell array (MCA) may include multiple first bottom protective layers BT1 and second bottom protective layers BT2. The first bottom protective layer BT1 prevents electrical contact between the bottom surface of the first conductor BL and the underlying structure LS. The second bottom protective layer BT2 prevents electrical contact between the data storage element CAP and the underlying structure LS. The first bottom protective layer BT1 may be formed below the first vertical conductor BLA and the second vertical conductor BLB. The second bottom protective layer BT2 may be formed below the common board PL. The first bottom protective layers BT1 and the second bottom protective layers BT2 may include silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

[0103] A vertical isolation layer BLF can be disposed between a first vertical conductor BLA and a second vertical conductor BLB of the first conductor BL. The vertical isolation layer BLF may include a dielectric material. The vertical isolation layer BLF may be disposed between the first vertical conductors BLA arranged along a third direction D3. The vertical isolation layer BLF may be disposed between the second vertical conductors BLB arranged along a third direction D3. The vertical isolation layer BLF can also be referred to as a "support" and can be used to provide structural stability for semiconductor devices. The vertical isolation layer BLF may include silicon oxide, silicon nitride, a gas gap, or a combination thereof.

[0104] The second electrode PN of the data storage element CAP can be coupled to the common board PL.

[0105] According to the above embodiments, the semiconductor device 200 may include vertically stacked nanosheets HL, a vertically oriented first wire BL co-coupled to a first edge of the nanosheets HL, a data storage element CAP coupled to a second edge of the nanosheets HL, a horizontally oriented second wire WL surrounding the nanosheets HL, and a second inter-unit dielectric layer IL2 disposed between the second wires WL and including an air gap AG.

[0106] From another perspective, the semiconductor device 200 may include a column array and a row array of nanosheets HL, a second conductive line WL that co-surrounds the nanosheets HL in the row array and the nanosheets HL in the column array, an air gap AG disposed between the second conductive line WL in the column array, a data storage element CAP coupled to the nanosheets HL in the column array and the row array, and a first conductive line BL that is co-coupled to the nanosheets HL in the column array. The first conductive line BL may include a first vertical conductive line BLA and a second vertical conductive line BLB, and the first vertical conductive line BLA and the second vertical conductive line BLB may be formed by masking and etching processes.

[0107] From another perspective, the semiconductor device 200 may include: a first sub-cell array MCA1, which includes vertically stacked first memory cells MC1; a second sub-cell array MCA2, which includes vertically stacked second memory cells MC2; a linear opening LO between the first sub-cell array MCA1 and the second sub-cell array MCA2; and a first wire BL, which is formed in the linear opening LO and electrically coupled to the first memory cells MC1 and the second memory cells MC2 arranged horizontally adjacent to each other.

[0108] From another perspective, the semiconductor device 200 may include: a first conductor BL, which is vertically oriented along a first direction D1; a data storage element CAP, which is horizontally spaced from the first conductor BL; a nanosheet HL, which is horizontally oriented along a second direction D2 perpendicular to the first direction D1, and includes a flat sheet NS in contact with the first conductor BL and a fan-shaped sheet WS in contact with the data storage element CAP; and a second conductor WL, which surrounds the nanosheet HL and extends along a third direction D3 perpendicular to the first direction D1 and the second direction D2.

[0109] From another perspective, the semiconductor device 200 may include: a vertically stacked array AR1 comprising a column array AR1 of nanosheet transistors TR stacked vertically along a first direction D1; and an air gap AG disposed between the nanosheet transistors TR in the array AR1. Each nanosheet transistor TR may include a horizontal conductor WL extending along a third direction D3 perpendicular to the first direction D1 and the second direction D2, and surrounding a planar sheet NS of a nanosheet HL extending along the second direction D2 perpendicular to the first direction D1. Here, the nanosheet HL may include the planar sheet NS and a fan-shaped sheet WS, the horizontal length of which is shorter than that of the planar sheet NS.

[0110] From another perspective, the semiconductor device 200 may include: a first array MCA1 of nanosheet transistors TR stacked vertically along a first direction D1; a second array MCA2 of nanosheet transistors TR stacked vertically along the first direction D1, horizontally spaced from the first array MCA1; a vertical conductor BL that shares the nanosheet transistors TR in the first array MCA1 and the nanosheet transistors TR in the second array MCA2, and extends along the first direction D1; and a data storage element CAP coupled to the nanosheet transistors TR in the first array MCA1 and the second array MCA2. Each nanosheet transistor TR may include a horizontal conductor WL extending along a third direction D3 perpendicular to the first direction D1 and the second direction D2, and surrounding a flat plate NS extending along the second direction D2 perpendicular to the first direction D1 of the nanosheet HL. Here, the nanosheet HL may include the flat plate NS and a fan-shaped piece WS with a horizontal length shorter than the flat plate NS. The horizontal conductor WL in the first array MCA1 and the second array MCA2 may extend along the third direction D3 and surround the nanosheet HL at the same horizontal height. Each air gap AG can be set between the horizontal conductors WL in the first column array MCA1 and the second column array MCA2.

[0111] From another perspective, the semiconductor device 200 may include: a vertical arrangement of nanosheet transistors TR, each transistor TR having a gate-all-around (GAA) structure; and air gaps AG disposed between the vertical gaps in the vertical arrangement of the nanosheet transistors TR. Each nanosheet transistor TR may include horizontal conductors WL, and each air gap may be disposed between the horizontal conductors WL.

[0112] From another perspective, the semiconductor device 200 may include: a vertical arrangement of memory cells comprising nanosheet transistors TR, each nanosheet transistor TR having a gate-all-around (GAA) structure and an air gap AG disposed between vertical gaps in the vertical arrangement of memory cells. Each nanosheet transistor TR may include horizontal conductors WL, and each air gap may be disposed between the horizontal conductors WL.

[0113] Figures 5A to 26B Various views of a semiconductor device are shown to illustrate a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0114] Figure 5A A plan view showing the structure at the second module layer level is provided to describe the method for forming the module stack SB. Figure 5B To show along Figure 5A The cross-sectional view of the structure intercepted by line A-A' shown in the figure. Figure 5C To show along Figure 5A The cross-sectional view of the structure cut by line B-B' shown.

[0115] like Figures 5A to 5C As shown, the mold stack SB can be formed on the substrate 11. The mold stack SB can include an alternating stack of a first mold layer 12 and a second mold layer 13.

[0116] The first module layer 12 and the second module layer 13 can be epitaxially grown multiple times to form a module stack SB.

[0117] The first layer 12 and the second layer 13 can be made of different semiconductor materials. The first layer 12 may include silicon germanium or single-crystal silicon germanium. The second layer 13 may include single-crystal silicon. The first layer 12 and the second layer 13 can be formed by an epitaxial growth process. The bottommost first layer 12 may act as a seed layer during the epitaxial growth process. The first layer 12 may be thinner than the second layer 13. The first layer 12 may include a first epitaxial growth layer, while the second layer 13 may include a second epitaxial growth layer.

[0118] In one embodiment, in the first mode stack SB, multiple silicon-germanium layers can be stacked alternately with multiple monocrystalline silicon layers. The silicon-germanium layer / monocrystalline silicon layer stack (SiGe / Si stack) can be stacked multiple times. The first mode layer 12 can be referred to as the "sacrificial layer", while the second mode layer 13 can be referred to as the "nanosheet target layer" or "recessed target layer".

[0119] Modular stacked SB can be referred to as "vertical stacking". Modular stacked SB can be formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a silicon-germanium layer, while the nanosheet target layer can be a single-crystal silicon layer.

[0120] The thickness ratio of the first module layer 12 and the second module layer 13 in the module stack SB can be modified in various ways. For example, the thickness of each first module layer 12 can be approximately 5 to 20 nm, while the thickness of each second module layer 13 can be approximately 50 to 80 nm. The number of first module layers 12 and the number of second module layers 13 in the module stack SB can be modified in various ways. In some embodiments, a triple stack including a first module layer 12 / a second module layer 13 / a third module layer 12 can be defined at the bottom and top of the module stack SB. The second module layer 13 in the triple stack can have a thickness thinner than the other second module layer 13.

[0121] A first hard mask layer 14 may be formed on the die stack SB. The first hard mask layer 14 may include a dielectric material, such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first hard mask layer 14 may include SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0122] Subsequently, reference Figure 5C A first hard mask layer 14 can be used as a barrier to etch portions of the die stack SB, and multiple sacrificial isolation openings 15 can be formed in the die stack SB. The sacrificial isolation openings 15 can be initial openings for cell isolation. From a top view, the cross-section of the sacrificial isolation openings 15 can all be rectangular. In some embodiments, the cross-section of the sacrificial isolation openings 15 can all be circular or elliptical. In some embodiments, the sacrificial isolation openings 15 can be referred to as "sacrificial isolation trenches". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation openings 15 can be arranged at predetermined intervals in a third direction D3. The bottom surface of the sacrificial isolation openings 15 can extend into the interior of the substrate 11.

[0123] Figure 6A This is a plan view showing the structure at the second module layer level, used to describe the method for forming the sacrificial isolation layer 16. Figure 6B To show along Figure 6A The cross-sectional view of the structure cut by line B-B' shown.

[0124] like Figure 6A and Figure 6B As shown, a sacrificial isolation layer 16 can be formed to fill the sacrificial isolation opening 15. The sacrificial isolation layer 16 may comprise the same material. The sacrificial isolation layer 16 may be formed of a dielectric material. The sacrificial isolation layer 16 may have etch selectivity relative to the mold stack SB. For example, the sacrificial isolation layer 16 may all comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. Forming the sacrificial isolation layer 16 may include forming a sacrificial isolation material on the mold stack SB to fill the sacrificial isolation opening 15 and planarizing the sacrificial isolation material so that the surface of the first hard mask layer 14 is exposed.

[0125] The sacrificial isolation layer 16 may extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation layer 16 may be disposed at predetermined intervals in a third direction D3. Each sacrificial isolation layer 16 may comprise a stack of a first sacrificial pad layer and a first sacrificial gap fill layer. The first sacrificial pad layer may be silicon nitride, and the first sacrificial gap fill layer may be silicon oxide. The sacrificial isolation layer 16 may penetrate the mold stack SB in the first direction D1.

[0126] Figure 7A A plan view showing the structure at the second module level is provided to describe the method for forming the sacrificial linear openings 18 and 19. Figure 7B To show along Figure 7A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0127] like Figure 7A and Figure 7B As shown, a second hard mask layer 17 can be formed on the die stack SB and the sacrificial isolation layer 16. The second hard mask layer 17 may include silicon nitride. The second hard mask layer 17 can be formed by etching a second hard mask material using a mask layer such as photoresist. The second hard mask layer 17 may have a plurality of linear openings defined therein.

[0128] A second hard mask layer 17 can be used as an etching barrier to etch portions of the mold stack SB. Therefore, a plurality of sacrificial linear openings 18 and 19 can be formed between the sacrificial isolation layers 16. The sacrificial linear openings 18 and 19 may include a first sacrificial linear opening 18 and a second sacrificial linear opening 19. From a top view, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend vertically in a first direction D1. The sacrificial isolation layer 16 may be disposed between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 in a second direction D2. From a top view, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may both be rectangular. In some embodiments, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may both be circular or elliptical. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may both have a width in the second direction D2 that is smaller than their width in the third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be referred to as "sacrificial linear trenches". The sacrificial isolation layer 16 may not contact the first sacrificial linear opening 18 and the second sacrificial linear opening 19.

[0129] Figure 8AA plan view illustrating the structure at the second module layer level is provided to describe the method used to form the linear sacrificial layers 18L and 19L. Figure 8B To show along Figure 8A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0130] like Figure 8A and Figure 8B As shown, linear sacrificial layers 18L and 19L can be formed to fill sacrificial linear openings 18 and 19. Linear sacrificial layers 18L and 19L may include a first linear sacrificial layer 18L and a second linear sacrificial layer 19L. From a top view, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a linear shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend perpendicularly along a first direction D1. A sacrificial isolation layer 16 may be disposed between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L in a second direction D2. From a top view, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may both have a rectangular shape. In some embodiments, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may both have a circular or elliptical shape. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may include the same material. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may be formed of a dielectric material. For example, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may both comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. The sacrificial isolation layer 16 may not contact the first linear sacrificial layer 18L and the second linear sacrificial layer 19L.

[0131] Figure 9A A plan view showing the structure at the second module layer level is provided to illustrate the partial recesses of the first module layer 12 and the second module layer 13. Figure 9B To show along Figure 9A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 9C To show along Figure 9A The cross-sectional view of the structure cut by line B-B' shown.

[0132] like Figures 9A to 9C As shown, the first linear sacrificial layer 18L can be selectively removed from the first linear sacrificial layer 18L and the second linear sacrificial layer 19L. A third hard mask layer 17T can be used as an etching barrier to remove the first linear sacrificial layer 18L. This forms the first linear opening 20. From a top viewpoint, as... Figure 9A As shown, the first linear opening 20 can be horizontally spaced apart from the second linear sacrificial layer 19L in the second direction D2.

[0133] The first mold layer 12 can be selectively recessed through the first linear opening 20. The difference in etching selectivity between the first mold layer 12 and the second mold layer 13 can be used to selectively recess the first mold layer 12. The first mold layer 12 can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12 comprises a silicon-germanium layer and the second mold layer 13 comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer. Through the partial recess of the first mold layer 12, the upper and lower surfaces of the second mold layer 13 can be partially exposed. A portion of each first mold layer can be retained and can maintain its original thickness, as indicated by reference numeral "12A".

[0134] Subsequently, the exposed portion (first portion) of each second mold layer 13 can be selectively recessed, leaving only the narrow strip 13P. The second mold layer 13 can be recessed using either wet etching or dry etching processes.

[0135] The original body portion 13A and the narrow sheet 13P can be formed by partial recesses in each of the second molding layers 13. The original body portion 13A can maintain its original thickness T1, while the narrow sheet 13P can have a thickness T2 less than the original thickness T1. The horizontal length of the original body portion 13A in the second direction D2 can be equal to or different from the horizontal length of the narrow sheet 13P in the second direction D2. The combination of the original body portion 13A and the narrow sheet 13P can be referred to as a "preliminary nanosheet". The narrow sheet 13P can be referred to as a "flat sheet" or a "protruding narrow sheet".

[0136] The recessed process used to form the narrow wafer 13P can be referred to as a "thinning process" or "trimming process" for the second template layer 13. To form the narrow wafer 13P, the upper surface, lower surface, and side surfaces of the second template layer 13 can be recessed. The narrow wafer 13P can be referred to as a "thin active layer." The narrow wafer 13P may comprise a monocrystalline silicon layer. The recessed process used to form the narrow wafer 13P can use, for example, thermal SC-1 (HSC1). HSC1 may comprise a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. Using HSC1, the second template layer 13 can be selectively etched.

[0137] Narrow sheets 13P can be formed by the local recessing process for the second template layer 13 as described above, and nanosheet recesses 20 can be formed between the vertically arranged narrow sheets 13P. The upper and lower surfaces of the narrow sheets 13P can both be flat surfaces. The boundary portion between the original body portion 13A and the narrow sheets 13P can be vertical or can have curvature. Each first template layer 12A can be disposed between the vertically stacked original body portions 13A. The horizontal arrangement of the narrow sheets 13P can be formed in a third direction D3. The vertical arrangement of the narrow sheets 13P can be formed in a first direction D1. The nanosheet recesses 21 can be referred to as vertical gaps between the vertically arranged narrow sheets 13P.

[0138] Figure 10A This is a plan view showing the structure at the narrow layer level, used to describe the method of forming the opening 22 of the sacrificial isolation layer level. Figure 10B To show along Figure 10A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 10C To show along Figure 10A The cross-sectional view of the structure cut by line B-B' shown.

[0139] like Figures 10A to 10C As shown, the sacrificial isolation layer 16 can be selectively peeled off via the inter-nanosheet recesses 21. Therefore, each sacrificial isolation layer hierarchical opening 22 can be formed on the third-direction D3 between the original body portions 13A.

[0140] The sides of the first module layer 12A, the sides of the original main body portion 13A, and the sides of the narrow strip 13P can be exposed on the third-party direction D3 through the sacrificial isolation layer hierarchical opening 22.

[0141] When the sacrificial isolation layer hierarchical opening 22 is formed, a portion of the first hard mask layer 14 (refer to reference numeral "14A") can be recessed. Therefore, the recess 21 between the uppermost nanosheets can be enlarged.

[0142] Figure 11A A plan view of the structure at the narrow layer level is shown to describe the method for forming the first inter-cell dielectric layer 23. Figure 11B To show along Figure 11A The cross-sectional view of the structure cut by line B-B' shown.

[0143] like Figure 11A and Figure 11BAs shown, a first inter-cell dielectric layer 23 can be formed in the sacrificial isolation layer level opening 22. The first inter-cell dielectric layer 23 may all comprise a dielectric material. The first inter-cell dielectric layer 23 may all comprise silicon oxide, silicon nitride, silicon carbide, or a combination thereof. The steps of forming the first inter-cell dielectric layer 23 may include: forming a dielectric material filling the sacrificial isolation layer level opening 22, and performing an etch-back process on the dielectric material. The etch-back process for forming the first inter-cell dielectric layer 23 may be performed along the second direction D2.

[0144] The first inter-cell dielectric layer 23 may fill a portion of the sacrificial isolation layer hierarchy opening 22. The sides of the first mold layer 12A and the original body portion 13A may be covered by the first inter-cell dielectric layer 23 on the third direction D3. The first inter-cell dielectric layer 23 may expose the sides of the narrow strip 13P. Other portions of the sacrificial isolation layer hierarchy opening 22 (i.e., the non-gap-fill portion 22A) may expose the sides of the narrow strip 13P and extend to be disposed in the substrate 11. The first inter-cell dielectric layer 23 may be an inter-cell vertical dielectric layer.

[0145] After forming the first inter-unit dielectric layer 23, a fully open nanosheet recess 24A can be formed that exposes all the narrow sheets 13P. The fully open nanosheet recess 24A can expose all the narrow sheets 13P on the third direction D3. For example, the fully open nanosheet recess 24A extending along the third direction D3 can surround all surfaces of the narrow sheets 13P at the same horizontal height.

[0146] The fully open nanosheet recess 24A can refer to a combination of the inter-nanosheet recess 21 and the non-gap-filling portion 22A of the sacrificial isolation layer hierarchical opening 22. The fully open nanosheet recess 24A can include multiple surrounding recesses 24. The surrounding recesses 24 can expose all the narrow sheets 13P in the third direction D3. For example, any surrounding recess 24 extending along the third direction D3 can surround all surfaces of the narrow sheets 13P at the same horizontal height.

[0147] Each surrounding recess 24 may include multiple first gaps 24G. First gaps 24G may be included between the narrow strips 13P on the third-direction D3.

[0148] The horizontal arrangement of the narrow strips 13P can be formed in the third direction D3. The vertical arrangement of the narrow strips 13P can be formed in the first direction D1. The first gap 24G can be referred to as the horizontal gap between the narrow strips 13P in the horizontal arrangement.

[0149] Figure 12A A plan view of the structure at the narrow layer level is shown to describe the method for forming the first spacer layer 26A. Figure 12B To show along Figure 12A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 12C To show along Figure 12A The cross-sectional view of the structure cut by line B-B' shown.

[0150] like Figures 12A to 12C As shown, the nanosheet dielectric layer 25 can be formed on the exposed portion of the narrow strip 13P. The nanosheet dielectric layer 25 can be referred to as the "gate dielectric layer".

[0151] The nanosheet dielectric layer 25 can be formed by oxidizing the surface of the narrow wafer 13P. In some embodiments, the nanosheet dielectric layer 25 can be formed by a silicon oxide deposition process and a surface oxidation process of the narrow wafer 13P. The nanosheet dielectric layer 25 may include silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 25 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 25 can be formed on all surfaces of the narrow wafer 13P.

[0152] The first spacer layer 26A may be formed on the nanosheet dielectric layer 25. The first spacer layer 26A may include silicon nitride. The first spacer layer 26A may surround and cover the nanosheet 13P on the nanosheet dielectric layer 25. The first spacer layer 26A may be thicker than the nanosheet dielectric layer 25. The first spacer layer 26A may be in direct contact with the first inter-unit dielectric layer 23.

[0153] The nanosheet dielectric layer 25 and the first spacer layer 26A can also be formed on the surface of the substrate 11.

[0154] As described above, the first spacer layer 26A can be disposed between the narrow strips 13P along a third direction D3. The first spacer layer 26A can define an internal space 26B in the upper and lower parts of the narrow strips 13P.

[0155] Figure 13A A plan view of the structure at the narrow layer level is shown to describe the method for forming the air-gap target layer PF. Figure 13B To show along Figure 13A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 13C To show along Figure 13A The cross-sectional view of the structure cut by line B-B' shown.

[0156] like Figures 13A to 13CAs shown, the air gap target layer PF can be formed on the first spacer layer 26A. The air gap target layer PF can fill the internal space 26B of the first spacer layer 26A. The air gap target layer PF can all comprise a material with etch selectivity relative to the first spacer layer 26A. The air gap target layer PF can all comprise a material that is easy to peel off, such as polysilicon or silicon oxide. For example, the step of forming the air gap target layer PF can include: forming polysilicon on the first spacer layer 26A to fill the area surrounding the recess 24, and etching the polysilicon.

[0157] The air gap target layer PF can expose a portion of the first spacer layer 26A.

[0158] A release barrier layer (SDL) can be formed on the exposed portion of the first spacer layer 26A that is exposed to the air gap target layer PF. The SDL can be selectively deposited only on the exposed portion of the first spacer layer 26A. The SDLs can be discontinuous. The SDLs can all comprise a dielectric material, such as silicon carbide (SiOC). When the first spacer layer 26A comprises silicon nitride, silicon carbide can be selectively deposited on silicon nitride within silicon nitride and polysilicon. In some embodiments, silicon carbide can be selectively deposited on silicon nitride within silicon nitride and silicon oxide. Each release path (STP) exposing the side of the air gap target layer PF can be formed between the SDLs.

[0159] Figure 14A A plan view of the structure at the narrow plate level is shown to describe the method used to form the initial air gap AG'. Figure 14B To show along Figure 14A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 14C To show along Figure 14A The cross-sectional view of the structure cut by line B-B' shown.

[0160] like Figures 14A to 14C As shown, the air gap target layer PF can be peeled off through the peeling path STP to form the initial air gap AG'. When the air gap target layer PF is peeled off, the erosion of the first spacer layer 26A can be prevented by peeling off the barrier layer SDL.

[0161] Figure 15A A plan view of the structure at the narrow layer level is shown to describe the air gap AG method. Figure 15B To show along Figure 15A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 15C To show along Figure 15A The cross-sectional view of the structure cut by line B-B' shown.

[0162] like Figures 15A to 15CAs shown, an air gap forming layer (AGC) can be formed to fill the initial air gap (AG'). The air gap forming layer (AGC) can all comprise a dielectric material such as, for example, silicon oxide.

[0163] The steps of forming the air gap forming layer AGC may include depositing an air gap forming material to fill the initial air gap AG' on the first spacer layer 26A and the release barrier layer SDL, and etching the air gap forming material to form the air gap forming layer AGC. Each air gap forming layer AGC may include an air gap AG. When depositing the air gap forming material, the air gap AG may be defined by the contour of each release barrier layer SDL. That is, the entrance to the space where the air gap forming material is to be deposited can be narrowed by the release barrier layer SDL, and therefore, the air gap AG can be formed as an embedded portion of the film in each air gap forming layer AGC. The embedded air gap AG may be disposed within the air gap forming layer AGC and may not contact the release barrier layer SDL and the first spacer layer 26A.

[0164] The air gap forming layer (AGC) and the release barrier layer (SDL) can constitute the second inter-cell dielectric layer 27. The second inter-cell dielectric layer 27 can all be made of silicon oxide-based material. The second inter-cell dielectric layers 27, arranged perpendicularly to each other, can be discontinuous. The second inter-cell dielectric layer 27 can also be a first inter-cell horizontal dielectric layer.

[0165] Figure 16A A plan view of the structure at the narrow plate level is shown to describe the method for forming the first spacer 26. Figure 16B To show along Figure 16A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 16C To show along Figure 16A The cross-sectional view of the structure cut by line B-B' shown.

[0166] like Figures 16A to 16C As shown, the first spacer layer 26A can be selectively recessed through the first linear opening 20. The remaining first spacer layer can become the first spacer 26. The first spacer 26 can surround the narrow strips 13P that are spaced apart from each other on the third direction D3 and are at the same horizontal height.

[0167] With the formation of the first spacer 26, a linear surrounding recess 28 can be formed around the narrow strip 13P on the nanosheet dielectric layer 25. Each second inter-unit dielectric layer 27 can be disposed between the linear surrounding recesses 28. An upper dummy horizontal recess 28U can be formed on the uppermost second inter-unit dielectric layer 27, and a lower dummy horizontal recess 28L can be formed below the lowermost second inter-unit dielectric layer 27. Both the upper dummy horizontal recess 28U and the lower dummy horizontal recess 28L can have a non-surrounding shape, i.e., a flat shape.

[0168] Figure 17AA plan view of the structure at the narrow layer level is shown to describe the method for forming the horizontal conductor 29. Figure 17B To show along Figure 17A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 17C To show along Figure 17A The cross-sectional view of the structure cut by line B-B' shown.

[0169] like Figures 17A to 17C As shown, a horizontal guide 29 can be formed to fill the linear space around the recess 28. The horizontal guide 29 can extend horizontally along the third direction D3.

[0170] The step of forming the horizontal wires 29 may include depositing a conductive material that fills the nanosheet dielectric layer 25 linearly around the recess 28, and performing a horizontal etch-back process on the conductive material. Each horizontal wire 29 may simultaneously surround a narrow strip 13P at the same height. The horizontal wires 29 may all comprise a metal-based material, a semiconductor material, or a combination thereof. The horizontal wires 29 may all comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, each horizontal wire 29 may comprise a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal wires 29 may all comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. Each second inter-unit dielectric layer 27 may be disposed between multiple horizontal wires 29 in a first direction D1. The horizontal wires 29 surrounding the narrow strip 13P may be referred to as "gate all-around (GAA) electrodes". Narrow-film 13P can be referred to as "nanosheet channel", "nanowire" or "nanowire channel".

[0171] The lower dummy horizontal electrode 29L can be formed on the surface of the substrate 11, and the upper dummy horizontal electrode 29U can be formed on the uppermost horizontal conductor 29. Both the dummy horizontal electrodes 29L and 29U can have a non-surrounding shape.

[0172] The horizontal conductor 29 and the first spacer 26 may extend along the third direction D3. The horizontal conductor 29 and the first spacer 26 may surround the narrow strip 13P of the initial nanosheet disposed at the same horizontal height along the third direction D3.

[0173] Each second inter-cell dielectric layer 27 can be disposed between horizontal conductors 29 arranged perpendicularly to each other. Each second inter-cell dielectric layer 27 may include a release barrier layer SDL and an air gap forming layer AGC, and the air gap AG may be embedded in the air gap forming layer AGC. The release barrier layer SDL may include silicon carbide (SiOC), and the air gap forming layer AGC may include silicon oxide. The air gap forming layer AGC may be silicon oxide in which the air gap AG is embedded. The parasitic capacitance between the horizontal conductors 29 stacked along the first direction D1 can be reduced by the air gap AG, thereby also reducing the RC delay (resistance-capacitance delay). When the RC delay is reduced, the cell matrix size can be increased, and therefore the cell density can also be increased.

[0174] As described above, a method for manufacturing a semiconductor device may include: forming a nanosheet target layer 13 on a substrate 11, which are vertically stacked and spaced apart from each other along a first direction D1; trimming a first portion of the nanosheet target layer 13 and forming a narrow strip 13P extending along a second direction D2 intersecting the first direction D1; forming an initial air gap AG' between the narrow strips 13P stacked along the first direction D1; forming an air gap forming layer AGC that fills the initial air gap AG' and embeds the air gap AG therein; forming a surrounding recess 28 between the air gap forming layers AGC that exposes the narrow strips 13P in a third direction D3 intersecting the first direction D1 and the second direction D2; and forming a horizontal wire 29 that fills the surrounding recess 28 on the third direction D3 and is disposed between the air gap forming layers AGC.

[0175] Figure 18A This is a plan view of the structure at the narrow layer level, used to describe the method for forming the second spacer 30. Figure 18B To show along Figure 18A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0176] like Figure 18A and Figure 18B As shown, each second spacer 30 may be formed on one side of the horizontal conductor 29. The second spacer 30 may comprise silicon oxide, silicon nitride, silicon carbide, embedded air gap, or a combination thereof. A deposition and etch-back process of spacer material may be performed to form the second spacer 30. The second spacer 30 may comprise a stack of silicon oxide pads 31A and silicon nitride pads 31B. A portion of the silicon nitride pad 31B may protrude into the first linear opening 20. The second spacer 30 may surround a narrow strip 13P disposed at the same horizontal height on a third direction D3. The second spacer 30 may extend along the third direction D3.

[0177] Subsequently, a deposition and etch-back process for the first bottom protective layer 32 can be performed. The upper surface of the first bottom protective layer 32 can be positioned below the level of the lowest horizontal conductor 29. The first bottom protective layer 32 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0178] After the first bottom protective layer 32 is formed, a portion of the nanosheet dielectric layer 25 can be cut to expose each side of the narrow strip 13P.

[0179] Figure 19A A plan view of the structure at the narrow plate level is shown to describe the method for recessing the narrow plate 13P. Figure 19B To show along Figure 19A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0180] like Figure 19A and Figure 19B As shown, the narrow sheet 13P can be horizontally recessed. The nanosheet-level recess 33 can be formed by the recess of the narrow sheet 13P. Each nanosheet-level recess 33 can be a lateral recess disposed in the second spacer 30.

[0181] Figure 20A A plan view of the structure at the narrow layer level is shown to describe the method for forming the first contact node 34. Figure 20B To show along Figure 20A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0182] like Figure 20A and Figure 20B As shown, the first contact node 34 can be formed to fill the nanosheet-level depression 33. The steps of forming the first contact node 34 may include depositing a conductive material to fill the nanosheet-level depression 33 and performing an etch-back process on the conductive material. The first contact node 34 may all comprise a semiconductor material (e.g., doped polysilicon), and the doped polysilicon may comprise an N-type dopant. The first contact node 34 can fill the nanosheet-level depression 33 disposed in the second spacer 30. Another method for forming the first contact node 34 may also include applying selective epitaxial growth (SEG) of a doped semiconductor material.

[0183] Each first doped region 35 can be formed on one side of each sliver 13P. A thermal processing step can be performed to form the first doped region 35, and thus the dopant can diffuse from the first contact node 34.

[0184] Figure 21A A plan view of the structure at the narrow layer level is shown to describe the method for forming vertical conductors 37A and 37B. Figure 21B To show along Figure 21AThe cross-sectional view of the structure cut by line A-A' shown in the figure.

[0185] like Figure 21A and Figure 21B As shown, an ohmic contact layer 36 can be formed on the first contact node 34. Each ohmic contact layer 36 may include a metal silicide.

[0186] Vertical conductors 37A and 37B can be formed on the ohmic contact layer 36. Vertical conductors 37A and 37B can be jointly coupled to the ohmic contact layer 36. Therefore, vertical conductors 37A and 37B can be jointly coupled to the narrow strip 13P disposed along the first direction D1. Vertical conductors 37A and 37B can both comprise a metal base material. Vertical conductors 37A and 37B can both comprise titanium nitride, tungsten, or a combination thereof.

[0187] Deposition and etching processes can be performed on the vertical conductor material to form vertical conductors 37A and 37B.

[0188] The bottoms of vertical conductors 37A and 37B can be merged together (refer to reference numeral "38" in the accompanying drawings). Vertical conductors 37A and 37B can be disposed in the first linear opening 20. Vertical conductors 37A and 37B can extend vertically along the first direction D1. The bottoms of vertical conductors 37A and 37B can be merged together. Vertical conductors 37A and 37B can be jointly coupled to the ohmic contact layer 36. Therefore, vertical conductors 37A and 37B can be jointly coupled to the narrow strip 13P disposed along the first direction D1.

[0189] Figure 22A A planar view of the structure at the nanosheet level is shown to describe the method for forming the second linear opening 41. Figure 22B To show along Figure 22A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0190] like Figure 22A and Figure 22B As shown, a vertical isolation layer 39 can be formed on vertical conductors 37A and 37B to fill the first linear opening 20. The vertical isolation layer 39 can extend vertically along a first direction D1 and horizontally along a third direction D3. Vertical conductors 37A and 37B disposed adjacent to each other in the third direction D3 can be isolated by the vertical isolation layer 39. The vertical isolation layer 39 may include a dielectric material. The vertical isolation layer 39 may include silicon oxide, silicon nitride, an air gap, or a combination thereof.

[0191] Subsequently, the second linear sacrificial layer 19L can be removed using the fourth hard mask layer 40 as a barrier. This forms the second linear opening 41.

[0192] After the second linear opening 41 is formed, the first mold layer 12A can be selectively recessed through the second linear opening 41. The difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be used to selectively recess the first mold layer 12A. The first mold layer 12A can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a monocrystalline silicon layer, an etchant or etching gas that is selective relative to the monocrystalline silicon layer can be used to etch the silicon-germanium layer.

[0193] Subsequently, the original body portion 13A can be recessed. This recessing can be achieved using either wet or dry etching processes. The vertical thickness of the original body portion 13A can be reduced, as indicated by the reference numeral "13S". Hereinafter, the original body portion with reduced vertical thickness will be referred to as the "recessed body portion 13S".

[0194] Each recess 42 can be formed between the vertically arranged recessed body portions 13S.

[0195] Figure 23A A planar diagram illustrating the structure at the narrow sheet level is provided to describe the method used to form nanosheets HL. Figure 23B To show along Figure 23A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0196] like Figure 23A and Figure 23B As shown, a third inter-unit dielectric layer 43 can be formed to fill the inter-unit recess 42. The third inter-unit dielectric layer 43 may all comprise silicon oxide. The third inter-unit dielectric layer 43 may be a second inter-unit horizontal dielectric layer.

[0197] After forming the third inter-unit dielectric layer 43, a second bottom protection layer 44T may be formed on the bottom of the second linear opening 41. The second bottom protection layer 44T may include a material with etching selectivity relative to the substrate 11. The second bottom protection layer 44T may include a dielectric material. The second bottom protection layer 44T may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0198] After forming the second bottom protective layer 44T, a storage opening 44 can be formed by a horizontal recess in the recessed main body portion 13S. The storage opening 44 can be referred to as a "capacitor opening". The nanosheet HL can be formed by a horizontal recess in the recessed main body portion 13S. Each nanosheet HL can include a narrow sheet 13P and a wide sheet 13E. The wide sheet 13E of the nanosheet HL can refer to the remaining recessed main body portion 13S after the recess. The average vertical height of the wide sheet 13E of the nanosheet HL in the first direction D1 can be greater than the average vertical height of the narrow sheet 13P. The thickness of the wide sheet 13E of the nanosheet HL can gradually increase in the second direction D2. The horizontal length of the wide sheet 13E in the second direction D2 can be less than the horizontal length of the narrow sheet 13P. The wide sheet 13E of the nanosheet HL can have a fan-shaped shape. The wide sheet 13E can be referred to as a "fan-shaped sheet", while the narrow sheet 13P can be referred to as a "flat sheet".

[0199] The recessing process for forming the body portion 13S of the recesses for the wafer 13E and the storage opening 44 may include an isotropic etching process or an anisotropic etching process. One side of each wafer 13E (i.e., the side exposed by each storage opening 44) may have a flat shape (see reference numeral "RF" in the figures). One side of the wafer 13E may have various shapes. For example, one side of the wafer 13E may have a rounded concave shape, a rounded convex shape, an angled concave shape, or an angled convex shape.

[0200] The second bottom protective layer 44T and the bottommost second inter-unit dielectric layer 27 can prevent the loss of substrate 11 during the recess process of the recessed main body portion 13S.

[0201] Each nanosheet HL may include a first edge and a second edge. The first edge may refer to the portion coupled to the vertical wires 37A and 37B, while the second edge may refer to the portion exposed by each storage opening 44.

[0202] Each storage opening 44 can be disposed between the third inter-unit dielectric layers 43.

[0203] In some embodiments, the horizontal recess of the main body portion 13S used to form the recess of the wide piece 13E may stop at the boundary region between the narrow piece 13P and the wide piece 13E.

[0204] Figure 24A A planar view of the structure at the nanosheet level is shown to describe the method for forming the second contact node 45 and the first electrode 48. Figure 24B To show along Figure 24A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0205] like Figure 24A and Figure 24BAs shown, a pre-cleaning process can be performed on one side of each nanosheet HL (i.e., the surface of each wide sheet 13E).

[0206] Subsequently, a second contact node 45 can be formed on the second edge of the nanosheet HL (i.e., the wide wafer 13E). The step of forming the second contact node 45 may include a deposition and etching process of doped polycrystalline silicon. In some embodiments, forming the second contact node 45 may include selective epitaxial growth (SEG). For example, a semiconductor material can be grown from the side of the wide wafer 13E by selective epitaxial growth (SEG). The second contact nodes 45 may all comprise SEG Si. Since the wide wafer 13E comprises monocrystalline silicon, a silicon layer can be epitaxially grown along the crystal plane of the side of the wide wafer 13E. The second contact nodes 45 may all comprise a dopant. Therefore, the second contact nodes 45 may all be doped epitaxial layers. The second contact nodes 45 may all comprise an N-type dopant as a dopant. The N-type dopant may include phosphorus, arsenic, antimony, or a combination thereof. The second contact node 45 may comprise a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., doped SEG SiP. In some embodiments, the first contact node 34 may also be formed by selective epitaxial growth (SEG).

[0207] Because the second contact node 45 is formed using selective epitaxial growth (SEG), a void-free or gapless second contact node 45 can be formed. Because the second contact node 45 is formed using selective epitaxial growth (SEG), the process for forming the second contact node 45 can be simplified.

[0208] Each second contact node 45 can be disposed between the vertically stacked third inter-unit dielectric layers 43.

[0209] In some embodiments, the sides of the second contact node 45 may all have a circular concave shape, a circular convex shape, an angled concave shape, or an angled convex shape.

[0210] The second doped region 46 can be formed in the wide sheet 13E of the nanosheet HL. A thermal processing process can be performed to form the second doped region 46, and thus, the dopant can diffuse from the second contact node 45.

[0211] Each nanosheet HL may include a first doped region 35, a second doped region 46, and a channel 47. The first doped region 35 and the channel 47 may be formed in a narrow wafer 13P, while the second doped region 46 may be formed in a wide wafer 13E. A portion of each second doped region 46 may extend into the narrow wafer 13P. One side of each second doped region 46 of the nanosheet HL may be coupled to the channel 47, and the other side of each second doped region 46 of the nanosheet HL may be coupled to a second contact node 45.

[0212] In some embodiments, after forming the second contact node 45, an ohmic contact layer comprising metal silicide may also be formed.

[0213] Subsequently, a first electrode 48 of the data storage element CAP can be formed on the second contact node 45. The first electrodes 48 can all have a horizontally oriented cylindrical shape. The first electrodes 48 can be respectively disposed in the storage opening 44. First electrodes 48 disposed adjacent to each other in the second direction D2 can be spaced apart from each other by the second linear opening 41. First electrodes 48 disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the first inter-cell dielectric layer 23. The steps of forming the first electrodes 48 may include depositing a metal material, filling gaps with a sacrificial material, and isolating metal materials in the vertical / horizontal directions. The sacrificial material may include oxide or polysilicon.

[0214] Each first electrode 48 may include an internal space and multiple outer surfaces, and the internal space of the first electrode 48 may include multiple inner surfaces. The outer surfaces of the first electrode 48 may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode 48 may extend vertically along a first direction D1, while the horizontal outer surfaces of the first electrode 48 may extend horizontally along a second direction D2 or a third direction D3. The internal space of the first electrode 48 may be a three-dimensional space.

[0215] In the outer surface of the first electrode 48, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 45.

[0216] The first electrode 48 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode 48 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof.

[0217] Figure 25A This is a planar diagram showing the structure at the nanosheet level, used to describe the method of creating a recess in the first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 43. Figure 25B It shows along Figure 25A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0218] like Figure 25A and Figure 25BAs shown, portions of the first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 43 may be horizontally recessed (refer to reference numeral "43R" in the accompanying drawings). Therefore, the outer wall of the first electrode 48 may be partially exposed. The first electrode 48 may all have a semi-cylindrical shape. The semi-cylindrical shape of the first electrode 48 may include a cylindrical inner surface and a semi-cylindrical outer surface.

[0219] Figure 26A This is a planar diagram showing the structure at the nanosheet level, used to describe the method for forming the second electrode 50 of the data storage element CAP. Figure 26B It shows along Figure 26A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0220] like Figure 26A and Figure 26B As shown, a dielectric layer 49 and a second electrode 50 can be sequentially formed on the first electrode 48. The first electrode 48, the dielectric layer 49, and the second electrode 50 can be data storage elements (CAPs). The second electrodes 50 of the data storage elements (CAPs) can be merged together to form a common board PL.

[0221] The dielectric layer 49 and the second electrode 50 may be disposed on the cylindrical inner surface of the first electrode 48. A portion of the dielectric layer 49 and a portion of the second electrode 50 may extend to be disposed on the semi-cylindrical outer surface of the first electrode 48. The second electrode 50 may extend perpendicularly along the first direction D1.

[0222] The dielectric layer 49 may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 49 may include silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 49 may include high-k materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Dielectric layer 49 may include ZA (ZrO2 / Al2O3) stacks, ZAZ (ZrO2 / Al2O3 / ZrO2) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HA (HfO2 / Al2O3) stacks, HAH (HfO2 / Al2O3 / HfO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH ( Stacked structures include HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2, HZAZH(HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2), ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), HZHZ(HfO2 / ZrO2 / HfO2) / ZrO2), or AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3).

[0223] The second electrode 50 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second electrode 50 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode 50 may also include a combination of metal-based materials and silicon-based materials. For example, the second electrode 50 may have a structure in which titanium nitride, tungsten, and polycrystalline silicon are sequentially stacked.

[0224] In some embodiments, an interface control layer may be formed between the first electrode 48 and the dielectric layer 49 to mitigate leakage current. The interface control layer may include titanium dioxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or combinations thereof. The interface control layer may also be formed between the second electrode 50 and the dielectric layer 49.

[0225] As described above, a method for manufacturing a semiconductor device may include: forming a vertically stacked and spaced-apart nanosheet target layer 13 on a substrate 11; forming a planar sheet 13P by trimming a first portion of the nanosheet target layer 13; forming horizontal wires 29 that surround and extend around the planar sheet 13P disposed at the same horizontal height; forming a first contact node 34 coupled to the planar sheet 13P; forming vertical wires 37A and 37B coupled to the first contact node 34; horizontally recessing a second portion of the nanosheet target layer 13 to form a fan-shaped sheet 13E; selectively growing a second contact node 45 on the side of the fan-shaped sheet 13E; and forming a data storage element CAP coupled to the second contact node 45. Before forming the horizontal conductors 29, a method for manufacturing a semiconductor device may include: forming a first spacer layer 26A defining an internal space 26B in the upper and lower portions of a planar wafer 13P; forming an air gap target layer PF filling the internal space 26B; forming a stripping path STP between a stripping barrier layer SDL and the stripping barrier layer SDL at the entrance of the internal space 26B; removing the air gap target layer PF through the stripping path STP to form an initial air gap AG'; forming an air gap forming layer AGC in which the air gap AG is embedded and the initial air gap AG' is filled; and horizontally recessing the first spacer layer 26A to form a first spacer 26 covering the sides of the air gap forming layer AGC and a surrounding recess 28 exposing the upper and lower portions of the planar wafer 13P. Each horizontal conductor 29 may fill the surrounding recess 28 and be disposed between the air gap forming layers AGC.

[0226] Figure 27 and Figure 28 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0227] like Figure 27 As shown, a semiconductor device COP may include a memory cell array (MCA), a peripheral circuitry section (PERI), and a bonding interface (BS). The bonding interface BS may be disposed between the memory cell array (MCA) and the peripheral circuitry section (PERI). In the semiconductor device COP, the memory cell array (MCA) may be disposed at a level higher than the peripheral circuitry section (PERI). The semiconductor device COP may be referred to as a "peripheral under-cell array (PUC) structure." The memory cell array (MCA) may include a substrate that has undergone back-side grinding and an array of memory cells. For example, as shown in the reference... Figure 26BAfter forming the data storage element CAP, the substrate 11 can be flipped by wafer flipping, and then the substrate 11 can be partially back-side ground.

[0228] like Figure 28 As shown, a semiconductor device POC may include a memory cell array (MCA), a peripheral circuitry section (PERI), and a bonding interface (BS). The bonding interface BS may be disposed between the memory cell array (MCA) and the peripheral circuitry section (PERI). In the semiconductor device POC, the memory cell array (MCA) may be disposed below the level of the peripheral circuitry section (PERI). The semiconductor device POC may be referred to as a "cell array lower periphery (CUP) structure." Forming the peripheral circuitry section (PERI) may include forming multiple control circuits on the peripheral circuitry substrate, and forming multi-level interconnects on the control circuits.

[0229] exist Figure 27 and Figure 28 In this context, the bonding interface BS can include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof. Hybrid bonding can refer to a combination of pad bonding and oxide-oxide bonding. Pad bonding can include forming cell bonding pads for a memory cell array, forming peripheral circuit bonding pads for peripheral circuit portions, performing wafer flipping so that the cell bonding pads and peripheral circuit bonding pads face each other, and performing wafer bonding.

[0230] Figure 27 The semiconductor device COP shown can perform wafer flipping on the substrate on which the memory cell array is formed after the formation of cell bonding pads and peripheral circuit bonding pads, so that the cell bonding pads and peripheral circuit bonding pads face each other. Figure 28 The semiconductor device POC shown can perform wafer flipping on the substrate on which the peripheral circuit portion is formed after the formation of the unit bonding pads and the peripheral circuit bonding pads, so that the unit bonding pads and the peripheral circuit bonding pads face each other.

[0231] Figure 29 and Figure 30 Various views of a stacked assembly according to embodiments of the present disclosure are shown.

[0232] like Figure 29 As shown, the stacked assembly 300 may include a component of semiconductor dies. For example, the stacked assembly 300 may include a first semiconductor die BSD and a plurality of second semiconductor dies 301. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 301 may include a memory cell array according to the above embodiment. Each second semiconductor die 301 may include a structure in which the memory cell array and peripheral circuitry are partially stacked, for example, Figure 27 The semiconductor device shown has COP or Figure 28 The semiconductor device proof of concept (POC) is shown. The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 301. The second semiconductor die 301 may be chip-level or wafer-level.

[0233] The second semiconductor die 301 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 301 can be electrically coupled to each other through bonding interfaces (CBSs). The second semiconductor die 301 can be referred to as a "core die," a "semiconductor chip," or a "memory chip."

[0234] Bonding interfaces (CBS) can include microbump bonding, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0235] In some embodiments, the second semiconductor die 301 may be wafer flipped and back-side ground to form a bonding interface CBS.

[0236] like Figure 30 As shown, the stacked assembly 400 may include a component of semiconductor dies. For example, the stacked assembly 400 may include a first semiconductor die BSD, a plurality of second semiconductor dies 401, and a plurality of third semiconductor dies 402. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 401 and each third semiconductor die 402 may include a memory cell array according to the above embodiment. The second semiconductor dies 401 and the third semiconductor dies 402 may have different structures.

[0237] Each second semiconductor die 401 may include Figure 27 The semiconductor device COP shown includes a memory cell array stacked on top of a peripheral circuitry portion. Each third semiconductor die 402 may include, for example... Figure 28 The semiconductor device POC shown has its peripheral circuitry stacked on top of the memory cell array.

[0238] In some embodiments, each second semiconductor die 401 may include Figure 28 The semiconductor device POC shown includes peripheral circuitry stacked on top of a memory cell array, and each third semiconductor die 402 may include... Figure 27 The semiconductor device COP shown has a memory cell array stacked on top of the peripheral circuitry.

[0239] The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 401 and the third semiconductor die 402. The second semiconductor die 401 and the third semiconductor die 402 may be chip-level or wafer-level.

[0240] The second semiconductor die 401 and the third semiconductor die 402 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 401 can be electrically coupled to each other through bonding interfaces (CBSs). The second semiconductor die 401 and the third semiconductor die 402 can be referred to as "core dies," "semiconductor chips," or "memory chips."

[0241] Bonding interfaces (CBS) can include microbumps, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0242] In some embodiments, wafer flipping and back-side grinding can be performed to form a bonding interface CBS. For example, the second semiconductor die 401 and / or the third semiconductor die 402 may be wafer flipped and back-side ground.

[0243] Figure 29 and Figure 30 The stacked components 300 and 400 shown can be high-bandwidth memories.

[0244] According to various embodiments of the present invention, the parasitic capacitance between the vertically stacked horizontal conductors is reduced because an air gap is formed between them.

[0245] While embodiments of this disclosure have been described and illustrated in conjunction with specific examples and accompanying drawings, the disclosed embodiments are not intended to limit this disclosure. Furthermore, it should be noted that those skilled in the art, based on their understanding of this disclosure, can implement the embodiments of this disclosure in various ways through substitutions, alterations, and modifications without departing from the spirit and / or scope of this disclosure and its appended claims. Moreover, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a plurality of nanosheets vertically stacked; a first wire co-coupled with a first edge of the nanosheets, the first wire being vertically oriented; a plurality of data storage elements, each data storage element coupled to a second edge of the nanosheets; a plurality of second wires, each second wire surrounding the nanosheets and being horizontally oriented; and a plurality of inter-cell dielectric layers disposed between the second wires and each inter-cell dielectric layer including an air gap. Each of the inter-cell dielectric layers includes an air gap forming layer in which the air gap is embedded.

2. The semiconductor device of claim 1, wherein, The air gap forming layer includes silicon oxide.

3. The semiconductor device of claim 2, wherein, Each of the inter-cell dielectric layers further includes silicon oxycarbide in contact with the first wire.

4. The semiconductor device of claim 1, wherein, 5. The semiconductor device of claim 1, further comprising: a first spacer disposed between each of the inter-cell dielectric layers and each of the data storage elements; and a second spacer disposed between each of the inter-cell dielectric layers and the first wire. The first spacer has a shape surrounding the nanosheets at a same horizontal level and covering sides of each of the inter-cell dielectric layers. Each of the nanosheets includes a flat sheet in contact with the first wire and a sector-shaped sheet in contact with each of the data storage elements.

6. The semiconductor device of claim 1, wherein, Each of the nanosheets includes a first doped region and a second doped region spaced apart from each other in a second direction and a channel between the first doped region and the second doped region, and wherein the first doped region and the channel are disposed in the flat sheet, and the second doped region is disposed in the sector-shaped sheet.

7. The semiconductor device of claim 1, wherein, 9. The semiconductor device of claim 1, further comprising:

8. The semiconductor device of claim 7, wherein, a first contact node disposed between the nanosheets and the first wire; and a second contact node disposed between the nanosheets and the data storage elements. The second contact node includes a selective epitaxial growth layer.

11. A method for manufacturing a semiconductor device, the method comprising: forming nanosheet target layers vertically stacked and spaced apart from each other over a substrate; 10. The semiconductor device of claim 9, wherein, trimming a first portion of the nanosheet target layers and forming flat sheets; forming a first spacer layer defining an inner space in an upper portion and a lower portion of the flat sheets; forming an air gap target layer filling the inner space; forming a lift-off barrier layer at an entrance of the inner space and a lift-off path between the lift-off barrier layers; removing the air gap target layer through the lift-off path and forming an initial air gap; forming an air gap forming layer filling the initial air gap, the air gap forming layer having an air gap embedded therein; horizontally recessing the first spacer layer to form a first spacer covering sides of the air gap forming layer and a surrounding recess exposing the upper portion and the lower portion of the flat sheets; and forming a horizontal wire filling the surrounding recess, the horizontal wire disposed between the air gap forming layers. The air gap forming layer includes a dielectric material. The air gap forming layer includes silicon oxide. The air gap target layer includes polysilicon or silicon oxide. The lift-off barrier layer is selectively deposited from an exposed surface of the first spacer layer.

12. The method of claim 11, wherein, ​ 13. The method of claim 11, wherein, ​ 14. The method of claim 11, wherein, ​ 15. The method of claim 11, wherein, ​ 16. The method of claim 11, wherein, The peeling barrier layers each include silicon oxycarbide, and the first spacer layer includes silicon nitride.

17. The method of claim 11, wherein, The nanosheet target layers each include monocrystalline silicon.

18. The method of claim 11, further comprising: forming a first contact node coupled with the flat plate-like sheet; forming a vertical wire commonly coupled with the first contact node; horizontally recessing a second portion of the nanosheet target layers and forming a fan-shaped sheet; selectively growing the second contact node on a side of the fan-shaped sheet; and forming a data storage element coupled to the second contact node.

19. The method of claim 18, wherein, Selectively growing the second contact node on the side of the fan-shaped sheet includes growing a doped silicon layer by selective epitaxial growth.

20. The method of claim 11, wherein, The horizontal wires extend around and surround the flat plate-like sheets disposed at the same horizontal level, and each of the air gap formation layers is disposed between the horizontally stacked horizontal wires.

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