Preparation method of semiconductor memory

Abstract

The invention provides a preparation method of a semiconductor memory, which is applied to the technical field of semiconductors. According to the semiconductor memory and the manufacturing method thereof, the first supporting layer is formed on the side wall of the top of each lower electrode, the thickness of the insulating isolation material between the tops of the adjacent lower electrodes is increased through the first supporting layers, the risk of short circuit of the adjacent lower electrodes is reduced, and the efficiency and reliability of the semiconductor memory are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a preparation method of semiconductor memory. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a volatile memory and is an indispensable key element in many electronic products. DRAM is an array area formed by a large number of memory cells, and is used to store data, and each memory cell is composed of a metal oxide semiconductor (MOS) transistor and a capacitor structure in series. The capacitor structure forms a large array. In order to improve the density of the capacitor structure, the top of the lower electrode arranged in the array is prone to short circuit. SUMMARY

[0003] The present application aims to provide a preparation method of semiconductor memory, so as to reduce short circuit of adjacent lower electrodes and improve the performance and reliability of the semiconductor memory.

[0004] To solve the above technical problems, the present application provides a preparation method of semiconductor memory, comprising: providing a substrate;

[0005] forming a plurality of stack structures arranged at intervals on the substrate, the stack structure comprising a first sacrificial layer at the top;

[0006] forming a lower electrode layer filled in the interval between adjacent stack structures and extending to cover the top surface of the first sacrificial layer;

[0007] removing the first sacrificial layer and part of the lower electrode layer, and forming a plurality of lower electrodes arranged at intervals and having a top surface higher than the top surface of the remaining stack structure;

[0008] forming a first support layer covering the exposed top surface and sidewall of the lower electrode and the top surface of the stack structure, and the first support layer defining a first groove between adjacent lower electrodes;

[0009] forming a second sacrificial layer covering the first support layer and filling the first groove;

[0010] removing part of the second sacrificial layer and part of the first support layer to form a second groove;

[0011] forming a filling layer covering the second sacrificial layer and the stack structure and filling the second groove;

[0012] Remove part of the filler layer until the top surface of the second sacrificial layer is exposed;

[0013] The second sacrificial layer is removed to form the third groove;

[0014] A second support layer is formed and filled into the third groove.

[0015] Furthermore, the step of forming the second groove may also include:

[0016] A portion of the second sacrificial layer and a portion of the first support layer located on the stacked structure are removed, and the second groove exposes the top surface of the stacked structure.

[0017] Furthermore, at least one projection of the second groove on the substrate overlaps with the projection of the first groove on the substrate, so that the second groove re-exposes the first groove.

[0018] Furthermore, the width of the second groove in the horizontal direction is equal to the width of the first groove in the horizontal direction.

[0019] Furthermore, the second groove extends horizontally to expose a portion of the top surface of the lower electrode.

[0020] Furthermore, the maximum width of the second groove in the horizontal direction is greater than the maximum width of the first groove in the horizontal direction.

[0021] Furthermore, the filling layer also extends to cover the top surface of the lower electrode exposed in the second groove.

[0022] Furthermore, the adjacent third grooves are isolated by the filling layer.

[0023] Furthermore, after forming the second support layer, it may also include:

[0024] Remove a portion of the second support layer until the top surface of the remaining fill layer is exposed;

[0025] Remove the remaining filler layer to re-expose the second groove, which exposes the first support layer located between adjacent lower electrodes and on opposite sidewalls.

[0026] Furthermore, the remaining second support layer extends and covers the first support layer on a portion of the top surface of the lower electrode.

[0027] Furthermore, the method for fabricating the semiconductor memory may further include:

[0028] The lower support layer is flush with the sides of the remaining first and second support layers.

[0029] As described above, by removing the first sacrificial layer and part of the lower electrode layer at the top of the stacked structure, multiple lower electrodes are formed, and there is an opening at the top between adjacent lower electrodes. Then, by forming a first support layer on the sidewall of the opening, an insulating protective film is formed on the sidewall of the top of each lower electrode. This increases the thickness of the insulating isolation material between the tops of adjacent lower electrodes through the first support layer, reducing the risk of short circuits between adjacent lower electrodes and ultimately improving the performance and reliability of the semiconductor memory. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 This is a schematic flowchart of the semiconductor memory fabrication method provided in the embodiments of the present invention;

[0032] Figures 2-16 This is a schematic diagram of the semiconductor memory fabrication method provided in the first embodiment of the present invention during the fabrication process;

[0033] Figures 17-24 This is a schematic diagram of the semiconductor memory fabrication method provided in the second embodiment of the present invention during the fabrication process.

[0034] The attached figures are labeled as follows:

[0035] 100 - Substrate, 100A - First region, 100B - Second region, 110 - Stacked structure, 111 - First stacked layer, 112 - Second stacked layer, 113 / 113' - Third stacked layer, 114 - Fourth stacked layer, 115 - First sacrificial layer, 101 - Spacer, 120 - Lower electrode layer, 121 - Lower electrode, 102 - Opening, 130 / 131 - First support layer, 103 - First groove, 140 / 141 - Second sacrificial layer, 150 - Photoresist layer, 104 - Second groove, 160 / 161 - Filling layer, 105 - Third groove, 170 / 171 / 172 - Second support layer, 180 - Dielectric layer, 190 - Upper electrode.

[0036] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0037] To enable those skilled in the art to further understand this invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that features in several different embodiments can be substituted, rearranged, or mixed to complete other embodiments without departing from the spirit of the invention.

[0038] To facilitate easy understanding and maintain the simplicity of the illustrations, many of the diagrams in this invention depict only a portion of the semiconductor structure, and specific components are not drawn to scale. Furthermore, the number and dimensions of each component in the diagrams are for illustrative purposes only and are not intended to limit the scope of the invention. For simplification, some components may be omitted from the diagrams. The descriptions of the vertical relationships between components in the diagrams should be understood by those skilled in the art to refer to their relative positions; therefore, the same structure can be obtained by flipping the diagrams, and all such interpretations should fall within the scope of this specification.

[0039] For ease of understanding, the horizontal and vertical directions are defined below, where the horizontal direction is the direction parallel to the surface of the substrate 100, and the vertical direction is the direction perpendicular to the surface of the substrate 100.

[0040] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the semiconductor memory fabrication method provided in an embodiment of the present invention. Figure 1 As shown, the semiconductor memory fabrication method provided in this embodiment includes at least the following steps:

[0041] Step S101: Provide a substrate.

[0042] Step S102: Forming multiple stacked structures, which are disposed on the substrate at intervals, wherein the stacked structures include a first sacrificial layer located on top.

[0043] Step S103: Form a lower electrode layer, fill the gaps between adjacent stacked structures and extend to cover the top surface of the first sacrificial layer.

[0044] Step S104: Remove the first sacrificial layer and part of the lower electrode layer, and form a plurality of lower electrodes spaced apart from each other and with their top surfaces higher than the top surfaces of the remaining stacked structure.

[0045] Step S105: A first support layer is formed to cover the exposed top surface and sidewalls of the lower electrode, as well as the top surface of the stacked structure. The first support layer defines a first groove between adjacent lower electrodes.

[0046] Step S106: Form a second sacrificial layer to cover the first support layer and fill the first groove.

[0047] Step S107: Remove a portion of the second sacrificial layer and a portion of the first support layer to form a second groove.

[0048] Step S108: A filling layer is formed to cover the second sacrificial layer and the stacked structure, and to fill the second groove.

[0049] Step S109: Remove part of the filler layer until the top surface of the second sacrificial layer is exposed.

[0050] Step S110: Remove the second sacrificial layer to form the third groove.

[0051] Step S111: A second support layer is formed and filled into the third groove.

[0052] To enable those skilled in the art to easily understand the semiconductor memory fabrication method in the embodiments of this invention, the following will further explain the semiconductor memory fabrication method proposed in this invention with reference to various structural schematic diagrams during the fabrication process. Among them, Figures 2-16 This is a schematic diagram of the semiconductor memory fabrication method provided in the first embodiment of the present invention during the fabrication process.

[0053] Please see Figure 2 Performing step S101 above, a substrate 100 is provided, and the substrate 100 is divided into a first region 100A and a second region 100B. The first region 100A is, for example, a cell region of a semiconductor memory, and the second region 100B is, for example, a peripheral region of the semiconductor memory. The first region 100A and the second region 100B are arranged adjacent to each other, exemplarily. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but not limited thereto. Bit line structures, sidewall structures, contact structures, and connection pad structures (not shown) may be formed within the substrate 100, but not limited thereto.

[0054] Please continue reading. Figure 2In step S102, a stacked structure layer is formed on the substrate 100 using at least one of the deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The stacked structure layer includes a first stacked layer 111, a second stacked layer 112, a third stacked layer 113, and a fourth stacked layer 114, as well as a first sacrificial layer 115, which are stacked sequentially from bottom to top. By setting the first sacrificial layer 115 on the top of the stacked structure layer, preparation is made for the subsequent formation of a support layer and / or a sacrificial layer on the top two sidewalls of the lower electrode. The first sacrificial layer 115 is subsequently completely removed without affecting the structure of the capacitor itself. The setting of the first stacked layer 111 to the fourth stacked layer 114 provides a more solid support for the lower electrode that is subsequently formed, but this is not a limitation. It should be understood that the top surface height of the first sacrificial layer 115 in the first region 100A and the second region 100B of the substrate 100 may be different. For example, the top surface height of the first sacrificial layer 115 in the second region 100B may be higher than that in the first region 100A, but this is not a limitation.

[0055] Next, a patterned photoresist layer (not shown) can be formed on the surface of the first sacrificial layer 115. Using the patterned photoresist layer as a mask, a vertically downward etching process, such as a dry etching process, is performed on the stacked structure layer to form a plurality of spacers 101 (which can also be understood as vias or through holes) within the stacked structure layer, and to form a plurality of discrete stacked structures 110 separated by the plurality of spacers 101. The spacers 101 pass vertically through the first sacrificial layer 115, the fourth stacked layer 114, the third stacked layer 113, the second stacked layer 112, and the first stacked layer 111 until the top surface of the substrate 100 is exposed. Their shape can be a regular quadrilateral, such as a rectangle, or an inverted trapezoid, and is not limited thereto. In one embodiment, the first sacrificial layer 115, the fourth stacked layer 114, and the second stacked layer 112 may each comprise a single or multiple layers of oxide material, such as silicon oxide, boro-phospho-silicate glass (BPSG), or other sacrificial materials having a desired etch selectivity ratio with the materials of the first stacked layer 111 and the third stacked layer 113, but are not limited thereto. The materials of the first stacked layer 111 and the third stacked layer 113 may be silicon carbonitride (SiCN).

[0056] Please see Figure 3In step S103, a lower electrode layer 120 is formed on the substrate 100 where the spacers 101 are formed using a deposition process such as chemical vapor deposition. After the lower electrode layer 120 fills the plurality of spacers 101, it also extends laterally to the top surface of the first sacrificial layer 115 exposed on both sides of the spacers 101, so as to bury all film structures on the substrate 100. In one embodiment, the lower electrode layer 120 may include a single layer or multiple layers of conductive material, such as doped silicon, tungsten, copper, titanium nitride or other suitable conductive materials, but is not limited thereto.

[0057] Please see Figure 4 In step S104, an etching process, such as a dry etching process, or a polishing process, such as a chemical mechanical polishing process, can be used to remove / remove part of the first sacrificial layer 115 and part of the lower electrode layer 120 in the vertical direction to form a plurality of mutually spaced lower electrodes 121 on the first region 100A of the substrate 100. At this time, since the top surfaces of the first sacrificial layer 115 in the stacked structure 110 in the first region 100A and the second region 100B are not flush, the top surface of the lower electrode 121 is flush with the top surface of the remaining first sacrificial layer 115 in the stacked structure 110 on both sides, but lower than the top surface of the remaining first sacrificial layer 115 in the stacked structure 110 in the second region 100A.

[0058] Please see Figure 5 Following step S104, the remaining first sacrificial layers 115 on the first region 100A and the second region 100B of the substrate 100 can be further removed. Since the top surface of the lower electrode 121 is higher than the top surface of the fourth stacked layer 114 in the remaining stacked structure 110, an opening 102 is formed between the tops of adjacent lower electrodes 121. At this time, the sidewalls of the opening 102 expose the top sidewalls of the lower electrode 121, while the bottom of the opening 102 exposes the top surface of the fourth stacked layer 114 in the stacked structure 110.

[0059] Please see Figure 6In step S105, a first support layer 130 is formed on the inner surface of the opening 102 and the top surface of the lower electrodes 121 on both sides of the opening 102 using a deposition process such as chemical vapor deposition, and a first groove 103 is defined in the remaining space of the opening 102. In this embodiment, the sidewall of the opening 102 exposes the top sidewall of the lower electrode 121, and the bottom surface of the opening 102 exposes the top surface of the fourth stacked layer 114 in the stacked structure 110 between adjacent lower electrodes 121. Therefore, the first support layer 130 is formed by covering the exposed top surface and sidewall of the lower electrode 121, as well as the top surface of the stacked structure 110 (or the fourth stacked layer 114). At the same time, the first groove 103 is also located between adjacent lower electrodes 121. At this time, the first groove 103 is located in the opening 102, but its width in the horizontal direction is smaller than the width of the opening 102 in the horizontal direction. In one embodiment, the material of the first support layer 130 may be the same as the material of the first stacked layer 111 and the third stacked layer 113, for example, silicon carbonitride (SiCN), but is not limited thereto.

[0060] Please see Figure 7 Following step S106, a second sacrificial layer 140 is formed on both the first region 100A and the second region 100B of the substrate 100. At this time, the second sacrificial layer 140 at least fills a plurality of the first grooves 103. Then, a photoresist layer 150 is formed on the top surface of the second sacrificial layer 140; the photoresist layer 150 has a groove pattern formed on it for subsequent formation of grooves in the second sacrificial layer 140. In one embodiment, the groove pattern in the photoresist layer 150 is only applied to a portion of the first grooves 103, for example... Figure 7 The first groove 103, located inside the outermost two sides of the plurality of lower electrodes 121, and the edge region in the second region 100B, i.e., the photoresist layer 150, exposes not only a portion of the top surface of the second sacrificial layer 140 in the first region 100A, but also the top surface of the second sacrificial layer 140 located at the edge in the second region 100B. The material of the second sacrificial layer 140 can be, exemplarily, an oxide material, such as silicon oxide or borosilicate glass.

[0061] Please see Figure 8In step S107, using the photoresist layer 150 as a mask, the second sacrificial layer 140 and the first support layer 130 below it are etched downwards in the vertical direction to remove the second sacrificial layer 140 and the first support layer 130 corresponding to the groove pattern in the photoresist layer 150, thereby forming a second groove 104. Simultaneously, at least one first groove 103 is re-exposed, meaning that the projection of at least one second groove 104 onto the substrate 100 overlaps with the projection of one first groove 103 onto the substrate 100, so that the second groove 104 re-exposes the first groove 103. At this time, the width of the second groove 104 that re-exposes the first groove 103 in the horizontal direction is equal to the width of the first groove 103 in the horizontal direction. In this step, any groove formed after etching away the second sacrificial layer 140 and the first support layer 130 below it can be called a second groove 104. However, since some second grooves 104 are re-exposed first grooves 103, this embodiment... Figure 8 The second groove 104, which is re-exposed from the first groove 103, is still identified by the reference numeral for the first groove 103, while the second groove 104 located on the second region 100B of the substrate 100 is identified by reference numeral 104. The sidewalls of the re-exposed first groove 103 now expose the first support layer 131 covering the top sidewall of the lower electrode 121 (in this embodiment, the remaining first support layer after this step is identified by reference numeral 131, e.g., ...). Figure 8 As shown in the figure, its bottom exposes the top surface of the fourth stacked layer 114 in the stacked structure 110. For easy distinction, in this embodiment, the remaining second sacrificial layer after this step is identified by reference numeral 141.

[0062] Please see Figure 9 After performing step S108, a filling layer 160 can be formed on the first region 100A and the second region 100B. The filling layer 160 covers the second sacrificial layer 141 and the stacked structure 110, and fills the second groove 104 and the re-exposed first groove 103. Exemplarily, the material of the filling layer 160 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, nitrogen-doped silicon carbide, low-dielectric-constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low-dielectric-constant dielectric materials, or combinations thereof, but is not limited thereto.

[0063] Please see Figure 10 Then, performing step S109, a portion of the filler layer 160 is removed using an etching process, such as a dry etching process, until the top surface of the second sacrificial layer 141 is exposed, so that the remaining filler layer 161 only fills the second groove 104. At this time, the top surface of the filler layer 161 is flush with the top surface of the second sacrificial layer 141.

[0064] Please seeFigure 11 After performing step S110, a portion of the second sacrificial layer 141 and a portion of the filling layer 161 are removed vertically downwards to form at least one third groove 105. In this embodiment, the third groove 105 overlaps with a portion of the first groove 103, while the remaining portion overlaps with the second groove 104, exposing the first support layer 131 on both the sidewalls and the bottom. This results in the third groove 105 having a horizontal width smaller than the first groove 103 and also smaller than the second groove 104.

[0065] Please see Figure 12 Performing step S111 above, a second support layer 170 is formed on the substrate 100; the second support layer 170 fills the third groove 105 and extends to cover the top surface of the filling layer 161 located on the second region 100B and the top surface of the first support layer 131 exposed on the first region 100A. For example, the material of the second support layer 170 may be the same as the material of the first support layer 131, such as silicon carbonitride (SiCN).

[0066] Please see Figure 13 and Figure 14 Following step S111, a portion of the second support layer 170 and the filling layer 161 and the first support layer 131 below it are then etched and removed in a vertical direction to re-expose at least one first groove 103 and the second groove 104 located on the second region 100B. The remaining second support layer after this step is marked with reference numeral 171. At this point, the semiconductor structure in this embodiment does not include the filling layer 161, meaning that the filling layer 161 has been completely removed through multiple steps. Then, the fourth stacked layer 114 and a portion of the third stacked layer 113 in the stacked structure 110 can be removed further using an etching solution along the first groove 103 and the second groove 104 located on the second region 100B that were re-exposed in this step. In this embodiment, the removed portion of the third stacked layer 113 at least partially overlaps with the first groove 103 or the second groove 104 on the second region 100B that is exposed after the removal of the second support layer 170 and the filling layer 161 and the first support layer 131 below it, while the remaining third stacked layer 113' continues to cover the sidewall of the lower electrode 121.

[0067] Please see Figure 15 Following step S111, at least one first groove 103 is exposed again in the first region 100A and the second groove 104 in the second region 100B. All second stacked layers 112 are removed, and the second support layer 171 with its top surface higher than the first support layer 131 is removed simultaneously, so that the remaining second support layer 172 only fills part of the first groove 103.

[0068] Please see Figure 16 Following step S111 above, a dielectric layer 180 can be formed on the sidewall of the lower electrode 131, the top surface of the first support layer 131, and the sidewall using semiconductor manufacturing processes such as deposition and etching. An upper electrode 190 is then formed on the dielectric layer 180, thus forming a capacitor composed of the lower electrode 131, the dielectric layer 180, and the upper electrode 190. In one embodiment, the dielectric layer 180 may include a high dielectric constant metal oxide layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials, or other suitable dielectric materials, while the material of the upper electrode 190 may include titanium nitride, tantalum nitride, SiGe, combinations of the above materials, or other suitable conductive materials, but is not limited thereto. Furthermore, the materials of the dielectric layer 180 and the upper electrode 190 may extend to fill the regions corresponding to the fourth stacked layer 114, the third stacked layer 113, and the second stacked layer 112 in the stacked structure 110 located on the first region 100A and the second region 100B as removed in the above steps, but are not limited thereto.

[0069] Obviously, in this embodiment, a first support layer 131 is formed on the top outer surface (side wall and top surface) of the lower electrode 131 in the capacitor. The top gap between some adjacent lower electrodes 131 is filled with not only the first support layer 131 but also the second support layer 172. This allows the adjacent lower electrodes 131 to be separated by the dielectric layer 180 and the upper electrode 190, which increases the thickness of the insulating material between adjacent lower electrodes 131 and reduces the risk of short circuit between adjacent lower electrodes.

[0070] Those skilled in the art will readily understand that, to meet actual product requirements, the method for fabricating the semiconductor memory of this invention may have other forms and is not limited to those described above. Further embodiments or variations of the method for fabricating the semiconductor memory of this invention will be described below. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0071] in, Figures 2-6 and 17~ Figure 24 This is a schematic diagram of the semiconductor memory fabrication method provided in the second embodiment of the present invention during the fabrication process.

[0072] like Figures 2-6 As shown, the method for fabricating the semiconductor memory in the second embodiment of the present invention is largely the same as the method for fabricating the semiconductor memory in the first embodiment described above, and the similarities will not be repeated here. The main difference between the method for fabricating the semiconductor memory in the second embodiment of the present invention and the method for fabricating the semiconductor memory in the first embodiment described above is:

[0073] Please see Figure 17 and Figure 18 After performing steps S106 and S107, and forming the second sacrificial layer 140 on both the first region 100A and the second region 100B of the substrate 100, the second embodiment of the present invention also forms a photoresist layer 150 on the second sacrificial layer 140. However, the groove pattern in the photoresist layer 150 in this embodiment differs in the horizontal width from the groove pattern in the first embodiment. Specifically, the horizontal width of the groove pattern in the photoresist layer 150 in this embodiment is greater than the horizontal width of the groove pattern in the first embodiment. Therefore, in this embodiment, when using the photoresist layer 150 as a mask, the maximum horizontal width of the second groove 104 formed is larger than the maximum horizontal width of the second groove 104 in the first embodiment; for example... Figure 18 As shown, in this embodiment, the second groove 104 not only re-exposes the first groove 103, but also exposes part of the top surface of the lower electrodes 121 on both sides of the first groove 103. At this time, the maximum width of the second groove 104 in the horizontal direction is greater than the maximum width of the first groove 103 that it re-exposes in the horizontal direction.

[0074] Please see Figure 19 After performing the above step S108, a filling layer 160 can also be formed on the first region 100A and the second region 100B. However, the filling layer 160 in this embodiment is different from the filling layer 160 in the first embodiment. The filling layer 160 covers the second sacrificial layer 141 and the stacked structure 110, and fills the second groove 104. It also extends to cover the top surface of the lower electrode 121 exposed in the second groove 104.

[0075] Please see Figure 20 , combined Figure 11 In step S110, the second sacrificial layer 141 and part of the filler layer 160 are removed vertically downwards to form a third groove 105. In this embodiment, the third groove 105 is a portion of the first groove 103. During the formation of the third groove 105, the remaining filler layer 161 and the re-exposed first support layer 131 are obtained through the third groove 105. This ensures that adjacent third grooves 105 are isolated by the filler layer 161, and the top surface of the remaining filler layer 161 is higher than the top surface of the first support layer 131.

[0076] Please see Figure 21 , combined Figure 12 Perform the above step S111 to form a second support layer 170 on the substrate 100. At this time, the second support layer 170 buries the lower electrode layer 121, the first support layer 131 and the filling layer 161, that is, the top surface of the second support layer 170 is higher than the top surface of the filling layer 161. Then, a portion of the second support layer 170 can be removed in the vertical direction until the top surface of the remaining filling layer 161 is exposed. At this time, the remaining second support layer 171 fills the third groove 105, extends and covers the first support layer 131 on part of the top surface of the lower electrode 121, and is flush with the top surfaces of the filling layers 161 on both sides.

[0077] Please see Figure 22 Following step S111, the remaining filling layer 161 from the previous step is removed vertically using an etching solution to re-expose the second groove 104, which exposes the first support layer 131 located between adjacent lower electrodes 121 and on opposite sidewalls. Then, the fourth stacked layer 114 in the stacked structure 110 is removed along the re-exposed second groove 104 using an etching solution.

[0078] It is understood that, in other embodiments, after the second recess 104 is re-exposed and before the fourth stacked layer 114 is removed, it is also possible to... Figure 22 A lower support layer (not shown) is formed on the sidewalls of the first support layer 131 and the second support layer 171 shown.

[0079] Please see Figure 23 Following step S111 above, a portion of the third stacked layer 113 and the second stacked layer 112 are removed downwards along the fourth stacked layer 114 removed in the previous step, leaving the third stacked layer 113' and the second support layer 172 located on the sidewall of the lower electrode 121.

[0080] Please see Figure 24 Following step S111 above, and similar to the first embodiment, a dielectric layer 180 and an upper electrode 190 can be further formed, which will not be described again here.

[0081] In summary, by removing the first sacrificial layer and part of the lower electrode layer at the top of the stacked structure to form multiple lower electrodes with openings at the top between adjacent lower electrodes, and then forming an insulating protective film on the sidewall of the opening by forming a first support layer, the thickness of the insulating isolation material between the tops of adjacent lower electrodes is increased by the first support layer, reducing the risk of short circuits between adjacent lower electrodes, and ultimately improving the performance and reliability of the semiconductor memory.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0083] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor memory, characterized in that, Comprising: providing a substrate; forming a plurality of stack structures spaced apart from each other on the substrate, the stack structures comprising a first sacrificial layer on top; forming a lower electrode layer filling in the spaces between adjacent stack structures and extending to cover the top surface of the first sacrificial layer; removing the first sacrificial layer and part of the lower electrode layer and forming a plurality of lower electrodes spaced apart from each other and having a top surface higher than the top surface of the remaining stack structures; forming a first support layer covering the exposed top surface and sidewalls of the lower electrodes and the top surface of the stack structures, the first support layer defining first recesses between adjacent lower electrodes; forming a second sacrificial layer covering the first support layer and filling in the first recesses; removing part of the second sacrificial layer and part of the first support layer to form second recesses; forming a filling layer covering the second sacrificial layer and the stack structures and filling in the second recesses; removing part of the filling layer until the top surface of the second sacrificial layer is exposed; removing the second sacrificial layer to form third recesses; forming a second support layer filling in the third recesses.

2. The method of claim 1, wherein the semiconductor memory is a DRAM. The step of forming the second recesses further comprises: removing part of the second sacrificial layer and part of the first support layer on the stack structures, the second recesses exposing the top surface of the stack structures.

3. The method for fabricating a semiconductor memory as described in claim 1, characterized in that, The projection of at least one of the second recesses on the substrate overlaps with the projection of one of the first recesses on the substrate, such that the second recesses re-expose the first recesses.

4. The method of producing a semiconductor memory device according to Claim 3, wherein The width of the second recesses in the horizontal direction is equal to the width of the first recesses in the horizontal direction.

5. The method of claim 1, wherein the semiconductor memory is a DRAM. The second recesses further extend horizontally to expose part of the top surface of the lower electrodes.

6. The method of producing a semiconductor memory device according to claim 5, wherein The maximum width of the second recesses in the horizontal direction is greater than the maximum width of the first recesses in the horizontal direction.

7. The method of producing a semiconductor memory device according to claim 5, wherein The filling layer further extends to cover the top surface of the lower electrodes exposed by the second recesses.

8. The method of producing a semiconductor memory device according to Claim 7, wherein The third recesses are isolated from each other by the filling layer.

9. The method of producing a semiconductor memory device according to Claim 8, wherein After forming the second support layer, further comprising: removing part of the second support layer until the top surface of the remaining filling layer is exposed; removing the remaining filling layer to re-expose the second recesses, the second recesses exposing the first support layer on the opposing sidewalls between adjacent lower electrodes.

10. The method of producing a semiconductor memory device according to Claim 9, wherein The remaining second support layer further extends to cover the first support layer on part of the top surface of the lower electrodes.

11. The method of producing a semiconductor memory device according to Claim 9, wherein Further comprising: a lower support layer, the lower support layer being flush with the side surfaces of the remaining first and second support layers.

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