Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the semiconductor device comprises a plurality of superlattice structures which are stacked in the direction perpendicular to a substrate; any two adjacent superlattice structures in the direction perpendicular to the substrate are a lower superlattice structure close to the substrate and an upper superlattice structure away from the substrate. The superlattice structure comprises a plurality of storage units, and the storage units are distributed in different layers and are distributed in a stacked mode in the direction perpendicular to the substrate; the memory cell includes a transistor including a semiconductor layer; the semiconductor layer extends along a column direction parallel to the substrate; the semiconductor columns are located between the lower superlattice structures and the upper superlattice structures which are adjacent in the direction perpendicular to the substrate; the first ends of the semiconductor columns are spaced from the lower superlattice structure, and the second ends of the semiconductor columns are connected with the upper superlattice structure. According to the semiconductor device provided by the embodiment of the invention, stacking of more layers of storage units can be realized, and the semiconductor device has higher storage density.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device can realize the stacking of more layers of memory cells, thereby achieving higher storage density and reducing production costs.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Multiple superlattice structures are distributed in different layers and stacked along a direction perpendicular to the substrate; any two adjacent superlattice structures along the direction perpendicular to the substrate are respectively the lower superlattice structure closer to the substrate and the upper superlattice structure farther from the substrate; each superlattice structure includes multiple memory cells, which are distributed in different layers and stacked along a direction perpendicular to the substrate; each memory cell includes a transistor, and each transistor includes a semiconductor layer; the semiconductor layer extends along a column direction parallel to the substrate;

[0008] A semiconductor pillar is located between the lower superlattice structure and the upper superlattice structure, which are adjacent to each other along a direction perpendicular to the substrate; the semiconductor pillar has a first end and a second end opposite to each other, the first end of the semiconductor pillar being spaced apart from the lower superlattice structure, and the second end of the semiconductor pillar being connected to the upper superlattice structure.

[0009] In some embodiments of this application, the second end of the semiconductor pillar is connected to the lowest semiconductor layer of the upper superlattice structure, and each of the lowest semiconductor layers is connected to at least one of the semiconductor pillars.

[0010] In some embodiments of this application, the semiconductor pillar extends in a direction perpendicular to the substrate;

[0011] The height of the semiconductor pillar in a direction perpendicular to the substrate is greater than its width in any direction parallel to the substrate.

[0012] In some embodiments of this application, the semiconductor pillar is made of the same material as the semiconductor layer.

[0013] In some embodiments of this application, the semiconductor layer connected to the semiconductor pillar is formed by laser-induced crystallization of the semiconductor pillar.

[0014] In some embodiments of this application, in the superlattice structure located at the bottom layer, the semiconductor layers are all formed by epitaxial growth process;

[0015] In all superlattice structures except the bottommost superlattice structure, all semiconductor layers except the bottommost semiconductor layer are formed by epitaxial growth.

[0016] In some embodiments of this application, the semiconductor device further includes word lines extending in a direction perpendicular to the substrate;

[0017] The word line passes through a plurality of memory cells stacked along a direction perpendicular to the substrate within the same superlattice structure; and / or,

[0018] The word lines pass through the memory cells of a plurality of superlattice structures stacked along a direction perpendicular to the substrate.

[0019] In some embodiments of this application, the transistor further includes a gate electrode that at least partially surrounds the semiconductor layer, and a gate insulating layer is present between the gate electrode and the semiconductor layer;

[0020] The gate electrode is part of the word line, and the gate electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are located in different regions of the same word line.

[0021] In some embodiments of this application, the semiconductor device further includes bit lines extending along a row direction parallel to the substrate;

[0022] The bit line is connected to a row of transistors of the memory cells distributed along the row direction within the same superlattice structure; and / or,

[0023] The bit line is connected to the transistors of a row of the superlattice structure distributed along the row direction.

[0024] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0025] A first stacked structure is obtained by forming multiple crystalline semiconductor layers stacked and spaced apart along a direction perpendicular to the substrate on a substrate using a first crystalline semiconductor material.

[0026] The uppermost semiconductor layer in the first stacked structure is etched to form a semiconductor pillar extending in a direction perpendicular to the substrate;

[0027] An amorphous initial semiconductor layer is formed on the surface of the semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material;

[0028] Using the crystallized semiconductor pillar as a mother plate, the initial semiconductor layer is induced to transform into the semiconductor layer;

[0029] Multiple semiconductor layers are stacked and spaced apart along a direction perpendicular to the substrate on the side of the uppermost semiconductor layer away from the substrate, resulting in a second stacked structure located on the side of the semiconductor pillar away from the substrate;

[0030] A gate insulating layer and a gate electrode are sequentially formed on the sidewall of the semiconductor layer.

[0031] In some embodiments of this application, the manufacturing method further includes repeating the following process one or more times after obtaining the second stacked structure and before forming the gate insulating layer:

[0032] The uppermost semiconductor layer is etched to form a semiconductor pillar extending in a direction perpendicular to the substrate;

[0033] The initial semiconductor layer is formed on the surface of the uppermost semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material;

[0034] Using the uppermost semiconductor pillar as a template, the initial semiconductor layer is induced to transform into the semiconductor layer;

[0035] A plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate.

[0036] In some embodiments of this application, each of the semiconductor layers in the first stacked structure is formed using an epitaxial growth process; and / or,

[0037] The plurality of semiconductor layers, stacked and spaced apart along a direction perpendicular to the substrate, are formed on the side of the uppermost semiconductor layer away from the substrate, including:

[0038] Using an epitaxial growth process, a plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate.

[0039] In some embodiments of this application, the height of the semiconductor pillar in the direction perpendicular to the substrate is greater than the thickness of the semiconductor layer;

[0040] The height of the semiconductor pillar in a direction perpendicular to the substrate is greater than its width in any direction parallel to the substrate.

[0041] In some embodiments of this application, the first stacked structure is formed on a substrate using a crystalline first semiconductor material, wherein a plurality of crystalline semiconductor layers are stacked and spaced apart along a direction perpendicular to the substrate, resulting in a first stacked structure, comprising:

[0042] Using an epitaxial growth process, multiple sacrificial layers and multiple preset semiconductor layers are sequentially and alternately formed on the substrate to obtain a first initial stacked structure; the preset semiconductor layers are formed from the crystallized first semiconductor material.

[0043] The first initial stacked structure is etched to form a plurality of first trenches penetrating the first initial stacked structure; the plurality of first trenches extend along a column direction parallel to the substrate and are spaced apart in a row direction parallel to the substrate; the plurality of first trenches space the preset semiconductor layer into a plurality of semiconductor layers that extend along the column direction and are spaced apart in the row direction, thereby obtaining the first stacked structure.

[0044] In some embodiments of this application, the uppermost semiconductor layer is etched to form semiconductor pillars extending in a direction perpendicular to the substrate, including:

[0045] An insulating layer is filled between adjacent semiconductor layers;

[0046] The uppermost semiconductor layer is etched to form a plurality of vias spaced apart along the column direction in the uppermost semiconductor layer. The plurality of vias space each of the uppermost semiconductor layers into a plurality of semiconductor pillars extending in a direction perpendicular to the substrate.

[0047] In some embodiments of this application, an amorphous initial semiconductor layer is formed on the surface of the semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material, including:

[0048] An insulating layer is filled between adjacent semiconductor pillars;

[0049] A predetermined initial semiconductor layer is formed on the substrate using an amorphous first semiconductor material, covering the exposed surface of each of the semiconductor pillars;

[0050] The preset initial semiconductor layer is etched to form a plurality of second trenches penetrating the preset initial semiconductor layer; the plurality of second trenches extend along a column direction parallel to the substrate and are spaced apart in a row direction parallel to the substrate; the plurality of second trenches space the preset initial semiconductor layer into a plurality of initial semiconductor layers extending along the column direction and spaced apart in the row direction; the initial semiconductor layers and the underlying semiconductor layer are stacked and aligned with each other in a direction perpendicular to the substrate.

[0051] In some embodiments of this application, a plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate, including:

[0052] The uppermost semiconductor layer is transformed from the initial semiconductor layer, and the uppermost semiconductor layer and the semiconductor layer in the first stacked structure are stacked and aligned with each other in a direction perpendicular to the substrate;

[0053] On the side of the uppermost semiconductor layer away from the substrate, a plurality of semiconductor layers are formed, stacked and spaced apart along a direction perpendicular to the substrate, and the plurality of semiconductor layers stacked on one side of the uppermost semiconductor layer are aligned with one of the uppermost semiconductor layers.

[0054] In some embodiments of this application, the manufacturing method further includes:

[0055] Before inducing the initial semiconductor layer to transform into the semiconductor layer using the crystallized semiconductor pillar as a mother plate, a suppression layer covering the initial semiconductor layer is formed on a substrate; the suppression layer is configured to suppress spontaneous crystallization of the initial semiconductor layer; and

[0056] After the initial semiconductor layer is transformed into the semiconductor layer, before forming multiple semiconductor layers again on one side of the uppermost semiconductor layer, the suppression layer is removed to expose the top surface of the semiconductor layer formed by the transformation of the initial semiconductor layer.

[0057] In some embodiments of this application, the step of using the crystallized semiconductor pillar as a mother plate to induce the initial semiconductor layer to transform into the semiconductor layer includes:

[0058] Using the crystallized semiconductor pillar as a mother plate, a laser-induced crystallization process is employed to induce the initial semiconductor layer to transform into the semiconductor layer.

[0059] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a gate electrode on the sidewall of the semiconductor layer includes:

[0060] Remove the insulating layer between adjacent semiconductor layers to expose the sacrificial layer;

[0061] Remove the sacrificial layer;

[0062] An insulating material is filled between adjacent semiconductor layers;

[0063] Etching is performed on a film layer formed of insulating material between two adjacent semiconductor layers to form a gate hole extending along the row direction between two adjacent semiconductor layers, and a word line hole extending in a direction perpendicular to the substrate between two adjacent semiconductor layers along the row direction, wherein the gate hole and the word line hole expose at least a portion of the sidewalls of the semiconductor layer.

[0064] The gate insulating layer and the gate electrode, which at least partially surround the semiconductor layer, are sequentially formed on the sidewalls of the gate hole and the word line hole.

[0065] In some embodiments of this application, the step of sequentially forming at least partially surrounding the gate insulating layer and the gate electrode on the sidewalls of the gate via and the word line via includes:

[0066] A gate insulating layer and a gate electrode layer, at least partially surrounding the semiconductor layer, are sequentially formed on the sidewalls of the gate via and the word line via; the gate electrode layer located between two adjacent semiconductor layers along the row direction is disconnected in the row direction;

[0067] The remaining gate electrode layers form gate electrodes that at least partially surround the semiconductor layer, and a plurality of gate electrodes located in different layers are connected within the word line vias.

[0068] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0069] The semiconductor device manufacturing method of this application embodiment can form a multi-layer superlattice structure to realize a 3D semiconductor device with an ultra-high number of horizontally stacked layers. This can effectively avoid a series of crystal quality problems caused by the excessive number of superlattice layers in traditional single-layer semiconductor devices, which exceeds the critical thickness.

[0070] The semiconductor device manufacturing method of this application embodiment can also replace the wafer bonding process to achieve 3D stacking, reducing the high cost and cumbersome process of wafer bonding.

[0071] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0072] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0073] Figure 1A A schematic diagram of the longitudinal section structure of a semiconductor device in an exemplary embodiment of this application, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0074] Figure 1B for Figure 1A A top view of the semiconductor device shown;

[0075] Figure 1C for Figure 1A The diagram shows a schematic cross-sectional view of the semiconductor device in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0076] Figure 2 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0077] Figure 3 This is a schematic diagram of a longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first initial stacked structure, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0078] Figure 4A A schematic diagram of a longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first stacked structure, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0079] Figure 4B for Figure 4A The diagram shows a top view of the semiconductor structure.

[0080] Figure 5 A top view of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after filling an insulating layer in a first trench;

[0081] Figure 6A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming semiconductor pillars, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0082] Figure 6B for Figure 6A A schematic diagram of the cross-section of the semiconductor structure shown, parallel to the substrate.

[0083] Figure 7A This is a schematic diagram of a longitudinal section structure in a longitudinal section perpendicular to the substrate and extending along the column direction after filling an insulating layer between adjacent semiconductor pillars, which is an exemplary embodiment of this application.

[0084] Figure 7B for Figure 7A A schematic diagram of the cross-section of the semiconductor structure shown, parallel to the substrate.

[0085] Figure 8 This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a predetermined initial semiconductor layer, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0086] Figure 9 This is a schematic diagram of a longitudinal section structure in a longitudinal section perpendicular to the substrate and extending along the row direction after filling an insulating layer between adjacent semiconductor pillars, which is an exemplary embodiment of this application.

[0087] Figure 10A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the suppression layer, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0088] Figure 10B for Figure 10A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0089] Figure 11A This is a schematic diagram of a longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after an initial semiconductor layer is converted into a semiconductor layer, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0090] Figure 11B for Figure 11A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0091] Figure 12A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the removal of the suppression layer, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0092] Figure 12B for Figure 12A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0093] Figure 13A A schematic diagram of a longitudinal section structure in a longitudinal section perpendicular to the substrate and extending along the column direction after a method for manufacturing a semiconductor device according to an exemplary embodiment of this application has been re-formed with multiple stacked semiconductor layers.

[0094] Figure 13B for Figure 13A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0095] Figure 14 A schematic diagram of a longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after opening a trench to form a transistor, on a longitudinal section perpendicular to the substrate and extending along the row direction;

[0096] Figure 15A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the removal of the sacrificial layer, on a longitudinal section perpendicular to the substrate and extending along the column direction;

[0097] Figure 15B for Figure 15A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0098] Figure 16A This is a schematic diagram of a longitudinal section structure in a longitudinal section perpendicular to the substrate and extending along the column direction, after removing the sacrificial layer and filling the space between adjacent semiconductor layers, according to an exemplary embodiment of this application.

[0099] Figure 16B for Figure 16A The diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0100] Figure 17A A side view in the column direction of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after forming gate vias and word line vias;

[0101] Figure 17B for Figure 17A The diagram shows a top view of the semiconductor structure.

[0102] Figure 17C for Figure 17AThe diagram shows a schematic cross-sectional view of the semiconductor structure in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0103] The meanings of the symbols in the attached diagram are as follows:

[0104] 10-Substrate; 11-Sacrificial layer; 12-Isolation layer; 13-Insulating layer; 13'-Insulating material; 14-Initial semiconductor layer; 14'-Preset initial semiconductor layer; 15-Suppression layer; 20-Transistor; 21-Semiconductor layer; 21'-Preset semiconductor layer; 22-Gate electrode; 23-Gate insulating layer; 24-First electrode; 25-Second electrode; 30-Semiconductor pillar; 100-Superlattice structure; 101-Lower superlattice structure; 102-Upper superlattice structure; 200-Memory cell; WL-Word line; BL-Bit line; T1-First trench; T2-Second trench; T3-Isolation trench; K1-Through hole; K2-Gate hole; K3-Word line hole. Detailed Implementation

[0105] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0106] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0107] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0108] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0109] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0110] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0111] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0112] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0113] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0114] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0115] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0116] In this application, "A and B are set in the same layer" means that A and B are distributed on the same horizontal plane, or although they are not on the same horizontal plane, they are both in different areas of the same supporting surface. In one embodiment, A and B are formed simultaneously by patterning the same film layer in the same single process.

[0117] In this application, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is defined as a film layer patterned to form a connected structure. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed into a connected structure through the same patterning process, or B may be directly grown epitaxially on A, and the materials of the two may not be exactly the same.

[0118] In this application, "A and B are aligned" means that the orthographic projection of A on the substrate and the orthographic projection of B on the substrate completely overlap or substantially overlap.

[0119] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0120] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0121] Monolithic 3DIC offers a seamless approach to achieving highly compact heterogeneous integration. It allows for the creation of diverse materials, devices, and technologies on different vertical layers of the same chip. The architecture and concepts of 3D Dynamic Random Access Memory (DRAM) have emerged as a result, with one approach being the use of Si / SiGe stacks as channel and sacrificial layers to realize 3D DRAM devices.

[0122] Due to the lattice mismatch of 4% between Si and Ge, direct epitaxial growth of Si on Si is possible. 1-x Ge x The epitaxial layer experiences strain due to lattice mismatch. When the thickness of the epitaxial layer exceeds a critical value, strain relaxation occurs, leading to dislocations and affecting the performance of the Si channel. Therefore, 3D DRAMs obtained using traditional epitaxial methods have a maximum layer count. How to continue growing a high-quality top film above the active layer to overcome this critical thickness, thus enabling unlimited stacking, has become a major research focus.

[0123] This application provides a semiconductor device.

[0124] Figure 1A A schematic diagram of the longitudinal section structure of a semiconductor device in an exemplary embodiment of this application, on a longitudinal section perpendicular to the substrate and extending along the column direction; Figure 1B for Figure 1A A top view of the semiconductor device shown; Figure 1C for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device in a longitudinal section perpendicular to the substrate and extending along the row direction.

[0125] like Figures 1A to 1C As shown, the semiconductor device includes: a plurality of superlattice structures 100 and semiconductor pillars 30;

[0126] Multiple superlattice structures 100 are distributed in different layers and stacked along a direction perpendicular to the substrate 10; any two superlattice structures adjacent along a direction perpendicular to the substrate 10 are respectively the lower superlattice structure 101 closer to the substrate 10 and the upper superlattice structure 102 farther from the substrate 10.

[0127] The superlattice structure includes a plurality of memory cells 200, which are distributed in different layers and stacked along a direction perpendicular to the substrate 10; each memory cell 200 includes a transistor 20, which includes a semiconductor layer 21; the semiconductor layer 21 extends along a column direction parallel to the substrate 10.

[0128] Semiconductor pillar 30 is located between the lower superlattice structure 101 and the upper superlattice structure 102, which are adjacent to each other along a direction perpendicular to the substrate 10; the semiconductor pillar 30 has a first end and a second end opposite to each other, the first end of the semiconductor pillar 30 is spaced apart from the lower superlattice structure 101, and the second end of the semiconductor pillar 30 is connected to the upper superlattice structure 102.

[0129] In some embodiments of this application, such as Figures 1A to 1C As shown, the second end of the semiconductor pillar 30 is connected to the lowest semiconductor layer 21 of the upper superlattice structure 102, and each of the lowest semiconductor layers 21 is connected to at least one of the semiconductor pillars 30.

[0130] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor pillar 30 extends in a direction perpendicular to the substrate 10;

[0131] The height of the semiconductor pillar 30 in the direction perpendicular to the substrate 10 is greater than its width in any direction parallel to the substrate 10.

[0132] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor pillar 30 is made of the same material as the semiconductor layer 21.

[0133] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor layer 21 connected to the semiconductor pillar 30 is formed by laser-induced crystallization of the semiconductor pillar 30.

[0134] In some embodiments of this application, in the superlattice structure located at the bottom layer, the semiconductor layer 21 is formed by an epitaxial growth process;

[0135] In all superlattice structures except the one located at the bottom, the semiconductor layers 21, except for the one located at the bottom, are formed by epitaxial growth.

[0136] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor device also includes word lines WL extending in a direction perpendicular to the substrate 10;

[0137] The word line WL passes through a plurality of memory cells 200 stacked along a direction perpendicular to the substrate 10 within the same superlattice structure; and / or,

[0138] The word line WL passes through the memory cells 200 of the multiple superlattice structures stacked along a direction perpendicular to the substrate 10.

[0139] In some embodiments of this application, such as Figures 1A to 1C As shown, the transistor 20 further includes a gate electrode 22, which at least partially surrounds the semiconductor layer 21, and a gate insulating layer 23 is provided between the gate electrode 22 and the semiconductor layer 21;

[0140] The gate electrode 22 is part of the word line WL, and the gate electrodes 22 of the plurality of memory cells 200 stacked along a direction perpendicular to the substrate 10 are located in different regions of the same word line WL.

[0141] In some embodiments of this application, the semiconductor device further includes bit lines extending along a row direction parallel to the substrate 10;

[0142] The bit line is connected to transistors 20 of a row of memory cells 200 distributed along the row direction within the same superlattice structure; and / or,

[0143] The bit line is connected to the transistor 20 of a row of the superlattice structure distributed along the row direction.

[0144] In some embodiments of this application, such as Figures 1A to 1C As shown, transistor 20 also includes a first electrode 24 and a second electrode 25 located on both sides of semiconductor layer 21, with the first electrode 24 connected to the bit line.

[0145] In some embodiments of this application, the first electrode 24, semiconductor layer 21 and second electrode 25 of the same transistor 20 may be distributed along the column direction.

[0146] In some embodiments of this application, the first electrode 24, semiconductor layer 21 and second electrode 25 of the same transistor 20 can be an integral structure.

[0147] The aforementioned storage unit may be a storage unit containing transistors, which may be access transistors. The storage unit may also contain other components, such as capacitors in a 1T1C storage unit, or read transistors and storage nodes in a 2T0C storage unit.

[0148] In some embodiments of this application, the storage cell may further include a capacitor 40, which includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the second electrode of a transistor located in the same storage cell.

[0149] In some embodiments of this application, the second electrode and the first capacitor electrode located in the same memory cell can be an integral structure.

[0150] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0151] In some embodiments of this application, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0152] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0153] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0154] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0155] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0156] In some embodiments of this application, the material of the bit line can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0157] In some embodiments of this application, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0158] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0159] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0160] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0161] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0162] Low-K materials, such as silicon oxide.

[0163] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0164] In some embodiments of this application, the dielectric layer may be made of silicon oxide or a high-K dielectric material. High-K materials, in some embodiments, may include any one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0165] In some embodiments of this application, the semiconductor device can be a 3D memory, such as a 3D DRAM. The 3D memory can be a 1T1C or 2T1C structure, or a 2T0C structure (containing a read transistor and a write transistor).

[0166] This application also provides a method for manufacturing a semiconductor device, which can be used to obtain the semiconductor device described above.

[0167] Figure 2 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.

[0168] like Figure 2 As shown, the manufacturing method includes:

[0169] A first stacked structure is obtained by forming multiple crystalline semiconductor layers stacked and spaced apart along a direction perpendicular to the substrate on a substrate using a first crystalline semiconductor material.

[0170] The uppermost semiconductor layer in the first stacked structure is etched to form a semiconductor pillar extending in a direction perpendicular to the substrate;

[0171] An amorphous initial semiconductor layer is formed on the surface of the semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material;

[0172] Using the crystallized semiconductor pillar as a mother plate, the initial semiconductor layer is induced to transform into the semiconductor layer;

[0173] Multiple semiconductor layers are stacked and spaced apart along a direction perpendicular to the substrate on the side of the uppermost semiconductor layer away from the substrate, resulting in a second stacked structure located on the side of the semiconductor pillar away from the substrate;

[0174] A gate insulating layer and a gate electrode are sequentially formed on the sidewall of the semiconductor layer.

[0175] In some embodiments of this application, the manufacturing method further includes repeating the following process one or more times after obtaining the second stacked structure and before forming the gate insulating layer:

[0176] The uppermost semiconductor layer is etched to form a semiconductor pillar extending in a direction perpendicular to the substrate;

[0177] The initial semiconductor layer is formed on the surface of the uppermost semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material;

[0178] Using the uppermost semiconductor pillar as a template, the initial semiconductor layer is induced to transform into the semiconductor layer;

[0179] A plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate.

[0180] In some embodiments of this application, each of the semiconductor layers in the first stacked structure is formed using an epitaxial growth process; and / or,

[0181] The plurality of semiconductor layers, stacked and spaced apart along a direction perpendicular to the substrate, are formed on the side of the uppermost semiconductor layer away from the substrate, including:

[0182] Using an epitaxial growth process, a plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate.

[0183] In some embodiments of this application, the height of the semiconductor pillar in the direction perpendicular to the substrate is greater than the thickness of the semiconductor layer;

[0184] The height of the semiconductor pillar in a direction perpendicular to the substrate is greater than its width in any direction parallel to the substrate.

[0185] In some embodiments of this application, the first stacked structure is formed on a substrate using a crystalline first semiconductor material, wherein a plurality of crystalline semiconductor layers are stacked and spaced apart along a direction perpendicular to the substrate, resulting in a first stacked structure, comprising:

[0186] Using an epitaxial growth process, multiple sacrificial layers and multiple preset semiconductor layers are sequentially and alternately formed on the substrate to obtain a first initial stacked structure; the preset semiconductor layers are formed from the crystallized first semiconductor material.

[0187] The first initial stacked structure is etched to form a plurality of first trenches penetrating the first initial stacked structure; the plurality of first trenches extend along a column direction parallel to the substrate and are spaced apart in a row direction parallel to the substrate; the plurality of first trenches space the preset semiconductor layer into a plurality of semiconductor layers that extend along the column direction and are spaced apart in the row direction, thereby obtaining the first stacked structure.

[0188] In some embodiments of this application, the uppermost semiconductor layer is etched to form semiconductor pillars extending in a direction perpendicular to the substrate, including:

[0189] An insulating layer is filled between adjacent semiconductor layers;

[0190] The uppermost semiconductor layer is etched to form a plurality of vias spaced apart along the column direction in the uppermost semiconductor layer. The plurality of vias space each of the uppermost semiconductor layers into a plurality of semiconductor pillars extending in a direction perpendicular to the substrate.

[0191] In some embodiments of this application, an amorphous initial semiconductor layer is formed on the surface of the semiconductor pillar on the side away from the substrate using an amorphous first semiconductor material, including:

[0192] An insulating layer is filled between adjacent semiconductor pillars;

[0193] A predetermined initial semiconductor layer is formed on the substrate using an amorphous first semiconductor material, covering the exposed surface of each of the semiconductor pillars;

[0194] The preset initial semiconductor layer is etched to form a plurality of second trenches penetrating the preset initial semiconductor layer; the plurality of second trenches extend along a column direction parallel to the substrate and are spaced apart in a row direction parallel to the substrate; the plurality of second trenches space the preset initial semiconductor layer into a plurality of initial semiconductor layers extending along the column direction and spaced apart in the row direction; the initial semiconductor layers and the underlying semiconductor layer are stacked and aligned with each other in a direction perpendicular to the substrate.

[0195] In some embodiments of this application, a plurality of semiconductor layers are formed on the side of the uppermost semiconductor layer away from the substrate, stacked and spaced apart along a direction perpendicular to the substrate, including:

[0196] The uppermost semiconductor layer is transformed from the initial semiconductor layer, and the uppermost semiconductor layer and the semiconductor layer in the first stacked structure are stacked and aligned with each other in a direction perpendicular to the substrate;

[0197] On the side of the uppermost semiconductor layer away from the substrate, a plurality of semiconductor layers are formed, stacked and spaced apart along a direction perpendicular to the substrate, and the plurality of semiconductor layers stacked on one side of the uppermost semiconductor layer are aligned with one of the uppermost semiconductor layers.

[0198] In some embodiments of this application, the manufacturing method further includes:

[0199] Before inducing the initial semiconductor layer to transform into the semiconductor layer using the crystallized semiconductor pillar as a mother plate, a suppression layer covering the initial semiconductor layer is formed on a substrate; the suppression layer is configured to suppress spontaneous crystallization of the initial semiconductor layer; and

[0200] After the initial semiconductor layer is transformed into the semiconductor layer, before forming multiple semiconductor layers again on one side of the uppermost semiconductor layer, the suppression layer is removed to expose the top surface of the semiconductor layer formed by the transformation of the initial semiconductor layer.

[0201] In some embodiments of this application, the step of using the crystallized semiconductor pillar as a mother plate to induce the initial semiconductor layer to transform into the semiconductor layer includes:

[0202] Using the crystallized semiconductor pillar as a mother plate, a laser-induced crystallization process is employed to induce the initial semiconductor layer to transform into the semiconductor layer.

[0203] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a gate electrode on the sidewall of the semiconductor layer includes:

[0204] Remove the insulating layer between adjacent semiconductor layers to expose the sacrificial layer;

[0205] Remove the sacrificial layer;

[0206] An insulating material is filled between adjacent semiconductor layers;

[0207] Etching is performed on a film layer formed of insulating material between two adjacent semiconductor layers to form a gate hole extending along the row direction between two adjacent semiconductor layers, and a word line hole extending in a direction perpendicular to the substrate between two adjacent semiconductor layers along the row direction, wherein the gate hole and the word line hole expose at least a portion of the sidewalls of the semiconductor layer.

[0208] The gate insulating layer and the gate electrode, which at least partially surround the semiconductor layer, are sequentially formed on the sidewalls of the gate hole and the word line hole.

[0209] In some embodiments of this application, the step of sequentially forming at least partially surrounding the gate insulating layer and the gate electrode on the sidewalls of the gate via and the word line via includes:

[0210] A gate insulating layer and a gate electrode layer, at least partially surrounding the semiconductor layer, are sequentially formed on the sidewalls of the gate via and the word line via; the gate electrode layer located between two adjacent semiconductor layers along the row direction is disconnected in the row direction;

[0211] The remaining gate electrode layers form gate electrodes that at least partially surround the semiconductor layer, and a plurality of gate electrodes located in different layers are connected within the word line vias.

[0212] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0213] like Figures 3 to 17C As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0214] S10: Provide a substrate 10; using an epitaxial growth process, sequentially and alternately form multiple sacrificial layers 11 and multiple preset semiconductor layers 21' on the substrate 10 to obtain a first initial stacked structure formed by alternating stacking of multiple sacrificial layers 11 and multiple preset semiconductor layers 21', such as... Figure 3 As shown.

[0215] The preset semiconductor layer 21' is formed of a crystalline first semiconductor material. The first semiconductor material can be silicon, and the crystalline first semiconductor material can be single-crystal silicon.

[0216] like Figure 3 As shown, the thickness of the uppermost preset semiconductor layer 21' in the first initial stacked structure is relatively thick, which can be significantly greater than the thickness of the other preset semiconductor layers 21', so as to facilitate the subsequent formation of semiconductor pillars 30.

[0217] For example only. Figure 3 The stacked structure shown includes three sacrificial layers 11 and three preset semiconductor layers 21'. In other embodiments, the stacked structure may include more or fewer sacrificial layers 11 and preset semiconductor layers 21' arranged alternately.

[0218] S20: The first initial stacked structure is etched along the direction toward the substrate 10 to form a plurality of first trenches T1 penetrating the first initial stacked structure; the plurality of first trenches T1 extend along a column direction parallel to the substrate 10 and are spaced apart in a row direction parallel to the substrate 10; the plurality of first trenches T1 space the preset semiconductor layers 21' into a plurality of semiconductor layers 21 extending along the column direction and spaced apart in the row direction, thus obtaining the first stacked structure, as shown. Figure 4A and Figure 4B As shown.

[0219] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. Exemplarily, the row direction can be as follows: Figure 4B The column direction can be as shown in the X direction, where the column direction is as follows: Figure 4A The Y-direction shown, the direction perpendicular to the substrate, can be as follows: Figure 4A The Z direction is shown.

[0220] In this application, multiple components distributed along the row direction can be referred to as a row of components, for example, a row of memory cells. Multiple components distributed along the column direction can be referred to as a column of components, for example, a column of memory cells. Multiple components distributed along a direction perpendicular to the substrate can be referred to as a string of components, for example, a string of memory cells.

[0221] For example, the first trench may extend in a direction perpendicular to the substrate 10.

[0222] For example, such as Figure 4B As shown, step S20 may further include:

[0223] The first initial stack structure is etched along a direction toward the substrate 10, for example, a direction perpendicular to the substrate 10, to form a plurality of isolation trenches T3 that penetrate the first initial stack structure; the plurality of isolation trenches T3 extend along the row direction and are spaced apart in the column direction; there is one first stack structure between two adjacent isolation trenches T3;

[0224] An isolation layer 12 is filled in the trench T3. The isolation layer 12 is used to space two adjacent superlattice structures along the column direction, and the isolation layer 12 can serve as a support layer to provide support for the fabrication of semiconductor devices and prevent collapse.

[0225] For example, in step S20, the first trench T1 may be formed first, followed by the isolation trench T3; or the isolation trench T3 may be formed first, followed by the first trench T1; or the first trench T1 and the isolation trench T3 may be formed simultaneously through a single etching process.

[0226] S30: The uppermost semiconductor layer 21 in the first stacked structure is etched to form semiconductor pillars 30 extending in a direction perpendicular to the substrate 10, such as... Figures 5 to 6B As shown.

[0227] For example, step S30 may include:

[0228] S31: Fill the first trench T1 with insulating layer 13, such as Figure 5 As shown;

[0229] S32: The uppermost semiconductor layer 21 is etched to form a plurality of vias K1 spaced apart along the column direction in the uppermost semiconductor layer 21. The plurality of vias K1 space each of the uppermost semiconductor layers 21 into a plurality of semiconductor pillars 30 extending in a direction perpendicular to the substrate 10, such as... Figure 6A and Figure 6B As shown. Among them, Figure 6B The cross section passes through the semiconductor pillar 30.

[0230] For example, such as Figure 6A As shown, the height of the semiconductor pillar 30 in the direction perpendicular to the substrate 10 is greater than the thickness of the semiconductor layer 21.

[0231] For example, such as Figure 6A and Figure 6B As shown, the height of the semiconductor pillar 30 in the direction perpendicular to the substrate 10 is greater than its width in any direction parallel to the substrate 10, so as to facilitate the subsequent use of the semiconductor pillar 30 as a mother plate to induce crystallization.

[0232] For example, the material forming the insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0233] S40: An amorphous initial semiconductor layer 14 is formed on the surface of the semiconductor pillar 30 on the side away from the substrate 10 using the amorphous first semiconductor material, such as... Figures 7A to 9 As shown.

[0234] For example, step S40 may include steps S41 to S43 described below.

[0235] S41: An insulating layer 13 is filled between adjacent semiconductor pillars 30, such as... Figure 7A and Figure 7B As shown; where, Figure 7B The cross section passes through the semiconductor pillar 30.

[0236] S42: A predetermined initial semiconductor layer 14' is formed on the substrate 10 using an amorphous first semiconductor material, covering the exposed surfaces of each semiconductor pillar 30, such as... Figure 8 As shown.

[0237] For example, the thickness of the initial semiconductor layer 14' can be the same as the thickness of the initial semiconductor layer 21'.

[0238] S43: The initial semiconductor layer 14' is etched to form a plurality of second trenches T2 penetrating the initial semiconductor layer 14'; the plurality of second trenches T2 extend along the column direction and are spaced apart in the row direction; the plurality of second trenches T2 space the initial semiconductor layer 14' into a plurality of initial semiconductor layers 14 extending along the column direction and spaced apart in the row direction, such as Figure 9 As shown. Among them, Figure 9 The longitudinal section shown passes through semiconductor pillar 30.

[0239] For example, such as Figure 9 As shown, the initial semiconductor layer 14 and the underlying semiconductor layer 21 are stacked and aligned with each other in a direction perpendicular to the substrate 10.

[0240] For example, such as Figure 9 As shown, the orthographic projection of the initial semiconductor layer 14 on the substrate 10 completely overlaps with the orthographic projection of the underlying semiconductor layer 21 on the substrate 10.

[0241] For example, step S40 may also include:

[0242] S44: A suppression layer 15 is formed on the substrate 10 to cover the exposed surface of the initial semiconductor layer 14; the suppression layer 15 is configured to suppress spontaneous crystallization of the initial semiconductor layer 14, such as... Figure 10A and Figure 10B As shown. Among them, Figure 10B The longitudinal section shown passes through semiconductor pillar 30.

[0243] For example, the material of the suppression layer 15 can be silicon nitride or the like.

[0244] S50: Using the crystallized semiconductor pillar 30 as a motherboard, a laser-induced crystallization process is employed to induce the initial semiconductor layer 14 to transform into the semiconductor layer 21, such as... Figure 11A and Figure 11B As shown. Among them, Figure 11B The longitudinal section shown passes through semiconductor pillar 30.

[0245] like Figure 11BAs shown, a plurality of semiconductor layers 21 formed by the conversion of a plurality of initial semiconductor layers 14 extend along the column direction and are spaced apart in the row direction. The semiconductor layers 21 formed by the conversion of the initial semiconductor layers 14 are aligned with the semiconductor layers of the first stacked structure in both the row direction and the column direction.

[0246] For example, the process parameters of the laser-induced process may include: laser energy of 6W; laser wavelength of 532nm; pulse width of 13ns; frequency of 50kHz; scanning rate of 25mm / s; and beam size of 2190.6×42.2μm. 2 .

[0247] For example, step S50 may further include:

[0248] Remove the suppression layer 15 to expose the top surface of the semiconductor layer 21 formed by the transformation of the initial semiconductor layer 14, as shown below. Figure 12A and Figure 12B As shown. Among them, Figure 12B The longitudinal section shown passes through semiconductor pillar 30.

[0249] S60: On the side of the uppermost semiconductor layer 21 (i.e., the semiconductor layer 21 formed by transforming the initial semiconductor layer 14) away from the substrate 10, a plurality of semiconductor layers 21 are formed again, stacked and spaced apart along a direction perpendicular to the substrate 10, to obtain a second stacked structure located on the side of the semiconductor pillar 30 away from the substrate 10.

[0250] For example, step S60 may include:

[0251] Using an epitaxial growth process, multiple sacrificial layers 11 and multiple semiconductor layers 21 are sequentially and alternately formed on the side of the uppermost semiconductor layer 21 (i.e., the semiconductor layer 21 formed by transforming the initial semiconductor layer 14) away from the substrate 10, such as... Figure 13A and Figure 13B As shown, a second stacked structure is formed on the side of the semiconductor pillar 30 away from the substrate 10. Wherein, Figure 13B The longitudinal section shown passes through semiconductor pillar 30.

[0252] The semiconductor layer 21 is formed from the first semiconductor material that has been crystallized.

[0253] Unlike step S10, step S60 can directly form multiple spaced strip semiconductor layers 21 in each layer, while step S10 first forms a continuous preset semiconductor layer 21' in each layer, and then in step S20 the preset semiconductor layer 21' is spaced into multiple spaced strip semiconductor layers 21.

[0254] In step S60, multiple spaced strip-shaped semiconductor layers 21 are directly formed on each layer using an epitaxial growth process. The semiconductor layer 21 of the upper superlattice structure can be self-aligned with the semiconductor layer 21 of the lower superlattice structure, which facilitates the fabrication of subsequent devices.

[0255] In other embodiments, step S60 may first form a preset semiconductor layer 21', and then etch to form a plurality of spaced strip-shaped semiconductor layers 21.

[0256] For example, if only two superlattice structures are formed, the uppermost film layer formed in step S60 can be a sacrificial layer 11, such as... Figure 13A and Figure 13B As shown; it can also be a semiconductor layer 21.

[0257] In other embodiments, if at least three superlattice structures are formed, the uppermost film layer formed in step S60 is a semiconductor layer 21, and the thickness of the uppermost semiconductor layer 21 is relatively thick, which can be significantly greater than the thickness of the other semiconductor layers 21, so as to facilitate the subsequent formation of the uppermost semiconductor layer 21 into a semiconductor pillar 30.

[0258] If at least three superlattice structures are formed, then repeat steps S30 to S60 at least once after step S60.

[0259] S70: A gate insulating layer 23 and a gate electrode 22 are sequentially formed on the sidewall of the semiconductor layer 21.

[0260] For example, step S70 may include:

[0261] S71: An insulating layer 13 is filled between two adjacent semiconductor layers 21 along the row direction and between two adjacent sacrificial layers 11 along the row direction in the second stacked structure.

[0262] S72: Remove the insulating layer 13 between adjacent semiconductor layers 21, that is, open the trench to form the transistor, exposing the sacrificial layer 11, such as... Figure 14 As shown; where, Figure 14 The longitudinal section shown passes through semiconductor pillar 30.

[0263] For example, the insulating layer 13 between adjacent semiconductor layers 21 along the row direction is removed in a direction perpendicular to the substrate 10, such as... Figure 14 As shown, trenches are opened to form transistors. At this time, the insulating layers between adjacent semiconductor layers 21, adjacent sacrificial layers 11, and adjacent semiconductor pillars 30 are removed along the row direction, forming a plurality of trenches that extend perpendicular to the substrate direction and are spaced apart in the row direction for forming transistors.

[0264] S73: Remove all sacrificial layers 11, such as Figure 15A and Figure 15B As shown. Among them, Figure 15B The longitudinal section shown passes through semiconductor pillar 30.

[0265] In some embodiments, after all the sacrificial layer 11 is removed, the isolation layer 12 within the trench T3 can provide support to prevent the suspended semiconductor layer from collapsing. In other embodiments, the isolation layer 12 may be omitted, and the support may be provided by the insulating film layer between the semiconductor layers.

[0266] S74: Fill the spaces between adjacent semiconductor layers 21 with insulating material 13', such as... Figure 16A and Figure 16B As shown. Among them, Figure 16B The longitudinal section shown passes through semiconductor pillar 30.

[0267] In some embodiments of this application, the insulating material 13' may be the same material as the insulating layer 13, so the film formed by the insulating material 13' is the same as the insulating layer 13.

[0268] S75: Etching is performed on the film layer formed of insulating material 13' between two adjacent semiconductor layers 21, forming a gate hole K2 extending along the row direction between the two adjacent semiconductor layers 21, and a word line hole K3 extending in a direction perpendicular to the substrate 10 between the two adjacent semiconductor layers 21 along the row direction. The gate hole K2 and the word line hole K3 expose at least a portion of the sidewalls of the semiconductor layer 21, such as... Figures 17A to 17C As shown. Among them, Figure 17C The longitudinal section shown passes through semiconductor pillar 30.

[0269] S76: A gate insulating layer 23 and a gate electrode 22, at least partially surrounding the semiconductor layer 21, are sequentially formed on the sidewalls of the gate hole K2 and the word line hole K3.

[0270] For example, step S76 may include:

[0271] S761: A gate insulating layer 23 and a gate electrode layer, at least partially surrounding the semiconductor layer 21, are sequentially formed on the sidewalls of the gate hole K2 and the word line hole K3; the gate electrode layer located between two adjacent semiconductor layers 21 along the row direction is disconnected in the row direction;

[0272] S762: The remaining gate electrode layer forms a gate electrode 22 that at least partially surrounds the semiconductor layer 21. Multiple gate electrodes 22 located in different layers are connected within word line vias K3 to form word lines WL extending in a direction perpendicular to the substrate 10, resulting in... Figures 1A to 1C The semiconductor device shown.

[0273] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0274] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0275] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by, Comprising: a plurality of superlattice structures distributed in different layers and stacked along a direction perpendicular to the substrate; any two of the superlattice structures adjacent along the direction perpendicular to the substrate are a lower superlattice structure close to the substrate and an upper superlattice structure away from the substrate respectively; the superlattice structure comprises a plurality of memory cells distributed in different layers and stacked along a direction perpendicular to the substrate; the memory cell comprises a transistor, and the transistor comprises a semiconductor layer; the semiconductor layer extends along a column direction parallel to the substrate; a semiconductor pillar located between the lower superlattice structure and the upper superlattice structure adjacent along the direction perpendicular to the substrate; the semiconductor pillar has opposite first and second ends, the first end of the semiconductor pillar is spaced apart from the lower superlattice structure, and the second end of the semiconductor pillar is connected to the upper superlattice structure.

2. The semiconductor device according to claim 1, wherein The second end of the semiconductor pillar is connected to the semiconductor layer located in the lowermost layer of the upper superlattice structure, and each semiconductor layer located in the lowermost layer is connected to at least one semiconductor pillar.

3. The semiconductor device of claim 2, wherein, The semiconductor pillar extends along a direction perpendicular to the substrate; The height of the semiconductor pillar in the direction perpendicular to the substrate is greater than the width of the semiconductor pillar in any direction parallel to the substrate.

4. The semiconductor device of claim 2, wherein The semiconductor pillar is made of the same material as the semiconductor layer.

5. The semiconductor device of claim 3, wherein The semiconductor layer connected to the semiconductor pillar is formed by laser-induced crystallization of the semiconductor pillar.

6. The semiconductor device of claim 5, wherein, In the superlattice structure located in the lowermost layer, the semiconductor layer is formed by an epitaxial growth process; In the superlattice structure other than the one located in the lowermost layer, the semiconductor layer other than the one located in the lowermost layer is formed by an epitaxial growth process.

7. The semiconductor device according to any one of claims 1 to 6, wherein Further comprising a word line extending along a direction perpendicular to the substrate; The word line passes through a plurality of memory cells of the same superlattice structure stacked along a direction perpendicular to the substrate; and / or, The word line passes through the memory cells of a plurality of superlattice structures stacked along a direction perpendicular to the substrate.

8. The semiconductor device of claim 7, wherein, The transistor further comprises a gate electrode at least partially surrounding the semiconductor layer, and a gate insulating layer between the gate electrode and the semiconductor layer; The gate electrode is part of the word line, and the gate electrodes of a plurality of memory cells stacked along a direction perpendicular to the substrate are located in different regions of the same word line.

9. The semiconductor device according to any one of claims 1 to 6, wherein Further comprising a bit line extending along a row direction parallel to the substrate; The bit line is connected to the transistors of a row of memory cells of the same superlattice structure distributed along the row direction; and / or, The bit line is connected to the transistors of a row of superlattice structures distributed along the row direction.

10. A method of manufacturing a semiconductor device, characterized by Comprising: forming a plurality of crystalline semiconductor layers spaced apart and stacked along a direction perpendicular to the substrate on a substrate by using a crystalline first semiconductor material to obtain a first stacked structure; etching the semiconductor layer located in the uppermost layer of the first stacked structure to form a semiconductor pillar extending along a direction perpendicular to the substrate; forming an amorphous initial semiconductor layer on a side surface of the semiconductor pillar away from the substrate by using the amorphous first semiconductor material; inducing the initial semiconductor layer to transform into the semiconductor layer by taking the crystalline semiconductor pillar as a mother plate; forming a plurality of semiconductor layers stacked along a direction perpendicular to the substrate and spaced apart on a side of the semiconductor layer farthest from the substrate, to obtain a second stacking structure on a side of the semiconductor pillar farthest from the substrate; forming a gate insulating layer and a gate electrode on the sidewall of the semiconductor layer in sequence.

11. The production method according to claim 10, wherein Further comprising: after obtaining the second stacking structure and before forming the gate insulating layer, repeating one or more times the following process: etching the uppermost semiconductor layer to form a semiconductor pillar extending in a direction perpendicular to the substrate; forming the initial semiconductor layer on a side surface of the semiconductor pillar away from the substrate by using the amorphous first semiconductor material; inducing the initial semiconductor layer to transform into the semiconductor layer by taking the semiconductor pillar as a mother plate; forming a plurality of semiconductor layers stacked along a direction perpendicular to the substrate and spaced apart on a side of the semiconductor layer farthest from the substrate.

12. The manufacturing method according to claim 10, wherein Each semiconductor layer in the first stacking structure is formed by an epitaxial growth process; and / or, forming a plurality of semiconductor layers stacked along a direction perpendicular to the substrate and spaced apart on a side of the semiconductor layer farthest from the substrate, comprises: forming a plurality of semiconductor layers stacked along a direction perpendicular to the substrate and spaced apart on a side of the semiconductor layer farthest from the substrate by an epitaxial growth process.

13. The manufacturing method according to claim 10, wherein The height of the semiconductor pillar in a direction perpendicular to the substrate is greater than the thickness of the semiconductor layer; The height of the semiconductor pillar in a direction perpendicular to the substrate is greater than the width of the semiconductor layer in any direction parallel to the substrate.

14. The production method according to any one of claims 10 to 13, characterized by, forming a plurality of crystalline semiconductor layers stacked along a direction perpendicular to the substrate and spaced apart on the substrate by using the crystalline first semiconductor material to obtain a first stacking structure, comprises: forming a plurality of sacrificial layers and a plurality of preset semiconductor layers on the substrate in sequence and alternately by an epitaxial growth process to obtain a first initial stacking structure; the preset semiconductor layer is formed by the crystalline first semiconductor material; etching the first initial stacking structure to form a plurality of first grooves penetrating through the first initial stacking structure; the plurality of first grooves extend along a column direction parallel to the substrate and are spaced apart in a row direction parallel to the substrate; the plurality of first grooves space the preset semiconductor layers into a plurality of semiconductor layers extending along the column direction and spaced apart in the row direction to obtain the first stacking structure.

15. The manufacturing method according to claim 14, wherein etching the uppermost semiconductor layer to form a semiconductor pillar extending in a direction perpendicular to the substrate, comprises: filling an insulating layer between adjacent semiconductor layers; etching the semiconductor layer on the topmost layer to form a plurality of through holes in the semiconductor layer on the topmost layer, the plurality of through holes spacing the semiconductor layer on the topmost layer into a plurality of semiconductor columns extending in a direction perpendicular to the substrate.

16. The production method according to any one of claims 10 to 13, characterized by, forming an amorphous initial semiconductor layer on a side of the semiconductor column away from the substrate using the amorphous first semiconductor material, including: filling an insulating layer between adjacent semiconductor columns; forming a preset initial semiconductor layer covering exposed surfaces of each semiconductor column on the substrate using the amorphous first semiconductor material; etching the preset initial semiconductor layer to form a plurality of second grooves penetrating the preset initial semiconductor layer; the plurality of second grooves extending in a column direction parallel to the substrate and being spaced apart in a row direction parallel to the substrate; the plurality of second grooves spacing the preset initial semiconductor layer into a plurality of initial semiconductor layers extending in the column direction and being spaced apart in the row direction; the initial semiconductor layers and the semiconductor layers below are stacked in a direction perpendicular to the substrate and aligned with each other.

17. The manufacturing method according to claim 16, wherein forming a plurality of semiconductor layers on a side of the semiconductor layer on the topmost layer away from the substrate, the plurality of semiconductor layers being stacked and spaced apart in a direction perpendicular to the substrate, including: the semiconductor layer on the topmost layer being converted from the initial semiconductor layer, the semiconductor layer on the topmost layer and the semiconductor layers in the first stacked structure being stacked in a direction perpendicular to the substrate and aligned with each other; forming a plurality of semiconductor layers on a side of the semiconductor layer on the topmost layer away from the substrate, the plurality of semiconductor layers being stacked and spaced apart in a direction perpendicular to the substrate, and the plurality of semiconductor layers formed on a side of the semiconductor layer on the topmost layer being aligned with each other.

18. The production method according to any one of claims 10 to 13, characterized by, further including: forming an inhibition layer covering the initial semiconductor layer on the substrate before converting the initial semiconductor layer into the semiconductor layer using the crystalline semiconductor column as a mother plate; the inhibition layer being configured to inhibit spontaneous crystallization of the initial semiconductor layer; and after converting the initial semiconductor layer into the semiconductor layer, removing the inhibition layer before forming a plurality of semiconductor layers on a side of the semiconductor layer on the topmost layer again, exposing a top surface of the semiconductor layer formed by the conversion of the initial semiconductor layer.

19. The production method according to any one of claims 10 to 13, characterized by, the converting the initial semiconductor layer into the semiconductor layer using the crystalline semiconductor column as a mother plate, including: converting the initial semiconductor layer into the semiconductor layer using a laser-induced crystallization process using the crystalline semiconductor column as a mother plate.

20. The manufacturing method of claim 15, wherein, the sequentially forming a gate insulating layer and a gate electrode on the sidewall of the semiconductor layer, including: removing the insulating layer between adjacent semiconductor layers, exposing the sacrificial layer; removing the sacrificial layer; filling an insulating material between adjacent semiconductor layers; etching a film layer formed of the insulating material between two adjacent semiconductor layers to form a gate hole extending in the row direction between the two adjacent semiconductor layers and a word line hole extending in a direction perpendicular to the substrate between two semiconductor layers adjacent in the row direction, the gate hole and the word line hole exposing at least part of a side wall of the semiconductor layer; forming the gate insulating layer and the gate electrode layer at least partially surrounding the semiconductor layer in sequence on the side wall of the gate hole and the word line hole.

21. The manufacturing method according to claim 20, wherein The forming the gate insulating layer and the gate electrode layer at least partially surrounding the semiconductor layer in sequence on the side wall of the gate hole and the word line hole includes: forming the gate insulating layer and the gate electrode layer at least partially surrounding the semiconductor layer in sequence on the side wall of the gate hole and the word line hole; and disconnecting the gate electrode layer between two semiconductor layers adjacent in the row direction in the row direction; the remaining gate electrode layer forms a gate electrode at least partially surrounding the semiconductor layer, and a plurality of the gate electrodes in different layers are connected in the word line hole.

22. An electronic device, comprising: A semiconductor device including any one of the semiconductor devices according to claims 1 to 9, or a semiconductor device obtained by the manufacturing method according to any one of claims 10 to 21.

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