Semiconductor memory device

Abstract

A semiconductor memory device includes: a molding structure including a plurality of gate electrodes; a gate electrode cutting pattern separating the molded structure into a plurality of blocks by cutting the plurality of gate electrodes along a plane; a plurality of first capacitor structures penetrating the molding structure within the first block, a plurality of second capacitor structures, the first block being at least one of the plurality of blocks; a plurality of second capacitor structures penetrating the molded structure within the first block; a first capacitor connection structure on the first block and connected to the plurality of first capacitor structures; and a second capacitor connection structure on the first block and connected to the plurality of second capacitor structures. A first signal line connected to the first capacitor connection structure and a second signal line connected to the second capacitor connection structure are electrically separated.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0119517, filed September 3, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Some example embodiments relate to a semiconductor memory device. BACKGROUND

[0003] As semiconductor memory devices capable of storing a large amount of data are required in electronic systems, methods of increasing the data storage capacity of semiconductor memory devices are being researched. As one of the methods of increasing the data storage capacity of semiconductor memory devices, semiconductor memory devices including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells are being proposed.

[0004] As the input / output speed of semiconductor memory devices continues to increase, more precise control of signal noise is desired. The input / output speed can be increased by removing signal noise using a high-capacity capacitor. SUMMARY

[0005] Some example embodiments can provide a semiconductor memory device by which the quality of an input / output signal is improved.

[0006] Alternatively or additionally, some example embodiments can provide a semiconductor memory device by which the input / output speed is improved.

[0007] However, the goals to be achieved by some example embodiments are not limited to the technical aspects described above, and other goals can be inferred from the following example embodiments.

[0008] According to some example embodiments, a semiconductor memory device includes a mold structure including a plurality of gate electrodes stacked in a first direction; a gate electrode cut pattern separating the mold structure into a plurality of blocks by cutting the plurality of gate electrodes along a plane including the first direction and a second direction crossing the first direction within a first block, the first block being at least one of the plurality of blocks; a plurality of first capacitor structures penetrating the mold structure in the first direction; a plurality of second capacitor structures penetrating the mold structure in the first direction and within the first block; a first capacitor connection structure on the first block and connected to the plurality of first capacitor structures; and a second capacitor connection structure on the first block and connected to the plurality of second capacitor structures. A first signal line connected to the first capacitor connection structure and a second signal line connected to the second capacitor connection structure are electrically separated.

[0009] Optionally or additionally, according to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a molding structure including a plurality of gate electrodes stacked in a first direction; a gate electrode cutting pattern extending along a plane including the first direction and a second direction intersecting the first direction, the gate electrode cutting pattern separating the molding structure into a plurality of blocks by cutting the plurality of gate electrodes; a plurality of first capacitor structures penetrating the molding structure within a first block, the first block being at least one of the plurality of blocks; a first electrode connection structure penetrating the molding structure within the first block and connecting the plurality of gate electrodes; a plurality of second capacitor structures penetrating the molding structure within a second block spaced apart from the first block, the gate electrode cutting pattern being between the first block and the second block, and the plurality of second capacitor structures penetrating the molding structure along a third direction intersecting the first and second directions; a second electrode connection structure penetrating the molding structure within the second block and connecting the plurality of gate electrodes; and a capacitor connection structure on the molding structure in the first direction and connected to the plurality of first capacitor structures and the plurality of second capacitor structures.

[0010] Optionally or additionally, a semiconductor memory device is provided, the semiconductor memory device comprising: a cell substrate including a first substrate and a second substrate opposite to the first substrate; a molding structure including a plurality of gate electrodes stacked on the first substrate in a first direction perpendicular to the first substrate; a gate electrode cutting pattern extending along a plane including the first direction and a second direction intersecting the first direction, and separating the molding structure into a plurality of blocks by cutting the plurality of gate electrodes; a plurality of first capacitor structures penetrating the molding structure within a first block, the first block being at least one of the plurality of blocks; a first electrode connection structure penetrating the molding structure within the first block and connecting the plurality of gate electrodes, the first capacitor connection structure being on the first block on a second substrate and connected to the plurality of first capacitor structures; a plurality of second capacitor structures penetrating the molding structure within a second block spaced apart from the first block along a third direction intersecting the first and second directions, the gate electrode cutting pattern being between the first block and the second block, the second block being at least one of the plurality of blocks; a second electrode connection structure penetrating the molding structure within the second block and connected to the plurality of gate electrodes; and a second capacitor connection structure being on the second block on a second substrate and connected to the plurality of second capacitor structures.

[0011] Additional aspects of some of the example embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of some of the example embodiments.

[0012] According to some example embodiments, the quality of input / output signals of semiconductor memory devices can be improved.

[0013] Optionally or additionally, according to some example embodiments, the input / output speed of a semiconductor memory device may be improved. Attached Figure Description

[0014] These and / or other aspects, features, and advantages will become clear and more readily understood from the following description of some exemplary embodiments in conjunction with the accompanying drawings.

[0015] Figure 1 This is a block diagram illustrating a semiconductor memory device according to some example embodiments.

[0016] Figure 2 This is a circuit diagram illustrating a semiconductor memory device according to some example embodiments.

[0017] Figure 3 This is a schematic layout diagram illustrating a semiconductor memory device according to some example embodiments.

[0018] Figure 4 This illustrates some example embodiments. Figure 3 A magnified view of part P.

[0019] Figure 5 This is an illustration along some example embodiments. Figure 3 The sectional view taken by line AA.

[0020] Figure 6 This illustrates some example embodiments. Figure 5 A diagram showing the magnified portion of R1.

[0021] Figure 7 This illustrates some example embodiments. Figure 5 Another diagram showing the magnified portion R1.

[0022] Figure 8 This illustrates some example embodiments. Figure 5 A diagram showing the magnified portion of R2.

[0023] Figure 9 This illustrates some example embodiments. Figure 5 Another diagram showing the magnified portion R2.

[0024] Figure 10 This is an illustration along some example embodiments. Figure 3 The sectional view taken by line BB.

[0025] Figure 11 This is an illustration along some example embodiments. Figure 3 Another view of the cross section taken by line BB.

[0026] Figure 12This is an illustration along some example embodiments. Figure 3 The sectional view taken by the CC line.

[0027] Figure 13 This is an illustration along some example embodiments. Figure 3 The sectional view taken by line DD.

[0028] Figure 3 to Figure 5 The semiconductor memory device shown is for the purpose of describing some other example embodiments. Figure 13 The magnified portion of P is shown in the diagram.

[0029] Figure 2 This is a schematic layout diagram used to describe a semiconductor memory device according to another example embodiment.

[0030] Figure 1 This illustrates some example embodiments. Figure 6 The enlarged portion of P is shown in the diagram.

[0031] Figure 6 This is an illustration along some example embodiments. Figure 7 The sectional view taken by line AA.

[0032] Figure 2 This is an illustration along some example embodiments. Figure 3 to Figure 5 The sectional view taken by the CC line.

[0033] Figure 3 It is a schematic layout diagram used to describe a semiconductor memory device according to some example embodiments.

[0034] Figure 4 This illustrates some example embodiments. Figure 3 The magnified portion of the P image.

[0035] Figure 4 This is an illustration along some example embodiments. Figure 5 The sectional view taken by line AA.

[0036] Figure 12 This is an illustration along some example embodiments. Figure 3 The sectional view taken by line BB.

[0037] Figure 4 This is an illustration along some example embodiments. Figure 5 Another view of the cross section taken by line BB.

[0038] Figure 12 This is an illustration along some example embodiments. Figure 8 Another view of the cross section taken by line AA.

[0039] Figure 8 This is a schematic layout diagram illustrating a semiconductor memory device according to some example embodiments.

[0040] Figure 9 This illustrates some example embodiments. Figure 3 The magnified portion of the P image.

[0041] Figure 4 This is an illustration along some example embodiments. Figure 10 The sectional view taken by line AA.

[0042] Figure 11 This is an illustration along some example embodiments. Figure 10 The sectional view taken by line BB.

[0043] Figure 13 This is a diagram illustrating an electronic system including a semiconductor memory device according to some example embodiments.

[0044] Figure 1 It is a perspective view used to describe an electronic system including a semiconductor memory device according to some example embodiments.

[0045] Figure 1 This is an illustration along some example embodiments. Figure 1 The sectional view taken from line II. Detailed Implementation

[0046] Prior to the detailed description of the exemplary embodiments, the terms or words used in the specification and claims should not be construed as limited to their common or dictionary meanings. Furthermore, given that the inventor may appropriately define the concepts of terms in order to clearly explain the principles of their invention, the terms or words should be interpreted as having meanings and concepts consistent with the technical concept of the exemplary embodiments. The exemplary embodiments described in this specification and the constructions shown in the accompanying drawings are merely some exemplary embodiments and do not necessarily represent the entire technical idea. Therefore, various equivalents and modifications may exist that can replace them.

[0047] In the following description, unless the context clearly indicates otherwise, singular expressions include plural expressions. It will be understood that when an element (e.g., a first element) is "(operably or communicatively) combined with another element (e.g., a second element)" / "(operably or communicatively) combined with" or "connected to" another element (e.g., a second element), the element may be directly combined with / directly combined to the other element, and an intermediary element (e.g., a third element) may exist between the element and the other element. The terms "having," "may have," "comprising," and "may include" as used herein indicate the presence of a corresponding feature (e.g., an element (such as a value, function, operation, or component)) and do not exclude the presence of additional features.

[0048] Additionally, in the following descriptions, terms such as top, top, bottom, side, front, and back are used based on the orientation shown in the diagram. If the orientation of the object changes, it can be expressed differently.

[0049] In the following, some exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 This is a block diagram illustrating a semiconductor memory device according to some example embodiments.

[0051] Reference Figure 14 The semiconductor memory device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0052] According to some example embodiments, the memory cell array 20 may include a plurality of memory cell blocks (first block BLK1 to nth block BLKn). Each of the memory cell blocks (first block BLK1 to nth block BLKn) may include a plurality of memory cells, and may or may not include the same number of memory cell blocks. The memory cell array 20 may be connected to peripheral circuitry 30 via bit line BL, word line WL, at least one string select line SSL, and at least one ground select line GSL. In some example embodiments, the memory cell blocks (first block BLK1 to nth block BLKn) may be connected to the line decoder 33 via word line WL, string select line SSL, and ground select line GSL. Furthermore, the memory cell blocks (first block BLK1 to nth block BLKn) may be connected to the page buffer 35 via bit line BL.

[0053] According to some example embodiments, peripheral circuitry 30 may receive one or more of address ADDR, command CMD, and control signal CTRL from outside the semiconductor memory device 10, and may transmit data DATA to and / or receive data DATA from devices outside the semiconductor memory device 10. Peripheral circuitry 30 may include control logic 37, a row decoder 33, and a page buffer 35. Although not shown, peripheral circuitry 30 may also include one or more of various sub-circuits, such as input / output circuitry, voltage generation circuitry for generating various voltages required for the operation of the semiconductor memory device 10, and error correction circuitry for correcting errors in the data DATA read from the memory cell array 20.

[0054] According to some example embodiments, control logic 37 may be connected to line decoder 33, page buffer 35, input / output circuitry, and voltage generation circuitry. Control logic 37 may control the overall operation of semiconductor memory device 10. Control logic 37 may generate various internal control signals used within semiconductor memory device 10 in response to control signal CTRL. For example, when performing memory operations (such as programming or erasing operations), control logic 37 may adjust the levels (such as voltage levels or voltage amplitudes) provided to word line WL and bit line BL.

[0055] According to some example embodiments, the row decoder 33 may select at least one of a plurality of memory cell blocks (first block BLK1 to nth block BLKn) in response to address ADDR, and the row decoder 33 may select at least one word line WL, at least one serial select line SSL, and at least one ground select line GSL of the selected memory cell block (first block BLK1 to nth block BLKn). In some example embodiments, the row decoder 33 may apply voltage to the word line WL of the selected memory cell block (first block BLK1 to nth block BLKn) to perform memory operations.

[0056] According to some example embodiments, page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a write driver or a sense amplifier. For example, when performing a programming operation, page buffer 35 acts as a write driver and can apply a voltage to bit line BL according to the data DATA to be stored in memory cell array 20. Simultaneously, when performing a read operation, page buffer 35 acts as a sense amplifier to detect the data DATA stored in memory cell array 20.

[0057] Figure 3 This is a circuit diagram illustrating a semiconductor memory device according to some example embodiments.

[0058] Reference Figure 1 to Figure 13Memory cell arrays of semiconductor memory devices (e.g., Figure 14 The memory cell array 20 may include a common source line CSL, multiple bit lines BL and multiple cell strings CSTR.

[0059] According to some example embodiments, multiple bit lines BL can be arranged two-dimensionally in a plane including a second direction D2 and a third direction D3. For example, each of the bit lines BL can extend in the third direction D3 and can be arranged spaced apart from each other along the second direction D2. Multiple cell strings CSTR can be connected in parallel to each of the bit lines BL. The cell strings CSTR can be collectively connected to the common source line CSL. For example, multiple cell strings CSTR can be placed between the bit lines BL and the common source line CSL. The multiple cell strings CSTR can extend in a first direction D1.

[0060] According to some example embodiments, each cell string CSTR may include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCTs placed between the ground select transistor GST and the string select transistor SST. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

[0061] According to some example embodiments, the common-source line CSL can be connected to the source of the ground select transistor GST. Additionally, the ground select line GSL, multiple word lines WL, and the serial select line SSL can be placed between the common-source line CSL and the bit line BL. The ground select line GSL can be used as the gate electrode of the ground select transistor GST, the word lines WL can be used as the gate electrode of the memory cell transistor MCT, and the serial select line SSL can be used as the gate electrode of the serial select transistor SST.

[0062] Figure 12 This is a schematic layout diagram illustrating a semiconductor memory device according to some example embodiments. Figure 8 This illustrates some example embodiments. Figure 9 A magnified view of part P. Figure 8 This is an illustration along some example embodiments. Figure 9 The sectional view taken by line AA. Figure 12 This illustrates some example embodiments. Figure 8 A diagram showing the magnified portion of R1. Figure 9 This illustrates some example embodiments. Figure 8 Another diagram showing the magnified portion R1. Figure 9 This illustrates some example embodiments. Figure 12 A diagram showing the magnified portion R2. Figure 8This illustrates some example embodiments. Figure 9 Another diagram showing the magnified portion R2. Figure 8 This is an illustration along some example embodiments. Figure 9 The sectional view taken by line BB. Figure 15 This is an illustration along some example embodiments. Figure 16 Another view of the cross section taken by line BB. Figure 15 This is an illustration along some example embodiments. Figure 17 The sectional view taken by the CC line. Figure 15 This is an illustration along some example embodiments. Figure 18 The sectional view taken by line DD.

[0063] Reference Figure 15 According to some example embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (or peripheral circuit region) (PERI).

[0064] According to some example embodiments, the cell structure CELL may include a cell substrate 100, an insulating substrate 101, a molded structure MS, a first interlayer insulating film 140, a gate electrode dicing pattern WLC, a channel structure CH, a bit line BL, a first capacitor structure CAP1, a second capacitor structure CAP2, and a gate contact 162 (see Figure 1 to Figure 13 ) and unit wiring structure 180.

[0065] According to some example embodiments, the cell substrate 100 may be or may include a semiconductor substrate (such as one or more of a silicon substrate, a germanium substrate, and a silicon-germanium substrate). Optionally or additionally, the cell substrate 100 may be or may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0066] According to some example embodiments, cell substrate 100 may contain impurities. For example, cell substrate 100 may contain n-type impurities (e.g., one or more of phosphorus (P), arsenic (As), etc.). However, cell substrate 100 is not limited thereto. For example, cell substrate 100 may optionally or additionally contain p-type impurities (such as, but not limited to, boron (B)). Cell substrate 100 may comprise polycrystalline silicon (poly-Si) doped with N-type and / or p-type impurities. Cell substrate 100 may be configured as a common source line of a semiconductor memory device according to some example embodiments (e.g., Figure 15 to Figure 18 Common source pole line (CSL).

[0067] According to some example embodiments, the cell substrate 100 may include a cell array region CAR and an extension region EXT.

[0068] According to some example embodiments, a memory cell array comprising multiple memory cells (e.g., Figure 19 The memory cell array 20 can be formed in the cell array region CAR. For example, in the cell array region CAR, the channel structure CH, bit line BL, and multiple gate electrodes (GSL, WL, and SSL, described later) can be arranged. In the example embodiment, the surface of the cell substrate 100 on which the memory cell array described above is arranged can be referred to as the first substrate 100a of the cell substrate. The first substrate 100a of the cell substrate can be the front side of the cell substrate 100. Conversely, the surface of the cell substrate 100 opposite to the first substrate 100a of the cell substrate can be referred to as the second substrate 100b of the cell substrate. The second substrate 100b of the cell substrate can be the back side of the cell substrate 100.

[0069] According to some example embodiments, the gate electrode dicing pattern WLC may extend in a first direction D1. For example, the gate electrode dicing pattern WLC may extend along a plane including the first direction D1 and a second direction D2. The gate electrode dicing pattern WLC extends from the cell substrate 100 in the first direction D1 and may dicing multiple gate electrodes (ground select line GSL, word line WL, and string select line SSL). The gate electrode dicing pattern WLC may dicing the multiple gate electrodes (ground select line GSL, word line WL, and string select line SSL) into multiple blocks along a plane including the first direction D1 and the second direction D2. The gate electrode dicing pattern WLC may include at least one of an insulating material (e.g., one or more of silicon oxide, silicon nitride, and silicon oxynitride), but the gate electrode dicing pattern WLC is not limited thereto.

[0070] According to some example embodiments, the gate electrode dicing pattern WLC may extend in the second direction D2. The gate electrode dicing pattern WLC may extend across the cell array region CAR and the extension region EXT in the second direction D2. For example, the gate electrode dicing pattern WLC may extend across the cell array region CAR and the extension region EXT adjacent to the cell array region CAR in the second direction D2.

[0071] According to some example embodiments, the gate electrode cutting pattern WLC may be spaced apart on a third direction D3. The gate electrode cutting pattern WLC may separate the molded structure MS into multiple blocks BLK1 and BLK2 on the third direction D3. The multiple blocks BLK1 and BLK2 may be arranged on the third direction D3. The multiple blocks BLK1 and BLK2 may include a first block BLK1 and a second block BLK2. The gate electrode cutting pattern WLC may be placed between the first block BLK1 and the second block BLK2. The gate electrode cutting pattern WLC may be placed between two adjacent second blocks BLK2. Each of the first block BLK1 and the second block BLK2 may be placed between two adjacent gate electrode cutting patterns WLC on the third direction D3.

[0072] According to some example embodiments, the molded structure MS may include a first BLK1 and a second BLK2. The first BLK1 and the second BLK2 may be arranged on a third direction D3. On the third direction D3, the first BLK1 may be placed further outward of the second BLK2.

[0073] According to some example embodiments, the extended region EXT can be placed around the cell array region CAR. For example, the extended region EXT can surround the cell array region CAR in a planar view. In the extended region EXT, the multiple gate electrodes (GSl, WL, and SSL, described below) can be stacked in a stepped manner.

[0074] According to some example embodiments, an insulating substrate 101 may be formed around the cell substrate 100. The insulating substrate 101 may form an insulating region around the cell substrate 100. The insulating substrate 101 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. However, the insulating substrate 101 is not limited thereto.

[0075] According to some example embodiments, the lower surface of the insulating substrate 101 may be coplanar with the first substrate 100a of the unit substrate, but the example embodiments are not limited thereto. Optionally, in some example embodiments, the lower surface of the insulating substrate 101 may be placed at a lower level than the first substrate 100a of the unit substrate.

[0076] According to some example embodiments, the cell substrate 100 and the insulating substrate 101 may further include an outer region OR. The outer region OR may be located outside the cell array region CAR and the extension region EXT. For example, the outer region OR may surround the cell array region CAR and the extension region EXT in a plan view. Contact plugs 166, described later, may be placed in the outer region OR.

[0077] According to some example embodiments, a molded structure MS may be formed on a first substrate 100a of a cell substrate. The molded structure MS may include a plurality of molded insulating films 110 and a plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL) stacked on the cell substrate 100. Each of the plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL) and each molded insulating film 110 may be a layered structure extending parallel to the first substrate 100a of the cell substrate. The plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL) may be sequentially stacked on the first substrate 100a of the cell substrate while being separated from each other by the molded insulating films 110. Although the plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL) is shown to include a single ground select line GSL and a single string select line SSL, some example embodiments thereof are not limited thereto. The plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL) may include two or more ground select lines and two or more string select lines.

[0078] Each of the plurality of word lines WL may have the same thickness; alternatively, at least one of the plurality of word lines WL may be thicker or thinner than at least another of the plurality of word lines WL. Each of the molded insulating films 110 may have the same thickness and may have the same or different thickness as the adjacent word line WL; alternatively or additionally, at least one of the plurality of molded insulating films 110 may be thicker or thinner than at least another of the plurality of molded insulating films 110.

[0079] According to some example embodiments, the molded structure MS may include a first molded structure and a second molded structure sequentially stacked on a first substrate 100a of a cell substrate. The channel structure CH may have a bend between the first and second molded structures. For example, the first molded structure may include a first gate electrode (ground select line GSL and word line WL) and a molded insulating film 110 alternately stacked on the cell substrate 100. In some example embodiments, the first gate electrode (ground select line GSL and word line WL) may include a ground select line GSL and a word line WL sequentially stacked on the cell substrate 100. The second molded structure may include a second gate electrode (word line WL and string select line SSL) and a molded insulating film 110 alternately stacked on the first molded structure. In some example embodiments, the second gate electrode (word line WL and string select line SSL) may include a word line WL and a string select line SSL sequentially stacked on the first molded structure.

[0080] According to some example embodiments, each of the plurality of gate electrodes (GSL, WL, and SSL) may include a conductive material, such as one or more metals (e.g., one or more of tungsten (W), cobalt (Co), and nickel (Ni)) and a semiconductor material (e.g., silicon, such as doped polycrystalline silicon). However, the gate electrodes are not limited thereto.

[0081] According to some example embodiments, each of the molded insulating films 110 may comprise an insulating material. For example, the molded insulating film 110 may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, the molded insulating film 110 is not limited thereto.

[0082] According to some example embodiments, a first interlayer insulating film 140 may be formed on a first substrate 100a and / or an insulating substrate 101 of the cell substrate to cover the molded structure MS. The first interlayer insulating film 140 may include at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. However, the first interlayer insulating film 140 is not limited thereto.

[0083] According to some example embodiments, a channel structure CH may be formed within a molded structure MS of the cell array region CAR. The channel structure CH may extend in a first direction D1 perpendicular to a first substrate 100a of the cell substrate and penetrate the molded structure MS. The channel structure CH may be placed in a second block BLK2. The channel structure CH may penetrate the molded structure MS in the first direction D1 within the second block BLK2. For example, the channel structure CH may be a cylindrical shape (e.g., a cylindrical shape) extending in the first direction D1. Therefore, the channel structure CH may intersect each of the plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL). The channel structure CH may have a bend within the molded structure MS. For example, the channel structure CH may have a bend between the first molded structure and the second molded structure. The channel structure CH may have a step between the first molded structure and the second molded structure.

[0084] According to some example embodiments, a channel structure CH can be placed within a channel aperture that penetrates a molded structure MS. The channel aperture penetrates the molded structure MS on a first substrate 100a of the cell substrate. The channel structure CH can be arranged in a zigzag shape. For example, the channel structure CH can be alternately arranged in a second direction D2 and a third direction D3 parallel to the upper surface of the cell substrate 100. Multiple channel structure CHs arranged in a zigzag shape can further improve the integration density of the semiconductor memory device. Multiple channel structure CHs can also be arranged in a honeycomb shape.

[0085] Reference Figure 20 The channel structure CH may include a semiconductor pattern 130 and an information storage film 132.

[0086] According to some example embodiments, the semiconductor pattern 130 may extend in a first direction D1 and intersect with a plurality of gate electrodes (ground select line GSL, word line WL, and string select line SSL). Although the semiconductor pattern 130 is shown as cup-shaped, this is merely an example embodiment. For example, the semiconductor pattern 130 may have various shapes (such as cylindrical, square, and solid-filled shapes). The semiconductor pattern 130 may include semiconductor materials (such as one or more of single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures). However, the semiconductor pattern 130 is not limited thereto.

[0087] According to some example embodiments, the semiconductor pattern 130 may be connected to the cell substrate 100. For example, one end (e.g., the tip) of the semiconductor pattern 130 may be exposed from the information storage film 132 and connected to the cell substrate 100. In some example embodiments, the semiconductor pattern 130 may penetrate the first substrate 100a of the cell substrate 100. For example, one end (e.g., the tip) of the semiconductor pattern 130 may protrude beyond the information storage film 132. The semiconductor pattern 130 can improve contact resistance by increasing the contact area with the cell substrate 100.

[0088] According to some example embodiments, the information storage film 132 may be interposed between the semiconductor pattern 130 and each gate electrode (GSL, WL, and SSL). For example, the information storage film 132 may extend along the outer side of the semiconductor pattern 130. The information storage film 132 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-dielectric material having a higher dielectric constant than silicon oxide. The high-dielectric material may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0089] According to some example embodiments, the information storage film 132 may be formed as a multilayer film. For example, such as Figure 19 As shown, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c sequentially stacked on the outer side of the semiconductor pattern 130.

[0090] According to some example embodiments, the tunnel insulating film 132a may include one or more of silicon oxide or a high dielectric material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2), etc.). For example, the charge storage film 132b may include silicon nitride. For example, the barrier insulating film 132c may include silicon oxide or a high dielectric material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2), etc.).

[0091] According to some example embodiments, the channel structure CH may also include a filling insulating film 134; however, the example embodiments are not limited thereto. The filling insulating film 134 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. The filling insulating film 134 may include an insulating material, such as silicon oxide, but the filling insulating film 134 is not limited thereto.

[0092] Reference Figure 21 The channel structure CH may also include a source pattern 138. The source pattern 138 may be formed on the cell substrate 100. The source pattern 138 may be connected to the semiconductor pattern 130. For example, the semiconductor pattern 130 may penetrate the information storage film 132 and contact the source pattern 138. The source pattern 138 may include a conductive material, such as polysilicon (e.g., doped polysilicon) and / or a metal doped with impurities. However, the source pattern 138 is not limited thereto. The source pattern 138 and the cell substrate 100 may be configured as a common source line for the semiconductor memory device (e.g., ...). Figure 19 Common source pole line (CSL).

[0093] In some example embodiments, the source pattern 138 may be an epitaxial pattern, for example, a pattern epitaxially formed from the cell substrate 100 by a selective epitaxial growth process. A seam or interface may or may not exist between the cell substrate 100 and the source pattern 138; the example embodiments are not limited thereto.

[0094] Return to reference Figure 22 The channel structure CH may also include a channel pad 136. The channel pad 136 may be formed to connect to the other end (e.g., the bottom) of the semiconductor pattern 130. The channel pad 136 may include a conductive material, such as doped polysilicon or metal. However, the channel pad 136 is not limited thereto.

[0095] According to some example embodiments, a bit line BL may be formed on a molded structure MS. The bit line BL may extend in a third direction D3 and intersect with the gate electrode dicing pattern WLC. Additionally, the bit line BL may extend in the third direction D3 and connect to a plurality of channel structures CH arranged along the third direction D3. For example, bit line contacts 182 may be formed on a first interlayer insulating film 140 to connect to the upper portion of each channel structure CH. The bit line BL may be electrically connected to the channel structures CH via the bit line contacts 182.

[0096] According to some example embodiments, a capacitor structure CAP may be placed within a first block BLK1. The capacitor structure CAP may include multiple first capacitor structures CAP1 and multiple second capacitor structures CAP2. The multiple first capacitor structures CAP1 and multiple second capacitor structures CAP2 may penetrate the molded structure MS within the first block BLK1.

[0097] According to some example embodiments, a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 may be placed within a first block BLK1. The plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 may be arranged within the first block BLK1 in a second direction D2. For example, the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 may be arranged spaced apart in the second direction D2. An electrode connection structure 120 may be placed between the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2.

[0098] According to some example embodiments, the distance between two adjacent first capacitor structures CAP1 in the second direction D2 and the distance between two adjacent second capacitor structures CAP2 in the second direction D2 may be shorter than the distance between a first capacitor structure CAP1 and a second capacitor structure CAP2 that are adjacent to each other in the second direction D2. For example, the first distance D11 between two adjacent first capacitor structures CAP1 in the second direction D2 and the second distance D22 between two adjacent second capacitor structures CAP2 in the second direction D2 may be shorter than the third distance D12 between a first capacitor structure CAP1 and a second capacitor structure CAP2 that are adjacent to each other in the second direction D2. This may be because the electrode connection structure 120 is arranged between a first capacitor structure CAP1 and a second capacitor structure CAP2 that are adjacent to each other in the second direction D2, thus separating the first capacitor structure CAP1 and the second capacitor structure CAP2.

[0099] According to some example embodiments, a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can penetrate the molded structure MS within a dummy block (not shown). The plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 can be separated from the channel structure CH on a third direction D3. A first block BLK1 with the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 and a second block BLK2 with the channel structure CH can be separated on a third direction D3 by a gate electrode cutting pattern WLC.

[0100] According to some example embodiments, a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can be arranged in the same shape as the channel structure CH. For example, the plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can be arranged in a zigzag shape. The plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can be arranged alternately in the second direction D2 and the third direction D3. The plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can be arranged in a honeycomb shape.

[0101] According to some example embodiments, the width of the capacitor structure CAP and the width of the channel structure CH may be the same. For example, the width of the capacitor structure CAP may be, or correspond to, the diameter or longest axis of the capacitor hole CPH on the upper surface of the molded structure MS. For example, the width of the channel structure CH may be, or correspond to, the diameter or longest axis of the channel hole on the upper surface of the molded structure MS. In the string select line SSL placed on top of the molded structure MS, the width WCAP of the capacitor structure may be the same as the width WCH of the channel structure. However, some example embodiments are not limited thereto. The diameter of the capacitor hole CPH and the diameter of the channel hole may be different.

[0102] According to some example embodiments, a plurality of first capacitor structures CAP1 may be connected to a first capacitor connection structure 175a. The first capacitor connection structure 175a may be placed on a first block BLK1 on a first substrate 100a of the cell substrate. For example, the first capacitor connection structure 175a may be connected to a plurality of first capacitor structures CAP1. The first capacitor connection structure 175a may include a plurality of connecting lines extending in a third direction D3. Each of the plurality of connecting lines of the first capacitor connection structure 175a extending in a third direction D3 may be connected to a plurality of first capacitor structures CAP1 arranged in a third direction D3.

[0103] According to some example embodiments, a plurality of second capacitor structures CAP2 may be connected to a second capacitor connection structure 175b. The second capacitor connection structure 175b may be placed on a first block BLK1 on a first substrate 100a of the cell substrate. For example, the second capacitor connection structure 175b may be connected to all of the plurality of second capacitor structures CAP2. The second capacitor connection structure 175b may include a plurality of connecting lines extending in the third direction D3. Each of the plurality of connecting lines of the second capacitor connection structure 175b extending in the third direction D3 may be connected to a plurality of second capacitor structures CAP2 arranged in the third direction D3.

[0104] According to some example embodiments, the first capacitor connection structure 175a and the second capacitor connection structure 175b may be separated from the bit line BL on a third direction D3. The first capacitor connection structure 175a and the second capacitor connection structure 175b may be separated from the bit line BL, and the gate electrode dicing pattern WLC is placed between the first capacitor connection structure 175a and the second capacitor connection structure 175b and the bit line BL.

[0105] Figure 19 and Figure 23 A first capacitor connection structure 175a is shown that connects to a plurality of first capacitor structures CAP1 (e.g., a plurality of first capacitor structures CAP1 on the left and a plurality of first capacitor structures CAP1 on the right) arranged in a manner such that a plurality of second capacitor structures CAP2 are spaced apart in a second direction D2, but is not connected to each other, but is arranged to be separated in the second direction D2. However, the example embodiment is not limited thereto. For example, it is clear that the first capacitor connection structure 175a connected to the plurality of first capacitor structures CAP1 on the left based on the plurality of second capacitor structures CAP2 and the first capacitor connection structure 175a connected to the plurality of first capacitor structures CAP1 on the right based on the plurality of second capacitor structures CAP2 can be connected by separate connecting lines extending in the second direction D2.

[0106] According to some example embodiments, the first capacitor connection structure 175a and the second capacitor connection structure 175b may be separated in the second direction D2. This may be because the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 are separated in the second direction D2, with the electrode connection structure 120 located between the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2.

[0107] According to some example embodiments, the first capacitor structure CAP1 and the second capacitor structure CAP2 may receive different signals. Multiple first capacitor structures CAP1 may receive a first signal V1, and multiple second capacitor structures CAP2 may receive a second signal V2. The level (e.g., voltage level or logic level) of the first signal V1 applied to the multiple first capacitor structures CAP1 and the level (e.g., voltage level or logic level) of the second signal V2 applied to the multiple second capacitor structures CAP2 may be different. For example, the first signal V1 may be, or may include, or correspond to a power supply voltage. For example, the second signal V2 may be, or may include, or correspond to a ground voltage.

[0108] According to some example embodiments, each of the first signal V1 and the second signal V2 can be provided to a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 via a first capacitor connection structure 175a and a second capacitor connection structure 175b, respectively. Each of the first signal V1 and the second signal V2 can be provided to the peripheral circuit wiring structure 260 via the input / output pad 320 and the contact plug 166, and can be passed to the first capacitor connection structure 175a and the second capacitor connection structure 175b.

[0109] According to some example embodiments, a first signal line connected to a first capacitor connection structure 175a and a second signal line connected to a second capacitor connection structure 175b are electrically isolated. Each of the first and second signal lines can be electrically isolated to provide different electrical signals to the first capacitor structure CAP1 and the second capacitor structure CAP2. The first signal line can provide a first signal V1 to a plurality of first capacitor structures CAP1 via the first capacitor connection structure 175a. The second signal line can provide a second signal V2 to a plurality of second capacitor structures CAP2 via the second capacitor connection structure 175b.

[0110] According to some example embodiments, each of the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 placed within a first block BLK1 is applied with a first signal V1 and a second signal V2 of different levels, so that the capacitors formed by the plurality of first capacitor structures CAP1 and the capacitors formed by the plurality of second capacitor structures CAP2 can be connected in series with each other. For example, the capacitors formed by the word line WL and the conductive film 172 of the first capacitor structure CAP1 and the capacitors formed by the word line WL and the conductive film 172 of the second capacitor structure CAP2 can be connected in series.

[0111] Reference Figure 19 , Figure 1 to Figure 18 , Figure 19 to Figure 23 and Figure 8 Multiple first capacitor structures CAP1 can be electrically connected to the peripheral circuit wiring structure 260 of the peripheral circuit region PERI via the first capacitor connection structure 175a and the first cover bonding metal 177a. The multiple first capacitor structures CAP1 can receive the first signal V1 from the peripheral circuit wiring structure 260 via the first capacitor connection structure 175a and the first cover bonding metal 177a.

[0112] According to some example embodiments, a plurality of second capacitor structures CAP2 can be electrically connected to the peripheral circuit wiring structure 260 of the peripheral circuit region PERI via a second capacitor connection structure 175b and a second cover bonding metal 177b. The plurality of second capacitor structures CAP2 can receive a second signal V2 from the peripheral circuit wiring structure 260 via the second capacitor connection structure 175b and the second cover bonding metal 177b.

[0113] According to some example embodiments, a capacitor connection structure 175 and a cover bonding metal 177 may be connected to a capacitor structure CAP. The capacitor connection structure 175 and the cover bonding metal 177 may be formed within a first inter-wire insulating film 145. The capacitor connection structure 175 may include a first capacitor connection structure 175a and a second capacitor connection structure 175b. The cover bonding metal 177 may include a first cover bonding metal 177a and a second cover bonding metal 177b.

[0114] Figure 9 , Figure 8 , Figure 9 and Figure 22 The example illustrates that the capacitor structure CAP does not receive signals directly from the input / output pad 320, but rather through the peripheral circuit wiring structure 260. However, the example embodiment is not limited to this. The capacitor structure CAP is not connected to the peripheral circuit wiring structure 260 via the cap-bonding metal 177, but can be directly connected to the input / output pad 320, such as directly to the contact plug 166. For example, the capacitor structure CAP is electrically connected to the input / output pad 320 via contacts or wiring connected to the capacitor structure CAP on the second substrate 100b of the cell substrate, and can receive signals directly from the input / output pad 320.

[0115] Reference Figure 23 The capacitor structure CAP can be placed within the capacitor aperture CPH. The capacitor aperture CPH can penetrate the molded structure MS in the first direction D1. The capacitor structure CAP may include a dielectric film 171, a conductive film 172, and a filling film 173.

[0116] According to some example embodiments, the dielectric film 171 may extend along the capacitor aperture CPH. The dielectric film 171 may contact the molded structure MS within the capacitor aperture CPH. Figure 24 The dielectric film 171 is shown extending only along the inner wall of the capacitor aperture CPH, but the example embodiment is not limited thereto. For example, it is clear that the dielectric film 171 may also be placed on the bottom surface of the capacitor aperture CPH so as to contact the cell substrate 100 within the capacitor aperture CPH.

[0117] According to some example embodiments, dielectric film 171 may include a high-dielectric material, including silicon oxide, silicon nitride, silicon oxynitride, and metals. Dielectric film 171 is shown as a single film, but this is for illustrative purposes only, and dielectric film 171 is not limited thereto.

[0118] According to some example embodiments, dielectric film 171 may include a laminated film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. Dielectric film 171 may include a dielectric film containing hafnium (Hf). Dielectric film 171 may have a laminated film structure having a ferroelectric material film and a paraelectric material film.

[0119] According to some example embodiments, the conductive film 172 may be placed on the dielectric film 171 within the capacitor aperture CPH. The conductive film 172 may extend along the dielectric film 171. The conductive film 172 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, and / or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, and / or tantalum), and a conductive metal oxide (e.g., iridium oxide and / or niobium oxide). However, the conductive film 172 is not limited thereto.

[0120] According to some example embodiments, a filler film 173 may be placed on a conductive film 172 within a capacitor aperture CPH. The filler film 173 may fill the capacitor aperture CPH on the conductive film 172. The filler film 173 may be surrounded by the conductive film 172. The filler film 173 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, the filler film 173 is not limited thereto.

[0121] According to some example embodiments, the capacitor may be formed of a conductive film 172, a dielectric film 171, and a plurality of gate electrodes (ground select line GSL, word line WL, and series select line SSL). For example, each of the first capacitor structure CAP1 and the second capacitor structure CAP2 may have an equivalent circuit in which a plurality of capacitors are connected in parallel, each of the capacitors being formed of a plurality of word lines WL, a conductive film 172, and a dielectric film 171 between the plurality of word lines WL and the conductive film 172.

[0122] Reference Figure 19 The capacitor structure CAP may include or define a void vo. The void vo may be surrounded by a conductive film 172 within the capacitor aperture CPH. The void vo may contain air (such as, but not limited to, clean, dry air).

[0123] Return to reference Figure 19 to Figure 23 , Figure 24 and Figure 25The electrode connection structure 120 can penetrate the molded structure MS in the first direction D1 within the first BLK1. The electrode connection structure 120 can penetrate the molded structure MS and connect to multiple gate electrodes (GSL, WL, and SSL). The electrode connection structure 120 can connect multiple gate electrodes (GSL, WL, and SSL).

[0124] According to some example embodiments, the electrode connection structure 120 may be positioned between capacitor structures CAP in the second direction D2. For example, in the second direction D2, the electrode connection structure 120 may be positioned between the first capacitor structure CAP1 and the second capacitor structure CAP2. In the third direction, the electrode connection structure 120 may be arranged in a zigzag shape. The electrode connection structure 120 may include a conductive material, such as a metal (e.g., tungsten (W), cobalt (Co), nickel (Ni)) or a semiconductor material (e.g., silicon). However, the electrode connection structure 120 is not limited thereto.

[0125] According to some example embodiments, the multiple gate electrodes (GSL, WL, and SSL) connected by the electrode connection structure 120 within the first BLK1 can be electrically floated. For example, in the first BLK1, voltage may not be applied to the electrode connection structure 120 or the multiple gate electrodes (GSL, WL, and SSL).

[0126] Reference Figure 26 In the first BLK1, no electrode connection wires were placed. Figure 25 Instead of the electrode connection structure 120 in the first BLK1, an insulating post 125 may be placed there. The insulating post 125 may penetrate the molded structure MS in the first direction D1 within the first BLK1. The insulating post 125 may penetrate the molded structure MS and contact multiple gate electrodes (GSL, WL, and SSL). The insulating post 125 may insulate the multiple gate electrodes (GSL, WL, and SSL) without electrically connecting them. The insulating post 125 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the insulating post 125 is not limited thereto.

[0127] According to some example embodiments, the insulating post 125 may be placed between the first capacitor structure CAP1 and the second capacitor structure CAP2 in the second direction D2. To prevent electrical short circuits caused by the small gap between the first capacitor structure CAP1 and the second capacitor structure CAP2 receiving different signals, the insulating post 125 may be placed between the first capacitor structure CAP1 and the second capacitor structure CAP2.

[0128] Reference Figure 27According to some example embodiments, the cell wiring structure 180 may be formed on a molded structure MS. For example, a first inter-wiring insulating film 145 may be formed on a first inter-layer insulating film 140, and the cell wiring structure 180 may be formed within the first inter-wiring insulating film 145. The cell wiring structure 180 may be electrically connected to the bit line BL, the gate contact 162, the source contact 164, and the contact plug 166. Therefore, the cell wiring structure 180 may be electrically connected to the channel structure CH, the gate electrode (ground select line GSL, word line WL, and serial select line SSL), and the cell substrate 100. The number of layers and / or layout of the shown cell wiring structure 180 are not limited thereto.

[0129] According to some example embodiments, cell wiring structure 180 may be electrically connected to a plurality of memory cells formed in the cell array region CAR. For example, cell wiring structure 180 may be electrically connected to bit line BL. Therefore, cell wiring structure 180 may be electrically connected to channel structure CH. In addition, cell wiring structure 180 is electrically connected to gate contact 162, thereby electrically connected to the gate electrode (ground select line GSL, word line WL, and serial select line SSL).

[0130] According to some example embodiments, the gate contact 162 may be connected to each gate electrode (GSL, word line WL, and string select line SSL). For example, the gate contact 162 extends in a first direction D1 within the first interlayer insulating film 140 and may be connected to each gate electrode (GSL, word line WL, and string select line SSL). In some example embodiments, the gate contact 162 may have a bend between the first molding structure and the second molding structure.

[0131] According to some example embodiments, the source contact 164 may be connected to the cell substrate 100. For example, the source contact 164 may extend within the first interlayer insulating film 140 in a first direction D1 and be connected to the cell substrate 100. The source contact 164 may electrically connect the cell substrate 100 and the cell wiring structure 180.

[0132] According to some example embodiments, the peripheral circuit region PERI may include a peripheral circuit substrate 200, a peripheral circuit device PT, and a peripheral circuit wiring structure 260.

[0133] According to some example embodiments, the peripheral circuit substrate 200 may be placed below the cell substrate 100. For example, the peripheral circuit substrate 200 may face the first substrate 100a of the cell substrate. The peripheral circuit substrate 200 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, and a silicon-germanium substrate). Optionally, the peripheral circuit substrate 200 may include an SOI substrate or a GOI substrate.

[0134] According to some example embodiments, a peripheral circuit device PT may be formed on a peripheral circuit substrate 200. The peripheral circuit device PT may constitute or correspond to peripheral circuitry that controls the operation of a semiconductor memory device (e.g., Figure 25 The peripheral circuitry 30 in the circuitry. For example, the peripheral circuitry device PT may include control logic (e.g., Figure 28 Control logic 37), line decoder (e.g., Figure 25 The line decoder 33) and page buffer (e.g., Figure 19 to Figure 23 (Page buffer 35). In the following description, the surface on which the peripheral circuit device PT of the peripheral circuit substrate 200 is placed may be referred to as the first substrate 200a of the peripheral circuit substrate. The first substrate 200a of the peripheral circuit substrate may be the front side of the peripheral circuit substrate 200. Conversely, the surface of the peripheral circuit substrate 200 opposite to the first substrate 200a of the peripheral circuit substrate may be referred to as the second substrate 200b of the peripheral circuit substrate. The second substrate 200b of the peripheral circuit substrate may be the back side of the peripheral circuit substrate.

[0135] According to some example embodiments, the peripheral circuit device PT may include, for example, a transistor, but the peripheral circuit device PT is not limited thereto. For example, the peripheral circuit device PT may include various active elements (such as transistors) and various passive elements (such as one or more of capacitors, resistors and inductors).

[0136] According to some example embodiments, the cell structure can be stacked on the peripheral circuit structure PERI. For example, the cell structure can be stacked on the second inter-wire insulating film 240.

[0137] The number of layers (such as the number of metal layers), and / or the orientation of the layers, and / or the thickness of each layer are not limited to the features shown in the figures. Optionally or additionally, in some example embodiments, the peripheral circuit device PT may be or include planar transistors and / or three-dimensional transistors; the example embodiments are not limited thereto.

[0138] According to some example embodiments, the first substrate 100a of the cell substrate may face the peripheral circuit structure PERI. For example, the first substrate 100a of the cell substrate may face the first substrate 200a of the peripheral circuit substrate.

[0139] According to some example embodiments, a semiconductor memory device may have a chip-to-chip (C2C) structure. In a C2C structure, an upper chip including a cell structure (CELL) is fabricated on a first wafer (e.g., cell substrate 100), and a lower chip including a peripheral circuit structure (PERI) is fabricated on a second wafer (e.g., peripheral circuit substrate 200) different from the first wafer. The upper and lower chips are then connected to each other by a bonding method.

[0140] In some example embodiments, the bonding method may refer to a method of electrically connecting a first bonding metal 195 formed on an upper metal layer of an upper chip and a second bonding metal 295 formed on an upper metal layer of a lower chip. For example, when the first bonding metal 195 and the second bonding metal 295 are formed of copper (Cu), the bonding method may be or may include a Cu-Cu bonding method. However, this is merely an example embodiment, and it is clear that the first bonding metal 195 and the second bonding metal 295 may optionally or additionally be formed of a variety of other metals, such as one or more of aluminum (Al) and tungsten (W).

[0141] According to some example embodiments, since the first bonding metal 195 and the second bonding metal 295 are bonded, the cell wiring structure 180 can be connected to the peripheral circuit wiring structure 260. Therefore, the bit line BL, each gate electrode (ground select line GSL, word line WL, and string select line SSL) and / or the cell substrate 100 can be electrically connected to the peripheral circuit device PT.

[0142] According to some example embodiments, the input / output pad 320 may be placed on the second substrate 100b of the cell substrate 100. For example, a second interlayer insulating film 310 covering the cell substrate 100 and the insulating substrate 101 may be formed on the second substrate 100b of the cell substrate 100. The input / output pad 320 may be formed on the second interlayer insulating film 310. The second interlayer insulating film 310 may include at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. However, the second interlayer insulating film 310 is not limited thereto.

[0143] According to some example embodiments, the input / output pad 320 may be electrically connected to the cell structure (CELL) and / or the peripheral circuit structure (PERI). For example, a contact plug 166 may be configured to connect the cell wiring structure 180 and the input / output pad 320. For example, the contact plug 166 may extend in a first direction D1 and penetrate the second interlayer insulating film 310, the insulating substrate 101, and the first interlayer insulating film 140. The input / output pad 320 may be electrically connected to the cell wiring structure 180 via the contact plug 166.

[0144] According to some example embodiments, the width of the contact plug 166 may be reduced as it faces the cell wiring structure 180. This may be due to the characteristics of the etching process used to form the contact plug 166.

[0145] According to some example embodiments, the insulating spacer may be formed to extend along the side surface of the contact plug 166. For example, the insulating spacer may surround the side surface of the contact plug 166. For example, the insulating spacer may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. However, the insulating spacer is not limited thereto.

[0146] According to some example embodiments, a cover insulating film 330 may be formed on the input / output pad 320. The cover insulating film 330 may include a pad opening OP that exposes at least a portion of the input / output pad 320. The input / output pad 320 may be electrically connected to an external device through the pad opening OP.

[0147] Figure 25 to Figure 28 The illustrations are provided to depict a semiconductor memory device according to some other example embodiments. Figure 8 The amplification portion P. To aid in understanding the semiconductor memory device according to some other example embodiments, the following explanation is provided in relation to the reference. Figure 9 The differences in the descriptions.

[0148] Reference Figure 8 In the first BLK1, the capacitor structure CAP may include a first capacitor structure CAP1, a second capacitor structure CAP2, and a third capacitor structure CAP3. Each of the first capacitor structure CAP1, the second capacitor structure CAP2, and the third capacitor structure CAP3 can be connected to a corresponding one of the first capacitor connection structure 175a, the second capacitor connection structure 175b, and the third capacitor connection structure 175c. Through the first capacitor connection structure 175a, the second capacitor connection structure 175b, and the third capacitor connection structure 175c, a first signal V1, a second signal V2, and a third signal V3 can be applied to the first capacitor structure CAP1, the second capacitor structure CAP2, and the third capacitor structure CAP3, respectively. The signal levels of the first signal V1, the second signal V2, and the third signal V3 can all be different.

[0149] According to some example embodiments, when a first signal V1 is applied to a first capacitor structure CAP1, the first capacitor may consist of multiple gate electrodes ( Figure 9 The ground selection line GSL, word line WL, and serial selection line SSL) and the conductive film of the first capacitor structure CAP1 ( Figure 29 and Figure 29 The conductive film 172) and the dielectric film ( Figure 1 to Figure 28 and Figure 1 to Figure 28 The dielectric film 171 is formed. When the second signal V2 is applied to the second capacitor structure CAP2, the second capacitor may be formed by multiple gate electrodes (e.g., Figure 1 The ground selection line GSL, word line WL, and serial selection line SSL) and the conductive film of the second capacitor structure CAP2 ( Figure 1 and Figure 1 The conductive film 172) and the dielectric film ( Figure 1 to Figure 28 and Figure 2The dielectric film 171 is formed. When the third signal V3 is applied to the third capacitor structure CAP3, the third capacitor can be formed by multiple gate electrodes ( Figure 1 to Figure 28 The ground selection line GSL, word line WL, and serial selection line SSL) and the conductive film of the third capacitor structure CAP3 ( Figure 1 and Figure 1 to Figure 28 The conductive film 172) and the dielectric film ( Figure 30 and Figure 31 A dielectric film 171 is formed. The first capacitor, the second capacitor, and the third capacitor can be connected in series.

[0150] Figure 30 This is a schematic layout diagram used to describe a semiconductor memory device according to another example embodiment. Figure 30 This illustrates some example embodiments. Figure 31 The enlarged portion of P is shown in the diagram. Figure 29 This is an illustration along some example embodiments. Figure 29 The sectional view taken by line AA. Figure 1 to Figure 28 This is an illustration along some example embodiments. ​ The cross-sectional view taken by line CC. To aid in understanding the semiconductor memory device according to some other example embodiments, the following explanations and references... ​ The differences in the descriptions.

[0151] Reference ​ Multiple first capacitor structures CAP1 can be arranged along the second direction D2. Multiple second capacitor structures CAP2 can be arranged along the second direction D2. The multiple first capacitor structures CAP1 and the multiple second capacitor structures CAP2 can be spaced apart along the third direction D3.

[0152] According to some example embodiments, a first capacitor connection structure 175a connecting multiple first capacitor structures CAP1 and a second capacitor connection structure 175b connecting multiple second capacitor structures CAP2 may be spaced apart from each other in a third direction D3. The first capacitor connection structure 175a and the second capacitor connection structure 175b may be spaced apart from the bit line BL of the second block BLK2 in the third direction D3. The first capacitor connection structure 175a and the second capacitor connection structure 175b may be arranged at the same height level as the bit line BL along a first direction D1. The bit line BL, the first capacitor connection structure 175a, and the second capacitor connection structure 175b may be arranged on a first substrate 100a of the cell substrate.

[0153] According to some example embodiments, a first signal V1 can be applied to a plurality of first capacitor structures CAP1 via a first capacitor connection structure 175a, and a second signal V2 can be applied to a plurality of second capacitor structures CAP2 via a second capacitor connection structure 175b. The first capacitors formed by the plurality of first capacitor structures CAP1 by applying the first signal V1 to the plurality of first capacitor structures CAP1 and the second capacitors formed by the plurality of second capacitor structures CAP2 by applying the second signal V2 to the plurality of second capacitor structures CAP2 can be connected in series with each other.

[0154] ​ It is a schematic layout diagram used to describe a semiconductor memory device according to some example embodiments. ​ This illustrates some example embodiments. ​ The enlarged portion of P is shown in the diagram. ​ This is an illustration along some example embodiments. ​ The sectional view taken by line AA. ​ This is an illustration along some example embodiments. ​ The sectional view taken by line BB. ​ This is an illustration along some example embodiments. ​ Another view showing a cross-section taken by line BB. To aid in understanding the semiconductor memory device according to some example embodiments, the following explanations and references... ​ The differences in the descriptions.

[0155] Reference ​ The molded structure MS may include a first BLK1, a second BLK2, and a third BLK3. The first BLK1, second BLK2, and third BLK3 may be arranged on a third-direction D3. On the third-direction D3, the third BLK3 may be placed outside the first BLK1 and second BLK2. On the third-direction D3, the first BLK1 may be placed between the second BLK2 and the third BLK3.

[0156] According to some example embodiments, a plurality of first capacitor structures CAP1 may be placed within a first block BLK1. The plurality of first capacitor structures CAP1 may penetrate the molding structure MS within the first block BLK1. The plurality of first capacitor structures CAP1 may be connected to a first capacitor connection structure 175a. Based on a first substrate 100a of a cell substrate, the first capacitor connection structure 175a may be placed on the first block BLK1.

[0157] According to some example embodiments, a plurality of second capacitor structures CAP2 may be placed within a third BLK3. The plurality of second capacitor structures CAP2 may penetrate the molding structure MS within the third BLK3. The plurality of second capacitor structures CAP2 may be connected to a second capacitor connection structure 175b. Based on a first substrate 100a of a cell substrate, the second capacitor connection structure 175b may be placed on the third BLK3.

[0158] According to some example embodiments, the first capacitor connection structure 175a and the second capacitor connection structure 175b can be connected. For example, the first capacitor connection structure 175a and the second capacitor connection structure 175b can be stacked with the gate electrode dicing pattern WLC between the first BLK1 and the third BLK3, and can be connected to each other via lines extending in the second direction D2. Since the first capacitor connection structure 175a and the second capacitor connection structure 175b are connected to each other, a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 can be connected to each other. For example, when a specific signal is applied to the first capacitor connection structure 175a, the same signal can also be applied to the second capacitor connection structure 175b, the plurality of first capacitor structures CAP1, and the plurality of second capacitor structures CAP2.

[0159] According to some example embodiments, the first capacitor connection structure 175a and the second capacitor connection structure 175b may be electrically floating. Electrical signals may not be applied to the first capacitor connection structure 175a and the second capacitor connection structure 175b. In this case, the conductive films 172 of the plurality of first capacitor structures CAP1 and the plurality of second capacitor structures CAP2 may be electrically floating.

[0160] According to some example embodiments, the first electrode connection structure 121 may be placed within the first BLK1. The first electrode connection structure 121 may penetrate the molded structure MS within the first BLK1. The first electrode connection structure 121 may connect to multiple gate electrodes (GSL, WL, and SSL) of the first BLK1.

[0161] According to some example embodiments, the first electrode connection structure 121 may be connected to the first electrode connection wiring 321. The first electrode connection structure 121 may be connected to the first electrode connection wiring 321 via a first via 181a. A first signal may be applied through the first electrode connection wiring 321. Therefore, the first signal may be applied to multiple gate electrodes (GSL, WL, and SSL) within the first BLK1 via the first electrode connection wiring 321 and the first electrode connection structure 121.

[0162] According to some example embodiments, the second electrode connection structure 122 may be placed within the third BLK3. The second electrode connection structure 122 may penetrate the molded structure MS within the third BLK3. The second electrode connection structure 122 may connect to multiple gate electrodes (GSL, WL, and SSL) of the third BLK3.

[0163] According to some example embodiments, the second electrode connection structure 122 can be connected to the second electrode connection wiring 322. The second electrode connection structure 122 can be connected to the second electrode connection wiring 322 via a second via 181b. A second signal can be applied through the second electrode connection wiring 322. Therefore, through the second electrode connection wiring 322 and the second electrode connection structure 122, the second signal can be applied to multiple gate electrodes (GSL, WL, and SSL) within the third BLK3.

[0164] According to some example embodiments, a first signal applied via the first electrode connection wiring 321 and a second signal applied via the second electrode connection wiring 322 may have different levels. For example, the first signal may be a power supply voltage, and the second signal may be a ground voltage.

[0165] According to some example embodiments, the first electrode connection wiring 321 and the second electrode connection wiring 322 can be exposed to the outside through openings in the cover insulating film 330. Through the first electrode connection wiring 321 and the second electrode connection wiring 322, signals can be directly applied to multiple gate electrodes (GSL, WL, and SSL) of the first BLK1 and the third BLK3.

[0166] According to some example embodiments, in the first direction D1, the first electrode connection wiring 321 and the second electrode connection wiring 322 may be placed on the same side with respect to the molding structure MS. The first electrode connection wiring 321 and the second electrode connection wiring 322 may be arranged on the second substrate 100b of the cell substrate. In the first direction D1, the first electrode connection wiring 321 and the second electrode connection wiring 322 may be arranged on opposite sides of the capacitor connection structure 175 with respect to the molding structure MS. The capacitor connection structure 175 is placed on the first substrate 100a of the cell substrate, and the first electrode connection wiring 321 and the second electrode connection wiring 322 are arranged on the second substrate 100b of the cell substrate, so the capacitor connection structure 175 and the first electrode connection wiring 321 and the second electrode connection wiring 322 may be arranged on opposite sides with respect to the molding structure MS in the first direction D1.

[0167] According to some example embodiments, when a first signal is applied through the first electrode connection wiring 321, the first capacitor may be formed within the first block BLK1 by a plurality of gate electrodes (ground select line GSL, word line WL, and serial select line SSL) and a conductive film of the first capacitor structure CAP1. ​ and ​ The conductive film 172 is formed. When the second signal is applied to the second electrode connection wiring 322, the second capacitor can be formed within the third block BLK3 by multiple gate electrodes (ground select line GSL, word line WL, and serial select line SSL) and the conductive film of the second capacitor structure CAP2. ​ and ​ A conductive film 172 is formed. The first capacitor structure CAP1 and the second capacitor structure CAP2 are connected by a first capacitor connection structure 175a and a second capacitor connection structure 175b, so the first capacitor formed in the first BLK1 and the second capacitor formed in the third BLK3 can be connected in series.

[0168] Reference ​ The second electrode connection structure 122 may not be connected to the unit wiring structure 180. The second electrode connection structure 122 may not receive signals from the unit wiring structure 180, but may receive signals through the second electrode connection wiring 322.

[0169] Reference ​ The second electrode connection structure 122 can be connected to the cell wiring structure 180. For example, the second electrode connection structure 122 can be electrically connected to the cell wiring structure 180 via the cell contact via 188. In addition to receiving signals through the second electrode connection wiring 322, the second electrode connection structure 122 can also receive signals provided to the peripheral circuit wiring structure 260 through the input / output pad 320 and contact plug 166 via the cell wiring structure 180.

[0170] ​ This is an illustration along some example embodiments. ​ Another view showing a cross-section taken by line AA. To aid in understanding the semiconductor memory device according to some other example embodiments, the following description focuses on the references... ​ The differences in the descriptions.

[0171] Reference ​The capacitor connection structure 175 can be placed on the second substrate 100b of the cell substrate. The first capacitor connection structure 175a and the second capacitor connection structure 175b can be arranged on the second substrate 100b of the cell substrate. The first capacitor connection structure 175a can be connected to a plurality of first capacitor structures CAP1 on the second substrate 100b of the cell substrate. The second capacitor connection structure 175b can be connected to a plurality of second capacitor structures CAP2 on the second substrate 100b of the cell substrate.

[0172] ​ This is a schematic layout diagram illustrating a semiconductor memory device according to some example embodiments. ​ This illustrates some example embodiments. ​ The enlarged portion of P is shown in the diagram. ​ This is an illustration along some example embodiments. ​ The sectional view taken by line AA. ​ This is an illustration along some example embodiments. ​ The cross-sectional view taken by line BB. To aid in understanding the semiconductor memory device according to some other example embodiments, the following description focuses on references to... ​ The differences in the descriptions.

[0173] Reference ​ The first capacitor connection structure 175a and the second capacitor connection structure 175b can be separated on the third direction D3, and the gate electrode cutting pattern WLC is between the first capacitor connection structure 175a and the second capacitor connection structure 175b.

[0174] According to some example embodiments, the first capacitor connection structure 175a can be electrically connected to the peripheral circuit wiring structure 260 of the peripheral circuit region PERI via the first cap bonding metal 177a. Through the first capacitor connection structure 175a and the peripheral circuit wiring structure 260, a plurality of first capacitor structures CAP1 can receive a first signal applied to the input / output pad 320.

[0175] According to some example embodiments, the second capacitor connection structure 175b can be electrically connected to the peripheral circuit wiring structure 260 of the peripheral circuit region PERI via the second cover bonding metal 177b. Through the second capacitor connection structure 175b and the peripheral circuit wiring structure 260, a plurality of second capacitor structures CAP2 can receive a second signal applied to the input / output pad 320.

[0176] According to some example embodiments, the first electrode connection structure 121 and the second electrode connection structure 122 can be connected. A bridging connection wiring 325 extending on the third direction D3 can be arranged to overlap with the first BLK1 and the third BLK3. The bridging connection wiring 325 can be connected to the first electrode connection structure 121 and the second electrode connection structure 122. The bridging connection wiring 325 can be connected to the first electrode connection structure 121 and the second electrode connection structure 122 via contact vias 181.

[0177] According to some example embodiments, the first electrode connection structure 121 and the second electrode connection structure 122 may be electrically floating. Electrical signals may not be applied to the first electrode connection structure 121 and the second electrode connection structure 122.

[0178] According to some example embodiments, when a first signal is applied to the first capacitor connection structure 175a and the plurality of first capacitor structures CAP1, the first capacitor may be composed of a plurality of gate electrodes (ground select line GSL, word line WL and serial select line SSL) and the conductive film of the first capacitor structure CAP1 within the first block BLK1. ​ and ​ The conductive film 172 is formed. When the second signal is applied to the second capacitor connection structure 175b and the multiple second capacitor structures CAP2, the second capacitor can be formed within the third block BLK3 by multiple gate electrodes (ground select line GSL, word line WL and serial select line SSL) and the conductive film of the second capacitor structure CAP2. ​ and ​ A conductive film 172 is formed. Since the first electrode connection structure 121 and the second electrode connection structure 122 are connected by bridging connection wiring 325, the first capacitor formed in the first BLK1 and the second capacitor formed in the third BLK3 can be connected in series.

[0179] ​ This is a diagram illustrating an electronic system including a semiconductor memory device according to some example embodiments.

[0180] Reference ​ Electronic system 1000 may include semiconductor memory device 1100 and controller 1200 electrically connected to semiconductor memory device 1100. Electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including a storage device. For example, electronic system 1000 may be a solid-state drive (SSD device), universal serial bus (USB), computing system, medical device, or communication device including one or more semiconductor memory devices 1100.

[0181] According to some example embodiments, semiconductor memory device 1100 may be or may include a non-volatile memory device (e.g., a NAND flash memory device) or be included in a non-volatile memory device. For example, semiconductor memory device 1100 may be or include as referred to ​ The semiconductor memory device described or included in, as referenced ​ In the described semiconductor memory device, the semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0182] According to some example embodiments, the first structure 1100F may include a decoder circuit (decoder circuit 1110; for example...). ​ (Line decoder 33), page buffer (page buffer 1120; for example, ​ Page buffer 35) and logic circuits (logic circuit 1130; for example, ​ The peripheral circuit structure of the control logic 37). The first structure 1100F can correspond to, for example, the use of... ​ The described peripheral circuit structure is PERI.

[0183] According to some example embodiments, the second structure 1100S may include, as referenced ​ The described common-source line CSL, multiple bit lines BL, and multiple cell strings CSTR are described. The cell strings CSTR can be connected to the decoder circuit 1110 via the word line WL, at least one string select line SSL, and at least one ground select line GSL. Additionally, the cell strings CSTR can be connected to the page buffer 1120 via the bit line BL. For example, the second structure 1100S may correspond to the reference. ​ The described cell structure.

[0184] According to some example embodiments, the common source line CSL and the cell string CSTR can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0185] According to some example embodiments, the circuit is electrically connected to a logic circuit (logic circuit 1130; for example...). ​ The semiconductor memory device 1100 can communicate with the controller 1200 via the input / output pad 1101 of the control logic 37). The input / output pad 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S. The input / output connection wiring 1135 can correspond to, for example, the above-described use of...​ The described contact plug 166.

[0186] According to some example embodiments, controller 1200 may include processor 1210, NAND controller 1220, and host interface (I / F) 1230. In some example embodiments, electronic system 1000 may include multiple semiconductor memory devices 1100. In this case, controller 1200 may control multiple semiconductor memory devices 1100.

[0187] According to some example embodiments, processor 1210 can control the operation of the entire electronic system 1000, including controller 1200. Processor 1210 can operate with specific firmware and control NAND controller 1220 to access semiconductor memory device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor memory device 1100. Through NAND interface 1221, control commands for controlling semiconductor memory device 1100, data to be written to memory cell transistors (MCTs) of semiconductor memory device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor memory device 1100 can be transmitted. Host interface 1230 provides communication between electronic system 1000 and an external host. When a control command is received from an external host through host interface 1230, processor 1210 can control semiconductor memory device 1100 in response to the control command.

[0188] ​ It is a perspective view used to describe an electronic system including a semiconductor memory device according to some example embodiments. ​ This is an illustration along some example embodiments. ​ The sectional view taken from line II.

[0189] Reference ​ and ​ The electronic system may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be interconnected with the main controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0190] According to some example embodiments, the main substrate 2001 may include a connector 2006 having a plurality of pins that mate with an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host via any one or more of Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), and Mobile Physical Layer (M-Phy) for Universal Flash Storage (UFS). In some example embodiments, the electronic system 2000 may be powered by the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0191] According to some example embodiments, the main controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000.

[0192] According to some example embodiments, DRAM 2004 may be a buffer memory for reducing the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in the electronic system 2000 may optionally or additionally serve as a type of cache memory and may also provide space for temporary data storage during the control operation of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, the main controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0193] According to some example embodiments, the semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package containing a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100 and semiconductor chips 2200 on the package substrate 2100, a bonding layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0194] According to some example embodiments, the package substrate 2100 may be a printed circuit board (PCB) including a package pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to... ​ Input / output pad 1101.

[0195] According to some example embodiments, the connection structure 2400 may be a bonding wiring that electrically connects the input / output pad 2210 and the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other via a bonding wiring method and electrically connected to the package pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other via a connection structure including through-silicon vias (also known as "through-silicon vias," TSVs) instead of a bonding wiring type connection structure 2400.

[0196] According to some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate in addition to the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be interconnected with each other via wiring formed on the intermediate substrate.

[0197] According to some example embodiments, the package substrate 2100 may be a PCB. The package substrate 2100 may include a package substrate body 2120, an upper package pad 2130 disposed on the upper surface of the package substrate body 2120, a lower package pad 2125 positioned on or exposed through the lower surface of the package substrate body 2120, and internal wiring 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 within the package substrate body 2120. The upper package pad 2130 may be electrically connected to a connection structure 2400. The lower package pad 2125 may be connected via a conductive connection portion 2800 to, for example, ​ Wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 shown.

[0198] In an electronic system according to some example embodiments, each of the semiconductor chips 2200 may include the above references. ​The semiconductor memory device described. For example, semiconductor chip 2200 may include a first capacitor structure CAP1 and a second capacitor structure CAP2 disposed in a first block BLK1. Each of the first capacitor structure CAP1 and the second capacitor structure CAP2 may be connected to a first capacitor connection structure 175a and a second capacitor connection structure 175b.

[0199] In an electronic system according to some example embodiments, when a signal is input / output to a semiconductor memory device of a semiconductor chip 2200, noise in the input / output signal can be mitigated by using a plurality of first capacitor structures CAP1 and a plurality of second capacitor structures CAP2 arranged in a first block BLK1.

[0200] Any elements and / or functional blocks disclosed above may include processing circuitry (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof) or be implemented in processing circuitry (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof). For example, processing circuitry may more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include electrical components such as transistors, resistors, capacitors, etc. Processing circuitry may include electronic components such as logic gates, including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0201] Various exemplary embodiments have been described in detail above. However, it will be clear to those skilled in the art that the scope of the claims is not limited thereto, and various modifications and / or variations can be made without departing from the spirit of the technology set forth in the claims. Furthermore, the above exemplary embodiments can be implemented by deleting some elements, and each exemplary embodiment can be implemented in combination with each other; the exemplary embodiments are not necessarily mutually exclusive.

Claims

1. A semiconductor memory device comprising: a molded structure including a plurality of gate electrodes stacked in a first direction; a gate electrode cut pattern separating the molded structure into a plurality of blocks by cutting the plurality of gate electrodes along a plane, the plane including the first direction and a second direction crossing the first direction; a plurality of first capacitor structures penetrating the molded structure in the first direction, the plurality of first capacitor structures within a first block among the plurality of blocks; a plurality of second capacitor structures penetrating the molded structure in the first direction within the first block; a first capacitor connection structure on the first block and connected to the plurality of first capacitor structures; and a second capacitor connection structure on the first block and connected to the plurality of second capacitor structures, wherein a first signal line connected to the first capacitor connection structure and a second signal line connected to the second capacitor connection structure are electrically separated.

2. The semiconductor memory device of claim 1, wherein each of the plurality of first capacitor structures and the plurality of second capacitor structures defines a capacitor hole penetrating the molded structure, and the semiconductor memory device further comprises a dielectric film extending along the capacitor hole and in contact with the molded structure, and a conductive film on the dielectric film. each of the plurality of first capacitor structures and the plurality of second capacitor structures further comprises 3. The semiconductor memory device of claim 2, wherein, a fill film on the conductive film and configured to fill the capacitor hole.

4. The semiconductor memory device of claim 2, wherein the plurality of first capacitor structures and the plurality of second capacitor structures define a void within the capacitor hole surrounded by the conductive film.

5. The semiconductor memory device of claim 1, further comprising: an electrode connection structure penetrating the molded structure in the first direction within the first block and connected to the plurality of gate electrodes. The electrode connection structure is between the plurality of first capacitor structures and the plurality of second capacitor structures in the second direction.

6. The semiconductor memory device of claim 5, wherein, The first capacitor connection structure and the second capacitor connection structure are spaced apart in the second direction.

7. The semiconductor memory device of claim 1, wherein, 8. The semiconductor memory device of claim 1, wherein a first distance between two first capacitor structures of the plurality of first capacitor structures adjacent in the second direction and a second distance between two second capacitor structures of the plurality of second capacitor structures adjacent in the second direction are each shorter than a third distance between one first capacitor structure of the plurality of first capacitor structures and one second capacitor structure of the plurality of second capacitor structures adjacent to each other in the second direction.

9. The semiconductor memory device of claim 1, further comprising: a second block spaced apart from the first block along a third direction crossing the first direction and the second direction, the gate electrode cut pattern being between the first block and the second block; a channel structure penetrating the molded structure in the first direction within the second block; and a bit line extending in the third direction on the molded structure within the second block and connected to the channel structure, wherein the first capacitor connection structure and the second capacitor connection structure are spaced apart from the bit line in the third direction. ​ ​ 10. The semiconductor memory device of claim 9, wherein, The first capacitor connection structure and the second capacitor connection structure are at the same height level as the bit line in the first direction.

11. The semiconductor memory device according to claim 1, wherein, in the first block, the plurality of first capacitor structures are arranged in a second direction, and the plurality of second capacitor structures are arranged in the second direction.

12. The semiconductor memory device of claim 11, wherein, The first capacitor connection structure and the second capacitor connection structure are spaced apart in a third direction intersecting the first direction and the second direction.

13. The semiconductor memory device according to claim 1, wherein, the plurality of first capacitor structures are configured to receive a first signal, and the plurality of second capacitor structures are configured to receive a second signal, wherein a level of the first signal and a level of the second signal are different.

14. A semiconductor memory device comprising: a molded structure including a plurality of gate electrodes stacked in a first direction; a gate electrode cut pattern extending along a plane defined by the first direction and a second direction intersecting the first direction, and separating the molded structure into a plurality of blocks by cutting the plurality of gate electrodes; a plurality of first capacitor structures penetrating the molded structure within a first block, the first block being at least one of the plurality of blocks; a first electrode connection structure penetrating the molded structure within the first block, and connecting the plurality of gate electrodes; a plurality of second capacitor structures penetrating the molded structure within a second block spaced apart from the first block along a third direction intersecting the first direction and the second direction, the gate electrode cut pattern being between the first block and the second block, the second block being at least one of the plurality of blocks; a second electrode connection structure penetrating the molded structure within the second block, and connecting the plurality of gate electrodes; and a capacitor connection structure on the molded structure in the first direction, and connected to the plurality of first capacitor structures and the plurality of second capacitor structures.

15. The semiconductor memory device according to claim 14, wherein, the first electrode connection structure is configured to receive a first signal, and the second electrode connection structure is configured to receive a second signal, wherein a level of the first signal and a level of the second signal are different. each of the plurality of first capacitor structures and the plurality of second capacitor structures includes:

16. The semiconductor memory device of claim 14, wherein, a dielectric film in contact with the molded structure; and a conductive film on the dielectric film, and connected to the capacitor connection structure, wherein the conductive film of the plurality of first capacitor structures and the plurality of second capacitor structures is electrically floating.

17. The semiconductor memory device according to claim 14, further comprising: a first electrode connection wiring connected to the first electrode connection structure, wherein the capacitor connection structure and the first electrode connection wiring are on opposite sides with respect to the molded structure in the first direction.

18. The semiconductor memory device according to claim 17, further comprising: a second electrode connection wiring connected to the second electrode connection structure, wherein the first electrode connection wiring and the second electrode connection wiring are on the same side with respect to the molded structure in the first direction.

19. The semiconductor memory device according to claim 14, further comprising: ​ a plurality of first capacitors between the plurality of gate electrodes and the plurality of first capacitor structures in the first block; and a plurality of second capacitors between the plurality of gate electrodes and the plurality of second capacitor structures in the second block, wherein the plurality of first capacitors and the plurality of second capacitors are connected in series.

20. A semiconductor memory device comprising: a cell base including a first base and a second base opposite the first base; a molded structure including a plurality of gate electrodes stacked on the first base in a first direction perpendicular to the first base; a gate electrode cut pattern extending along a plane defined by the first direction and a second direction crossing the first direction, and the gate electrode cut pattern separates the molded structure into a plurality of blocks by cutting the plurality of gate electrodes; a plurality of first capacitor structures penetrating the molded structure in a first block, the first block being at least one block among the plurality of blocks; a first electrode connection structure penetrating the molded structure in the first block and connecting the plurality of gate electrodes; a first capacitor connection structure on the second base on the first block and connected to the plurality of first capacitor structures; a plurality of second capacitor structures penetrating the molded structure in a second block spaced apart from the first block along a third direction crossing the first direction and the second direction, the gate electrode cut pattern being between the first block and the second block, the second block being at least one block among the plurality of blocks; a second electrode connection structure penetrating the molded structure in the second block and connecting the plurality of gate electrodes; and a second capacitor connection structure on the second base on the second block and connected to the plurality of second capacitor structures.

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