Semiconductor device having electrode structure

Abstract

The invention relates to a semiconductor device having an electrode structure. The semiconductor device includes: a cell region; a first peripheral circuit region adjacent to a first side of the cell region in the first direction; and a second peripheral circuit region adjacent to a second side of the cell region in the second direction. The first direction is perpendicular to the second direction. The cell region includes: a first sub-region including a first memory cell; and a second sub-region including a second memory cell. The first memory cell includes a first electrode structure. The second memory cell includes a second electrode structure. The first electrode structure comprises a first lower electrode and a first upper electrode. The second electrode structure comprises a second lower electrode and a second upper electrode. The first lower electrode is thicker than the second lower electrode. The first upper electrode is thinner than the second upper electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0123247, filed on September 10, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically to semiconductor devices including memory cells and methods of manufacturing the same, each memory cell including a variable resistor device and an electrode structure. Background Technology

[0004] In recent years, the demand for miniaturization, low power consumption, high performance, and versatility in electronic devices has required semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices. Researchers and industry are researching and developing such semiconductor devices. These semiconductor devices include those capable of storing data by utilizing the property of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse). Summary of the Invention

[0005] The embodiments of this disclosure are designed to reduce the holding current I-hold of memory cells in semiconductor devices.

[0006] The embodiments of this disclosure are intended to homogenize the characteristics of memory cells in semiconductor devices.

[0007] According to one embodiment of this disclosure, a semiconductor device includes: a cell region; a first peripheral circuit region adjacent to a first side of the cell region in a first direction; and a second peripheral circuit region adjacent to a second side of the cell region in a second direction. The first and second directions are perpendicular to each other. The cell region includes: a first sub-region including a first memory cell; and a second sub-region including a second memory cell. The first memory cell includes a first electrode structure. The second memory cell includes a second electrode structure. The first electrode structure includes a first lower electrode and a first upper electrode. The second electrode structure includes a second lower electrode and a second upper electrode. The first lower electrode is thicker than the second lower electrode. The first upper electrode is thinner than the second upper electrode.

[0008] According to another embodiment of this disclosure, a semiconductor device includes: a cell region; and a first peripheral circuit region adjacent to a first side of the cell region. The cell region includes: a first sub-region including a first memory cell; and a second sub-region including a second memory cell. The first memory cell is closer to the first peripheral circuit region than the second memory cell. The first memory cell includes a first variable resistor element and a first electrode. The second memory cell includes a second variable resistor element and a second electrode. The first electrode includes a first lower electrode and a first upper electrode. The second electrode includes a second lower electrode and a second upper electrode. The first lower electrode is thicker than the second lower electrode. The first upper electrode is thinner than the second upper electrode. Attached Figure Description

[0009] Figure 1A This is a three-dimensional schematic diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1B This is a top view schematic diagram illustrating the block arrangement of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 2A to 2D This is a simplified schematic diagram illustrating a cell region CA of a semiconductor device comprising multiple sub-regions according to an embodiment of the present disclosure.

[0012] Figure 3A and Figure 3B , Figure 4A and Figure 4B , Figure 5A and Figure 5B as well as Figure 6 These are cross-sectional views and enlarged views illustrating the memory cell structure of a semiconductor device according to different embodiments of the present disclosure.

[0013] Figures 7A to 7F This is a simplified schematic diagram illustrating a method for forming an electrode structure according to an embodiment of the present disclosure. Detailed Implementation

[0014] Various embodiments of this disclosure have been described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of these embodiments are provided by way of example only to illustrate specific implementations of the technical concepts of this disclosure. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described herein.

[0015] All the crosshairs in the diagram represent corresponding or similar areas between the diagrams, rather than representing material related to those areas.

[0016] When one element is identified as “connected” or “coupled” to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between the elements. When two elements are identified as “directly connected” or “directly coupled”, one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0017] When one element is identified as being "above", "on top of", "below", or "under" another element, the two elements can be in direct contact with each other, or an intermediate element can be placed between the two elements.

[0018] Terms such as "vertical," "horizontal," "top," "bottom," "above," "below," "under," "underneath," "above," "over," "side," "upper part," "uppermost part," "lower part," "lowest part," "front," "back," "left," "right," "column," "row," and "horizontal," as well as other terms indicating relative spatial relationships or orientations, are used for the purpose of facilitating description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or orientations may exist that are not shown in the accompanying drawings or described in the specification.

[0019] Terms such as "first" and "second" are used to distinguish between multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, while in another example, the second element may be named the first element.

[0020] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0021] The above concepts have been disclosed in conjunction with the examples and embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concept of this disclosure. The embodiments disclosed in this specification should be considered exemplary, not restrictive. Therefore, the scope of this disclosure is not limited to the above description. All changes within the equivalent meaning and scope of the claims are included within its scope.

[0022] The accompanying drawings are not necessarily drawn to scale, and in some cases the scale may be exaggerated in order to clearly illustrate the features of the embodiments. When referring to the first layer as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that a third layer exists between the first layer and the second layer or the substrate.

[0023] Figure 1AThis is a three-dimensional schematic diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure. Figure 1B This is a top schematic view illustrating a bulk arrangement of semiconductor devices according to embodiments of the present disclosure. Reference Figure 1A and Figure 1B A semiconductor device according to embodiments of this disclosure may include: a plurality of row interconnects RL extending parallel to each other along a first direction X; a plurality of column interconnects CL extending parallel to each other along a second direction Y; and a memory cell MC disposed at the intersection between the row interconnects RL and the column interconnects CL. The memory cell MC may be configured to have a pillar shape extending along a vertical direction Z between the row interconnects RL and the column interconnects CL. The first direction X, the second direction Y, and the vertical direction Z may be perpendicular to each other. Figure 1B In order to facilitate understanding of the inventive concept of this disclosure, the memory cell MC is shown as exposed on the column interconnect CL.

[0024] The semiconductor device may include a cell region CA, a first peripheral circuit region PA1, and a second peripheral circuit region PA2. The first peripheral circuit region PA1 may be configured to be adjacent to a first side of the cell region CA in a first direction X. For example, the first peripheral circuit region PA1 may include row interconnect driving circuitry. The second peripheral circuit region PA2 may be configured to be adjacent to a second side of the cell region CA in a second direction Y. For example, the second peripheral circuit region PA2 may include column interconnect driving circuitry. Therefore, a row interconnect RL may extend from the first peripheral circuit region PA1 along the first direction X and pass through the cell region CA. A column interconnect CL may extend from the second peripheral circuit region PA2 along the second direction Y and pass through the cell region CA. The row interconnect RL and the column interconnect CL may intersect each other in the cell region CA. According to one embodiment of this disclosure, the row interconnect RL may correspond to a word line, while the column interconnect CL may correspond to a bit line. According to another embodiment of the invention, the row interconnect RL may correspond to a bit line, while the column interconnect CL may correspond to a word line.

[0025] Figures 2A to 2D A cell region CA of a semiconductor device according to an embodiment of the present disclosure is shown, the cell region comprising a plurality of sub-regions A1 to A4. For example, a cell region CA can be virtually divided into a plurality of sub-regions A1 to A4. That is, a cell region may include a plurality of sub-regions A1 to A4. Reference Figures 2A to 2CThe cell region CA can include multiple sub-regions A1 to A4. Sub-regions A1 to A4 can be divided according to their distances from the reference point P, such as d1 to d3, r1 to r3, and dx to dy. The reference point P can be the memory cell MC located in the cell region CA that is closest to the first peripheral circuit region PA1 and the second peripheral circuit region PA2. For example, the reference point P can be set as the first corner of the adjacent cell region CA. The first corner can be closest to the first peripheral circuit region PA1 and the second peripheral circuit region PA2.

[0026] refer to Figure 2A The cell region CA may include multiple sub-regions A1 to A4, which are divided by multiple boundary lines L1, L2, and L3 (referred to as L1 to L3). Boundary lines L1 to L3 may extend along a second diagonal direction D2 to have a first shortest interval distance d1, a second shortest interval distance d2, and a third shortest interval distance d3 from the reference point P in a first diagonal direction D1. Therefore, the first sub-region A1 may include storage cells MCa disposed within the first boundary line L1 at the reference point P, the second sub-region A2 may include storage cells MCb disposed between the first boundary line L1 and the second boundary line L2 at the reference point P, the third sub-region A3 may include storage cells MCc disposed between the second boundary line L2 and the third boundary line L3 at the reference point P, and the fourth sub-region A4 may include storage cells MCd disposed outside the third boundary line L3 at the reference point P. According to embodiments of this disclosure, the boundary lines L1 to L3 may have a serpentine shape so that they do not pass through the storage cells MC from a microscopic perspective.

[0027] refer to Figure 2BThe unit region CA may include multiple sub-regions A1 to A4 (e.g., A1, A2, A3, and A4), which are divided by multiple concentric circular boundary curves C1 to C3. Boundary curves C1 to C3 may have a concentric circular arc shape centered on a reference point P. Therefore, sub-regions A1 to A4 may have a fan-shaped or orbital fan-shaped shape. The first sub-region A1 may include a storage unit MCa disposed within the first boundary curve C1, which has a radius of a first interval distance r1 from the reference point P in the diagonal direction D1. The second sub-region A2 may include a storage unit MCb disposed between the first boundary curve C1 with a radius of a first interval distance r1 from the reference point P and a second boundary curve C2 with a radius of a second interval distance r2. The third sub-region A3 may include a storage unit MCc disposed between the second boundary curve C2 with a radius of a second interval distance r2 from the reference point P and a third boundary curve C3 with a radius of a third interval distance r3. The fourth sub-region A4 may include a storage cell MCd, which is located outside a third boundary curve C3 having a radius of a third interval distance r3 from the reference point P. The boundary curves C1 to C3 may also have a serpentine shape so that they do not pass through the storage cell MC from a microscopic perspective.

[0028] refer to Figure 2C The unit region CA may include multiple sub-regions A1 to A4, which are divided based on predetermined distances dx and dy from the reference point P in the first direction X and the second direction Y. The multiple sub-regions A1 to A4 may include: a first sub-region A1, which includes a storage unit MCa, disposed within a first distance dx from the reference point P in the first direction X and within a second distance dy from the reference point P in the second direction Y; a second sub-region A2, which includes a storage unit MCb, disposed outside the first distance dx from the reference point P in the first direction X and within the second distance dy from the reference point P in the second direction Y; a third sub-region A3, which includes a storage unit MCc, disposed within the first distance dx from the reference point P in the first direction X and outside the second distance dy from the reference point P in the second direction Y; and a fourth sub-region A4, which includes a storage unit MCd, disposed outside the first distance dx from the reference point P in the first direction X and outside the second distance dy from the reference point P in the second direction Y.

[0029] refer to Figure 2DThe unit region CA may include multiple sub-regions A1 to A4 (A1, A2, A3 and A4), which are divided based on the first distance dxa, the second distance dxb and the third distance dxc in the first direction X and based on the first distance dya, the second distance dyb and the third distance dyc in the second direction Y. The multiple sub-regions A1 to A4 may include: a first sub-region A1, which includes a storage unit MCa, the storage unit MCa being disposed within a first distance dxa from the reference point P in the first direction X and within a first distance dya from the reference point P in the second direction Y; a second sub-region A2, which includes a storage unit MCb, the storage unit MCb being disposed outside the first distance dxa from the reference point P in the first direction X and within a second distance dxb, and outside the first distance dya from the reference point P in the second direction Y and within a second distance dyb; a third sub-region A3, which includes a storage unit MCc, the storage unit MCc being disposed outside the second distance dxb from the reference point P in the first direction X and within a third distance dxc, and outside the second distance dyb from the reference point P in the second direction Y and within a third distance dyc; and a fourth sub-region A4, which includes a storage unit MCd, the storage unit MCd being disposed outside the third distance dxc from the reference point P in the first direction X and outside the third distance dyc from the reference point P in the second direction Y.

[0030] According to the technical concept of this disclosure, the cell region CA may include at least two or more sub-regions A1 to A4. The cell region CA can be divided into at least two or more sub-regions. According to the technical concept of this disclosure, the cell region CA can be divided into multiple sub-regions A1 to A4 from the region A1 closest to the reference point P to the region A4 furthest from the reference point P.

[0031] Figure 3A and Figure 3B , Figure 4A and Figure 4B , Figure 5A and Figure 5B as well as Figure 6 These are cross-sectional and enlarged views showing memory cell structures 101a to 101d, 102a to 102d, 103a to 103d and 104a to 104d of semiconductor devices according to different embodiments of the present disclosure.

[0032] refer to Figure 3A and Figure 3BA semiconductor device according to one embodiment of the present disclosure may include first to fourth memory cell structures 101a to 101d. Each of the first to fourth memory cell structures 101a to 101d may include: a lower interconnect 10, memory cells MC1a to MC1d disposed on the lower interconnect 10, and an upper interconnect 70 disposed on the memory cells MC1a to MC1d.

[0033] The lower interconnect 10 can correspond to Figure 1A and Figure 1B The row interconnect RL in the middle. The upper interconnect 70 can correspond to Figure 1A and Figure 1B The column interconnects CL in the middle. Each of the lower interconnects 10 and the upper interconnects 70 may include at least one of the following: a metal layer (such as tungsten (W)), a metal compound layer (such as titanium nitride (TiN)), a metal alloy layer, and a metal silicide layer.

[0034] refer to Figures 2A to 2C The first storage cell structure 101a can be set in the first sub-region A1, the second storage cell structure 101b can be set in the second sub-region A2, the third storage cell structure 101c can be set in the third sub-region A3, and the fourth storage cell structure 101d can be set in the fourth sub-region A4.

[0035] The first memory cell MC1a may include a bottom electrode 20, a selection element 30, a middle electrode 40, a variable resistor element 50, and a first top electrode 60a. The first top electrode 60a may include a first lower top electrode 61a and a first upper top electrode 62a. The second memory cell MC1b may include a bottom electrode 20, a selection element 30, a middle electrode 40, a variable resistor element 50, and a second top electrode 60b. The second top electrode 60b may include a second lower top electrode 61b and a second upper top electrode 62b. The third memory cell MC1c may include a bottom electrode 20, a selection element 30, a middle electrode 40, a variable resistor element 50, and a third top electrode 60c. The third top electrode 60c may include a third lower top electrode 61c and a third upper top electrode 62c. The fourth memory cell MC1d includes a bottom electrode 20, a selection element 30, a middle electrode 40, a variable resistor element 50, and a fourth top electrode 60d. The fourth top electrode 60d includes a fourth lower top electrode 61d and a fourth upper top electrode 62d.

[0036] The bottom electrode 20 may include at least one of the following: a metal layer (such as tungsten (W)), a metal compound layer (such as titanium nitride (TiN)), a metal alloy layer, and a metal silicide layer. The selection element 30 may include a bidirectional threshold switch (OTS) material (such as a chalcogenide-based material), a mixed ion-electron conduction (MIEC) material (such as a metal chalcogenide-based material), a metal-insulator transition (MIT) material (such as niobium oxide (NbO2) or vanadium oxide (VO2)), or an ion-doped dielectric layer. According to one embodiment of this disclosure, the selection element 30 may include arsenic (As)-doped silicon oxide (SiO2) or arsenic (As)-doped silicon nitride (SiN). The intermediate electrode 40 may include a carbon layer. The variable resistor element 50 may include one of the following: a transition metal oxide layer, a metal oxide layer such as a perovskite-based material, a phase change material layer such as a chalcogenide-based material, a ferroelectric material layer, and a ferromagnetic material layer. In all memory cells MC1a to MC1d of all memory cell structures 101a to 101d, the bottom electrode 20 may have the same vertical thickness.

[0037] The first to fourth lower top electrodes 61a to 61d may comprise a carbon layer, an ion-doped carbon layer, or an ion-doped titanium nitride layer. For example, the ions may comprise at least one of arsenic (As), germanium (Ge), silicon (Si), nitrogen (N), and oxygen (O). The first to fourth upper top electrodes 62a to 62d may comprise a metal layer (such as a tungsten (W) layer) or a metal compound layer (such as a titanium nitride (TiN) layer).

[0038] Figure 3B yes Figure 3A Enlarged views of the first to fourth top electrodes 60a to 60d. See also Figure 3B The first lower top electrode 61a of the first top electrode 60a may have a first lower thickness Tla, while the second lower top electrode 62b of the second top electrode 60b may have a second lower thickness Tlb. The third lower top electrode 61c of the third top electrode 60c may have a third lower thickness Tlc, and the fourth lower top electrode 61d of the fourth top electrode 60d may have a fourth lower thickness Tld. The first lower thickness Tla may be greater than the second lower thickness Tlb. The second lower thickness Tlb may be greater than the third lower thickness Tlc. The third lower thickness Tlc may be greater than the fourth lower thickness Tld. According to an embodiment of this disclosure, the second lower thickness Tlb and the third lower thickness Tlc may be substantially the same.

[0039] Furthermore, the first upper top electrode 62a of the first top electrode 60a may have a first upper thickness Tua, while the second upper top electrode 62b of the second top electrode 60b may have a second upper thickness Tub. The third upper top electrode 62c of the third top electrode 60c may have a third upper thickness Tuc, while the fourth upper top electrode 62d of the fourth top electrode 60d may have a fourth upper thickness Tud. The first upper thickness Tua may be less than the second upper thickness Tub, the second upper thickness Tub may be less than the third upper thickness Tuc, and the third upper thickness Tuc may be less than the fourth upper thickness Tud. According to one embodiment of this disclosure, the second upper thickness Tub and the third upper thickness Tuc may be substantially the same.

[0040] The sum of the first lower thickness Tla and the first upper thickness Tua, Tta; the sum of the second lower thickness Tlb and the second upper thickness Tub, Ttb; the sum of the third lower thickness Tlc and the third upper thickness Tuc, Ttc; and the sum of the fourth lower thickness Tld and the fourth upper thickness Tud, Ttd, can be the same. In the illustrated embodiment, the total thicknesses Tta, Ttb, Ttc, and Ttd of each of the first top electrode 60a, the second top electrode 60b, the third top electrode 60c, and the fourth top electrode 60d can be the same.

[0041] The resistance of each of the lower top electrodes 61a to 61d can be much higher than the resistance of the upper top electrodes 62a to 62d. The upper top electrodes 62a to 62d can have very low resistance, i.e., high conductivity. The upper top electrodes 62a to 62d can have different thicknesses Tua to Tud, but their resistance differences can be very small. The upper top electrodes 62a to 62d do not affect the resistance of the top electrodes 60a to 60d. Therefore, the resistance of the first top electrode 60a can be higher than the resistance of the second top electrode 60b. The resistance of the second top electrode 60b can be higher than the resistance of the third top electrode 60c. The resistance of the third top electrode 60c can be higher than the resistance of the fourth top electrode 60d.

[0042] Each of the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 may have a drive circuit. Therefore, the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 can supply voltage or current to the memory cells MC1a to MC1d in the cell region CA. Memory cells closer to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MC1a) can be supplied with relatively higher voltage or current. Therefore, the holding current of memory cells closer to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MC1a) can be higher than the holding current of memory cells farther away from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the fourth memory cell MC1d). Therefore, in memory cells closer to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MC1a), the holding current "I-hold" may become higher than the cell current Ic. Although the selection element 30 is turned off in memory cells (e.g., first memory cell MC1a) near the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2, a current higher than the current in the on-state may still flow in memory cell MC1a. Therefore, in memory cells near the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., first memory cell MC1a), oscillations may occur in the region between the holding current I-hold and the threshold current Ith of the selection element 30, where the current value repeatedly changes between the on / off states. According to one embodiment of this disclosure, the resistance of the top electrodes 60a to 60d can vary depending on the location of the memory cells MC1a to MC1d. For example, the first top electrode 60a of the memory cell closest to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., first memory cell MC1a) may have a relatively high resistance, while the fourth top electrode 60d of the memory cell furthest from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., fourth memory cell MC1d) may have a relatively low resistance. Overall, the holding current I-hold of memory cells MC1a to MC1d can be made uniform, and the operation of memory cells MC1a to MC1d can be stable. Figure 3A and Figure 3B In the middle, the positions and / or resistances of the lower top electrodes 61a to 61d and the upper top electrodes 62a to 62d can be interchanged.

[0043] refer to Figure 4A and Figure 4BThe semiconductor device according to embodiments of the present disclosure may include first to fourth memory cell structures 102a to 102d. Each of the first to fourth memory cell structures 102a to 102d may include: a lower interconnect 10, memory cells MC2a to MC2d disposed on the lower interconnect 10, and an upper interconnect 70 disposed on the memory cells MC2a to MC2d.

[0044] refer to Figures 2A to 2C The first storage cell structure 102a can be set in the first sub-region A1, the second storage cell structure 102b can be set in the second sub-region A2, the third storage cell structure 102c can be set in the third sub-region A3, and the fourth storage cell structure 102d can be set in the fourth sub-region A4.

[0045] The first memory cell MC2a may include a bottom electrode 20, a selection element 30, a first intermediate electrode 40a, a variable resistor element 50, and a top electrode 60. The first intermediate electrode 40a may include a first lower intermediate electrode 41a and a first upper intermediate electrode 42a. The second memory cell MC2b may include a bottom electrode 20, a selection element 30, a second intermediate electrode 40b, a variable resistor element 50, and a top electrode 60. The second intermediate electrode 40b may include a second lower intermediate electrode 41b and a second upper intermediate electrode 42b. The third memory cell MC2c may include a bottom electrode 20, a selection element 30, a third intermediate electrode 40c, a variable resistor element 50, and a top electrode 60. The third intermediate electrode 40c may include a third lower intermediate electrode 41c and a third upper intermediate electrode 42c. The fourth memory cell MC2d may include a bottom electrode 20, a selection element 30, a fourth intermediate electrode 40d, a variable resistor element 50, and a top electrode 60. The fourth intermediate electrode 40d may include a fourth lower intermediate electrode 41d and a fourth upper intermediate electrode 42d. The first to fourth lower intermediate electrodes 41a to 41d may include a carbon layer. The first to fourth upper intermediate electrodes 42a to 42d may include a metal compound layer (such as titanium nitride (TiN)) or a metal layer (such as tungsten (W)).

[0046] Figure 4B yes Figure 4A Enlarged view of the first to fourth intermediate electrodes 40a to 40d shown. (Reference) Figure 4BThe first lower intermediate electrode 41a of the first intermediate electrode 40a may have a first lower thickness Mla, the second lower intermediate electrode 41b of the second intermediate electrode 40b may have a second lower thickness Mlb, the third lower intermediate electrode 41c of the third intermediate electrode 40c may have a third lower thickness Mlc, and the fourth lower intermediate electrode 41d of the fourth intermediate electrode 40d may have a fourth lower thickness Mld. The first lower thickness Mla may be greater than the second lower thickness Mlb, the second lower thickness Mlb may be greater than the third lower thickness Mlc, and the third lower thickness Mlc may be greater than the fourth lower thickness Mld. According to an embodiment of this disclosure, the second lower thickness Mlb and the third lower thickness Mlc may be substantially the same.

[0047] Furthermore, the first upper intermediate electrode 42a of the first intermediate electrode 40a may have a first upper thickness Mua, the second upper intermediate electrode 42b of the second intermediate electrode 40b may have a second upper thickness Mub, the third upper intermediate electrode 42c of the third intermediate electrode 40c may have a third upper thickness Muc, and the fourth upper intermediate electrode 42d of the fourth intermediate electrode 40d may have a fourth upper thickness Mud. The first upper thickness Mua may be less than the second upper thickness Mub. The second upper thickness Mub may be less than the third upper thickness Muc. The third upper thickness Muc may be less than the fourth upper thickness Mud. According to an embodiment of this disclosure, the second upper thickness Mub and the third upper thickness Muc may be substantially the same.

[0048] The sum of the first lower thickness Mla and the first upper thickness Mua, Mta; the sum of the second lower thickness Mlb and the second upper thickness Mub, Mtb; the sum of the third lower thickness Mlc and the third upper thickness Muc, Mtc; and the sum of the fourth lower thickness Mld and the fourth upper thickness Mud, Mtd, can be the same. In the illustrated embodiment, the total thicknesses Mta, Mtb, Mtc, and Mtd of the first to fourth intermediate electrodes 40a, 40b, 40c, and 40d can be the same.

[0049] The resistance of each of the lower intermediate electrodes 41a to 41d can be higher than the resistance of the upper intermediate electrodes 42a to 42d. Therefore, the resistance of the first intermediate electrode 40a can be higher than the resistance of the second top electrode 40b, the resistance of the second intermediate electrode 40b can be higher than the resistance of the third intermediate electrode 40c, and the resistance of the third intermediate electrode 40c can be higher than the resistance of the fourth intermediate electrode 40d.

[0050] The resistance of each of the lower intermediate electrodes 41a to 41d can be much higher than the resistance of the upper intermediate electrodes 42a to 42d. The upper intermediate electrodes 42a to 42d can have very low resistance, i.e., high conductivity. The upper intermediate electrodes 42a to 42d can have different thicknesses Mua to Mud, but their resistance differences can be very small. The upper intermediate electrodes 42a to 42d do not affect the resistance of the intermediate electrodes 40a to 40d. Therefore, the resistance of the first intermediate electrode 40a can be higher than the resistance of the second intermediate electrode 40b. The resistance of the second intermediate electrode 40b can be higher than the resistance of the third intermediate electrode 40c. The resistance of the third intermediate electrode 40c can be higher than the resistance of the fourth intermediate electrode 40d. According to one embodiment of this disclosure, the resistance of the intermediate electrodes 40a to 40d can vary depending on the position of the memory cells MC2a to MC2d. For example, the first top electrode 60a of the memory cell closest to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MC2a) can have a relatively high resistance, while the fourth top electrode 60d of the memory cell furthest from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the fourth memory cell MC2d) can have a relatively low resistance. Overall, the holding current I-hold of memory cells MC2a to MC2d can become uniform, and memory cells MC2a to MC2d can operate stably. Figure 4A and Figure 4B The positions and / or resistances of the lower intermediate electrodes 41a to 41d and the upper intermediate electrodes 42a to 42d can be interchanged.

[0051] refer to Figure 5A and Figure 5B The semiconductor device according to embodiments of the present disclosure may include first to fourth memory cell structures 103a to 103d. Each of the first to fourth memory cell structures 103a to 103d may include: a lower interconnect 10, memory cells MC3a to MC3d located above the lower interconnect 10, and an upper interconnect 70 located above the memory cells MC3a to MC3d.

[0052] refer to Figures 2A to 2C The first storage cell structure 103a can be set in the first sub-region A1, the second storage cell structure 103b can be set in the second sub-region A2, the third storage cell structure 103c can be set in the third sub-region A3, and the fourth storage cell structure 103d can be set in the fourth sub-region A4.

[0053] The first to fourth memory cells MC3a to MC3d may each include first to fourth bottom electrodes 20a, 20b, 20c, and 20d. Furthermore, the first to fourth bottom electrodes 20a, 20b, 20c, and 20d may each include first to fourth lower bottom electrodes 21a, 21b, 21c, and 21d. Additionally, the first to fourth bottom electrodes 20a, 20b, 20c, and 20d may each include first to fourth upper bottom electrodes 22a, 22b, 22c, and 22d. More specifically, the first memory cell MC3a may include a first bottom electrode 20a, a selection element 30, an intermediate electrode 40, a variable resistor element 50, and a top electrode 60. The first bottom electrode 20a may include a first lower bottom electrode 21a and a first upper bottom electrode 22a. The second memory cell MC3b may include a second bottom electrode 20b, a selection element 30, an intermediate electrode 40, a variable resistor element 50, and a top electrode 60. The second bottom electrode 20b may include a second lower bottom electrode 21b and a second upper bottom electrode 22b. The third memory cell MC3c may include a third bottom electrode 20c, a selection element 30, an intermediate electrode 40, a variable resistor element 50, and a top electrode 60. The third bottom electrode 20c may include a third lower bottom electrode 21c and a third upper bottom electrode 22c. The fourth memory cell MC4d may include a fourth bottom electrode 20d, a selection element 30, an intermediate electrode 40, a variable resistor element 50, and a top electrode 60. The fourth bottom electrode 20d may include a fourth lower bottom electrode 21d and a fourth upper bottom electrode 22d. The first to fourth lower bottom electrodes 21a to 21d may contain a carbon layer. The first to fourth upper bottom electrodes 22a to 22d may contain a metal compound layer (such as titanium nitride (TiN)) or a metal layer (such as tungsten (W)).

[0054] Figure 5B yes Figure 5A Enlarged views of the first to fourth bottom electrodes 20a to 20d. (Reference) Figure 5BThe first to fourth lower bottom electrodes 21a, 21b, 21c, and 21d of the first bottom electrode 20a can each have a first to fourth lower thickness Bla, Bla, Blc, and Bld, respectively. More specifically, the first lower bottom electrode 21a of the first bottom electrode 20a can have a first lower thickness Bla, the second lower bottom electrode 21b of the second bottom electrode 20b can have a second lower thickness Bla, the third lower bottom electrode 21c of the third bottom electrode 20c can have a third lower thickness Blc, and the fourth lower bottom electrode 21d of the fourth bottom electrode 20d can have a fourth lower thickness Bld. The first lower thickness Bla can be greater than the second lower thickness Bla, the second lower thickness Bla can be greater than the third lower thickness Blc, and the third lower thickness Blc can be greater than the fourth lower thickness Bld. According to one embodiment of this disclosure, the second lower thickness Bla and the third lower thickness Blc can be substantially the same.

[0055] Furthermore, the first upper bottom electrode 22a of the first bottom electrode 20a may have a first upper thickness Bua, the second upper bottom electrode 22b of the second bottom electrode 20b may have a second upper thickness Bub, the third upper bottom electrode 22c of the third bottom electrode 20c may have a third upper thickness Buc, and the fourth upper bottom electrode 22d of the fourth bottom electrode 20d may have a fourth upper thickness Bud. The first upper thickness Bua may be less than the second upper thickness Bub. The second upper thickness Bub may be less than the third upper thickness Buc. The third upper thickness Buc may be less than the fourth upper thickness Bud. According to one embodiment of this disclosure, the second upper thickness Bub and the third upper thickness Buc may be substantially the same.

[0056] The sum of the first lower thickness Bla and the first upper thickness Bua (Bta), the sum of the second lower thickness Blab and the second upper thickness Bub (Btb), the sum of the third lower thickness Blc and the third upper thickness Buc (Btc), and the sum of the fourth lower thickness Blad and the fourth upper thickness Bud (Btd) can be the same. The total thickness of the first to fourth bottom electrodes 20a, 20b, 20c, and 20d can also be the same.

[0057] Each of the lower bottom electrodes 21a to 21d can have a sufficiently high resistance, higher than that of the upper bottom electrodes 22a to 22d. The upper bottom electrodes 22a to 22d can have very low resistance, i.e., high conductivity. The upper bottom electrodes 22a to 22d can have different thicknesses Bua to Bud, but their resistance differences can be small. The upper bottom electrodes 22a to 22d do not affect the resistance of the bottom electrodes 20a to 20d. Therefore, the resistance of the first bottom electrode 20a can be higher than that of the second bottom electrode 20b, the resistance of the second bottom electrode 20b can be higher than that of the third bottom electrode 20c, and the resistance of the third bottom electrode 20c can be higher than that of the fourth bottom electrode 20d. According to one embodiment of this disclosure, the resistance of the bottom electrodes 20a to 20d can vary depending on the position of the memory cells MC3a to MC3d. For example, the first bottom electrode 20a of the memory cell closest to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MC3a) can have a relatively high resistance, while the fourth bottom electrode 20d of the memory cell furthest from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the fourth memory cell MC3d) can have a relatively low resistance. Overall, the holding current I-hold of memory cells MC3a to MC3d can become uniform, and memory cells MC3a to MC3d can operate stably. Figure 5A and Figure 5B In the middle, the positions and / or resistances of the lower bottom electrodes 21a to 21d and the upper bottom electrodes 22a to 22d can be interchanged.

[0058] refer to Figure 6 The semiconductor device according to embodiments of this disclosure may include first to fourth memory cell structures 104a to 104d. Each of the first to fourth memory cell structures 104a to 104d may include: memory cells MC4a to MC4d disposed above the lower interconnect 10, and an upper interconnect 70 disposed above the memory cells MC4a to MC4d. (See reference...) Figures 2A to 2C The first storage cell structure 104a can be set in the first sub-region A1, the second storage cell structure 104b can be set in the second sub-region A2, the third storage cell structure 104c can be set in the third sub-region A3, and the fourth storage cell structure 104d can be set in the fourth sub-region A4.

[0059] The first to fourth memory cells MC4a, MC4b, MC4c, and MC4d may each include first to fourth bottom electrodes 20a, 20b, 20c, and 20d. Furthermore, the first to fourth memory cells MC4a, MC4b, MC4c, and MC4d may each include first to fourth intermediate electrodes 40a, 40b, 40c, and 40d. Additionally, the first to fourth memory cells MC4a, MC4b, MC4c, and MC4d may each include first to fourth top electrodes 60a, 60b, 60c, and 60d.

[0060] The first memory cell MC4a may include a first bottom electrode 20a, a selection element 30, a first intermediate electrode 40a, a variable resistor element 50, and a first top electrode 60a. The first bottom electrode 20a may include a first lower bottom electrode 21a and a first upper bottom electrode 22a. The first intermediate electrode 40a may include a first lower intermediate electrode 41a and a first upper intermediate electrode 42a. The first top electrode 60a may include a first lower top electrode 61a and a first upper top electrode 62a.

[0061] The second memory cell MC4b may include a second bottom electrode 20b, a selection element 30, a second intermediate electrode 40b, a variable resistor element 50, and a second top electrode 60b. The second bottom electrode 20b may include a second lower bottom electrode 21b and a second upper bottom electrode 22b. The second intermediate electrode 40b may include a second lower intermediate electrode 41b and a second upper intermediate electrode 42b. The second top electrode 60b may include a second lower top electrode 61b and a second upper top electrode 62b.

[0062] The third memory cell MC4c may include a third bottom electrode 20c, a selection element 30, a third intermediate electrode 40c, a variable resistor element 50, and a third top electrode 60c. The third bottom electrode 20c may include a third lower bottom electrode 21c and a third upper bottom electrode 22c. The third intermediate electrode 40c may include a third lower intermediate electrode 41c and a third upper intermediate electrode 42c. The third top electrode 60c may include a third lower top electrode 61c and a third upper top electrode 62c.

[0063] The fourth memory cell MC4d may include a fourth bottom electrode 20d, a selection element 30, a fourth intermediate electrode 40d, a variable resistor element 50, and a fourth top electrode 60d. The fourth bottom electrode 20d may include a fourth lower bottom electrode 21d and a fourth upper bottom electrode 22d. The fourth intermediate electrode 40d may include a fourth lower intermediate electrode 41d and a fourth upper intermediate electrode 42d. The fourth top electrode 60d may include a fourth lower top electrode 61d and a fourth upper top electrode 62d.

[0064] Figures 7A to 7FA method for forming electrode structures 90a to 90d according to embodiments of the present disclosure is shown. Reference Figure 7A A method for forming electrode structures 90a to 90d according to embodiments of the present disclosure may include: forming a first preliminary lower electrode layer 91p1 over a base layer 80p in first to fourth sub-regions A1 to A4. The first preliminary lower electrode layer 91p1 may include a carbon layer or a metal compound layer (such as titanium nitride). The first preliminary lower electrode layer 91p1 may have a first thickness t1. The base layer 80p may be a material layer for forming one of: a lower interconnect 10, a select element 30, and a variable resistor element 50.

[0065] See Figure 7B The method may further include: covering a first sub-region A1; forming a first mask pattern M1 exposing second to fourth sub-regions A2 to A4; and performing a first etch-back process to partially remove the upper portion of the first preliminary lower electrode layer 91p1 exposed in the second to fourth sub-regions A2 to A4. For example, the method may include: thinning the first preliminary lower electrode layer 91p1 exposed in the second to fourth sub-regions A2 to A4. In the first sub-region A1, the first preliminary lower electrode layer 91p1 may remain as a first lower electrode layer 91pa, while in the second to fourth sub-regions A2 to A4, the first preliminary lower electrode layer 91p1 may be thinned to a second preliminary lower electrode layer 91p2 having a second thickness t2. Subsequently, the first mask pattern M1 may be removed.

[0066] refer to Figure 7C The method may further include: covering a first sub-region A1 and a second sub-region A2; forming a second mask pattern M2 exposing a third sub-region A3 and a fourth sub-region A4; and performing a second etch-back process to partially remove the upper portion of the second preliminary lower electrode layer 91p2 exposed in the third sub-region A3 and the fourth sub-region A4. For example, the method may include: thinning the second preliminary lower electrode layer 91p2 exposed in the third sub-region A3 and the fourth sub-region A4. The first lower electrode layer 91pa may remain in the first sub-region A1, the second preliminary lower electrode layer 91p2 may remain in the second sub-region A2 as the second lower electrode layer 91pb, and the second preliminary lower electrode layer 91p2 may be thinned in the third sub-region A3 and the fourth sub-region A4 to a third preliminary lower electrode layer 91p3 having a third thickness t3. Subsequently, the second mask pattern M2 may be removed.

[0067] refer to Figure 7DThe method may further include: covering the first to third sub-regions A1 to A3 by forming a third mask pattern M3 that exposes only the fourth sub-region A4; and performing a third etch-back process to partially remove the upper portion of the third preliminary lower electrode layer 91p3 exposed in the fourth sub-region A4. For example, the method may include: thinning the third preliminary lower electrode layer 91p3 exposed in the fourth sub-region A4. The first lower electrode layer 91pa may remain in the first sub-region A1, the second lower electrode layer 91pb may remain in the second sub-region A2, the third preliminary lower electrode layer 91p3 may remain in the third sub-region A3 as the third lower top electrode layer 91pc, and the third preliminary lower electrode layer 91p3 may be thinned in the fourth sub-region A4 to a fourth lower electrode layer 91pd having a fourth thickness t4. Subsequently, the third mask pattern M3 may be removed.

[0068] refer to Figure 7E The method may further include forming an upper electrode layer 92p over lower electrode layers 91pa to 91pd in the respective first to fourth sub-regions A1 to A4. Forming the upper electrode layer 92p may include performing a deposition process and a planarization process, such as chemical mechanical polishing (CMP). The upper electrode layer 92p may include a metal layer, such as tungsten (W). The upper surface of the upper electrode layer 92p may be planar in the first to fourth sub-regions A1 to A4.

[0069] refer to Figure 7F The method may further include: forming a fourth mask pattern M4; and forming first to fourth electrode structures 90a to 90d and a base element 80 by patterning an upper electrode layer 92p, lower electrode layers 91pa to 91pd, and a base layer 80p. The first electrode structure 90a may be formed in a first sub-region A1, the second electrode structure 90b may be formed in a second sub-region A2, the third electrode structure 90c may be formed in a third sub-region A3, and the fourth electrode structure 90d may be formed in a fourth sub-region A4. The fourth mask pattern M4 may include photoresist and / or a hard mask. The hard mask may include at least one inorganic layer. The fourth mask pattern M4 may be removed.

[0070] The first to fourth electrode structures 90a to 90d can correspond to Figure 3A and Figures 3B to 6 The illustration shows bottom electrodes 20a to 20d, middle electrodes 40a to 40d, or top electrodes 60a to 60d. The base element 80 can correspond to... Figure 3A and Figures 3B to 6 The diagram shows the lower interconnect 10, the selection element 30, or the variable resistor element 50.

[0071] According to embodiments of this disclosure, the holding current of a memory cell based on the location of the semiconductor element can be stabilized.

[0072] According to embodiments of this disclosure, the characteristics and operation of the memory cells of a semiconductor device can be homogenized and stabilized.

[0073] While this disclosure has been described in conjunction with specific example embodiments, those skilled in the art will understand that various changes and modifications can be made without departing from the technical concept and scope of this disclosure as defined in the following claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device comprising: a cell region; a first peripheral circuit region adjacent to a first side of the cell region in a first direction; and a second peripheral circuit region adjacent to a second side of the cell region in a second direction, wherein the first direction and the second direction are perpendicular to each other, and wherein the cell region comprises: a first sub-region including first storage cells; and a second sub-region including second storage cells, wherein: the first storage cells include first electrode structures, the second storage cells include second electrode structures, the first electrode structures include first lower electrodes and first upper electrodes, the second electrode structures include second lower electrodes and second upper electrodes, the first lower electrodes are thicker than the second lower electrodes, and the first upper electrodes are thinner than the second upper electrodes. the first sub-region is disposed closer to the first peripheral circuit region than the second sub-region.

2. The semiconductor device of claim 1, wherein, 3. The semiconductor device of claim 1, wherein: the cell region further comprises a third sub-region including third storage cells, the third storage cells include third electrode structures, the third electrode structures include third lower electrodes and third upper electrodes, the second lower electrodes are thicker than the third lower electrodes, and the second upper electrodes are thinner than the third upper electrodes.

4. The semiconductor device of claim 3, wherein: the first sub-region is disposed closer to the second peripheral circuit region than the second sub-region, and the third sub-region is disposed farther from the second peripheral circuit region than the second sub-region.

5. The semiconductor device of claim 3, wherein: the cell region further comprises a fourth sub-region including fourth storage cells, the fourth storage cells include fourth electrode structures, the fourth electrode structures include fourth lower electrodes and fourth upper electrodes, the third lower electrodes are thicker than the fourth lower electrodes, and the third upper electrodes are thinner than the fourth upper electrodes.

6. The semiconductor device of claim 1, the first electrode structures include: wherein a first bottom electrode; a first variable resistance element over the first bottom electrode; and a first top electrode over the first variable resistance element, wherein the second electrode structures include: a second bottom electrode; a second variable resistance element over the second bottom electrode; and a second top electrode over the second variable resistance element, wherein the first top electrode includes the first lower electrode and the first upper electrode, and wherein the second top electrode includes the second lower electrode and the second upper electrode. the first bottom electrode and the second bottom electrode have the same thickness.

7. The semiconductor device of claim 6, wherein, 8. The semiconductor device of claim 6, wherein: the first lower electrodes and the second lower electrodes include at least one of a carbon layer, an ion-doped carbon layer, and an ion-doped titanium nitride layer, and the first upper electrodes and the second upper electrodes include one of a metal layer and a metal compound layer. ​ 9. The semiconductor device of claim 6, wherein: the first electrode structure further comprises a first selection element and a first intermediate electrode between the first bottom electrode and the first variable resistance element, and the second electrode structure further comprises a second selection element and a second intermediate electrode between the second bottom electrode and the second variable resistance element.

10. The semiconductor device of claim 9, wherein: the first and second selection elements comprise one of: an OTS material, an MIEC material, an MIT material, and an ion-doped dielectric layer, OTS referring to a bidirectional threshold switch, MIEC referring to a mixed ionic electronic conductor, and MIT referring to a metal-insulator transition, and the first and second intermediate electrodes comprise a carbon layer.

11. The semiconductor device of claim 1, wherein, the first electrode structure comprises: a first bottom electrode; a first variable resistance element on the first bottom electrode; and a first top electrode on the first variable resistance element, wherein the second electrode structure comprises: a second bottom electrode; a second variable resistance element on the second bottom electrode; and a second top electrode on the second variable resistance element, wherein the first bottom electrode comprises the first lower electrode and the first upper electrode, and wherein the second bottom electrode comprises the second lower electrode and the second upper electrode.

12. The semiconductor device of claim 1, wherein, a sum of a thickness of the first lower electrode and a thickness of the first upper electrode is the same as a sum of a thickness of the second lower electrode and a thickness of the second upper electrode.

13. The semiconductor device of claim 1, wherein: a resistance of the first lower electrode is higher than a resistance of the first upper electrode, and a resistance of the second lower electrode is higher than a resistance of the second upper electrode.

14. The semiconductor device of claim 1, wherein: the first upper electrode is disposed directly on the first lower electrode, and the second upper electrode is disposed directly on the second lower electrode.

15. A semiconductor device, comprising: a cell region, and a first peripheral circuit region adjacent to a first side of the cell region, wherein the cell region comprises: a first sub-region comprising first memory cells; and a second sub-region comprising second memory cells, wherein the first memory cells are closer to the first peripheral circuit region than the second memory cells, wherein: the first memory cells comprise first variable resistance elements and first electrodes, the second memory cells comprise second variable resistance elements and second electrodes, the first electrodes comprise first lower electrodes and first upper electrodes, the second electrodes comprise second lower electrodes and second upper electrodes, the first lower electrodes are thicker than the second lower electrodes, and the first upper electrodes are thinner than the second upper electrodes.

16. The semiconductor device of claim 15, further comprising: a second peripheral circuit region adjacent to a second side of the cell region, wherein the first memory cells are closer to the second peripheral circuit region than the second memory cells.

17. The semiconductor device according to claim 15, wherein the first storage unit includes: a first bottom electrode; a first selection element over the first bottom electrode; a first intermediate electrode over the first selection element; the first variable resistance element over the first intermediate electrode; and the first electrode over the first variable resistance element, wherein the second storage unit includes: a second bottom electrode; a second selection element over the second bottom electrode; a second intermediate electrode over the second selection element; the second variable resistance element over the second intermediate electrode; and the second electrode over the second variable resistance element.

18. The semiconductor device according to claim 15, wherein, the first storage unit includes: a first selection element over the first electrode; a first intermediate electrode over the first selection element; the first variable resistance element over the first intermediate electrode; and a first top electrode over the first variable resistance element, wherein the second storage unit includes: a second selection element over the second electrode; a second intermediate electrode over the second selection element; the second variable resistance element over the second intermediate electrode; and a second top electrode over the second variable resistance element.

19. The semiconductor device according to claim 15, wherein: the cell region further includes a third sub-region including a third storage unit, the third storage unit is farther from the first peripheral circuit region than the second storage unit, the third storage unit includes a third variable resistance element and a third electrode, the third electrode includes a third lower electrode and a third upper electrode, the second lower electrode is thicker than the third lower electrode, and the second upper electrode is thinner than the third upper electrode.

20. The semiconductor device according to claim 15, wherein: the first lower electrode and the second lower electrode include at least one of a carbon layer, an ion-doped carbon layer, and an ion-doped titanium nitride layer, and the first upper electrode and the second upper electrode include one of a metal layer and a metal compound layer.

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