A gallium nitride power device with gate hot electron blocking structure and a method of fabricating the same

By introducing a hot electron blocking structure into the p-GaN gate structure and utilizing the stacked structure of gallium nitride and indium gallium nitride/aluminum gallium nitride material layers, the problem of easy failure of p-GaN gates is solved, and the reliability and stability of gallium nitride high electron mobility transistors are improved.

CN121645937BActive Publication Date: 2026-04-21GUANGDONG UNIV OF TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
GUANGDONG UNIV OF TECH
Filing Date
2026-02-04
Publication Date
2026-04-21

AI Technical Summary

Technical Problem

In the prior art, the p-GaN gate structure is prone to failure under high thermal electron bombardment and strong electric field stress, resulting in insufficient gate reliability and difficulty in realizing stable enhancement-mode gallium nitride high electron mobility transistors.

Method used

A hot electron blocking structure is designed at the p-GaN gate structure, consisting of multiple periodically stacked gallium nitride material layers and indium gallium nitride/aluminum gallium nitride material layers. By changing the band structure, it can prevent hot electron bombardment, promote hot electron recombination, or block their movement.

Benefits of technology

It effectively reduces the damage of hot electrons to the gate Schottky junction, improves the reliability and stability of the device, and enhances the resistance to gate breakdown.

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Abstract

The application discloses a gallium nitride power device with a gate hot electron blocking structure, which comprises a substrate layer, a buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top; a first P-type material layer, a hot electron blocking structure layer, a second P-type material layer and a gate metal are sequentially arranged above the barrier layer; and a source metal and a drain metal are respectively arranged at both ends of the barrier layer. The barrier layer, the source metal part sidewall, the drain metal part sidewall, the first P-type material layer sidewall, the hot electron blocking structure layer sidewall, the second P-type material layer sidewall and the gate metal part sidewall are all covered with a passivation layer. The application introduces a hot electron blocking structure in the p-GaN gate gallium nitride power device, which can effectively prevent the movement process of hot electrons, thereby significantly reducing the bombardment damage of the hot electrons to the gate Schottky junction and improving the reliability of the device.
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Description

Technical Field

[0001] This invention relates to the technical field of gallium nitride high electron mobility transistors, and more specifically, to a gallium nitride power device with a gate hot electron blocking structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a representative of third-generation semiconductor materials, has become a core material for next-generation power electronic devices due to its excellent properties such as wide bandgap, high electron saturation drift velocity, high breakdown electric field, and high electron mobility. Among them, gallium nitride high electron mobility transistors (GaN HEMTs) have attracted much attention in the field of power electronics because of their advantages such as low on-resistance, fast switching response, and high energy conversion efficiency.

[0003] Traditional AlGaN / GaN HEMTs typically exhibit depletion-mode (normally on) devices due to the spontaneous formation of a two-dimensional electron gas (2DEG) channel at the heterojunction interface caused by polarization effects. However, in practical applications, enhancement-mode (normally off) devices better meet system safety and actuation requirements. Currently, the main technical approaches to achieving enhancement-mode GaN HEMTs include recessed gate, fluorine ion implantation, p-type gate, and cascode structures. Among these, the p-GaN gate structure, while achieving stable normally-off characteristics, maintains low gate leakage current and has become the most widely adopted solution in commercial applications.

[0004] Although p-GaN gate devices have achieved large-scale commercialization, their gate structures still face challenges in terms of reliability. When the device is under forward gate bias, electrons escaping from the 2DEG channel are accelerated in the p-GaN region, reaching their energy peak near the p-GaN surface and bombarding the gate metal, where the electric field also reaches its strongest. The combined effect of high-thermal electron bombardment and strong electric field stress accelerates the degradation of the metal / p-GaN Schottky junction, ultimately leading to gate failure.

[0005] To improve gate reliability, the academic community has currently proposed two main approaches: (i) enhancing the resistance to hot electron bombardment at the electric field peak and (ii) reducing the hot electron energy by mitigating the electric field. When using method (i), GaON, gallium oxide, or Al is introduced onto the p-GaN surface. x Ga 1-x Nitrogen (N) is used as a reinforcing layer, making it more immune to thermionic bombardment. In method (ii), an intrinsic GaN (i-GaN) layer is often epitaxially grown on the p-GaN surface to reduce the electric field. However, neither of these methods addresses the problem at its source, and thermionic bombardment remains significant.

[0006] Therefore, developing a technical solution that can suppress hot electron bombardment at the source and improve the reliability of the gate structure is an urgent technical need and has important application value. Summary of the Invention

[0007] The purpose of this application is to overcome the aforementioned shortcomings of the prior art and provide a gallium nitride power device with a gate hot electron blocking structure, thereby overcoming the technical problems existing in the prior art. This invention blocks the movement of hot electrons escaping from the 2DEG by changing the band structure of the p-GaN gate, thus preventing the occurrence of hot electron bombardment.

[0008] Another objective of this application is to provide a method for fabricating the gallium nitride power device having the above-mentioned gate hot electron blocking structure.

[0009] To achieve the above-mentioned application objectives, this application provides a gallium nitride power device with a gate hot electron blocking structure, the gallium nitride power device comprising a substrate layer, a buffer layer, a channel layer and a barrier layer arranged sequentially from bottom to top;

[0010] The barrier layer is provided with a first P-type material layer, a hot electron blocking structure layer, a second P-type material layer and a gate metal in sequence above the middle part; the barrier layer is provided with a source metal and a drain metal at both ends above the barrier layer; the hot electron blocking structure layer is composed of multiple gallium nitride material layers and sandwich structure material layers stacked alternately in a period; the sandwich structure material layer is an indium gallium nitride / aluminum gallium nitride material layer.

[0011] The upper surface of the barrier layer, the sidewalls of the source metal portion, the sidewalls of the drain metal portion, both sides of the first P-type material layer, both sides of the hot electron blocking structure layer, and both sides of the second P-type material layer are all covered with passivation layers, and both sides of the gate metal portion are covered with passivation layers.

[0012] This invention proposes a gallium nitride (GaN) power device with a gate hot electron blocking structure. A hot electron blocking structure is designed at the original p-GaN gate structure, consisting of multiple periodically stacked GaN material layers and indium gallium nitride / aluminum gallium nitride (IGGaN) material layers. This stacked structure effectively reduces the bombardment damage of hot electrons to the gate Schottky junction. Due to the introduction of this hot electron blocking structure, when a positive bias voltage is applied to the gate, the movement of hot electrons is effectively blocked, thereby significantly reducing their bombardment damage to the gate Schottky junction and improving device reliability. Furthermore, the hot electron blocking structure, through the stacking of different materials, can respectively act as an electron barrier to promote hot electron recombination or to block hot electron movement. When using a hot electron recombination structure, the photons generated by the recombination of hot electrons and holes help to expel trapped charge carriers, thereby enhancing device stability. When using an electron barrier structure, hot electrons moving towards the gate metal side are blocked by the electron barrier and form charge accumulation within the gate structure, which helps improve the device's resistance to gate breakdown.

[0013] Preferably, the plurality of cycles is 1-10 cycles, more preferably 2-3 cycles; the gallium nitride material layer is unintentionally doped and has a thickness of 10-20 nm; the thickness of the sandwich structure material layer is 3-5 nm.

[0014] More preferably, when the sandwich structure material layer is indium gallium nitride, indium atoms in In x Ga 1-x In the N-type ternary alloy, the mole fraction or atomic percentage x takes a value of 0.1~1, preferably 0.1-0.25; this is used to suppress V-type defects and modulate the quantum confinement Stark effect. When the sandwich structure material layer is aluminum gallium nitride, aluminum atoms in Al x Ga 1-x The mole fraction or atomic percentage x in the N ternary alloy is 0.1 to 1, preferably 0.1 to 0.25, in order to increase the Fermi level height of the material layer.

[0015] Preferably, the gate metal forms a Schottky contact with the second P-type material layer to form a Schottky junction; the thickness of the first P-type material layer is greater than 20 nm, preferably 40-60 nm, to ensure that the two-dimensional electron gas at its bottom is effectively depleted to achieve normal off; the thickness of the second P-type material layer is greater than 40 nm, preferably 70-80 nm, to ensure that the depletion region in the Schottky junction does not extend to the hot electron blocking structure layer.

[0016] In this invention, the source metal and the drain metal both form ohmic contacts with the barrier layer; the gate metal forms a Schottky contact with the second P-type material layer, thus forming a Schottky junction.

[0017] Preferably, the first P-type material layer and the second P-type material layer have the same composition, namely gallium nitride, aluminum nitride, or aluminum gallium nitride. The first and second P-type material layers with the same composition have the same energy band relative to the hot electron blocking structure, which facilitates the use of a lower energy band indium gallium nitride material in the sandwich structure material layer of the hot electron blocking structure, combining with the first and second P-type material layers to form a hot electron composite structure that can effectively absorb hot electrons; or the sandwich structure material layer uses a higher energy band aluminum gallium nitride material, combining with the first and second P-type material layers to form an electron barrier that can effectively block the movement of hot electrons, thereby improving the gate reliability of gallium nitride with high electron mobility.

[0018] Preferably, the gate metal, the source metal, and the drain metal are all made of one or more of titanium, gold, aluminum, nickel, tungsten, titanium nitride, and indium tin oxide. The source, gate, and drain materials are all made of metals with low resistivity to reduce internal resistance and conduction losses; these materials are also commonly used in semiconductor processing.

[0019] Preferably, the material of the passivation layer is selected from at least one of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, gallium oxynitride, aluminum oxynitride, and silicon oxynitride. The oxides, nitrides, and oxynitrides used in the passivation layer all have insulating properties that hinder diffusion and prevent current flow, thereby ensuring the stable performance of the high electron mobility transistor during operation.

[0020] Preferably, the materials of the barrier layer, the channel layer, and the buffer layer are all selected from gallium nitride, aluminum nitride, and aluminum gallium nitride; and / or, the material of the substrate layer is selected from silicon, silicon carbide, and sapphire. The barrier layer and the channel layer form a two-dimensional electron gas with high electron mobility at the contact surface through a polarization effect. The presence of a first P-type material layer above the barrier layer raises the energy band at this location, effectively depleting the two-dimensional electron gas in the area directly below, achieving normally-off characteristics. The selection of the buffer layer material needs to consider the matching factors with the substrate material. The main function of the buffer layer is to provide a high-quality growth foundation for subsequent epitaxial layers, alleviate lattice mismatch and thermal mismatch between the substrate layer and the channel layer, and reduce defect density. Choosing silicon, silicon carbide, or sapphire as the substrate considers both heat dissipation characteristics and cost issues, as well as the technical compatibility with traditional industries. These materials have been proven suitable for commercial gallium nitride epitaxial technology.

[0021] In this invention, both the source metal sidewalls and the drain metal sidewalls are covered with passivation layers. This invention does not limit the coverage height of the passivation layers on the source and drain metals. Passivation layers are also covered on both sides of the gate metal; the coverage height of these layers can be set according to actual needs and is not limited in this invention. The passivation layer coverage height is sufficient as long as proper windowing is done to expose the contact area between the device's gate metal and the source / drain metals for testing.

[0022] The present invention also provides a method for fabricating the gallium nitride power device having a gate hot electron blocking structure, comprising the following steps:

[0023] S1. Provide an epitaxial structure, wherein the epitaxial structure comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer, and a barrier layer;

[0024] S2. The first P-type material layer, the hot electron blocking structure layer, and the second P-type material layer are grown sequentially.

[0025] S3. In the pre-defined gate region of the second P-type material layer, using the gate as a hard mask, selectively etch the first P-type material layer, the hot electron blocking structure layer and the second P-type material layer outside the gate coverage;

[0026] S4. Photolithography defines the source and drain regions, ohmic metal is deposited, and ohmic contacts are formed by high-temperature annealing; then gate metal is deposited on the second P-type material layer to form Schottky contacts;

[0027] S5, deposited passivation layer.

[0028] The preparation method, manufacturing cost, and process feasibility of the above-mentioned materials are compatible with existing gate reliability processes aimed at enhancing Schottky junctions, forming a synergistic enhancement effect, thereby maximizing the overall reliability level of the gate.

[0029] In this invention, electron beam evaporation, thermal evaporation or magnetron sputtering processes are used for the deposition of ohmic contact metals for the source and drain electrodes and the deposition of gate metals.

[0030] Compared with the prior art, this application has the following technical effects:

[0031] 1. This invention proposes a gallium nitride power device with a gate hot electron blocking structure. A hot electron blocking structure is designed at the original p-GaN gate structure. This hot electron blocking structure is composed of multiple periodically stacked gallium nitride material layers and indium gallium nitride / aluminum gallium nitride material layers. This stacked structure can effectively reduce the bombardment damage of hot electrons to the gate Schottky junction.

[0032] 2. The hot electron blocking structure of the present invention can play the role of promoting the recombination of hot electrons or blocking the movement of hot electrons by stacking different materials.

[0033] 3. The technical solution of this invention is compatible with existing gate reliability enhancement processes for Schottky junctions, forming a synergistic enhancement effect, thereby maximizing the overall reliability level of the gate. Attached Figure Description

[0034] Figure 1 This is a simplified structural diagram of the gallium nitride power device with a gate hot electron blocking structure according to the present invention;

[0035] Figure 2 This is a schematic diagram of the gallium nitride power device with a gate hot electron blocking structure according to the present invention;

[0036] Figure 3 This is a top view of the gallium nitride power device with a gate hot electron blocking structure according to the present invention;

[0037] Figure 4 This is a left view of the gallium nitride power device with a gate hot electron blocking structure according to the present invention.

[0038] Figure 5 The transfer characteristic curves of the gallium nitride power device with a gate hot electron blocking structure according to the present invention are shown.

[0039] Figure 6 The output characteristic curves of the gallium nitride power device with a gate hot electron blocking structure according to the present invention are shown.

[0040] In the attached figures: 1. Substrate layer; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. Source metal; 6. Gate metal; 7. Drain metal; 8. First P-type material layer; 9. Hot electron blocking structure layer; 10. Second P-type material layer; 11. Passivation layer; 12. First i-GaN material layer; 13. First In x Ga 1-x 14. Second i-GaN material layer; 15. Second In x Ga 1-x N material layer; 16. Third i-GaN material layer. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the present invention will now be further described in conjunction with specific embodiments.

[0042] The accompanying drawings are for illustrative purposes only and represent schematic diagrams, not actual physical objects. They should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable that some well-known structures and their descriptions may be omitted in the drawings for those skilled in the art. The same or similar reference numerals in the accompanying drawings of the embodiments of the invention correspond to the same or similar components. In the description of the invention, it should be understood that if terms such as "upper," "lower," "left," and "right" indicate orientation or positional relationships based on the orientation or positional relationships shown in the drawings, they are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms describing positional relationships in the drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0043] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations. The terms “comprising,” “including,” “having,” and variations thereof mean “including, but not limited to,” unless otherwise specifically emphasized. “A plurality” means one, two, or more.

[0044] Example 1:

[0045] like Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, a gallium nitride power device with a gate hot electron blocking structure is disclosed. The gallium nitride power device includes a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 arranged sequentially from bottom to top.

[0046] like Figure 1 As shown, a first P-type material layer 8, a hot electron blocking structure layer 9, a second P-type material layer 10, and a gate metal 6 are sequentially disposed above the center of the barrier layer 4; a source metal 5 and a drain metal 7 are respectively disposed at the two ends above the barrier layer 4. The hot electron blocking structure layer is composed of two periodically alternating gallium nitride material layers and a sandwich structure material layer. The sandwich structure material layer is an indium gallium nitride material layer, in which indium atoms are arranged in the In... x Ga 1-x The mole fraction or atomic percentage x in the N ternary alloy is 0.15. The hot electron blocking structure layer, from bottom to top, includes a first i-GaN material layer 12, a first In... x Ga 1-x N-material layer 13, second i-GaN material layer 14, second In x Ga 1-x N-material layer 15, third i-GaN material layer 16.

[0047] The upper surface of the barrier layer 4, the partial sidewalls of the source metal 5, the partial sidewalls of the drain metal 7, both sides of the first P-type material layer 8, both sides of the hot electron blocking structure layer 9, and both sides of the second P-type material layer 10 are all covered with passivation layers 11. The two sides of the gate metal 6 are also partially covered with passivation layers 11. Specifically, the partial sidewalls of the source metal and the partial sidewalls of the drain metal are covered with passivation layers, and the height of the passivation layers is half the height of the source and drain metals; the two sides of the gate metal are covered with passivation layers, and the height of the passivation layers is half the height of the gate metal.

[0048] Specifically, the source metal and the drain metal both form ohmic contacts with the barrier layer, and the gate metal forms a Schottky contact with the second P-type material layer, constituting a Schottky junction. The first P-type material layer has a thickness of 50 nm to ensure effective depletion of the two-dimensional electron gas at its bottom for normally-off operation; the second P-type material layer has a thickness of 70 nm to ensure that the depletion region within the Schottky junction does not extend into the hot electron blocking structure layer. The gallium nitride material layer is unintentionally doped and has a thickness of 10 nm; the sandwich structure material layer has a thickness of 3 nm.

[0049] Specifically, the first P-type material layer and the second P-type material layer have the same composition, being one of gallium nitride, aluminum nitride, and aluminum gallium nitride. The gate metal, the source metal, and the drain metal are all made of one or more of titanium, gold, aluminum, nickel, tungsten, titanium nitride, and indium tin oxide. The passivation layer is made of at least one of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, gallium oxynitride, aluminum oxynitride, and silicon oxynitride. The barrier layer, the channel layer, and the buffer layer are all made of one of gallium nitride, aluminum nitride, and aluminum gallium nitride, and the substrate layer is made of any one of silicon, silicon carbide, and sapphire.

[0050] The method for fabricating the gallium nitride power device with a gate hot electron blocking structure includes the following steps:

[0051] S1. Provide an epitaxial structure, wherein the epitaxial structure comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer, and a barrier layer;

[0052] S2. The first P-type material layer, the hot electron blocking structure layer, and the second P-type material layer are grown sequentially.

[0053] S3. In the pre-defined gate region of the second P-type material layer, using the gate as a hard mask, selectively etch the first P-type material layer, the hot electron blocking structure layer and the second P-type material layer outside the gate coverage;

[0054] S4. Photolithography defines the source and drain regions, ohmic metal is deposited, and ohmic contacts are formed by high-temperature annealing; then gate metal is deposited on the second P-type material layer to form Schottky contacts;

[0055] S5, deposited passivation layer.

[0056] In the above methods, electron beam evaporation, thermal evaporation, or magnetron sputtering processes are used for the deposition of ohmic contact metals for the source and drain electrodes, as well as the deposition of gate metals.

[0057] Example 2:

[0058] Based on Example 1, the sandwich structure material layer is an aluminum gallium nitride material layer, where aluminum atoms are in Al x Ga 1-x The mole fraction or atomic percentage (x) of N in the ternary alloy is 0.25 to increase the Fermi level height of the material layer. Everything else is exactly the same as in Example 1.

[0059] Example 3:

[0060] Based on Example 1, the hot electron blocking structure layer consists of a gallium nitride material layer and a sandwich structure material layer stacked alternately in one period, that is, the first and third layers are gallium nitride material layers, and the middle layer is an indium gallium nitride material layer. Everything else is exactly the same as in Example 1.

[0061] Performance testing

[0062] For Example 1, the present invention provides simulation verification results based on Sentaurus TCAD software.

[0063] In the simulation model settings, the thickness of the first P-type material layer was set to 50 nm, and the thickness of the second P-type material layer was set to 70 nm; the thickness of the i-GaN material layer in both of the two periodic stacked materials was set to 10 nm. x Ga 1-x The thickness of the N material layer is set to 3 nm, and the molar composition x of In is 0.15.

[0064] like Figure 5 The figure shows the transfer characteristic curve of the device. The simulation conditions were set with the drain voltage maintained at 5V and the gate voltage scan range of 0~10V. As can be seen from the figure, the device current shows a significant upward trend with the increase of the gate voltage, exhibiting good turn-on characteristics.

[0065] like Figure 6 The figure shows the output characteristic curve of the device. The simulation conditions were set with a drain voltage scan range of 0~12V and gate voltages of 0V, 2V, 4V, 6V and 8V respectively. As can be seen from the figure, under different gate voltages, the output curve exhibits a clear linear region and a saturation region, and the drain current is effectively controlled by the gate voltage.

[0066] In summary, the simulation data shows that the device has excellent gate control capability and typical transistor current saturation characteristics, which fully demonstrates the feasibility and effectiveness of the technical solution proposed in this invention.

[0067] Based on the disclosure and teachings of the foregoing specification, those skilled in the art can make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the present invention should also fall within the protection scope of the claims of the present invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on the present invention.

Claims

1. A gallium nitride power device with a gate hot electron blocking structure, characterized in that, The gallium nitride power device includes a substrate layer, a buffer layer, a channel layer, and a barrier layer arranged sequentially from bottom to top. The barrier layer is provided with a first P-type material layer, a hot electron blocking structure layer, a second P-type material layer and a gate metal in sequence above the middle part; the barrier layer is provided with a source metal and a drain metal at both ends above the barrier layer; the hot electron blocking structure layer is composed of gallium nitride material layers and sandwich structure material layers stacked alternately in a period, and the two gallium nitride material layers and the sandwich structure material layer in the middle together form a period. The gallium nitride material layer is unintentionally doped, and the sandwich structure material layer is an indium gallium nitride material layer. The hot electron blocking refers to hot electron blocking by absorbing hot electrons. The upper surface of the barrier layer, the sidewalls of the source metal portion, the sidewalls of the drain metal portion, both sides of the first P-type material layer, both sides of the hot electron blocking structure layer, and both sides of the second P-type material layer are all covered with passivation layers, and both sides of the gate metal portion are covered with passivation layers.

2. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The number of cycles is 1-10, the thickness of the gallium nitride material layer is 10-20 nm, and the thickness of the sandwich structure material layer is 3-5 nm.

3. The gallium nitride power device with a gate hot electron blocking structure as described in claim 2, characterized in that, When the sandwich structure material layer is indium gallium nitride, indium atoms in In x Ga 1-x The mole fraction or atomic percentage x in the N ternary alloy is 0.1 to 1.

4. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The gate metal forms a Schottky contact with the second P-type material layer to form a Schottky junction; the thickness of the first P-type material layer is greater than 20 nm to ensure that the two-dimensional electron gas at its bottom is effectively depleted to achieve normal off; the thickness of the second P-type material layer is greater than 40 nm to ensure that the depletion region in the Schottky junction does not extend to the hot electron blocking structure layer.

5. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The first P-type material layer and the second P-type material layer have the same composition, which is one of gallium nitride, aluminum nitride, and aluminum gallium nitride.

6. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The gate metal, the source metal, and the drain metal are all made of one or more of the following materials: titanium, gold, aluminum, nickel, tungsten, titanium nitride, and indium tin oxide.

7. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The material of the passivation layer is selected from at least one of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, gallium oxynitride, aluminum oxynitride, and silicon oxynitride.

8. The gallium nitride power device with a gate hot electron blocking structure as described in claim 1, characterized in that, The materials of the barrier layer, the channel layer, and the buffer layer are all selected from gallium nitride, aluminum nitride, and aluminum gallium nitride; And / or, The substrate material is selected from any one of silicon, silicon carbide, and sapphire.

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