Passive electronic device

Abstract

The invention relates to a passive electronic device. The present disclosure relates to an integrated passive electronic device comprising a stack of, in order from a top surface of a support, an insulating layer, a metal layer, and a passivation layer made of an electrically insulating material, the passivation layer coating a top surface and sides of the metal layer, wherein a stress buffer layer made of another electrically insulating material different from the material of the passivation layer is formed on a top edge of the metal layer between the metal layer and the passivation layer, the stress buffer layer being in contact with the metal layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2409148 entitled “Dispositifélectronique passif”, filed on August 27, 2024, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This description generally relates to passive electronic devices, and more specifically to integrated passive electronic devices. Background Technology

[0004] Integrated passive electronic devices correspond to passive electronic components of the type of resistor, inductor, or capacitor, which are integrated individually or in groups in the same package or on the same substrate or support.

[0005] It is hoped that some aspects of such devices will be improved, at least partially. Summary of the Invention

[0006] To this end, one embodiment provides an integrated passive electronic device comprising a stack, wherein the stack, starting from the top surface of a support, comprises a support, an insulating layer, a metal layer, and a passivation layer made of an electrically insulating material, the passivation layer coating the top face and side flanks of the metal layer.

[0007] A stress buffer layer made of a different electrically insulating material than the passivation layer is formed on the top edge of the metal layer between the metal layer and the passivation layer. This stress buffer layer is in contact with the metal layer.

[0008] According to an embodiment, the metal layer is made of copper.

[0009] According to an embodiment, the passivation layer is made of a polymer material.

[0010] According to the embodiments, the passivation layer is made of polybenzoxazole, benzocyclobutene, or polyimide.

[0011] According to an embodiment, the stress buffer layer is made of silicon nitride, alumina, aluminum oxide, or aluminum nitride.

[0012] According to an embodiment, the stress buffer layer extends from the edge of the metal layer on the top and sides of the metal layer, with a width greater than 1.5 μm.

[0013] According to an embodiment, the stress buffer layer is coated on the bottom portion of the side of the metal layer.

[0014] According to an embodiment, the device comprises, between the insulating layer and the metal layer, a further insulating layer and a metal layer.

[0015] According to an embodiment, the stress buffer layer is made of a material having a tensile strength greater than the tensile strength of the material of the passivation layer.

[0016] According to an embodiment, the side portions of the metal layer comprise portions which are not coated with the stress buffer layer.

[0017] Another embodiment provides a method for manufacturing an integrated passive electronic device, comprising successively the following steps:

[0018] depositing a stress buffer layer on the stack, the stack comprising successively, starting from the top face of the support, the support, the insulating layer and the metal layer;

[0019] depositing a passivation layer made of an electrically insulating material, the passivation layer coating the stress buffer layer as well as the top face and the side portions of the metal layer,

[0020] the stress buffer layer being in contact with the metal layer and being made of another electrically insulating material different from the material of the passivation layer.

[0021] According to an embodiment, the method comprises a step of isotropic etching of the stress buffer layer so as to remove portions of the stress buffer layer formed on the side portions of the metal layer.

[0022] According to an embodiment, depositing the stress buffer layer is performed by a method of conformal deposition.

[0023] According to an embodiment, portions of the stress buffer layer positioned in alignment with the central portion of the metal layer are removed. BRIEF DESCRIPTION OF DRAWINGS

[0024] The foregoing features and advantages, as well as others, will be described in detail in the description of specific embodiments given below with reference to the accompanying drawings, in which:

[0025] Figure 1A is a partial schematic cross-sectional view illustrating an example passive electronic device;

[0026] Figure 1B is a diagram illustrating Figure 1A the mechanical stress distribution within the passive electronic device shown in

[0027] Figure 2 is a partial schematic cross-sectional view illustrating an example passive electronic device according to a first embodiment;

[0028] Figure 3 is a partial schematic cross-sectional view illustrating an example passive electronic device according to a second embodiment; and

[0029] Figure 4 is a partially schematic cross-sectional view illustrating an example passive electronic device according to a third embodiment. DETAILED DESCRIPTION

[0030] In the various figures, like features are designated by like reference numerals. In particular, structural and / or functional features common among the various embodiments can have the same reference numerals and can be arranged with identical structures, dimensions, and material properties.

[0031] For the sake of clarity, only the operations and elements that are useful in understanding the embodiments described herein are illustrated and described.

[0032] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection, without any intermediate element other than a conductor, while when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0033] In the following disclosure, unless otherwise indicated, when referring to an absolute position qualifier such as the terms "front", "back", "top", "bottom", "left", "right", etc. or a relative position qualifier such as the terms "above", "below", "higher", "lower", etc. or an orientation qualifier such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "… or so" mean within 10% or 10° and preferably within 5% or 5°.

[0035] Figure 1A is a partially schematic cross-sectional view illustrating an example passive electronic device 101.

[0036] The device 101 comprises a support 103 on which is formed a stack comprising successively, starting from the top face of the support 103, the support 103, an insulating layer 105, a metal layer 107 and a passivation layer 109.

[0037] As an example, the device 101 further comprises another metal layer 111 between the insulating layer 105 and the metal layer 107, the metal layer 111 being coated with another insulating layer 113.

[0038] As an example, the support 103 is made of a semiconductor material (for example, silicon, such as high-resistivity silicon) or a non-semiconductor material such as glass. As an example, the support substrate 103 is made of a material having an electrical resistivity greater than 200.5 KΩ.cm.

[0039] The insulating layer 105 is in contact with the top surface of the support 103, e.g. via its bottom surface. As an example, the insulating layer 105 coats the entire top surface of the support 103. As an example, the insulating layer 105 is a layer made of a dielectric material, e.g. an oxide, such as an undoped silicate glass (USG). As an example, the insulating layer 105 has a thickness ranging from 0.5 pm to 5 pm, e.g. about 1.2 pm.

[0040] As an example, the metal layer 111 is formed on the top surface of the insulating layer 105 and is in contact with the top surface of the insulating layer 105, e.g. via its bottom surface. The metal layer 111 extends over, e.g., only a portion of the surface of the insulating layer 105. As an example, the metal layer 111 is made of aluminum. As an example, the metal layer 111 has a thickness ranging from 0.5 pm to 5 pm, e.g. about 1.5 pm.

[0041] As an example, the insulating layer 113 coats the metal layer 111 as well as the portion of the insulating layer 105 around the metal layer 111 that is not coated by the metal layer 111. As an example, the insulating layer 113 is in contact with the top surface of the metal layer 111 and a portion of the top surface of the insulating layer 105, e.g. via its bottom surface. As an example, the insulating layer 113 coats the entire metal layer 111 except for a central portion of the metal layer 111 that is not coated by the insulating layer 113. As an example, the insulating layer 113 also coats the sides of the metal layer 111. The insulating layer 113 is, e.g., made of a dielectric material, e.g. an oxide, such as an undoped silicate glass (USG). As an example, the insulating layer 113 has a thickness ranging from 0.1 pm to 2 pm, e.g. about 0.8 pm.

[0042] The metal layer 107 coats the insulating layer 105. As an example, the metal layer 107 coats only a portion of the insulating layer 105. In the example shown in Fig. 1, the metal layer 107 also coats the insulating layer 113 as well as the portion of the metal layer 111 that is not coated by the insulating layer 113. Figure 1A In the example shown in Fig. 1, the metal layer 107 also coats the insulating layer 113 as well as the portion of the metal layer 111 that is not coated by the insulating layer 113. As an example, the metal layer 107 is formed in line with the metal layer 111 and its surface is at a level lower than the surface of the metal layer 111 when viewed from above. As an example, the bottom surface of the metal layer 107 is in contact with a portion of the top surface of the insulating layer 113 and the portion of the top surface of the metal layer 111 that is not coated by the insulating layer 113. As an example, the metal layer 107 has a width LI ranging from 10 pm to 275 pm, e.g. about 263 pm. The metal layer 107 is, e.g., made of copper. The metal layer 107 extends, e.g., over a height HI ranging from 3 pm to 15 pm, e.g. about 10 pm.

[0043] The passivation layer 109 coats the structure formed by the layers 105, 111, 113 and 107. More particularly, the passivation layer 109 coats the top face and the sides of the metal layer 107. The passivation layer 109 also coats the part of the top face of the insulating layer 113 that is not coated by the metal layer 107. As an example, the passivation layer 109 has a flat top face. The passivation layer 109 is for example made of an electrically insulating material. The passivation layer 109 is for example made of a polymeric material, for example made of polybenzoxazole (PBO), benzocyclobutene (BCB) and / or polyimide (PI). As an example, the passivation layer 109 extends over the metal layer 107 with a thickness ranging from 2 pm to 6 pm, for example ranging from 3 pm to 4 pm.

[0044] As an example, the device 101 corresponds to an integrated passive device (IPD) comprising a resistor, an inductor and a capacitor.

[0045] As an example, the metal layers 107 and 111 have a spiral shape when viewed from above, extending on the surface of the support 103. Thus, the assembly formed by the layers 105, 111, 113 and 107 corresponds to a coil or inductor of the IPD device 101. Alternatively, the metal layers 107 and 111 have a circular, square, rectangular shape or any other shape when viewed from above. As an alternative, the device 101 corresponds to a passive component other than an inductor, for example a resistor or a capacitor.

[0046] The support 103 supports one or more other components (not shown) formed for example in the vicinity of the inductor and electrically connected to the inductor, such as a capacitor or a resistor.

[0047] In such a device, the inventors have noticed that, in tests of the temperature reliability of the device 101, during thermal cycles, cracks appear in the passivation layer 109, starting from the top edge of the metal layer 107, through the thickness of the passivation layer 109. Such cracks can go through the thickness of the passivation layer 109, for example to reach the top face of the passivation layer 109. By the top edge of the metal layer 107, we mean the junction between the top face of the metal layer 107 and each side of the metal layer 107.

[0048] Such cracks can cause delamination of the metal layer 107 or of the passivation layer 109 and affect the reliability and lifetime of the component.

[0049] Figure 1B is a diagram illustrating Figure 1A the mechanical stress distribution undergone by the passive electronic device shown in

[0050] Figure 1B the diagram shown in Figure 1AThe mechanical stress (Stress) received and accumulated is illustrated by the dotted line. More particularly, in the graph of Figure 1 1, the curve 1 15 represents the evolution of the stress (Stress) (in megaPascal (MPa) on the y-axis) as a function of the position (Distance) along the bottom face of the passivation layer 109, in micrometers, the origin of which is located at X3, opposite the center of the metal layer 107. Figure 1B

[0051] The evolution of the stress along the bottom face of the passivation layer 109 shows that, when the layer 1 13 is in contact with the layer 105, at X1 and X1'on either side of the metal layer 107, the stress is negative and minimal, aligned with the layer 1 13. This negative stress value means that the stress received is a compressive stress.

[0052] Along the bottom face of the passivation layer 109, in the direction towards the center of the metal layer 107, the stress then increases to reach a positive maximum stress at X2 and X2' on the edges of the metal layer 107. This positive stress value means that the stress received is a tensile stress.

[0053] Along the central portion of the metal layer 107, the stress decreases again from the edges of the metal layer 107 to reach a constant value, here zero, at X3, the center of the metal layer 107. This zero value of the stress means that at these locations of the bottom face of the passivation layer 109, the layer is neither subjected to a tensile stress nor to a compressive stress.

[0054] The variations in stress are explained by the fact that the electronic device 101 is formed from several layers of different natures and materials. In particular, these layers have different thermomechanical behaviors and, more particularly, different coefficients of thermal expansion.

[0055] During the thermal cycles, the thermal expansions of the different layers accumulate with each other by generating stresses on the bottom face of the passivation layer 109. When the stress received locally is greater than the tensile strength expressed in MPa or N / mm2, the passivation layer 109 cracks by creating cracks of reference Figure 1A

[0056] Figure 2 is a partial and schematic cross-sectional view illustrating an example passive electronic device 201 according to a first embodiment. Figure 2 The device of Figure 2 comprises the same elements as the device illustrated in Figure 1, arranged in the same way, and differs from the device illustrated in Figure 1 in that it further comprises a stress buffer layer (SBL) 1 17 between the metal layer 107 and the passivation layer 109.

[0057] In the embodiment illustrated in Figure 3, the stress buffer layer 1 17 is formed on the top edge of the metal layer 107. Figure 2 In the embodiment illustrated in Figure 3, the stress buffer layer 1 17 is formed on the top edge of the metal layer 107.​​

[0058] The stress buffer layer 117 is made of a material having a tensile strength greater than the tensile strength of the material of the passivation layer 109, for example. The stress buffer layer 117 is a layer made of a different material than the passivation layer 109. As an example, the stress buffer layer 117 is made of an insulating material, for example a dielectric material. The stress buffer layer 117 is made of silicon nitride, alumina, aluminum oxide or aluminum nitride, for example.

[0059] As an example, the stress buffer layer 117 is formed on the edges of the metal layer 107 and extends on the sides and top of the metal layer 107 from the edges, with a width L2 greater than 1 pm, for example greater than 1.5 pm. The stress buffer layer 117 is in contact with the top of the metal layer 107 via its bottom. As an example, the stress buffer layer 117 is in contact with the bottom of the passivation layer 109 via its top.

[0060] As an example, the stress buffer layer 117 is formed on the stack formed by the layers 105, 111 and 113 on the top of the support 103 at the end of the formation of the metal layer 107. As an example, the stress buffer layer 117 is formed before the formation of the passivation layer 109. For example, the stress buffer layer 117 is formed on the entire wafer, i.e. on the entire top of the assembly mentioned above. As an example, the stress buffer layer 117 is deposited by an evaporation deposition method. Alternatively, the stress buffer layer 117 is deposited by a spray deposition method. Also alternatively, the stress buffer layer 117 is deposited by an atomic layer deposition (ALD) method. For example, the stress buffer layer 117 is conformally formed, with a thickness ranging from 0.2 pm to 5 pm, for example around 1 pm.

[0061] As an example, after the deposition of the stress buffer layer 117, it is locally removed, leaving it only on the edges of the metal layer 107 and in the vicinity thereof. As an example, the local removal of the stress buffer layer 117 is performed by an isotropic etching, so as to be able to remove the parts of the stress buffer layer 117 on the sides and top of the metal layer 107.

[0062] As an example, the local removal of the stress buffer layer 117 is performed by a wet etching. Alternatively, the local removal of the stress buffer layer 117 is performed by a physical etching, such as by a non-polarized plasma.

[0063] As an example, at the end of the formation of the stress buffer layer 117, the bottom of the sides of the metal layer 107 is exposed and not coated by the stress buffer layer 117. As an example, at the end of the formation of the stress buffer layer 117, a central part of the top of the metal layer 107 is exposed and not coated by the stress buffer layer 117.

[0064] As an example, although Figure 2The passivation layer 109 is not shown but, at the end of the formation of the passivation layer 109, it can be etched to form a through hole therein which opens on the top face of the metal layer 107, thus allowing the formation of a contact with the metal layer 107 using a conductive layer.

[0065] One advantage of this embodiment is that it allows thermal expansion at the interface of the absorbing layers 107 and 109 and limits the stress received by the bottom face of the passivation layer 109 aligned with the stress buffer layer 117.

[0066] Another advantage of this embodiment is that the stress received by the bottom face of the passivation layer 109 is less than the tensile strength, thus reducing the chances of cracks forming within the passivation layer 109.

[0067] Yet another advantage of this embodiment is that the stress buffer layer 117 allows the stress accumulated at the edges of the metal layer 107 to be redistributed over the entire top face of the metal layer 107.

[0068] Figure 3 is a partial schematic cross-sectional view illustrating an example passive electronic device 301 according to a second embodiment.

[0069] More particularly, Figure 3 illustrates a device 301 similar to the device 201 shown in Figure 2 The device 301 shown in Figure 3 The stress buffer layer 117 extends over the bottom part of the sides of the metal layer 107, as well as over the top face of the oxide layer 113 surrounding the metal layer.

[0070] Figure 4 is a partial schematic cross-sectional view illustrating an example passive electronic device 401 according to a third embodiment.

[0071] More particularly, Figure 4 illustrates a device 401 similar to the device 201 shown in Figure 2 The device 401 shown in Figure 4 The stress buffer layer 117 extends over the entire sides of the metal layer 107. In this embodiment, the stress buffer layer 117 also extends over the top face of the oxide layer 113, surrounding the metal layer 107. In addition, in this embodiment, the surface area over which the stress buffer layer 117 extends on the top face of the metal layer 107 is greater than the surface area described in the embodiment shown in reference Figure 2 In this embodiment, the stress buffer layer 117 extends over the entire surface of the top face of the metal layer, except for a central portion having a width ranging from 10 pm to 75 pm (for example, around 30 pm), thus allowing contact with the metal layer 107.

[0072] In this embodiment, the stress buffer layer 117 extends over the entire surface of the top face of the metal layer, except for a central portion having a width ranging from 10 pm to 75 pm (for example, around 30 pm), thus allowing contact with the metal layer 107. Figure 2In contrast to the description, the etching of the stress buffer layer can be anisotropic. Indeed, in this embodiment, the portions of the stress buffer layer 117 present on the sides of the metal layer 107 are conserved.

[0073] One advantage of the third embodiment is that it allows the stress buffer layer 117 to remain in place on the sides of the metal layer 107 and thus simplifies the step(s) of etching the stress buffer layer 117 after the deposition of the stress buffer layer 117.

[0074] Many applications can benefit from the advantages offered by the electronic device 201 and this device 201 can thus be integrated in various types of components.

[0075] As an example, the device 201 can be integrated in a component dedicated to the automotive industry. The electrification of vehicles leads to a significant increase in the number of electronic components present in vehicles. As an example, the device 201 can be integrated in a component dedicated to the industry. In particular, this component is intended to be used for the development of green energy or electrification infrastructures, for example, charging stations or the collection of solar energy. This component can also be used in the field of the Internet of Things or in the field of smart homes. For example, this component is intended to be implemented in a circuit for supplying power to equipment. This component can also be used to implement computer systems in the cloud, 5G RF communication networks, data centers and servers.

[0076] As an example, the device 201 can be integrated in a component intended to be used in a personal electronic device (for example to implement RF communication in a 5G communication system) or more generally in any connected component. This component is for example a mobile phone, a smartphone or is part of the Internet of Things. For example, this component is connected via 5G or via WiFi or via broadband communication. For example, this component comprises a high-speed interface, for example with advanced filtering and electrostatic discharge protection.

[0077] As an example, the device 201 can be integrated in a component intended to be used in communication equipment or in computers and peripherals. For example, this component is used in 5G infrastructures and in dedicated data centers. This component can also be used in satellites, for example comprising integrated passive components for RF applications.

[0078] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these embodiments can be combined and that other variants will readily suggest themselves to the person skilled in the art. In particular, while the stack formed by the layers 103, 105, 107 and 109 corresponds to a stack of capacitors herein, it can be provided that Figures 2 to 4The stress buffer layer 117 described in the embodiments above can be formed in other types of passive components, such as inductors (or coils) or resistors. In addition, such a stress buffer layer can more generally be formed at the interface between a metal layer (for example, made of copper) and a passivation layer (for example, made of a polymeric material, for example, PBO, BCB or polyimide), in order to reduce the stresses formed on the edges of the copper layer.

[0079] Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the capabilities of a person skilled in the art.

[0080] An integrated passive electronic device (201; 301; 401) is generalized as comprising a stack, in order from the top face of a support, the support, an insulating layer (113), a metal layer (107) and a passivation layer (109) made of an electrically insulating material, the passivation layer (109) coating the top face and the sides of the metal layer (107), wherein on the top edge of the metal layer (107) between the metal layer (107) and the passivation layer (109) is formed a stress buffer layer (117) made of another electrically insulating material different from that of the passivation layer (109), the stress buffer layer (117) being in contact with the metal layer (107).

[0081] The metal layer (107) is made of copper.

[0082] The passivation layer (109) is made of a polymeric material.

[0083] The passivation layer (109) is made of polybenzoxazole, benzocyclobutene or polyimide.

[0084] The stress buffer layer (117) is made of silicon nitride, alumina, aluminum oxide or aluminum nitride.

[0085] The stress buffer layer (117) extends over the top face and the sides of the metal layer (107), starting from the edges of the metal layer, with a width (L2) greater than 1.5 pm.

[0086] The stress buffer layer (117) coats a bottom portion of the sides of the metal layer (107).

[0087] The device comprises, between the insulating layer (105) and the metal layer (109), a further insulating layer (113) and a metal layer (111).

[0088] The stress buffer layer (117) is made of a material having a tensile strength greater than that of the material of the passivation layer (109).

[0089] The side portions of the metal layer (107) comprise portions which are not coated with the stress buffer layer (117).

[0090] A method for manufacturing an integrated passive electronic device (201; 301; 401) is summarized as comprising, in succession: depositing a stress buffer layer (117) on a stack comprising, in succession, starting from a top face of a support (103), the support (103), an insulating layer (113) and a metal layer (107); depositing a passivation layer (109) made of an electrically insulating material, the passivation layer (109) coating the stress buffer layer (117) and the top face and the side portions of the metal layer (107), the stress buffer layer (117) being in contact with the metal layer (107) and being made of another electrically insulating material different from the material of the passivation layer (109).

[0091] The method further comprises a step of isotropic etching of the stress buffer layer (117) so as to remove portions of the stress buffer layer (117) formed on the side portions of the metal layer (107).

[0092] The depositing of the stress buffer layer (117) is performed by a method of conformal deposition.

[0093] The portions of the stress buffer layer (117) positioned in alignment with the central portion of the metal layer (107) are removed.

[0094] The various embodiments described above can be combined to provide further embodiments. Aspects of an embodiment can be modified, if necessary to employ concepts of various patents, applications, and publications to provide yet further embodiments.

[0095] These and other changes can be made to the embodiments in light of the above Detailed Description. The terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the Specification and the claims are to include all possible embodiments and their equivalents. Accordingly, the claims are not limited to the embodiments described herein.

Claims

1. An integrated passive electronic device, comprising: a stack that is, in order from a top surface of a support, the support, an insulating layer, a metal layer, and a passivation layer of an electrically insulating material, the passivation layer coating a top surface and sides of the metal layer, and a stress buffer layer of another electrically insulating material having a tensile strength greater than a tensile strength of a material of the passivation layer, the stress buffer layer formed on a top edge of the metal layer between the metal layer and the passivation layer, the stress buffer layer in contact with the metal layer.

2. The device of claim 1, wherein the metal layer is of copper.

3. The device of claim 1, wherein the passivation layer is of a polymeric material.

4. The device of claim 1, wherein the passivation layer is of polybenzoxazole, benzocyclobutene, or polyimide.

5. The device of claim 1, wherein the stress buffer layer is of silicon nitride, alumina, aluminum oxide, or aluminum nitride.

6. The device of claim 1, wherein the stress buffer layer extends over the top surface and sides of the metal layer from an edge of the metal layer, a width greater than 1.5 pm.

7. The device of claim 1, wherein the stress buffer layer coats a bottom portion of the sides of the metal layer.

8. The device of claim 1, further comprising additional insulating layers and additional metal layers between the insulating layer and the metal layer.

9. The device of claim 1, wherein the sides of the metal layer include portions that are not coated with the stress buffer layer.

10. A method for manufacturing an integrated passive electronic device, comprising: depositing a stress buffer layer on a stack, the stack comprising a support, an insulating layer on a top surface of the support, and a metal layer on the insulating layer, and the stress buffer layer in contact with the metal layer; and depositing a passivation layer of an electrically insulating material, the passivation layer coating the stress buffer layer and a top surface and sides of the metal layer, the stress buffer layer of another electrically insulating material having a tensile strength greater than a tensile strength of a material of the passivation layer.

11. The method of claim 10, further comprising isotropically etching the stress buffer layer to remove portions of the stress buffer layer on the sides of the metal layer.

12. The method of claim 10, wherein depositing the stress buffer layer is conformal deposition.

13. The method of claim 10, further comprising removing portions of the stress buffer layer positioned in alignment with a central portion of the metal layer.

14. An electronic device, comprising: an insulating layer; a metal layer on the insulating layer, the metal layer having a top surface and sides, the sides connected to the top surface at edges of the metal layer; a stress buffer layer covering the edges of the metal layer; and a passivation layer covering the insulating layer, the metal layer, and the stress buffer layer, and a tensile strength of the stress buffer layer greater than a tensile strength of the passivation layer.

15. The electronic device of claim 14, wherein the sides of the metal layer are covered by the stress buffer layer.

16. The electronic device of claim 14, wherein a bottom portion of each side of the metal layer is covered by the stress buffer layer. ​ 17. The electronic device of claim 14, wherein the stress buffer layer is made of silicon nitride, alumina, aluminum oxide, or aluminum nitride.

18. The electronic device of claim 14, further comprising: another metal layer between the metal layer and the insulating layer; and another insulating layer between the metal layer and the another metal layer, the another insulating layer covering side portions of the another metal layer and portions of the insulating layer not covered by the metal layer, and the another insulating layer being between the stress buffer layer and the insulating layer.

19. The electronic device of claim 18, wherein the another insulating layer has a first opening into which the metal layer protrudes and is electrically coupled to the another metal layer, the stress buffer layer has a second opening exposing a portion of a top surface of the metal layer, and the first opening is aligned with the second opening.

20. The electronic device of claim 14, wherein the stress buffer layer extends a width of greater than 1 pm from an edge of the top surface of the metal layer.

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