Display panel, method for manufacturing the same, and electronic device including the same

Abstract

A display panel according to an embodiment, a method for manufacturing the same, and an electronic device including the same are provided. The display panel may include a base layer, a circuit layer, and a display element layer. The circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a capacitor including a first metal layer and a second metal layer, and a transistor. The first metal layer may include a first sub-metal layer and a second sub-metal layer, and the second metal layer may include a third sub-metal layer and a fourth sub-metal layer. The second sub-metal layer may include: a first portion; and a second portion extending from the first portion and disposed within the trench of the insulating layer. The fourth sub-metal layer may include: a third portion; and a fourth portion extending from the third portion and disposed within the trench of the insulating layer. In a plane, the second portion and the fourth portion may each extend in one direction perpendicular to the thickness direction.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0117336, filed on August 30, 2024, and Korean Patent Application No. 10-2024-0193797, filed on December 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display panel including a capacitor, a method for manufacturing the display panel, and an electronic device including the display panel. Background Technology

[0003] Electronic devices that provide images to users, such as smartphones, laptops, navigation devices, and smart TVs, include display devices for displaying images. Electronic devices such as augmented reality devices, virtual reality devices, and video projection devices include display devices that enable high-resolution image display. Research is underway to improve the display quality of display devices that enable high-resolution image display. Summary of the Invention

[0004] This disclosure provides a display panel exhibiting excellent reliability and superior display quality, as well as an electronic device including the display panel.

[0005] This disclosure also provides a method for manufacturing a display panel that exhibits excellent processability.

[0006] Embodiments of this disclosure provide a display panel including a substrate layer, a circuit layer disposed on the substrate layer, and a display element layer disposed on the circuit layer. The circuit layer includes a first insulating layer, a second insulating layer, a third insulating layer, a capacitor comprising a first metal layer and a second metal layer, and a transistor. A first trench is defined in the first insulating layer. A second insulating layer is disposed on the first insulating layer. The second trench and the third trench are defined in the second insulating layer and spaced apart from each other in a first direction perpendicular to the thickness direction. The third insulating layer is disposed on the second insulating layer. A fourth trench is defined in the third insulating layer. The first trench and the second trench are aligned with each other. Similarly, the third trench and the fourth trench are aligned with each other. The first metal layer includes a first sub-metal layer and a second sub-metal layer. The second sub-metal layer is at least partially disposed on the first sub-metal layer. The second sub-metal layer includes: a first portion separated from the first sub-metal layer, with the first insulating layer and the second insulating layer disposed between the first portion and the first sub-metal layer; and a second portion extending from the first portion and disposed within the first trench and the second trench. The second metal layer includes a third sub-metal layer disposed on the first sub-metal layer and a fourth sub-metal layer disposed at least partially on the third sub-metal layer. The fourth sub-metal layer includes: a third portion separated from the third sub-metal layer, with a second insulating layer and a third insulating layer disposed between the third portion and the third sub-metal layer; and a fourth portion extending from the third portion and disposed within the third trench and the fourth trench. In a plane, each of the second and fourth portions extends in a second direction perpendicular to the thickness direction and orthogonal to the first direction.

[0007] In one embodiment, a second portion of the second sub-metal layer may be disposed between the first sub-metal layer and the first portion of the second sub-metal layer. The second portion of the second sub-metal layer can electrically connect the first sub-metal layer to the first portion of the second sub-metal layer.

[0008] In one embodiment, a fourth portion of the fourth sub-metal layer may be disposed between the third sub-metal layer and the third portion of the fourth sub-metal layer. The fourth portion of the fourth sub-metal layer can electrically connect the third sub-metal layer to the third portion of the fourth sub-metal layer.

[0009] In an embodiment, the first portion of the second sub-metal layer may be disposed on a different layer from the third portion of the fourth sub-metal layer.

[0010] In an embodiment, the first portion of the second sub-metal layer and the fourth portion of the fourth sub-metal layer may be separated from each other in a first direction, and a region of the third insulating layer is disposed between the first portion and the fourth portion.

[0011] In an embodiment, the second portion of the second sub-metal layer and the third sub-metal layer can be separated from each other in a first direction, and a region of the second insulating layer is disposed between the third sub-metal layer and the second portion.

[0012] In an embodiment, each of the first to third insulating layers may have a single-layer structure.

[0013] In an embodiment, the first insulating layer may have a single-layer structure, and the first insulating layer may be directly disposed between the first sub-metal layer and the third sub-metal layer.

[0014] In an embodiment, the second insulating layer may have a single-layer structure, and the second insulating layer may be directly disposed between the third sub-metal layer and the first portion of the second sub-metal layer.

[0015] In an embodiment, the third insulating layer may have a single-layer structure, and the third insulating layer may be directly disposed between the first portion of the second sub-metal layer and the third portion of the fourth sub-metal layer.

[0016] In one embodiment, the transistor may include an oxide semiconductor pattern and a gate disposed on the oxide semiconductor pattern.

[0017] In one embodiment, the gate electrode may be formed from a first sub-metal layer.

[0018] In an embodiment, the gate electrode, the first portion of the second sub-metal layer, the third sub-metal layer, and the third portion of the fourth sub-metal layer may be stacked on top of each other.

[0019] In an embodiment, the display element layer may include a light-emitting element and a pixel defining film, with an emission opening defined in the pixel defining film. The light-emitting element may include a first electrode, a second electrode, and an emission layer. The first electrode has at least a portion in the emission opening, the second electrode is disposed above the first electrode, and the emission layer is disposed between the first electrode and the second electrode.

[0020] In an embodiment of the inventive concept, a method for manufacturing a display panel includes the following steps: preparing a substrate layer; forming a circuit layer on the substrate layer, the circuit layer including a first insulating layer, a second insulating layer, a third insulating layer, a capacitor comprising a first metal layer and a second metal layer, and a transistor. The method further includes: forming a display element layer on the circuit layer. The first metal layer of the capacitor includes a first sub-metal layer and a second sub-metal layer at least partially disposed on the first sub-metal layer, and the second metal layer includes a third sub-metal layer disposed on the first sub-metal layer and a fourth sub-metal layer at least partially disposed on the third sub-metal layer. The step of forming the circuit layer includes: forming a first sub-metal layer on the substrate layer; forming a preliminary first insulating layer on the first sub-metal layer; forming a third sub-metal layer on the preliminary first insulating layer; forming a first insulating layer defining a first trench, and forming a preliminary second insulating layer on the third sub-metal layer having a second trench aligned with the first trench. The step of forming the circuit layer may further include: forming a second sub-metal layer on a preliminary second insulating layer, including filling a first trench and a second trench with a material of the second sub-metal layer; forming a second insulating layer, including setting a third trench by the preliminary second insulating layer, and forming a third insulating layer on the second sub-metal layer in which a fourth trench is defined; and forming a fourth sub-metal layer on the third insulating layer, including filling the third trench and the fourth trench with a material of the fourth sub-metal layer. The second trench and the third trench are spaced apart from each other in a first direction perpendicular to the thickness direction. The second sub-metal layer includes a first portion and a second portion. The first portion of the second sub-metal layer is configured to be separated from the first sub-metal layer, and a first insulating layer and a second insulating layer are disposed between the first portion of the second sub-metal layer and the first sub-metal layer. The second portion of the second sub-metal layer is configured to extend from the first portion of the second metal layer and be disposed within the first trench and the second trench. The fourth sub-metal layer includes: a third portion, separated from the third sub-metal layer, wherein a second insulating layer and a third insulating layer are disposed between the third portion and the third sub-metal layer; and a fourth portion, extending from the third portion of the fourth sub-metal layer and disposed within the third trench and the fourth trench. In a plane, each of the second and fourth portions extends in a second direction perpendicular to the thickness direction and orthogonal to the first direction.

[0021] In an embodiment, each of the first to third insulating layers may have a single-layer structure.

[0022] In an embodiment, the first portion of the second sub-metal layer may be disposed on a different layer from the third portion of the fourth sub-metal layer.

[0023] In embodiments of the inventive concept, the electronic device includes a display panel for providing images and a processor. The display panel includes a substrate layer, a circuit layer disposed on the substrate layer, and a display element layer disposed on the circuit layer. The circuit layer includes a first insulating layer to a third insulating layer, a capacitor comprising a first metal layer and a second metal layer, and a transistor. A first trench is defined in the first insulating layer. A second insulating layer is disposed on the first insulating layer, and a second trench and a third trench, spaced apart from each other in a first direction perpendicular to the thickness direction, are defined in the second insulating layer. A third insulating layer is disposed on the second insulating layer, and a fourth trench is defined in the third insulating layer. The first trench is aligned with the second trench, and the third trench is aligned with the fourth trench. The first metal layer includes a first sub-metal layer and a second sub-metal layer at least partially disposed on the first sub-metal layer. The second sub-metal layer includes: a first portion spaced apart from the first sub-metal layer, with the first insulating layer and the second insulating layer disposed between the first portion and the first sub-metal layer; and a second portion extending from the first portion and disposed within the first trench and the second trench. The second metal layer includes a third sub-metal layer disposed on top of the first sub-metal layer and a fourth sub-metal layer disposed at least partially on the third sub-metal layer. The fourth sub-metal layer includes: a third portion spaced apart from the third sub-metal layer, with a second insulating layer and a third insulating layer disposed between the third portion and the third sub-metal layer; and a fourth portion extending from the third portion and disposed within the third trench and the fourth trench. In a plane, each of the second and fourth portions extends in a second direction perpendicular to the thickness direction and orthogonal to the first direction.

[0024] In an embodiment, the first portion of the second sub-metal layer may be disposed on a different layer from the third portion of the fourth sub-metal layer.

[0025] In an embodiment, a second portion of the second sub-metal layer may be disposed between the first sub-metal layer and the first portion of the second sub-metal layer, and the first sub-metal layer may be electrically connected to the first portion of the second sub-metal layer.

[0026] In an embodiment, the fourth portion of the fourth sub-metal layer may be disposed between the third sub-metal layer and the third portion of the fourth sub-metal layer, and the third sub-metal layer may be electrically connected to the third portion of the fourth sub-metal layer.

[0027] In an embodiment, the first portion of the second sub-metal layer may be disposed on a different layer from the third portion of the fourth sub-metal layer.

[0028] In an embodiment, in a first direction, a first portion of the second sub-metal layer and a fourth portion of the fourth sub-metal layer may be spaced apart from each other, and a region of the third insulating layer is disposed between the first portion and the fourth portion.

[0029] In an embodiment, the second portion of the second sub-metal layer and the third sub-metal layer may be spaced apart from each other in a first direction, and a region of the second insulating layer is disposed between the third sub-metal layer and the second portion.

[0030] In an embodiment, each of the first to third insulating layers may have a single-layer structure. Attached Figure Description

[0031] The accompanying drawings are included to provide a further understanding of aspects of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0032] Figure 1 This is a perspective view of an electronic device according to aspects of this disclosure.

[0033] Figure 2 This is an exploded perspective view of an electronic device according to aspects of this disclosure.

[0034] Figure 3 This is a block diagram of an electronic device according to aspects of this disclosure.

[0035] Figure 4 This is a view showing an electronic device according to various aspects of this disclosure.

[0036] Figure 5 This illustrates aspects related to this disclosure. Figure 2 A sectional view of the portion corresponding to line I-I' in the diagram.

[0037] Figure 6 This is a plan view showing a portion of an electronic device according to aspects of this disclosure.

[0038] Figure 7 This is a perspective view of an electronic device according to aspects of this disclosure.

[0039] Figure 8 This is a cross-sectional view showing a portion of the display module according to aspects of this disclosure.

[0040] Figure 9 This illustrates aspects according to this disclosure. Figure 8 An enlarged sectional view of region XX' in the diagram.

[0041] Figure 10 This is a cross-sectional view showing a capacitor according to aspects of this disclosure.

[0042] Figure 11 This is a perspective view showing a capacitor according to aspects of this disclosure.

[0043] Figure 12This is a perspective view showing the insulating layer defining the trench according to an aspect of this disclosure.

[0044] Figure 13A This is a perspective view showing the first metal layer according to aspects of this disclosure.

[0045] Figure 13B This is a perspective view showing the second metal layer according to aspects of this disclosure.

[0046] Figure 14 This is a schematic diagram showing a capacitor connected through a contact hole.

[0047] Figure 15 This illustrates aspects according to this disclosure. Figure 8 An enlarged sectional view of region XX' in the diagram.

[0048] Figure 16A This is a flowchart illustrating a method for manufacturing a display panel according to aspects of this disclosure.

[0049] Figure 16B This is a flowchart illustrating a method for manufacturing a display panel according to aspects of this disclosure.

[0050] Figure 17 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure.

[0051] Figure 18 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure.

[0052] Figure 19 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure.

[0053] Figure 20 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure.

[0054] Figure 21 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure.

[0055] Figure 22 This is a schematic diagram illustrating the steps of manufacturing a display panel according to aspects of this disclosure. Detailed Implementation

[0056] This disclosure may be modified in various forms, and specific embodiments of this disclosure will be shown in the accompanying drawings and described in detail herein. This disclosure should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0057] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on" another element, "connected to" or "integrated into" another element, the element may be directly disposed on, directly connected to or directly integrated into the other element, or other elements may be disposed therein.

[0058] The same reference numerals or symbols always refer to the same elements. In the drawings, the thickness, ratios, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. The term "and / or" includes one or more combinations that can be defined by the related elements.

[0059] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, the elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the inventive concept, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion. Similarly, a second element, component, region, layer, or portion may be referred to as a first element, component, region, layer, or portion. In this specification, unless the context clearly indicates otherwise, the singular expressions “a,” “an,” and “the” are intended to also include the plural forms.

[0060] Additionally, the terms "below," "under," "below," "above," "over (covering)," and "on top" can be used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0061] It will also be understood that when the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0063] In the following description, a display panel and an electronic device including the display panel according to aspects of the present disclosure will be described with reference to the accompanying drawings. Figure 1This is a perspective view showing an electronic device EA according to aspects of this disclosure. Figure 2 This is an exploded perspective view of an electronic device EA according to aspects of this disclosure. Figure 3 This is a block diagram of an electronic device EA according to aspects of this disclosure.

[0064] according to Figure 1 The electronic device EA in the embodiments shown can be a device that is activated in response to an electrical signal. For example, the electronic device EA can be a personal computer, a laptop computer, a personal digital assistant, a game console, a portable electronic device, a television, a monitor, an outdoor billboard, a vehicle navigation device, or a wearable device, but the embodiments are not limited thereto. Figure 1 An example of a smartphone as an electronic device (EA) is shown.

[0065] An electronic device EA may include a display surface ES defined by a first direction axis DR1 and a second direction axis DR2 orthogonal to the first direction axis DR1. The electronic device EA can provide an image IM to a user through the display surface ES. The electronic device EA can display the image IM on the display surface ES in a direction oriented towards the third direction axis DR3. The image IM can be displayed on the display surface ES parallel to each of the first direction axis DR1 and the second direction axis DR2. The image IM may include not only moving images but also still images.

[0066] The directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 used herein are relative concepts and can be changed to other directions. The directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 can also be referred to as the first direction to the third direction and can be represented by the same reference numerals or symbols.

[0067] In this disclosure, the first direction axis DR1 and the second direction axis DR2 intersect each other perpendicularly, and the third direction axis DR3 can be the normal direction of the plane defined by the first direction axis DR1 and the second direction axis DR2. The thickness direction of the electronic device EA can be a direction parallel to the third direction axis DR3. The thickness direction of the electronic device EA and the third direction axis DR3 can be represented by the same reference numerals or symbols. The front surface (or top surface) and the rear surface (or bottom surface) can be opposite each other relative to the third direction axis DR3, and the normal direction of each of the front surface (or top surface) and the rear surface (or bottom surface) can be parallel to the third direction axis DR3. The front surface (or top surface) indicates the surface adjacent to the display surface ES, and the rear surface (or bottom surface) indicates the surface spaced apart from the display surface ES. The upper side indicates the direction closer to the display surface ES, and the lower side indicates the direction farther away from the display surface ES.

[0068] As used herein, a cross-section indicates a surface parallel to the thickness direction DR3. A plane represents a surface perpendicular to the thickness direction DR3 and parallel to the plane defined by the first directional axis DR1 and the second directional axis DR2.

[0069] As used herein, when a component is stacked with another component, it means that the components are stacked on top of each other on a plane. Furthermore, when a component is stacked with another component, it is not limited to the case where the component and the other component have the same surface area and the same shape, but also includes the case where the component and the other component have different surface areas and / or different shapes.

[0070] An electronic device (EA) can sense external inputs applied from the outside. External inputs can include various types of inputs provided from outside the electronic device (EA). For example, external inputs can include not only touch through a part of the body (such as a user's hand), but also external inputs applied by approaching or being at a certain distance from the electronic device (EA) (e.g., hovering). In addition, external inputs can include various types such as force, pressure, temperature, and light.

[0071] The display surface ES may include a display area DA and a non-display area NDA. The display surface ES may also include a sub-region MH. Unlike the illustrated embodiment, the sub-region MH may be omitted.

[0072] The display area DA can be an area that is activated in response to an electrical signal. The display area DA can be an area in which an image IM is displayed and various types of external inputs can be sensed.

[0073] The display area DA may include a plane defined by a first direction axis DR1 and a second direction axis DR2. The display area DA may include a curved surface that bends from at least one side of the plane defined by the first direction axis DR1 and the second direction axis DR2. Figure 1 In the illustrated embodiment, the electronic device EA includes two curved surfaces that bend from opposite sides of a plane defined by a first direction axis DR1 and a second direction axis DR2, respectively. However, this is illustrative, and the shape of the display area DA is not limited thereto. However, the display area DA may only include the plane defined by the first direction axis DR1 and the second direction axis DR2, or alternatively, the display area DA may include two or more curved surfaces that bend from at least two sides of the plane defined by the first direction axis DR1 and the second direction axis DR2, for example, four curved surfaces that bend from four sides.

[0074] The electronic device EA according to an embodiment can be flexible. The term "flexible" refers to the property of being able to bend, and can include any implementation from a fully foldable structure to a structure that can be bent at the nanometer level. For example, but not limited to, the electronic device EA can be a rigid device. Alternatively, the electronic device EA can be a fully foldable device.

[0075] The non-display area NDA can have a certain color. The non-display area NDA can be an area adjacent to the display area DA. The non-display area NDA can surround the display area DA. Therefore, the shape of the display area DA can be substantially defined by the non-display area NDA. However, this is shown as an example, and the non-display area NDA can be arranged to be adjacent only to one side of the display area DA, or it can be omitted. The display area DA can be arranged in various shapes and is not limited to any one embodiment.

[0076] Sub-region MH can sense external objects received through display surface ES, or provide sound signals such as voice signals to the outside through display surface ES. Light signals such as visible light or infrared light can travel to sub-region MH.

[0077] The sub-region MH can be located within the display area DA. However, this is illustrative, and the arrangement of the sub-region MH is not limited to any one embodiment. For example, the sub-region MH can be surrounded by a non-display area NDA, or alternatively, it can be surrounded by both the display area DA and the non-display area NDA. Figure 1 A subregion MH is shown, but multiple subregions MH can be set.

[0078] Various second electronic modules (ELM) (see) Figure 2 ) can be arranged to correspond to sub-regions MH. For example, the second electronic module ELM (see Figure 2 The electronic device EA may include at least one of a camera, a speaker, a light detection sensor, and a thermal detection sensor. The electronic device EA may include a second electronic module ELM (see...). Figure 2 The second electronic module (ELM) uses visible light passing through the sub-region MH to transform the external image, or uses infrared light to determine the proximity of external objects. (See Second Electronic Module ELM) Figure 2 It may include multiple components and is not limited to any one embodiment.

[0079] Reference Figure 2The electronic device EA may include a display device DD and a housing HAU. The electronic device EA may also include a second electronic module ELM. The display device DD may include a display module DM and a window member CW disposed on the display module DM. The display module DM may be housed within the housing HAU. A module region DM-MH may be defined within the display module DM, and the second electronic module ELM may be arranged to correspond to the module region DM-MH. Specifically, the module region DM-MH may be defined within the display panel DP included by the display module DM (see...). Figure 8 The display panel DP will be described in more detail later (see [link]). Figure 8 ).

[0080] exist Figure 1 and Figure 2 In the illustrated electronic device EA, the window component CW and the housing HAU can be joined to form the appearance of the electronic device EA. The housing HAU can be disposed below the display module DM. The housing HAU can include a material with relatively high rigidity. For example, the housing HAU can include multiple frames and / or plates, each of which can include glass, plastic, or metal. The housing HAU provides a receiving space. The second electronic module ELM, the display module DM, etc., can be housed in the receiving space and protected from external impacts.

[0081] The display module DM can be activated in response to an electrical signal. The display module DM can be activated to display the electronic device EA in the display area DA (see...). Figure 1 The image IM is displayed in (see) Figure 1 The effective area DM-AA, the peripheral area DM-NAA, and the module area DM-MH can be limited to the display module DM.

[0082] The active region DM-AA can be a region activated in response to an electrical signal. Pixels can be disposed within the active region DM-AA. Pixels may include transistors TR, as described later (see [link to documentation]). Figure 8 ) and light-emitting elements (ED) (see Figure 8 The peripheral region DM-NAA can be a region adjacent to at least one side of the active region DM-AA. Circuits, wires, etc., used to drive the active region DM-AA can be set in the peripheral region DM-NAA.

[0083] Module area DM-MH can correspond to Figure 1 The sub-region MH is shown in the diagram. Optical signals, such as visible light or infrared light, can travel to the module region DM-MH. The module region DM-MH can be located within the active region DM-AA. Optionally, the module region DM-MH can be surrounded by the peripheral region DM-NAA or by both the active region DM-AA and the peripheral region DM-NAA.

[0084] The second electronic module (ELM) can be an electronic component that outputs or receives optical signals. For example, the second electronic module (ELM) may include a camera module and a photoelectric sensor. The camera module can convert external images through the module area DM-MH. The photoelectric sensor can convert the light incident on it, and the incident light can be infrared light. The photoelectric sensor can receive infrared light reflected from an external object and sense the proximity of the external object. The photoelectric sensor can be used as a proximity sensor.

[0085] Although not shown, the display device DD may further include an optical layer disposed between the display module DM and the window member CW. The optical layer can be formed on the display module DM using a continuous process. The optical layer may include a polarizer or a color filter layer. For example, the optical layer may include at least one of a retarder, a polarizer, a polarizing film, and a polarizing filter. Optionally, the optical layer may include a plurality of color filters arranged in a certain arrangement. For example, the color filters may be arranged considering the emission color of the pixels. Additionally, the optical layer may also include a black matrix adjacent to the color filters.

[0086] The window component CW may include a transmissive region TA and a border region BZA. The transmissive region TA may overlap with at least a portion of the effective area DM-AA of the display module DM. The transmissive region TA may be an optically transparent region. An image IM (see [link to image IM]) can be provided to the user through the transmissive region TA. Figure 1 ).

[0087] The border region BZA can be a region with relatively low light transmittance compared to the transmission region TA. The border region BZA can define the shape of the transmission region TA. The border region BZA can be adjacent to and surround the transmission region TA.

[0088] The border area BZA may have a specific color. The border area BZA may cover the peripheral area DM-NAA of the display module DM to prevent the peripheral area DM-NAA from being visible from the outside. However, the embodiments are not limited to the embodiments shown, and the border area BZA may be configured to be adjacent only to one side of the transmissive area TA, or at least a portion of it may be omitted.

[0089] Reference Figure 3 The electronic device EA according to the embodiment may include a display module DM, a processor 12, a memory 13 and a power module 14.

[0090] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. Power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module into a usable form and provides the form of power required for the operation of electronic device EA (operating wattage, voltage, ampere, phase, etc.).

[0091] The memory 13 can store the data information required for the operation of the processor 12 or the display module DM. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be sent to the display module DM, and the display module DM can process the received signals and output image information through the display screen.

[0092] In some implementations, at least one of the components of the electronic device EA may be included in the display device DD (see... Figure 2 In addition, among the components of the electronic device EA, some of the modules that are functionally included in one module may be included in the display device DD (see...). Figure 2 In ), and other modules can be integrated with the display device DD (see Figure 2 Separate settings. For example, but not limited to, display device DD (see...) Figure 2 The display device DD may include a display module DM, a processor 12, and a memory 13. The power module 14 may not be located in the display device DD (see [link to display module DD]). Figure 2 Instead of being located in the EA, it is set in the electronic device EA as a different type of device.

[0093] Figure 4 This is a schematic diagram illustrating an electronic device according to aspects of this disclosure. (Refer to...) Figure 4 , including display device DD (see Figure 2 The electronic devices of 10_1a can include not only electronic devices for displaying images (e.g., smartphones 10_1a, tablet computers (PCs) 10_1b, laptop computers 10_1c, TVs 10_1d, and monitors for desktop computers 10_1e), but can also include devices containing a display module DM (see Figure 3 Wearable electronic devices (e.g., smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and including display modules DM (see...) Figure 3 Vehicle electronic equipment 10_3 (e.g., vehicle dashboard, central dashboard, central information display (CID) set on the instrument panel, and interior mirror display).

[0094] Figure 5 It is shown that... Figure 2A sectional view of the portion corresponding to line I-I' in the diagram. Figure 5 It may be a schematic cross-sectional view showing the components of the display module DM.

[0095] Reference Figure 5 The display module DM may include a display panel DP and an input sensing unit TP disposed on the display panel DP. The display panel DP may be a component that substantially generates an image.

[0096] The display panel DP may include a stack of a substrate layer BS, a circuit layer DP-CL, a display element layer DP-EL, and a package layer TFE. As not shown in the illustrated embodiment, a separate component layer may also be disposed between two adjacent layers among the substrate layer BS, circuit layer DP-CL, display element layer DP-EL, and package layer TFE.

[0097] The substrate layer BS can provide a substrate surface on which the circuit layer DP-CL is disposed. The substrate layer BS can be a flexible substrate that can be bent, folded, rolled, etc. The substrate layer BS can be a glass substrate, a metal substrate, a polymer substrate, etc. However, the implementation is not limited to these, and the substrate layer BS can include inorganic layers, organic layers, or composite material layers.

[0098] The circuit layer DP-CL can be disposed on the substrate layer BS. The circuit layer DP-CL may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The display element layer DP-EL can be disposed on the circuit layer DP-CL. The display element layer DP-EL may include light-emitting elements ED (described later) (see [link to documentation]). Figure 8 For example, light-emitting elements (EDs) (see...) Figure 8 This can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots or quantum rods, etc. For example, light-emitting elements (EDs) (see...) Figure 8 This can include microLEDs or nanoLEDs.

[0099] The encapsulation layer TFE can be disposed on the display element layer DP-EL. The encapsulation layer TFE can protect the display element layer DP-EL from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may include at least one inorganic layer. For example, the encapsulation layer TFE may include inorganic layers, organic layers, or a stack of inorganic layers.

[0100] The input sensing unit TP can be disposed on the display panel DP. Alternatively, the input sensing unit TP can be directly disposed on the encapsulation layer TFE. Or, an adhesive member can be disposed between the input sensing unit TP and the display panel DP.

[0101] In this disclosure, when a component is referred to as being directly set / provided / formed on another component, it means that a third component is not set / provided / formed between the one component and the other component. That is, when a component is referred to as being "directly set / directly provided / directly formed" on another component, it means that the one component and the other component are "in contact" with each other.

[0102] The input sensing unit TP can sense external input, convert it into an input signal, and provide the input signal to the display panel DP. For example, the input sensing unit TP can be a touch sensing layer that senses touch. The input sensing unit TP can convert direct touch by a user, indirect touch by a user, direct touch by an object, indirect touch by an object, etc., into an input signal.

[0103] The input sensing unit TP can sense at least one of the position and intensity (pressure) of a touch applied from the outside. In embodiments, the input sensing unit TP can have various structures or include various materials, and is not limited to any one embodiment. For example, the input sensing unit TP can sense external input using a capacitive method. The display panel DP can receive the input signal from the input sensing unit TP and generate an image corresponding to the input signal.

[0104] Figure 6 This is an enlarged plan view showing a portion of the effective area DM-AA according to an embodiment. (Refer to...) Figure 6 The effective area DM-AA can include a light-emitting area PXA and a light-blocking area NPXA. The light-blocking area NPXA can surround the light-emitting area PXA.

[0105] The emitting region PXA can be configured as multiple emitting regions that emit light in different wavelength regions. The emitting region PXA may include a first emitting region PXA-B, a second emitting region PXA-G, and a third emitting region PXA-R. For example, the first emitting region PXA-B may be configured to emit blue light, the second emitting region PXA-G may be configured to emit green light, and the third emitting region PXA-R may be configured to emit red light. However, the embodiments are not limited to this, and the first emitting region PXA-B, the second emitting region PXA-G, and the third emitting region PXA-R may be configured to emit light of colors other than blue, green, and red.

[0106] Within the emitting region PXA, the first emitting region PXA-B, configured to emit blue light, can have the largest surface area, and the second emitting region PXA-G, configured to emit green light, can have the smallest surface area. Here, surface area refers to the surface area on a plane. However, this is illustrative, and the surface areas of the first emitting region PXA-B, the second emitting region PXA-G, and the third emitting region PXA-R are not limited thereto.

[0107] like Figure 6 As shown, the first luminous region PXA-B and the third luminous region PXA-R are arranged in an alternating order in the first row along the second direction DR2. The second luminous region PXA-G is arranged in the second row to be spaced apart from the first row generated by the first luminous region PXA-B and the third luminous region PXA-R. However, this is illustrative, and the arrangement of the first luminous region PXA-B, the second luminous region PXA-G, and the third luminous region PXA-R is not limited thereto. Furthermore, the respective shapes of the first luminous region PXA-B, the second luminous region PXA-G, and the third luminous region PXA-R in the plane are not limited to the shapes shown and may be defined as shapes different from those shown.

[0108] The light-blocking region NPXA can be the region between adjacent light-emitting regions among PXA-B, PXA-G, and PXA-R, and is connected to the pixel-defined film PDL (see below) which will be described later. Figure 8 The light-emitting region PXA can be the area corresponding to the light-emitting element ED, which will be described later (see [link to ED]). Figure 8 The corresponding area.

[0109] Figure 7 This is an exploded perspective view showing an electronic device EA-a according to aspects of this disclosure. Figure 7 An example of a head-mounted display (HMD) device as an electronic device EA-a is shown. A head-mounted display device can be a device mounted on a user's head and providing the user with a screen on which video or images are displayed. Head-mounted display devices can include perspective-based devices that provide augmented reality (AR) based on real external objects, and perspective-based devices that provide virtual reality (VR) to the user on a screen independent of external objects.

[0110] Electronic device EA-a may include a display panel DP and a lens portion LS facing the display panel DP. Additionally, electronic device EA-a may include a main frame MF, a cover frame CF, and a fixing portion FP.

[0111] The main frame MF can be a part worn on the user's face. The main frame MF can have a shape corresponding to the shape of the user's head (face). For example, the length of the fixing part FP can be adjusted according to the user's head circumference. The fixing part FP can include strips, straps, etc. as structures that allow easy installation of the main frame MF. However, the embodiments are not limited to this, and the fixing part FP can be, for example, in the form of a helmet or temple attached to the main frame MF.

[0112] The lens assembly LS, display panel DP, and cover frame CF can be mounted on the main frame MF. The main frame MF may include a space or structure that can accommodate the lens assembly LS and display panel DP.

[0113] The lens section LS can be disposed between the display panel DP and the user. The lens section LS can transmit light emitted from the display panel DP and provide light to the user. For example, the lens section LS can include various types of lenses such as multi-channel lenses, convex lenses, concave lenses, spherical lenses, aspherical lenses, single lenses, compound lenses, standard lenses, narrow-angle lenses, wide-angle lenses, fixed-focus lenses, and zoom lenses.

[0114] The lens section LS may include a first lens LS1 and a second lens LS2. The first lens LS1 and the second lens LS2 may be arranged to correspond to the positions of the user's left and right eyes, respectively. The first lens LS1 and the second lens LS2 may be housed inside the main frame MF.

[0115] The display panel (DP) can be fixed to the main frame (MF), or alternatively, it can be detachable from the main frame (MF). In the following, the various implementations and aspects of the display panel (DP) discussed throughout this disclosure can be applied to… Figure 5 and Figure 7 The display panel DP shown is shown.

[0116] The cover frame CF can be mounted on one surface of the display panel DP and protect the display panel DP. The cover frame CF and the lens part LS can be spaced apart from each other, and the display panel DP is disposed between the cover frame CF and the lens part LS.

[0117] Figure 8 This is a cross-sectional view specifically showing the effective area DM-AA of the display module DM according to aspects of this disclosure. Figure 8 It can also be understood as showing something like... Figure 6 The diagram shows a cross-sectional view of the first emitting region PXA-B and the corresponding portion of the light-blocking region NPXA adjacent to the first emitting region PXA-B. Although the features are discussed herein as applying to the first emitting region PXA-B, it should be understood that the features can also be applied to… Figure 6 The second luminescent region PXA-G and the third luminescent region PXA-R are shown in the figure.

[0118] Reference Figure 8 The matrix layer BS may comprise a single layer or multiple layers. For example, but not limited to, the matrix layer BS may comprise a first synthetic resin layer, an inorganic layer having a multilayer or single-layer structure, and a second synthetic resin layer disposed on the inorganic layer having a multilayer or single-layer structure. Both the first and second synthetic resin layers may comprise polyimide resins. Additionally, both the first and second synthetic resin layers may comprise at least one of acryloyl resins, methacryl resins, polyisoprene resins, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. The term "α-type" resin as used herein refers to a resin comprising the functional group "α".

[0119] The display panel DP may include a transistor TR, a light-emitting element ED, and a capacitor Cst. The transistor TR, light-emitting element ED, and capacitor Cst may be disposed on the substrate layer BS. Although Figure 8 A transistor TR is shown, but the display panel DP may include multiple transistors for driving the light-emitting element ED. Additionally, not shown in the illustrated embodiment, the display panel DP may include multiple capacitors Cst.

[0120] The circuit layer DP-CL may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. For example, the circuit layer DP-CL may include switching transistors and driving transistors for driving the light-emitting elements ED of the display element layer DP-EL.

[0121] The circuit layer DP-CL may include multiple insulating layers BFL and 10 to 60. The multiple insulating layers BFL and 10 to 60 may include a buffer layer BFL and a first insulating layer 10 to a sixth insulating layer 60.

[0122] A buffer layer BFL can be disposed on the substrate layer BS. The buffer layer BFL may include an inorganic layer. The buffer layer BFL can improve the adhesion between the substrate layer BS and the semiconductor pattern (or conductive pattern) disposed on the buffer layer BFL.

[0123] Semiconductor patterns S1, A1, D1, and SCL can be disposed on the buffer layer BFL. Semiconductor patterns S1, A1, D1, and SCL can be oxide semiconductor patterns. However, this is illustrative, and in a display panel DP, the semiconductor patterns can include amorphous silicon, low-temperature polycrystalline silicon, and / or polycrystalline silicon.

[0124] Figure 8Only a portion of the semiconductor patterns S1, A1, D1, and SCL are shown; the semiconductor patterns can also be set in other areas. The semiconductor patterns S1, A1, D1, and SCL can cover the entire effective area DM-AA (see...). Figure 2 The semiconductor patterns S1, A1, D1, and SCL are arranged in a manner that allows them to have different electrical properties depending on whether they are doped. The semiconductor patterns S1, A1, D1, and SCL may include a first region S1, D1, and SCL with high conductivity and a second region A1 with low conductivity. The first regions S1, D1, and SCL may be doped with n-type or p-type dopants. A p-type transistor may include a doped region doped with p-type dopants, while an n-type transistor may include a doped region doped with n-type dopants. The second region A1 may be an undoped region or a region doped at a lower concentration than each of the first regions S1, D1, and SCL. A display panel DP according to an embodiment may include n-type transistors.

[0125] Each of the first regions S1, D1, and SCL can have a higher conductivity than the second region A1 and is essentially used as an electrode or signal line. The second region A1 can essentially correspond to the channel A1 (or active region) of the transistor TR. That is, the second region A1 in the semiconductor pattern S1, A1, D1, and SCL can be the channel A1 of the transistor TR, its other parts (S1 and D1) can be the source S1 or drain D1 of the transistor TR, and another part (SCL) can be a connecting electrode or a connecting signal line SCL.

[0126] The source S1, channel A1, and drain D1 of transistor TR can be provided from semiconductor patterns S1, A1, D1, and SCL. The source S1 and drain D1 can extend in opposite directions from channel A1 in a cross-section. Figure 8 A portion of the connection signal line SCL provided from semiconductor patterns S1, A1, D1, and SCL is shown. Although not shown, the connection signal line SCL can be electrically connected on the plane to the drain D1 of transistor TR.

[0127] The capacitor Cst can be disposed on the buffer layer BFL. In an embodiment, the capacitor Cst may include a first metal layer ML-1 and a second metal layer ML-2. Both the first metal layer ML-1 and the second metal layer ML-2 may comprise conductive metals.

[0128] The first metal layer ML-1 may include a first sub-metal layer MT-S1 and a second sub-metal layer MT-S2 partially disposed on the first sub-metal layer MT-S1. The second metal layer ML-2 may include a third sub-metal layer MT-S3 and a fourth sub-metal layer MT-S4 partially disposed on the third sub-metal layer MT-S3. The first sub-metal layer MT-S1, the second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the fourth sub-metal layer MT-S4 may be composed of the same type of metal, or at least one of them may include different types of metal.

[0129] The first sub-metal layer MT-S1 may be disposed in a different layer from the third sub-metal layer MT-S3. At least a portion of the second sub-metal layer MT-S2 may be disposed in a different layer from the fourth sub-metal layer MT-S4. The first portion S2-P1 of the second sub-metal layer MT-S2, described later, (see...) Figure 9 This can be combined with the third part S4-P3 of the fourth sub-metal layer MT-S4, which will be described later (see...). Figure 9 (Set on different layers)

[0130] For example, each of the first sub-metal layer MT-S1, the second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the fourth sub-metal layer MT-S4 can be directly disposed on any of the insulating layers. The first sub-metal layer MT-S1 can be directly disposed on the buffer layer BFL. The third sub-metal layer MT-S3 can be directly disposed on the first insulating layer 10. A portion of the second sub-metal layer MT-S2 can be directly disposed on the second insulating layer 20. A portion of the fourth sub-metal layer MT-S4 can be directly disposed on the third insulating layer 30. However, this is illustrative, and the insulating layers on which the first sub-metal layer MT-S1, the second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the fourth sub-metal layer MT-S4 are directly disposed can be varied depending on the stacking structure of the circuit layers DP-CL.

[0131] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can cover the semiconductor patterns S1, A1, D1 and SCL and the first sub-metal layer MT-S1 of the capacitor Cst. In addition, the first insulating layer 10 can cover at least a portion of the connecting signal line SCL. The first insulating layer 10 can be configured as a common layer penetrating the first light-emitting region PXA-B and the light-blocking region NPXA.

[0132] The gate G1 of transistor TR can be disposed on the first insulating layer 10. The gate G1 can be part of a metal pattern. The gate G1 can be stacked with the channel A1. The gate G1 can be used as a mask in the process of doping or reducing semiconductor patterns S1, A1, D1 and SCL.

[0133] The second insulating layer 20 can be disposed on the first insulating layer 10 and cover the gate G1 of the transistor TR and the third sub-metal layer MT-S3 of the capacitor Cst. The second insulating layer 20 can be configured as a common layer penetrating the first light-emitting region PXA-B and the light-blocking region NPXA.

[0134] The third insulating layer 30 can be disposed on the second insulating layer 20 and cover the second sub-metal layer MT-S2 of the capacitor Cst. The first connecting electrode CNE1 can be disposed on the third insulating layer 30. The first connecting electrode CNE1 can be connected to the connecting signal line SCL through the first contact hole CH1 passing through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0135] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the fourth sub-metal layer MT-S4 of the first connecting electrode CNE1 and capacitor Cst.

[0136] A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a second contact hole CH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover the second connecting electrode CNE2. The sixth insulating layer 60 may be a planarization layer.

[0137] Each of the first insulating layer 10 to the sixth insulating layer 60 may be an inorganic layer and / or an organic layer. The first insulating layer 10 to the third insulating layer 30 may have a monolayer structure. Each of the fourth insulating layer 40 to the sixth insulating layer 60 may include a single layer or multiple layers. For example, but not limited to, the inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. By way of example and not by way of limitation, the organic layer may include at least one of acryloyl resins, methacrylamide resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In an exemplary embodiment, each of the first insulating layer 10 to the fourth insulating layer 40 may be an inorganic layer, and each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer.

[0138] The display element layer DP-EL may include a pixel-defining film (PDL) and a light-emitting element (ED). The ED may include a first electrode AE, a second electrode CE disposed above the first electrode AE, and an emission layer (EML) disposed between the first electrode AE ​​and the second electrode CE. Additionally, the ED may also include a hole control layer (HTR) and an electronic control layer (ETR). The hole control layer (HTR) may be disposed between the first electrode AE ​​and the emission layer (EML). The electronic control layer (ETR) may be disposed between the emission layer (EML) and the second electrode CE.

[0139] An ED (Emitting Light) element can be configured to emit light when provided with sufficient energy. For example, an ED can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, or quantum rods. For example, an ED can include microLEDs or nanoLEDs.

[0140] The first electrode AE ​​can be disposed on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through a third contact hole CH3 that passes through the sixth insulating layer 60 and is filled with the material of the first electrode AE. The first electrode AE ​​can be connected to the connecting signal line SCL through the first connecting electrode CNE1 and the second connecting electrode CNE2. Although not shown, the first electrode AE ​​can be electrically connected to the drain D1 of the transistor TR through the connecting signal line SCL.

[0141] The first electrode AE ​​may comprise a metallic material, a metallic alloy, or a conductive compound. The first electrode AE ​​may be an anode or a cathode. However, aspects of this disclosure should not be construed as limited thereto. The first electrode AE ​​may be a pixel electrode. The first electrode AE ​​may be a transmission electrode, a semi-transmission electrode, or a reflection electrode. The first electrode AE ​​may comprise at least one material selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, Zn, a compound selected from two or more of these materials, a mixture selected from two or more of these materials, or an oxide thereof.

[0142] When the first electrode AE ​​is a transmission electrode, the first electrode AE ​​may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). When the first electrode AE ​​is a semi-transmission electrode or a reflection electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, W, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). Optionally, the first electrode AE ​​may have a multilayer structure including one or more reflective or semi-transmission films and one or more transmission conductive films, each of which may include the aforementioned materials, and the one or more transmission conductive films may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto. However, the embodiments are not limited thereto, and the first electrode AE ​​may include the aforementioned metallic material, a combination of two or more metallic materials selected from the aforementioned metallic materials, or an oxide of the aforementioned metallic materials, etc.

[0143] A pixel-defining film (PDL) can be disposed on a sixth insulating layer 60. An emission opening (PX_OP) surrounding at least a portion of the first electrode AE ​​can be defined in the pixel-defining film (PDL). The portion of the first electrode AE ​​located in the emission opening (PX_OP) of the pixel-defining film (PDL) can be defined as a first light-emitting region (PXA-B).

[0144] The hole control layer HTR can be disposed on the first electrode AE ​​and the pixel defining film PDL. The hole control layer HTR can be configured as a common layer superimposed on the first light-emitting region PXA-B and the light-blocking region NPXA. Unlike the illustrated embodiment, the hole control layer HTR can be disposed in the region corresponding to the emission opening PX_OP. The hole control layer HTR can include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer. The hole control layer HTR can include conventional hole injection materials and / or conventional hole transport materials.

[0145] The emission layer EML can be disposed on the hole control layer HTR. The emission layer EML can be disposed in the region corresponding to the emission opening PX_OP. Optionally, the emission layer EML can be configured as a common layer superimposed on the first emitting region PXA-B and the light-blocking region NPXA. The emission layer EML can include organic and / or inorganic emitting materials. The emission layer EML can be configured to emit light of one color: red, green, and blue. The emission layer EML corresponding to the first emitting region PXA-B can be configured to emit blue light. The emission layer EML corresponding to the second emitting region PXA-G (see...) Figure 6 The emitting layer of the third emitting region PXA-R (see [link to PXA-R]) can be configured to emit green light. Figure 6 The corresponding emission layer can be constructed to emit red light.

[0146] The electronic control layer (ETR) can be disposed on the emitter layer (EML). The ETR can be configured as a common layer superimposed on the first emitting region PXA-B and the light-blocking region NPXA. In some embodiments that replace the illustrated embodiments, the ETR can be disposed in the region corresponding to the emission opening PX_OP. The ETR may include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer. The ETR may include conventional electron injection materials and / or conventional electron transport materials.

[0147] The second electrode CE can be disposed on the electronic control layer ETR. The second electrode CE can be configured as a common layer superimposed with the first light-emitting region PXA-B and the light-blocking region NPXA. The second electrode CE can be a common electrode. The second electrode CE can be a cathode or an anode, but the embodiments are not limited thereto. For example, when the first electrode AE ​​is an anode, the second electrode CE can be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE can be an anode.

[0148] The second electrode CE can be a transmission electrode, a semi-transmission electrode, or a reflection electrode. When the second electrode CE is a transmission electrode, it can include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0149] When the second electrode CE is a semi-transparent electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, or compounds or mixtures thereof (e.g., AgMg, AgYb, or MgYb). Optionally, the second electrode CE may have a multilayer structure including one or more reflective or semi-transparent films and one or more transparent conductive films, each of which may include the aforementioned materials, and the one or more transparent conductive films may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc. For example, the second electrode CE may include the aforementioned metallic materials, combinations of two or more metallic materials selected from the aforementioned metallic materials, or oxides of the aforementioned metallic materials, etc.

[0150] The encapsulation layer TFE can be disposed on the display element layer DP-EL. The encapsulation layer TFE can be disposed on the second electrode CE and cover the light-emitting element ED. The encapsulation layer TFE can protect the display element layer DP-EL from moisture, oxygen and / or foreign matter such as dust particles. The encapsulation layer TFE can include multiple thin films.

[0151] The encapsulation layer TFE may include at least one inorganic film. For example, the encapsulation layer TFE may include an inorganic film disposed on the second electrode CE and an organic film disposed between the inorganic films. The inorganic film can protect the light-emitting element ED from moisture / oxygen, and the organic film can protect the light-emitting element ED from foreign matter such as dust particles.

[0152] The input sensing unit TP can be disposed on the display panel DP. For example, the input sensing unit TP can be directly disposed on the encapsulation layer TFE of the display panel DP. Optionally, an adhesive member (not shown) can be disposed between the input sensing unit TP and the display panel DP.

[0153] The input sensing unit TP may include a first sensing insulating layer IL1, a second sensing insulating layer IL2, and a third sensing insulating layer IL3. The input sensing unit TP may include at least one conductive layer disposed on the sensing insulating layers. The input sensing unit TP may include a first conductive layer CL1 and a second conductive layer CL2.

[0154] A first sensing insulating layer IL1 may be disposed on the encapsulation layer TFE. The first sensing insulating layer IL1 may include at least one inorganic insulating layer. The first sensing insulating layer IL1 may be in contact with the encapsulation layer TFE. Optionally, the first sensing insulating layer IL1 may be omitted, and in this case, the first conductive layer CL1 may be in contact with the encapsulation layer TFE.

[0155] A first conductive layer CL1 may be disposed on a first sensing insulating layer IL1. The first conductive layer CL1 may include a plurality of first conductive patterns. The plurality of first conductive patterns may be disposed on the first sensing insulating layer IL1. A second sensing insulating layer IL2 may be disposed on the first sensing insulating layer IL1 and cover at least a portion of the first conductive layer CL1.

[0156] A second conductive layer CL2 may be disposed on a second sensing insulating layer IL2. The second conductive layer CL2 may include a plurality of second conductive patterns. The plurality of second conductive patterns may be disposed on the second sensing insulating layer IL2. Although not shown, the plurality of second conductive patterns may be connected to a plurality of first conductive patterns respectively through contact holes defined in the second sensing insulating layer IL2.

[0157] Each of the plurality of first conductive patterns in the first conductive layer CL1 and the plurality of second conductive patterns in the second conductive layer CL2 can be arranged across the corresponding light-blocking region NPXA. Each of the plurality of first conductive patterns in the first conductive layer CL1 and the plurality of second conductive patterns in the second conductive layer CL2 can be a grid pattern.

[0158] The third sensing insulating layer IL3 may be disposed on the second sensing insulating layer IL2 and may cover the second conductive layer CL2. Each of the second sensing insulating layer IL2 and the third sensing insulating layer IL3 may include an inorganic insulating layer or an organic insulating layer.

[0159] The first conductive layer CL1 and the second conductive layer CL2 can both have a single-layer structure, or have a multilayer structure in which the middle layers are stacked on a third-direction DR3. The conductive layers CL1 and CL2, both having a single-layer structure, can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer can include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer can include conductive polymers such as PEDOT, metal nanowires, or graphene.

[0160] The conductive layers CL1 and CL2, both having a multilayer structure, may include a metal layer. The metal layer may have a three-layer structure, such as titanium (Ti) / aluminum (Al) / titanium (Ti). Each of the conductive layers CL1 and CL2 having a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0161] Figure 9 It is shown Figure 8 An enlarged sectional view of region XX' in the diagram. Figure 9 A capacitor Cst and a first insulating layer 10 to a fifth insulating layer 50 adjacent to the capacitor Cst are shown.

[0162] A first trench CNT1 passing through the first insulating layer 10 in the thickness direction DR3 can be defined within the first insulating layer 10. A second trench CNT2 and a third trench CNT3 passing through the second insulating layer 20 in the thickness direction DR3 can be defined within the second insulating layer 20. A fourth trench CNT4 passing through the third insulating layer 30 in the thickness direction DR3 can be defined within the third insulating layer 30.

[0163] The second trench CNT2 and the third trench CNT3 can be spaced apart from each other in a second direction DR2 perpendicular to the thickness direction DR3. The second trench CNT2 can be stacked with the first trench CNT1. The third trench CNT3 can be stacked with the fourth trench CNT4. The first inner surface of the second insulating layer 20 defining the second trench CNT2 can be aligned with the inner surface of the first insulating layer 10 defining the first trench CNT1. The second inner surface of the second insulating layer 20 defining the third trench CNT3 can be aligned with the inner surface of the third insulating layer 30 defining the fourth trench CNT4.

[0164] The first trench CNT1 and the second trench CNT2 can be aligned on the first sub-metal layer MT-S1. The first trench CNT1 and the second trench CNT2 can be configured such that they do not intersect with the third sub-metal layer MT-S3. The third trench CNT3 and the fourth trench CNT4 can be aligned on the third sub-metal layer MT-S3. The third trench CNT3 and the fourth trench CNT4 can be configured such that they do not intersect with the second sub-metal layer MT-S2.

[0165] The second sub-metal layer MT-S2 may include a first portion S2-P1 and a second portion S2-P2 extending from the first portion S2-P1. The first portion S2-P1 may be disposed on the second insulating layer 20. The first portion S2-P1 and the second portion S2-P2 may be continuous. The first insulating layer 10, the second insulating layer 20, and the third sub-metal layer MT-S3 are disposed in the thickness direction DR3 between the first portion S2-P1 and the first sub-metal layer MT-S1, and separate the first portion S2-P1 of the second sub-metal layer MT-S2 from the first sub-metal layer MT-S1.

[0166] The second portion S2-P2 of the second sub-metal layer MT-S2 can be disposed within the first trench CNT1 and the second trench CNT2. The second portion S2-P2 of the second sub-metal layer MT-S2 can fill the first trench CNT1 and the second trench CNT2. The second portion S2-P2 of the second sub-metal layer MT-S2 can be disposed between the first sub-metal layer MT-S1 and the first portion S2-P1 of the second sub-metal layer MT-S2. The second portion S2-P2 of the second sub-metal layer MT-S2 can electrically connect the first sub-metal layer MT-S1 to the first portion S2-P1 of the second sub-metal layer MT-S2.

[0167] The fourth sub-metal layer MT-S4 may include a third portion S4-P3 and a fourth portion S4-P4 extending from the third portion S4-P3. The third portion S4-P3 may be disposed on the third insulating layer 30. The third portion S4-P3 and the fourth portion S4-P4 may be continuous. The second insulating layer 20, the third insulating layer 30, and the first portion S2-P1 of the second sub-metal layer MT-S2 are disposed in the thickness direction DR3 between the third portion S4-P3 and the third sub-metal layer MT-S3, and separate the third portion S4-P3 of the fourth sub-metal layer MT-S4 from the third sub-metal layer MT-S3.

[0168] The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be disposed within the third trench CNT3 and the fourth trench CNT4. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can fill the third trench CNT3 and the fourth trench CNT4. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be disposed between the third sub-metal layer MT-S3 and the third portion S4-P3 of the fourth sub-metal layer MT-S4. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can electrically connect the third sub-metal layer MT-S3 to the third portion S4-P3 of the fourth sub-metal layer MT-S4.

[0169] At least one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may have a single-layer structure. The single-layer structure may be in contact with two sub-metal layers adjacent to the insulating layer. The insulating layer having a single-layer structure may include silicon nitride. For example, but not limited to, the first insulating layer 10 may have a single-layer structure and may be directly disposed between the first sub-metal layer MT-S1 and the third sub-metal layer MT-S3. The second insulating layer 20 may have a single-layer structure and may be directly disposed between the third sub-metal layer MT-S3 and a first portion S2-P1 of the second sub-metal layer MT-S2. The third insulating layer 30 may have a single-layer structure and may be directly disposed between the first portion S2-P1 of the second sub-metal layer MT-S2 and a third portion S4-P3 of the fourth sub-metal layer MT-S4. The first sub-metal layer MT-S1, the first portion S2-P1 of the second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the third portion S4-P3 of the fourth sub-metal layer MT-S4 may be stacked on top of each other.

[0170] In the second direction DR2 perpendicular to the thickness direction DR3, the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be separated from the first portion S2-P1 of the second sub-metal layer MT-S2, and the region 30-AR of the third insulating layer 30 is disposed between the fourth portion S4-P4 and the first portion S2-P1. In the second direction DR2, the third sub-metal layer MT-S3 can be separated from the second portion S2-P2 of the second sub-metal layer MT-S2, and the region 20-AR of the second insulating layer 20 is disposed between the third sub-metal layer MT-S3 and the second portion S2-P2.

[0171] Figure 10 This is a schematic cross-sectional view showing a capacitor Cst according to an aspect of this disclosure. For ease of explanation, Figure 10 The capacitor Cst and the components adjacent to the capacitor Cst (i.e., the substrate layer BS and the insulating layer 1030) are schematically shown, and some components are not shown. Figure 10 The insulating layer 1030 shown corresponds to the reference. Figure 8 and Figure 9 The first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 are described and shown schematically for ease of explanation.

[0172] When viewed in cross-section, the capacitor Cst, comprising a first metal layer ML-1 and a second metal layer ML-2, can have a folded shape. Each of the first metal layer ML-1 and the second metal layer ML-2 can have a folded shape, and the folded shape can include three non-folded portions and two folded portions. The three non-folded portions can be spaced apart from each other, and the folded portions are each disposed between the non-folded portions. Among the three non-folded portions, one non-folded portion can be configured to have a relatively small surface area. The first metal layer ML-1 can have a right square bracket shape (i.e., a "]" shape) in cross-section. The second metal layer ML-2 can have a left square bracket shape (i.e., a "[" shape) in cross-section. Both the right square bracket shape and the left square bracket shape can be folded shapes.

[0173] In the first metal layer ML-1, the first portion S2-P1 of the first sub-metal layer MT-S1, the second portion S2-P2 of the second sub-metal layer MT-S2, and the third portion S2-P2 of the second sub-metal layer MT-S2 can correspond to the non-folded portions. The surface area of ​​the second portion S2-P2 of the second sub-metal layer MT-S2 can be smaller than the surface area of ​​each of the first portion S2-P1 of the second sub-metal layer MT-S2 and the first sub-metal layer MT-S1. The surface area indicates the surface area of ​​the first sub-metal layer MT-S1, the first portion S2-P1 of the second sub-metal layer MT-S2, and the second portion S2-P2 of the second sub-metal layer MT-S2 in a state where they are aligned with each other.

[0174] The first sub-metal layer MT-S1, the second portion S2-P2 of the second sub-metal layer MT-S2, and the first portion S2-P1 of the second sub-metal layer MT-S2 can have a right-sided bracket shape in cross-section. The capacitor Cst can be configured such that the first portion S2-P1 of the second sub-metal layer MT-S2 is located between the third portion S4-P3 of the left-sided bracket shape and the third sub-metal layer MT-S3. The first sub-metal layer MT-S1, the second portion S2-P2 of the second sub-metal layer MT-S2, and the first portion S2-P1 of the second sub-metal layer MT-S2 can include folded shapes.

[0175] In the second metal layer ML-2, the third portion S4-P3 of the third sub-metal layer MT-S3 and the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can correspond to the non-folded portions. The surface area of ​​the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be smaller than the surface area of ​​each of the third portion S4-P3 and the third sub-metal layer MT-S3. The surface area indicates the surface area of ​​the third sub-metal layer MT-S3, the third portion S4-P3 of the fourth sub-metal layer MT-S4, and the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 in a state where they are aligned with each other.

[0176] In cross-section, the third sub-metal layer MT-S3, the fourth portion S4-P4 of the fourth sub-metal layer MT-S4, and the third portion S4-P3 of the fourth sub-metal layer MT-S4 can have a left-sided bracket shape. The capacitor Cst can be configured such that the third sub-metal layer MT-S3 is located between the first sub-metal layer MT-S1 and the first portion S2-P1, which have a right-sided bracket shape. In cross-section, the third sub-metal layer MT-S3, the fourth portion S4-P4 of the fourth sub-metal layer MT-S4, and the third portion S4-P3 of the fourth sub-metal layer MT-S4 can include a folded shape.

[0177] Figure 11 This is a schematic perspective view showing a capacitor Cst according to an embodiment. Figure 11 It can be shown Figure 10 A schematic perspective view of the capacitor Cst and the insulating layer 1030. (Refer to...) Figure 11 The third sub-metal layer MT-S3 can be located between the bracket-shaped layers formed by the first sub-metal layer MT-S1 and the second sub-metal layer MT-S2. A portion of the second sub-metal layer MT-S2 (i.e., Figure 10 The first part S2-P1 shown can be located between the left bracket-shaped layers formed by the third sub-metal layer MT-S3 and the fourth sub-metal layer MT-S4.

[0178] Figure 12 This is a schematic perspective view showing the insulating layer 3010 that defines the trench CNTs therein. Figure 12 The insulating layer 3010 shown can correspond to the reference. Figure 8 and Figure 9 Any one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 is described and shown schematically for ease of explanation. For ease of explanation, Figure 12 An insulating layer 3010 directly disposed on the substrate layer BS is shown, but the embodiments are not limited thereto. See also... Figure 12 On a plane, the groove CNT can extend in a first direction DR1 perpendicular to the thickness direction DR3. Figure 12 The trench CNT shown can correspond to the reference. Figure 9 Any of the first trenches CNT1 to the fourth trench CNT4 described.

[0179] Figure 13A This is a perspective view showing the first metal layer ML-1 according to an embodiment. In the plane, the second portion S2-P2 of the second sub-metal layer MT-S2 can extend in a first direction DR1 perpendicular to the thickness direction DR3. The second portion S2-P2 of the second sub-metal layer MT-S2 can be disposed in a trench CNT extending along the first direction DR1 (see...). Figure 12Within the first direction DR1, the length LH1 of the second portion S2-P2 can be substantially the same as the length of the first portion S2-P1. However, this is illustrative, and the length LH1 of the second portion S2-P2 can be different from the length of the first portion S2-P1. In this disclosure, "substantially the same" includes cases where they are identical in terms of physical measurement as well as cases where there are differences within a margin of error that may arise during the manufacturing process.

[0180] Figure 13B This is a perspective view showing the second metal layer ML-2 according to an embodiment. In the plane, the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can extend in a first direction DR1 perpendicular to the thickness direction DR3. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be disposed in a trench CNT extending along the first direction DR1 (see...). Figure 12 Within the first direction DR1, the length LH2 of the fourth part S4-P4 can be substantially the same as the length of the third part S4-P3. However, this is illustrative, and the length LH2 of the fourth part S4-P4 can be different from the length of the third part S4-P3 in the first direction DR1.

[0181] In the embodiment, the first sub-metal layer MT-S1 (see...) Figure 11 and Figure 13A ), second sub-metal layer MT-S2 (see Figure 11 and Figure 13A The first part S2-P1 (see) Figure 11 and Figure 13A ) and the second sub-metal layer MT-S2 (see Figure 11 and Figure 13A Part S2-P2 of ) (see) Figure 11 and Figure 13A ) may include capacitor Cst (see Figure 11 The first metal layer ML-1 (see) Figure 11 and Figure 13A ), and the second sub-metal layer MT-S2 (see Figure 11 and Figure 13A The first part S2-P1 (see) Figure 11 and Figure 13A ) and the second sub-metal layer MT-S2 (see Figure 11 and Figure 13A Part S2-P2 of ) (see) Figure 11 and Figure 13A ) can increase capacitor Cst (see Figure 11 The surface area of ​​the second sub-metal layer MT-S2 (see...). Figure 11 and Figure 13A Part S2-P2 of ) (see) Figure 11 and Figure 13AThis can help capacitor Cst (see...) Figure 11 The increase in surface area.

[0182] Third sub-metal layer MT-S3 (see...) Figure 11 and Figure 13B ), fourth sub-metal layer MT-S4 (see Figure 11 and Figure 13B Part 3 S4-P3 (see) Figure 11 and Figure 13B ) and the fourth sub-metal layer MT-S4 (see Figure 11 and Figure 13B Part 4 of ) S4-P4 (see Figure 11 and Figure 13B ) may include capacitor Cst (see Figure 11 The second metal layer ML-2 (see) Figure 11 and Figure 13B ), and the fourth sub-metal layer MT-S4 (see Figure 11 and Figure 13B Part 3 S4-P3 (see) Figure 11 and Figure 13B ) and the fourth sub-metal layer MT-S4 (see Figure 11 and Figure 13B Part 4 of ) S4-P4 (see Figure 11 and Figure 13B This can increase the surface area of ​​the capacitor's Cst. That is, the fourth sub-metal layer MT-S4 (see...) Figure 11 and Figure 11 Part 4 of ) S4-P4 (see Figure 13A and Figure 11 This can help capacitor Cst (see...) Figure 13B The surface area of ​​) increases. That is, according to the embodiment, it includes the second part S2-P2 (see Figure 11 and Figure 11 ) and Part 4 S4-P4 (see Figure 11 and Figure 8 The capacitor Cst (see) Figure 11 ) can have a maximized surface area. This includes capacitors with folded shapes (see...). Figure 8 This can prevent foreign object defects and also has an increased surface area to exhibit high capacitance characteristics. Therefore, according to embodiments, the capacitor Cst (see...) Figure 11 ) display panel DP (see Figure 14 It can have minimal parasitic capacitance and also exhibit excellent display quality. Additionally, according to the embodiment, a capacitor Cst (see...) Figure 14 ) display panel DP (see Figure 11 It can exhibit excellent manufacturability.

[0183] Display panels used in electronic devices providing virtual reality (VR) can achieve ultra-high resolutions of approximately 1500 PPI (pixels per inch) or greater. Ultra-high resolution display panels, including n-type transistors, require capacitors with high capacitance characteristics. Parasitic capacitance can have a significant impact on ultra-high resolution display panels including n-type transistors. With low capacitor capacitance, display quality defects such as temporary image residues can be noticeable in the images produced by the display panel. Increasing the thickness of the insulating layer to increase capacitor capacitance significantly increases the chance of insulation loss and foreign matter defects, such as particles embedded in the metal layer during the process of forming the capacitor. Foreign matter such as particles is perceived as dark spots and leads to reduced manufacturing efficiency.

[0184] Compared to a typical capacitor that includes a first metal layer and a second metal layer, both having a single-layer structure, the capacitor Cst according to the embodiment (see...) Figure 13A A capacitor can be configured to have an increased surface area. A typical capacitor comprises two metal layers, each of which includes two sub-metal layers, and the two sub-metal layers in one metal layer are electrically connected to each other through contact holes. When the sub-metal layers are connected through contact holes, the portion disposed within the contact holes does not contribute to an increase in the capacitor's surface area. The portion disposed within the contact holes has a very small surface area and is not considered part of the capacitor's surface area.

[0185] Figure 13B This is a schematic diagram showing a capacitor connected via the contact hole CNT-X. (Refer to...) Figure 14 The two sub-metal layers M-1 and M-2 are connected to each other through contact hole CNT-X, and contact hole CNT-X has a very small surface area. Figure 15 , Figure 9 and Figure 15 Compared to the second portion S2-P2 of the second sub-metal layer MT-S2 or the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 shown in the figure, it is set with Figure 15 The portion of the contact hole CNT-X shown has a very small surface area. Therefore, the portion located in the contact hole CNT-X is not considered the surface area of ​​the capacitor.

[0186] Figures 1 to 14 This is a cross-sectional view showing region XX' according to an aspect of this disclosure. (and) Figure 15 compared to, Figure 14 The difference lies in the first sub-metal layer MT-S1a of the capacitor Cst. (Refer to...) Figure 9 By avoiding and referencing Figure 16A The description focuses on commonalities and primarily on the differences between the embodiments.

[0187] ReferenceFigure 16B The gate electrode G1 of the transistor TR can be a gate G1 and can also be part of the first sub-metal layer MT-S1a. At least a portion of the capacitor Cst can be arranged to be stacked with the transistor TR. The second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the fourth sub-metal layer MT-S4 of the capacitor Cst can be stacked with the transistor TR.

[0188] The gate electrode G1 may include a conductive metal. The gate electrode G1, the first portion S2-P1 of the second sub-metal layer MT-S2, the third sub-metal layer MT-S3, and the third portion S4-P3 of the fourth sub-metal layer MT-S4 may be stacked on top of each other.

[0189] A gate electrode G1 may be disposed on a first insulating layer 10a. A second insulating layer 20a may cover the gate electrode G1 and be disposed on the first insulating layer 10a. A third insulating layer 30a may cover a third sub-metal layer MT-S3 and be disposed on the second insulating layer 20a. A fourth insulating layer 40a may cover a second sub-metal layer MT-S2 and be disposed on the third insulating layer 30a. A fifth insulating layer 50a may cover a fourth sub-metal layer MT-S4 and be disposed on the fourth insulating layer 40a.

[0190] exist Figures 17 to 22 In, with Figures 16A to 22 Unlike other trenches, the first trench CNT1a can be defined within the second insulating layer 20a. The first trench CNT1a can penetrate the second insulating layer 20a in the thickness direction DR3. The second trench CNT2a and the third trench CNT3a can be defined within the third insulating layer 30a and spaced apart from each other in a second direction DR2 perpendicular to the thickness direction DR3. The second trench CNT2a and the third trench CNT3a can penetrate the third insulating layer 30a in the thickness direction DR3. The fourth trench CNT4a can be defined within the fourth insulating layer 40a. The fourth trench CNT4a can penetrate the fourth insulating layer 40a in the thickness direction DR3.

[0191] As shown in the figure, the first trench CNT1a and the second trench CNT2a can be aligned with each other. The third trench CNT3a and the fourth trench CNT4a can be aligned with each other. The inner surface of the second insulating layer 20a defining the first trench CNT1a can be aligned with the first inner surface of the third insulating layer 30a defining the second trench CNT2a. The second inner surface of the third insulating layer 30a defining the third trench CNT3a can be aligned with the inner surface of the fourth insulating layer 40a defining the fourth trench CNT4a.

[0192] The second portion S2-P2 of the second sub-metal layer MT-S2 can fill the first trench CNT1a and the second trench CNT2a. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can fill the third trench CNT3a and the fourth trench CNT4a. In the second direction DR2 perpendicular to the thickness direction DR3, the second portion S2-P2 of the second sub-metal layer MT-S2 and the third sub-metal layer MT-S3 can be spaced apart from each other, and a region of the third insulating layer 30a is disposed between the third sub-metal layer MT-S3 and the second portion S2-P2. In the second direction DR2 perpendicular to the thickness direction DR3, the fourth portion S4-P4 of the fourth sub-metal layer MT-S4 and the first portion S2-P1 of the second sub-metal layer MT-S2 can be separated from each other, and a region of the fourth insulating layer 40a is disposed between the fourth portion S4-P4 and the first portion S2-P1.

[0193] The display panel according to aspects of this disclosure can be manufactured by the methods for manufacturing display panels discussed herein. Figures 1 to 15 and Figure 16A All of these are flowcharts illustrating a method for manufacturing a display panel (DP) according to aspects of this disclosure. Figure 16B These are all schematic diagrams illustrating the steps of manufacturing a display panel (DP) according to aspects of this disclosure. In the following text, reference will be made to... Figure 17 By avoiding and referencing Figure 18 The description focuses on common content and primarily on the differences between the embodiments.

[0194] Reference Figure 19 A method for manufacturing a display panel according to aspects of this disclosure may include the following steps: preparing a substrate layer (S100); forming a circuit layer on the substrate layer (S200); and forming a display element layer on the circuit layer (S300). See also... Figure 18 The step of forming a circuit layer (S200) may include the following steps: forming a first sub-metal layer (S210); forming a preliminary first insulating layer (S220); forming a third sub-metal layer (S230); forming a first insulating layer and a preliminary second insulating layer (S240); forming a second sub-metal layer (S250); forming a second insulating layer and a third insulating layer (S260); and forming a fourth sub-metal layer (S270).

[0195] Reference Figure 18 A first sub-metal layer MT-S1 can be formed on the substrate layer BS. Specifically, the first sub-metal layer MT-S1 can be formed on a buffer layer BFL disposed on the substrate layer BS. For example, but not limited to, a conductive metal can be deposited and patterned to form the first sub-metal layer MT-S1.

[0196] Reference Figure 18A preliminary first insulating layer P-10 can be formed on the first sub-metal layer MT-S1. A preliminary third sub-metal layer P-MT-S3 can be formed on the preliminary first insulating layer P-10.

[0197] Then, as Figure 20 As shown, a preliminary third sub-metal layer P-MT-S3 can be patterned to form a third sub-metal layer MT-S3. A preliminary second insulating layer P-20 can be formed on the third sub-metal layer MT-S3. A second trench CNT2 can be formed in the preliminary second insulating layer P-20. The preliminary second insulating layer P-20 can cover the third sub-metal layer MT-S3.

[0198] It can be composed of the initial first insulating layer P-10 (see...) Figure 21 The first insulating layer 10 is formed. This can be achieved by initially forming the first insulating layer P-10 (see...). Figure 20 A first trench CNT1 is formed in the first insulating layer 10. The first insulating layer 10 may cover the first sub-metal layer MT-S1.

[0199] The first trench CNT1 and the second trench CNT2 can be formed in the same step to align with each other. Material for forming the preliminary second insulating layer P-20 can be deposited onto the preliminary first insulating layer P-10 (see...). Figure 20 The third sub-metal layer MT-S3 is covered on top, and after this deposition, the first trench CNT1 and the second trench CNT2 can be formed together.

[0200] Then, as Figure 20 As shown, a second sub-metal layer MT-S2 can be formed on the initial second insulating layer P-20. The second sub-metal layer MT-S2 can fill the first trench CNT1 and the second trench CNT2 during formation. A second portion S2-P2 of the second sub-metal layer MT-S2 is formed by the second sub-metal layer MT-S2 located within the first trench CNT1 and the second trench CNT2. Metallic material can be deposited onto the initial second insulating layer P-20, and the deposited metallic material can be patterned to form a first portion S2-P1 of the second sub-metal layer MT-S2.

[0201] Then, as Figure 22 As shown, it can be made of a preliminary second insulating layer P-20 (see...) ​ A second insulating layer 20 is formed therein. A preliminary second insulating layer P-20, in which the second trench CNT2 can be formed (see...). ​ A third trench CNT3 is formed in the second trench DR2, thereby forming the second insulating layer 20. This can be done by creating a fourth trench CNT4 as discussed below. The second trench CNT2 and the third trench CNT3 may be spaced apart from each other in the second direction DR2.

[0202] A third insulating layer 30 can be formed on the second sub-metal layer MT-S2. The third insulating layer 30 can cover the second sub-metal layer MT-S2. A fourth trench CNT4 can be formed in the third insulating layer 30. In some embodiments, the third trench CNT3 and the fourth trench CNT4 can be formed in the same step to be aligned with each other. The material used to form the third insulating layer 30 can be deposited onto the initial second insulating layer P-20 (see...). ​ On top of this, a second sub-metal layer MT-S2 is covered, and after this deposition, a third trench CNT3 and a fourth trench CNT4 can be formed together.

[0203] Reference ​ A fourth sub-metal layer MT-S4 can be formed on the third insulating layer 30. The fourth sub-metal layer MT-S4 can fill the third trench CNT3 and the fourth trench CNT4. The fourth portion S4-P4 of the fourth sub-metal layer MT-S4 can be located within the third trench CNT3 and the fourth trench CNT4. Metal material can be deposited on the third insulating layer 30, and the deposited metal material can be patterned to form the fourth portion S4-P4 of the fourth sub-metal layer MT-S4.

[0204] A method for manufacturing a display panel according to an embodiment may include forming sub-metal layers (i.e., a second sub-metal layer and a fourth sub-metal layer) comprising a portion (i.e., a first portion and a third portion) and another portion (i.e., a second portion and a fourth portion) extending from that portion, thereby exhibiting excellent processability. A display panel according to an embodiment manufactured using the method for manufacturing a display panel may include a capacitor having a folded shape. The capacitor may include a first metal layer and a second metal layer. Each of the first metal layer and the second metal layer may have a folded shape in cross-section comprising three non-folded portions and two folded portions. The first metal layer may include a first sub-metal layer and a second sub-metal layer disposed on the first sub-metal layer, and the first and second sub-metal layers may be arranged to have a folded shape in cross-section. The second metal layer may include a third sub-metal layer and a fourth sub-metal layer at least partially disposed on the third sub-metal layer, and the third and fourth sub-metal layers may be arranged to have a folded shape in cross-section. Compared to a typical capacitor, a capacitor including a first metal layer and a second metal layer, both having folded shapes, may have an increased surface area, thereby exhibiting high capacitance characteristics. Therefore, the display panel according to the embodiments, which includes a capacitor exhibiting high capacitance characteristics, can exhibit excellent display quality. In the embodiments, electronic devices including the display panel can exhibit excellent reliability due to the reduced chance of foreign object defects during manufacturing.

[0205] The display panel and the electronic device including the display panel according to the embodiment may include a capacitor including a second sub-metal layer and a fourth sub-metal layer, thereby exhibiting excellent reliability and excellent display quality.

[0206] The method for manufacturing a display panel according to an embodiment may include forming a second sub-metal layer and a fourth sub-metal layer to manufacture a display panel exhibiting excellent manufacturability.

[0207] The embodiments of this disclosure have been described above with reference to them. However, it will be understood by those skilled in the art or those of ordinary skill that various modifications and changes can be made to this disclosure, as long as such modifications and changes do not depart from the spirit and technical scope of the disclosure set forth in the described claims.

[0208] Therefore, the scope of the disclosed technology is not limited to what is stated in the specific embodiments of the specification, but should be determined by the claims.

Claims

1. A display panel comprising a base layer, a circuit layer provided on the base layer, and a display element layer provided on the circuit layer, wherein the circuit layer comprising a first insulating layer, a second insulating layer, a third insulating layer, a capacitor including a first metal layer and a second metal layer, and a transistor, wherein a first trench is defined in the first insulating layer, wherein the second insulating layer is provided on the first insulating layer, and a second trench and a third trench spaced apart from each other in a first direction perpendicular to a thickness direction are defined in the second insulating layer, wherein the third insulating layer is provided on the second insulating layer, and a fourth trench is defined in the third insulating layer, wherein the first trench and the second trench are aligned with each other, and the third trench and the fourth trench are aligned with each other, wherein the first metal layer includes a first sub-metal layer and a second sub-metal layer provided at least partially on the first sub-metal layer, wherein the second sub-metal layer includes a first portion separated from the first sub-metal layer with the first insulating layer and the second insulating layer provided therebetween, and a second portion extending from the first portion and provided within the first trench and the second trench, wherein the second metal layer includes a third sub-metal layer provided on the first sub-metal layer, and a fourth sub-metal layer provided at least partially on the third sub-metal layer, wherein the fourth sub-metal layer includes a third portion separated from the third sub-metal layer with the second insulating layer and the third insulating layer provided therebetween, and a fourth portion extending from the third portion and provided within the third trench and the fourth trench, wherein each of the second portion and the fourth portion extends in a second direction perpendicular to the thickness direction in a plane.

2. The display panel of claim 1, wherein, the second portion of the second sub-metal layer is provided between the first sub-metal layer and the first portion of the second sub-metal layer, and electrically connects the first sub-metal layer to the first portion of the second sub-metal layer.

3. The display panel of claim 1, wherein, the fourth portion of the fourth sub-metal layer is provided between the third sub-metal layer and the third portion of the fourth sub-metal layer, and electrically connects the third sub-metal layer to the third portion of the fourth sub-metal layer.

4. The display panel of claim 1, wherein, the first portion of the second sub-metal layer and the third portion of the fourth sub-metal layer are provided in different layers.

5. The display panel of claim 1, wherein, the first portion of the second sub-metal layer and the fourth portion of the fourth sub-metal layer are separated from each other in the first direction, and a region of the third insulating layer is provided between the first portion and the fourth portion.

6. The display panel of claim 1, wherein, the second portion of the second sub-metal layer and the third sub-metal layer are separated from each other in the first direction, and a region of the second insulating layer is provided between the third sub-metal layer and the second portion.

7. The display panel of claim 1, wherein, the first insulating layer has a single layer structure, and the first insulating layer is directly provided between the first sub-metal layer and the third sub-metal layer.

8. The display panel of claim 1, wherein, The second insulating layer has a single-layer structure, and the second insulating layer is directly provided between the third sub-metal layer and the first portion of the second sub-metal layer.

9. The display panel of claim 1, wherein, The third insulating layer has a single-layer structure, and the third insulating layer is directly provided between the first portion of the second sub-metal layer and the third portion of the fourth sub-metal layer.

10. The display panel of claim 1, wherein, The transistor includes an oxide semiconductor pattern and a gate electrode provided over the oxide semiconductor pattern.

11. The display panel of claim 10, wherein, The gate electrode is at least a portion of the first sub-metal layer.

12. The display panel of claim 10, wherein, The gate electrode, the first portion of the second sub-metal layer, the third sub-metal layer, and the third portion of the fourth sub-metal layer are stacked with each other.

13. The display panel of claim 1, wherein, The display element layer includes a light emitting element and a pixel defining film in which an emission opening is defined, wherein the light emitting element includes a first electrode having at least a portion in the emission opening, a second electrode provided over the first electrode, and an emission layer provided between the first electrode and the second electrode.

14. A method for manufacturing a display panel, the method comprising the steps of: preparing a base layer; forming a circuit layer over the base layer, the circuit layer including a first insulating layer, a second insulating layer, a third insulating layer, a capacitor including a first metal layer and a second metal layer, and a transistor; and forming a display element layer over the circuit layer, wherein the first metal layer includes a first sub-metal layer and a second sub-metal layer at least partially provided over the first sub-metal layer, wherein the second metal layer includes a third sub-metal layer provided over the first sub-metal layer and a fourth sub-metal layer at least partially provided over the third sub-metal layer, wherein the step of forming the circuit layer includes forming the first sub-metal layer over the base layer, forming a preliminary first insulating layer over the first sub-metal layer, forming the third sub-metal layer over the preliminary first insulating layer, forming the first insulating layer having a first trench defined therein from the preliminary first insulating layer, and forming a preliminary second insulating layer having a second trench aligned with the first trench over the third sub-metal layer, forming the second sub-metal layer over the preliminary second insulating layer including filling the first trench and the second trench with a material of the second sub-metal layer, forming the second insulating layer from the preliminary second insulating layer having the second trench and a third trench, and forming the third insulating layer having a fourth trench over the second sub-metal layer, and forming the fourth sub-metal layer over the third insulating layer including filling the third trench and the fourth trench with a material of the fourth sub-metal layer, wherein the second trench and the third trench are spaced apart from each other in a first direction perpendicular to a thickness direction, The second sub-metal layer includes a first portion separated from the first sub-metal layer, and the first insulating layer and the second insulating layer are arranged between the first portion and the first sub-metal layer, and a second portion extending from the first portion and arranged in the first trench and the second trench, The fourth sub-metal layer includes a third portion separated from the third sub-metal layer, and the second insulating layer and the third insulating layer are arranged between the third portion and the third sub-metal layer, and a fourth portion extending from the third portion and arranged in the third trench and the fourth trench, Each of the second portion and the fourth portion extends in a second direction perpendicular to the thickness direction in a plane.

15. An electronic device, the electronic device including a display panel configured to provide an image and a processor, the display panel being the display panel according to any one of claims 1 to 13.

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