Display panel, electronic device, and method for manufacturing display panel

Abstract

A display panel, an electronic device, and a method for manufacturing the display panel are provided. The display panel includes: a light emitting element on a base layer; and a pixel driving circuit electrically connected to the light emitting element. The pixel driving circuit includes: a first transistor including a first oxide semiconductor pattern; and a second transistor including a second oxide semiconductor pattern. The first oxide semiconductor pattern includes a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the second oxide semiconductor pattern includes a second channel region including a single-layer oxide semiconductor layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0122878, filed on September 10, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments described herein relate to a display panel with improved display characteristics, an electronic device including the display panel, and a method for manufacturing the display panel. Background Technology

[0003] The display device includes a display panel, and the display panel includes a plurality of pixels and pixel driving circuitry (e.g., scan driving circuitry and data driving circuitry) for controlling electrical signals applied to the pixels. The pixel driving circuitry may include a plurality of transistors systematically connected to each other. The transistors may include silicon semiconductors or oxide semiconductors. Summary of the Invention

[0004] The disclosed embodiments provide a display panel and an electronic device including the display panel, the display panel including oxide transistors having a wide range of high mobility and driving voltage.

[0005] The disclosed embodiments provide a method for manufacturing a display panel including oxide transistors.

[0006] According to a disclosed embodiment, a display panel may include: a light-emitting element on a substrate layer; and a pixel driving circuit electrically connected to the light-emitting element. The pixel driving circuit may include: a first transistor including a first oxide semiconductor pattern; and a second transistor including a second oxide semiconductor pattern. The first oxide semiconductor pattern may include a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the second oxide semiconductor pattern may include a second channel region including a single layer of oxide semiconductor layer.

[0007] The first transistor may further include: a first gate disposed on the second oxide semiconductor layer and stacked with the first channel region in a plan view; and a first gate insulating layer disposed between the first gate and the second oxide semiconductor layer.

[0008] The second oxide semiconductor layer and the single-layer oxide semiconductor layer may contain the same semiconductor material.

[0009] The second transistor can output a data voltage, and the first transistor can control the driving current of the light-emitting element to correspond to the data voltage.

[0010] The first oxide semiconductor pattern may have a thickness greater than or equal to about 250 Å, and the second oxide semiconductor pattern may have a thickness less than or equal to about 200 Å.

[0011] The first oxide semiconductor layer and the second oxide semiconductor layer may include different oxide semiconductors, and the first oxide semiconductor layer may include indium gallium zinc oxide (IGZO).

[0012] The second oxide semiconductor layer may include indium tin gallium zinc oxide (ITGZO).

[0013] In the second oxide semiconductor layer, the indium in indium tin gallium zinc oxide (ITiGaZ) may have a composition ratio in the range of about 60 wt% to about 80 wt%, the tin in ITiGaZ may have a composition ratio in the range of about 0.5 wt% to about 8 wt%, the gallium in ITiGaZ may have a composition ratio in the range of about 5 wt% to about 15 wt%, and the zinc in ITiGaZ may have a composition ratio in the range of about 10 wt% to about 30 wt%.

[0014] The display panel may further include: a lower metal layer disposed between the substrate layer and the first transistor; and a buffer layer disposed between the lower metal layer and the first oxide semiconductor pattern. The first oxide semiconductor pattern and the second oxide semiconductor pattern may be disposed on the buffer layer.

[0015] The source of the first transistor can be electrically connected to the lower metal layer.

[0016] The first connection electrode connecting the source of the first transistor to the lower metal layer and the second connection electrode connecting to the source of the second transistor can be disposed on the same layer.

[0017] Each of the first and second transistors can have a top-gate structure.

[0018] According to a disclosed embodiment, an electronic device may include: a light-emitting element on a substrate layer; and a pixel driving circuit electrically connected to the light-emitting element. The pixel driving circuit may include: a first transistor including a first oxide semiconductor pattern; and a second transistor including a second oxide semiconductor pattern. The first oxide semiconductor pattern may include a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the second oxide semiconductor pattern may include a second channel region including a single layer of oxide semiconductor layer.

[0019] The first oxide semiconductor pattern may have a thickness greater than or equal to about 250 Å, and the second oxide semiconductor pattern may have a thickness less than or equal to about 200 Å.

[0020] The first oxide semiconductor layer and the second oxide semiconductor layer may include different oxide semiconductors, and the first oxide semiconductor layer may include indium gallium zinc oxide (IGZO).

[0021] According to a disclosed embodiment, a method for manufacturing a display panel may include the following steps: forming a first oxide semiconductor layer on a substrate layer; forming a second oxide semiconductor layer on the substrate layer, the second oxide semiconductor layer including a first region superimposed on the first oxide semiconductor layer in a plan view and a second region not superimposed on the first oxide semiconductor layer; forming a first gate, the first gate being superimposed on the first region of the second oxide semiconductor layer in a plan view; forming a second gate, the second gate being superimposed on the second region of the second oxide semiconductor layer in a plan view; and forming an insulating layer to cover the first gate and the second gate.

[0022] The first oxide semiconductor layer may have a thickness greater than or equal to about 50 Å, and the second oxide semiconductor layer may have a thickness less than or equal to about 200 Å.

[0023] The method may further include the following steps: forming a lower metal layer between the substrate layer and the first oxide semiconductor layer; and forming a buffer layer to cover the lower metal layer and the substrate layer.

[0024] The step of forming the first gate may include: forming a first channel region, a first source region, and a first drain region from a second oxide semiconductor layer, wherein the first channel region is superimposed on the first gate in a plan view, and the first source region and the first drain region are disposed on opposite sides of the first channel region.

[0025] The lower metal layer can be superimposed on the first region in the plan view, and the lower metal layer and the first source region can be electrically connected to each other. Attached Figure Description

[0026] The above and other objects and features disclosed will become apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings.

[0027] Figure 1 This is a perspective view of a display device according to a disclosed embodiment.

[0028] Figure 2 yes Figure 1 A schematic cross-sectional view of the display device shown.

[0029] Figure 3 yes Figure 2 A schematic cross-sectional view of the display panel shown.

[0030] Figure 4 yes Figure 1 A schematic block diagram of the display device shown.

[0031] Figure 5A yes Figure 4 A schematic diagram of the equivalent circuit of one of the pixels shown.

[0032] Figure 5B yes Figure 4 A schematic diagram of the equivalent circuit of one of the pixels shown.

[0033] Figure 5C yes Figure 4 A schematic diagram of the equivalent circuit of one of the pixels shown.

[0034] Figure 6 It is used to describe Figure 5A The diagram shows a schematic timing sequence of the scanning and emission signals for the operation of the pixels.

[0035] Figure 7 This is a schematic cross-sectional view showing a portion of the display panel.

[0036] Figure 8A and Figure 8B It is a secondary ion mass spectrometry (SIMS) curve showing the variation of hydrogen content in the first channel region of the first transistor and the second channel region of the second transistor, according to the disclosure.

[0037] Figures 9A to 9K This is a schematic cross-sectional view illustrating a method for manufacturing a display panel according to a disclosed embodiment.

[0038] Figure 10 This is a block diagram of an electronic device according to a disclosed embodiment.

[0039] Figure 11 These are schematic diagrams of various electronic devices according to the disclosed embodiments. Detailed Implementation

[0040] When a layer or element is referred to as being "on," "connected to," or "bonded to" another element or layer, the layer or element may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, when an element is referred to as being "in contact" or "in contact with" another element, the element may be in "electrical contact" or "physical contact" with the other element; or in "indirect contact" or "direct contact" with the other element.

[0041] The same reference numerals will be assigned to the same components. Crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities and / or any other characteristics, properties, etc., of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0042] In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the groups...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood to be equivalent to "and / or".

[0043] Although the terms “first” or “second” can be used to describe various components, the components should not be construed as being limited by the terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of the disclosure, the first component can be referred to as the second component, and similarly, the second component can be referred to as the first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0044] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in a “sidewall”) may be used herein to describe the relationship of one element to another (or other) elements as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would subsequently be oriented “above” said other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0045] Unless otherwise expressly stated, the term "about" can include variations from a specified value, such as ±20%, ±10%, or ±5%. In some contexts, the term can interpret rounding, inherent measurement limitations, or standard tolerances recognized in the relevant art. When applied to dimensions, concentrations, or other quantifiable parameters, "about" can include minor deviations that would be understood by one of ordinary skill in the art as non-material in a given context. The scope of "about" should be interpreted in light of standard laboratory or clinical tolerances applicable to the field of use. Those skilled in the art will recognize that "about" allows for practical deviations that do not materially alter the intended nature of the invention. Similarly, for mechanical dimensions, "about" can include deviations within industry-accepted tolerances that do not materially affect the disclosed performance.

[0046] It will also be understood that the terms “comprising,” “including,” and variations thereof, or “having,” and variations thereof, indicate the presence of the stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0047] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this publication pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with that in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0048] In the following description, the disclosed embodiments will be illustrated with reference to the accompanying drawings.

[0049] Figure 1 This is a perspective view of a display device DD according to a disclosed embodiment. Figure 1As shown, the display device DD in the plan view can be rectangular in shape, having a long side extending parallel to the first direction DR1 and a short side extending in the second direction DR2 intersecting the first direction DR1. However, the disclosure is not limited thereto. For example, the display device DD in the plan view can have various shapes such as circles or polygons.

[0050] In the following description, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. In this specification, the term "in a plan view" may refer to the state when viewed from the third direction DR3. In other words, the term "in a plan view" will be described based on the plan view defined by the first direction DR1 and the second direction DR2. In this specification, the term "in a sectional view" may refer to the state when viewed from either the first direction DR1 or the second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts and can be changed to different directions.

[0051] The front surface of the display device DD can be defined as a display surface DS, and can be parallel to the plane defined by the first direction DR1 and the second direction DR2. The image IM generated from the display device DD can be provided to the user through the display surface DS.

[0052] The display surface DS may include a display area DA and a non-display area NDA adjacent to the display area DA. The display area DA may be an area in which an image is displayed, and the non-display area NDA may be an area in which no image is displayed. The non-display area NDA may be adjacent to at least one side of the display area DA. According to an embodiment, the non-display area NDA may have the form of a frame surrounding the display area DA.

[0053] The display device DD can sense input applied from outside the display device DD. For example, the display device DD can sense a first input via a stylus PEN and a second input via a touch TC. The stylus PEN can be an input device. In addition to displaying an image, the display area DA can also provide the user with a sensing area for sensing input.

[0054] The stylus pen (PEN) can be an active pen or an electromagnetic pen. Secondary input via the touchscreen (TC) can include various external inputs, such as a part of the user's body, light, heat, or pressure. The stylus pen (PEN) can be an active pen, a passive pen, or an electromagnetic pen, but the disclosure is not limited to any one embodiment.

[0055] Display devices (DDs) can be applied to large electronic items such as televisions, monitors, or outdoor billboards. Display devices (DDs) can also be applied to small to medium-sized electronic items such as personal computers, laptops, personal digital assistants, car navigation units, gaming units, smartphones, tablets, or cameras. However, the disclosure is not limited to these, and display devices (DDs) can be used in various forms.

[0056] Figure 2 It is shown Figure 1 A schematic cross-sectional view of the display device DD shown. Figure 3 It is shown Figure 2 A schematic cross-sectional view of the display panel DP shown. (Refer to...) Figure 2 and Figure 3 The description is public.

[0057] Reference Figure 2 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, an adhesive layer PSA, and a window WM.

[0058] The display panel DP according to the disclosed embodiments may be an emissive display panel, but the disclosure is not specifically limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, an organic light-emitting display panel will be described as a display panel DP.

[0059] The input sensing unit (ISP) can be directly mounted on the display panel (DP). The ISP can sense user input using, for example, electromagnetic induction and / or capacitive methods. The ISP can be directly mounted on the display panel (DP). Here, "directly mounted" can mean that a third component is not placed between the ISP and the display panel (DP), and the additional adhesive layer may not be placed between the ISP and the display panel (DP). The display panel (DP) and the ISP can be formed through a continuous process.

[0060] In one embodiment, the conductive pattern or insulating layer constituting the input sensing unit ISP can be directly deposited on the display panel DP or patterned. However, the disclosure is not limited thereto. For example, the input sensing unit ISP can be manufactured as a panel separate from the display panel DP, and can be bonded to the display panel DP via an adhesive layer.

[0061] An anti-reflective layer RPL can be disposed on the input sensing unit ISP. The anti-reflective layer RPL can reduce the reflectivity of external light incident on the display device DD, thereby improving the visibility of the image displayed on the display device DD. The anti-reflective layer RPL may include a phase retarder, polarizer, black matrix, or color filter, but the disclosure is not limited to any one embodiment. The anti-reflective layer RPL can be formed directly on the input sensing unit ISP by a coating process or a deposition process, or it can be provided in the form of a film and bonded to the input sensing unit ISP by an adhesive layer, but the disclosure is not limited thereto.

[0062] The adhesive layer PSA can be placed between the anti-reflective layer RPL and the window WM, and the anti-reflective layer RPL and the window WM can be bonded to each other through the adhesive layer PSA. However, the disclosure is not limited thereto. According to another embodiment, the adhesive layer PSA can be omitted.

[0063] The window WM can be disposed on the anti-reflective layer RPL. The window WM can protect the display panel DP, input sensing unit ISP, and anti-reflective layer RPL from external scratches and impacts. According to an embodiment, the window WM can be formed by coating. The window WM can be disposed directly on the display panel DP.

[0064] Reference Figure 3 The display panel DP may include a substrate layer BS, a circuit element layer DP-CL on the substrate layer BS, a display element layer DP-OLED on the circuit element layer DP-CL, and a thin film encapsulation layer TFE on the display element layer DP-OLED.

[0065] The substrate layer BS may include a display area DA and a non-display area NDA adjacent to the display area DA. The substrate layer BS may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite substrate.

[0066] The circuit element layer DP-CL and the display element layer DP-OLED can be disposed on the substrate layer BS. Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor in the circuit element layer DP-CL and a light-emitting element in the display element layer DP-OLED and connected to the transistor.

[0067] A thin-film encapsulation layer (TFE) can be disposed on the circuit element layer (DP-CL) and cover the display element layer (DP-OLED). The TFE protects the pixels from moisture, oxygen, and foreign matter. According to an embodiment, although the TFE covers the entire area of ​​the substrate layer (BS), the substrate layer (BS) may include a portion exposed from the TFE. In another embodiment, the area exposed from the TFE may be formed along the edge of the substrate layer (BS), but the disclosure is not limited to any one embodiment.

[0068] Figure 4 This is a schematic block diagram of a display device DD according to a disclosed embodiment. The display device DD may include a display panel DP, a timing controller TC, a scan drive circuit SDC, a data drive circuit DDC, a light emission drive circuit EDC, and a voltage generator VG.

[0069] The display panel DP may include multiple scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, multiple light emission lines EML1 to EMLm, multiple data lines DL1 to DLn and multiple pixels PX. “m” and “n” can be positive integers.

[0070] Pixel PX can be electrically connected to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, light emission lines EML1 to EMLm, and data lines DL1 to DLn. Each pixel PX can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding light emission line.

[0071] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include multiple initialization scan lines GIL1 to GILm, multiple compensation scan lines GCL1 to GCLm, multiple write scan lines GWL1 to GWLm, and multiple bias scan lines GBL1 to GBLm.

[0072] Each pixel PX can be connected to one of the initialization scan lines GIL1 to GILm, one of the compensation scan lines GCL1 to GCLm, one of the write scan lines GWL1 to GWLm, and one of the bias scan lines GBL1 to GBLm.

[0073] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm can be connected to the scan drive circuit SDC and can be arranged on the second direction DR2, while extending on the first direction DR1. Emitting lines EML1 to EMLm can be connected to the emitting drive circuit EDC and can be arranged on the second direction DR2, while extending on the first direction DR1. Data lines DL1 to DLn can be connected to the data drive circuit DDC and can be arranged on the first direction DR1, while extending on the second direction DR2.

[0074] According to an embodiment, the scan driving circuit SDC, the light-emitting driving circuit EDC, and the data driving circuit DDC can be substantially disposed in the display panel DP. However, the disclosure is not limited thereto. For example, at least one of the scan driving circuit SDC, the light-emitting driving circuit EDC, and the data driving circuit DDC can be disposed in an additional circuit board and electrically connected to the display panel DP, and electrical signals can be applied to the pixel PX. However, the disclosure is not limited to any one embodiment.

[0075] The timing controller TC can receive image signals RGB and control signals CTRL. The timing controller TC can generate an image data signal DAS by transforming the data format of the image signals RGB to match the interface specifications of the data drive circuit DDC. The timing controller TC can output a scan control signal SCS, a data control signal DCS, and an illumination control signal ECS in response to the control signal CTRL.

[0076] The scan drive circuit SDC can receive the scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal for initiating operation of the scan drive circuit SDC and a clock signal for determining the output timing of the signals.

[0077] The scan drive circuit SDC can generate a scan signal in response to the scan control signal SCS, and can output the scan signal to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signal can be applied to pixel PX through scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0078] The data drive circuit (DDC) receives data control signals (DCS) and image data signals (DAS) from the timing controller (TC). The DDC converts the image data signal (DAS) into a data signal and outputs it. The data signal can be defined as an analog voltage corresponding to the grayscale level of the image data signal (DAS). The data signal can be applied to pixel PX via data lines DL1 to DLn.

[0079] The light-emitting drive circuit (EDC) can receive the light-emitting control signal (ECS) from the timing controller (TC). In response to the ECS, the EDC can output light-emitting signals to the light-emitting lines EML1 to EMLm. These light-emitting signals can be applied to the pixel PX through the light-emitting lines EML1 to EMLm.

[0080] A pixel (PX) can receive a data voltage in response to a scan signal. A pixel (PX) can also display an image by emitting light of a brightness corresponding to the data voltage in response to a light emission signal.

[0081] The voltage generator VG generates voltages for the operation of the display panel DP. The voltage generator VG generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. These voltages can be applied to pixels PX.

[0082] Figures 5A to 5C yes Figure 4 A schematic diagram of the equivalent circuit of one of the pixels PX shown. Figure 6 This is a schematic timing diagram illustrating the scanning and emission signals of pixels according to a disclosed embodiment. For ease of explanation, Figure 6 yes Figure 5A A schematic timing diagram of pixel PXij. In the following text, reference will be made to... Figures 5A to 6 Describe the pixels in more detail.

[0083] For example, Figure 5A The diagram schematically illustrates a pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi. "i" and "j" can be positive integers.

[0084] Reference Figure 5A Pixel PXij may include a pixel driving circuit PC and a light-emitting element OLED connected to the pixel driving circuit PC. The pixel driving circuit PC can drive the light-emitting element OLED.

[0085] The pixel driving circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST control the amount of current flowing through the light-emitting element (OLED). The OLED can then generate light with brightness based on the provided current.

[0086] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCI. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th emission line EMLi can receive the i-th emission signal EMi.

[0087] Pixel PXij can be connected to the j-th data line DLj, the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0088] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS. The first power supply line PL1 can receive the first drive voltage ELVDD, and the second power supply line PL2 can receive the second drive voltage ELVSS.

[0089] Each of the first transistor T1 to the eighth transistor T8 may include a source electrode, a drain electrode, and a gate electrode. In the following text, when referring to… Figures 5A to 5C For ease of explanation, one of the source electrode and the drain electrode will be defined as the first electrode, and the remaining one of the source electrode and the drain electrode will be defined as the second electrode. The gate electrode can be defined as the control electrode.

[0090] Transistors T1 to T8 may include first transistor T1 to eighth transistor T8. First transistor T1, second transistor T2, and fifth transistor T5 to eighth transistor T8 may be PMOS transistors. Third transistor T3 and fourth transistor T4 may be NMOS transistors.

[0091] The first transistor T1 can be a driving transistor, and the second transistor T2 can be a switching transistor. The third transistor T3 can be a compensation transistor. The fourth transistor T4 and the seventh transistor T7 can be initialization transistors. The fifth transistor T5 and the sixth transistor T6 can be light-emitting control transistors. The eighth transistor T8 can be a bias transistor.

[0092] The light-emitting element (OLED) can be an organic light-emitting element. The OLED can include an anode (AE) and a cathode (CE). The anode (AE) can receive a first driving voltage (ELVDD) through a sixth transistor (T6), a first transistor (T1), and a fifth transistor (T5). The first driving voltage (ELVDD) can be applied to the pixel driving circuit (PC) through a first power line (PL1).

[0093] The cathode CE can receive a second driving voltage ELVSS with a level lower than the first driving voltage ELVDD. The second driving voltage ELVSS can be applied to the pixel driving circuit PC through the second power line PL2.

[0094] The first transistor T1 can be placed between the fifth transistor T5 and the sixth transistor T6, and connected to both the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can be connected to the first power supply line PL1 through the fifth transistor T5, and can be connected to the anode AE ​​through the sixth transistor T6.

[0095] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the anode AE ​​via a sixth transistor T6, and a control electrode connected to the first node N1.

[0096] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1 at the first node N1.

[0097] The second transistor T2 can be placed between the first transistor T1 and the j-th data line DLj, and can be connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWLi.

[0098] The second transistor T2 can be turned on in response to the i-th write scan signal GWi applied through the i-th write scan line GWLi, so as to electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage Vd received through the j-th data line DLj to the first electrode of the first transistor T1.

[0099] The third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0100] The third transistor T3 can be turned on in response to the i-th compensation scan signal GCI received through the i-th compensation scan line GCLi, so as to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 can be connected in the form of a diode.

[0101] A fourth transistor T4 may be connected to a first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to a first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on in response to an i-th initialization scan signal GIi received via the i-th initialization scan line GCLi, to provide a first initialization voltage VINT received via the first initialization line VIL1 to the first node N1.

[0102] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light-emitting line EMLi.

[0103] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light-emitting line EMLi.

[0104] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the i-th emission signal EMi received through the i-th emission line EMLi. The first driving voltage ELVDD can be provided to the light-emitting element OLED in response to the turned-on fifth transistor T5 and sixth transistor T6, so that driving current can flow through the light-emitting element OLED. Therefore, the light-emitting element OLED can emit light.

[0105] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBi received through the i-th bias scan line GBLi to provide the second initialization voltage VAINT received through the second initialization line VIL2 to the anode AE ​​of the light-emitting element OLED.

[0106] According to the disclosed embodiments, the levels of the second initialization voltage VAINT and the first initialization voltage VINT may be different from each other, but the disclosure is not limited thereto. In another embodiment, the second initialization voltage VAINT and the first initialization voltage VINT may have the same level.

[0107] The seventh transistor T7 can improve the black representation capability of pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the OLED light-emitting element can discharge. Therefore, when achieving black brightness, the OLED light-emitting element may not emit light due to the leakage current of the first transistor T1. Thus, the black representation capability can be improved.

[0108] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CST.

[0109] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0110] The eighth transistor T8 can be turned on in response to the i-th bias scan signal GBi, and can provide the bias voltage VBIAS received through the bias line VBL to the first electrode of the first transistor T1.

[0111] Reference Figure 5A and Figure 6 The i-th emission signal EMi can have a high level during the non-emission period NLP and a low level during the emission period LP.

[0112] When each of the i-th write scan signal GWi and the i-th bias scan signal GBi is at a low level, the i-th write scan signal GWi and the i-th bias scan signal GBi can be defined as active.

[0113] When each of the i-th compensation scan signal GCI and the i-th initialization scan signal GII is at a high level, the i-th compensation scan signal GCI and the i-th initialization scan signal GII can be defined as active.

[0114] After activating the i-th initialization scan signal GIi, the i-th compensation scan signal GCI and the i-th write scan signal GWi can be activated. Subsequently, the i-th bias scan signal GBi can be activated.

[0115] During the non-light-emitting NLP period, the activated i-th initialization scan signal GIi, the i-th compensation scan signal GCI, the i-th write scan signal GWi, and the i-th bias scan signal GBi can be applied to pixel PXij.

[0116] When the i-th initialization scan signal GIi is applied to the fourth transistor T4, the fourth transistor T4 can be turned on. The first initialization voltage VINT can be provided to the first node N1 through the fourth transistor T4. Therefore, the first initialization voltage VINT can be applied to the control electrode of the first transistor T1, and the first transistor T1 can be initialized in response to the first initialization voltage VINT. Such an operation can be defined as an initialization operation.

[0117] When the i-th write scan signal GWi is applied to the second transistor T2, the second transistor T2 can be turned on. When the i-th compensation scan signal GCI is applied to the third transistor T3, the third transistor T3 can be turned on.

[0118] The first transistor T1 and the third transistor T3 can be connected to each other as diodes, and a compensation voltage "Vd-Vth" obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data voltage Vd received through the j-th data line DLj can be applied to the gate electrode of the first transistor T1. Such an operation can be defined as a write operation and a compensation operation.

[0119] A first driving voltage ELVDD and a compensation voltage “Vd-Vth” can be applied to the first and second electrodes of capacitor CST. Capacitor CST can store a charge corresponding to the difference between the voltage at the first electrode of capacitor CST and the voltage at the second electrode of capacitor CST.

[0120] Subsequently, as the i-th bias scan signal GBi is applied to the seventh transistor T7 and the eighth transistor T8, the seventh transistor T7 and the eighth transistor T8 can be turned on. As the second initialization voltage VAINT is applied to the anode AE ​​through the seventh transistor T7, the anode AE ​​can be initialized to the second initialization voltage VAINT. The bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8.

[0121] Subsequently, during the light-emitting period LP, as the i-th light-emitting signal EMi is applied to the fifth transistor T5 and the sixth transistor T6 through the i-th light-emitting line EMLI, the fifth transistor T5 and the sixth transistor T6 can be turned on. A drive current Id corresponding to the difference between the voltage of the control electrode of the first transistor T1 and the first drive voltage ELVDD can be generated. As the drive current Id is applied to the light-emitting element OLED through the sixth transistor T6, the light-emitting element OLED can emit light.

[0122] The gate-source voltage (Vgs) of the first transistor T1 can be defined by the capacitor CST during the light-emitting period LP as "Vgs = ELVDD - (Vd - Vth)". The relationship between the current and voltage of the first transistor T1 can be defined as follows: This relationship is typical of the relationship between current and voltage in a transistor.

[0123] By substituting the gate-source voltage (Vgs) into the relationship between current and voltage, the threshold voltage (Vth) can be removed, and the drive current Id can be the square root of the value obtained by subtracting the data voltage Vd from the first drive voltage ELVDD. This is proportional to the threshold voltage (Vth) of the first transistor T1. Therefore, the drive current Id can be determined independently of the threshold voltage (Vth) of the first transistor T1. Such an operation can be defined as a threshold voltage compensation operation.

[0124] A bias voltage VBIAS can be applied to the first electrode of the first transistor T1 via the eighth transistor T8 after the threshold voltage of the first transistor T1 has been compensated and before the OLED emits light. The bias voltage VBIAS can suppress the shift in the hysteresis curve of the first transistor T1. Such an operation can be defined as a bias operation.

[0125] Reference Figure 5BPixel PXij-1 may include a pixel driving circuit PC-1 and an OLED light-emitting element connected to the pixel driving circuit PC-1. The pixel driving circuit PC-1 may include six transistors T11, T21, T31, T41, T51 and T61 and two capacitors CST and CHD.

[0126] The first transistor T11 can be a driving transistor, and the second transistor T21 can be a switching transistor.

[0127] The third transistor T31 can be a reset transistor. The third transistor T31 can respond to the scan drive circuit SDC (see...). Figure 4 The received reset signal GRi provides the reference voltage VREF to the first node N1. The first node N1 can be reset to the reference voltage VREF to minimize the effect of the remaining voltage in the previous stage.

[0128] The fourth transistor T41 can be an anode-initialized transistor. The fourth transistor T41 can correspond to... Figure 5A The seventh transistor T7 shown (see Figure 5A The fourth transistor T41 can initialize the anode AE ​​of the OLED element using the second initialization voltage VAINT in response to the i-th initialization scan signal GIi.

[0129] The fifth transistor T51 and the sixth transistor T61 can be light-emitting control transistors. According to an embodiment, the fifth transistor T51 and the sixth transistor T61 can be driven by different light-emitting control signals. For example, the fifth transistor T51 can transmit a first driving voltage ELVDD to the first transistor T11 in response to a first light-emitting signal EMi, while the sixth transistor T61 can be turned on in response to a second light-emitting signal EMBi. According to an embodiment, the fifth transistor T51 and the sixth transistor T61 can be turned on or off at different times to be driven independently of each other. According to an embodiment, the first light-emitting signal EMi can correspond to... Figure 5A The i-th emission signal EMi, and the second emission signal EMBi can be independent of Figure 5A The first light-emitting signal EMi is the signal in the image. However, the disclosure is not limited thereto. In another embodiment, the first light-emitting signal EMi and the second light-emitting signal EMBi can be applied at the same time.

[0130] Reference Figure 5CPixel PXij-2 may include a pixel driving circuit PC-2 and an OLED light-emitting element connected to the pixel driving circuit PC-2. The pixel driving circuit PC-2 may include seven transistors T12, T22, T32, T42, T52, T62, and T72, and two capacitors CST and CHD. The first transistor T12 may be a driving transistor, and the second transistor T22 may be a switching transistor. The third transistor T32 may be a reset transistor, and the fourth transistor T42 may be an anode initialization transistor. The fifth transistor T52 and the sixth transistor T62 may be light-emitting control transistors.

[0131] and Figure 5B Compared to the previous embodiment, the pixel driving circuit PC-2 may further include a seventh transistor T72. The seventh transistor T72 may be positioned between the first driving voltage ELVDD and the first electrode of the first transistor T12. The seventh transistor T72 may provide the first driving voltage ELVDD to the first transistor T12 in response to a reset signal GRi, and the seventh transistor T72 and the third transistor T32 may be turned on simultaneously in the same timing sequence. In other words, the first electrode of the first transistor T12 may receive the first driving voltage ELVDD in the timing sequence of the first node N1 reset.

[0132] The sixth transistor T62 can be driven in response to the i-th emitted light signal EMi. In other words, the sixth transistor T62 and the fifth transistor T52 can be turned on simultaneously in the same timing sequence.

[0133] Figure 7 This is a schematic cross-sectional view showing a portion of the display panel DP. Figure 7 The diagram schematically illustrates the area where two transistors TR1 and TR2 are disposed in the assembly containing each pixel PXij, PXij-1, and PXij-2, as well as the area of ​​the OLED light-emitting element. (Refer to...) Figure 7 The display panel DP may include a substrate layer BS, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0134] According to an embodiment, the matrix layer BS may include at least one synthetic resin layer. The synthetic resin layer included in the matrix layer BS may include at least one selected from acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, polyimide resin, and perylene resin.

[0135] The substrate layer BS can have a single-layer or multi-layer structure. For example, the substrate layer BS can include a stacked structure of multiple plastic films bonded by an adhesive, or it can have a stacked structure of a glass substrate and plastic films bonded by an adhesive.

[0136] According to an embodiment, the substrate layer BS can be a flexible substrate. When the substrate layer BS is a flexible substrate, it can be bendable, foldable, or rollable. However, the disclosure is not limited thereto. In another embodiment, the substrate layer BS can be arranged in a rigid state, and it is not limited to any one of the embodiments.

[0137] The circuit element layer DP-CL can be disposed on the substrate layer BS. The circuit element layer DP-CL may include circuit elements and multiple insulating layers 10, 20, 30, 40, and 50. The two transistors T1 and T2 described below can be elements constituting the circuit element layer DP-CL. Although... Figure 7 The diagram shows insulating layers 10, 20, 30, 40, and 50 comprising a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50 sequentially stacked on a substrate layer BS, but the disclosure is not limited thereto. The number of insulating layers constituting the circuit element layer DP-CL can vary, and the disclosure is not limited to any particular embodiment.

[0138] Two transistors TR1 and TR2 can be disposed on the substrate layer BS. The two transistors TR1 and TR2 may include a first transistor TR1 and a second transistor TR2. According to an embodiment, a first insulating layer 10 and a second insulating layer 20 can be disposed between the two transistors TR1 and TR2 and the substrate layer BS. According to an embodiment, the first transistor TR1 may be... Figures 5A to 5C The driving transistors T1, T11, or T12 shown, and the second transistor TR2 can be... Figures 5A to 5C The switching transistors T2, T21, or T22 are shown.

[0139] The first insulating layer 10 may be disposed on the substrate layer BS and integrally cover the top surface of the substrate layer BS. The first insulating layer 10 may include a barrier layer. In other words, the first insulating layer 10 can prevent oxygen or moisture that may be introduced through the substrate layer BS from being introduced into pixels PXij, PXij-1, and PXij-2.

[0140] The lower metal layer (BML) can also be placed between the first transistor TR1 and the substrate layer BS. The lower metal layer BML can be a light-blocking pattern and can include a black matrix or a reflective conductive material. For example, the lower metal layer BML can include a metallic material and can be stacked with the first transistor TR1 in a planar view to protect the semiconductor pattern of the first transistor TR1. The lower metal layer BML can be disposed below the first transistor TR1 to prevent potential from affecting the first transistor TR1 or to prevent external light from reaching the first transistor TR1.

[0141] According to one embodiment, the lower metal layer (BML) can be connected to an electrode or wiring to receive a constant voltage. According to another embodiment, the lower metal layer (BML) can be a floating electrode isolated from another electrode or wire.

[0142] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the lower metal layer BML. The second insulating layer 20 may integrally cover the substrate layer BS. The second insulating layer 20 may include a buffer layer. The buffer layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0143] In other words, the second insulating layer 20 can reduce the surface energy of the surface used to form the circuit element layer DP-CL, so that pixels PXij, PXij-1, and PXij-2 are stably formed on the substrate layer BS. At least one of the barrier layer and buffer layer may include multiple layers, or may be omitted. In the display panel according to the disclosed embodiments, the first insulating layer 10 and / or the second insulating layer 20 may be omitted, and the disclosure is not limited to any one embodiment.

[0144] The first transistor TR1 and the second transistor TR2 can be disposed on the second insulating layer 20. The first transistor TR1 may include a first oxide semiconductor pattern SP1 and a first gate G1. The first transistor TR1 may be a driving transistor in the current path between the first power line PL1 and the light-emitting element OLED to control the amount of current flowing through the light-emitting element OLED, but the disclosure is not limited thereto. The first oxide semiconductor pattern SP1 may include a first source region S1, a first drain region D1, and a first channel region A1.

[0145] The first oxide semiconductor pattern SP1 may include multiple regions with different electrical properties. The first oxide semiconductor pattern SP1 may include multiple regions divided according to whether the metal oxide is reduced. For example, the first oxide semiconductor pattern SP1 may include a first source region S1, a first drain region D1, and a first channel region A1 divided according to conductivity. For example, the first channel region A1 may be a region with lower conductivity than the first source region S1 and the first drain region D1, and may be a region with semiconductor properties. The first source region S1 and the first drain region D1 may be regions with higher conductivity than the first channel region A1. The first channel region A1 may be referred to as the first active region A1. For ease of explanation, the first oxide semiconductor pattern SP1 may be referred to as a semiconductor pattern, and the first source region S1 and the first drain region D1 may be referred to as the source and drain, respectively.

[0146] Each of the first source region S1 and the first drain region D1 can be formed by doping or reduction. For example, in a semiconductor pattern, a heavily doped region with a higher dopant concentration can have higher conductivity. A portion of the semiconductor pattern can be doped to form a source / drain, and the remaining region can be a channel. The dopant can be a P-type dopant or an N-type dopant, and the disclosure is not limited to any one embodiment.

[0147] The reduced regions of a semiconductor pattern can exhibit higher conductivity compared to the unreduced regions. Since the metal oxide constituting the semiconductor pattern is deposited as metal through a reduction process, the regions where the metal oxide can be reduced can be the source / drain regions, and the remaining regions can be the channel regions.

[0148] According to an embodiment, the first source region S1 and the first drain region D1 can be formed by a first oxide semiconductor pattern SP1. However, the disclosure is not limited thereto. In another embodiment, the source and drain of the first transistor TR1 can be provided by an additional conductive pattern connected to the first oxide semiconductor pattern SP1, and the disclosure is not limited to any one embodiment.

[0149] According to an embodiment, the first channel region A1 of the first oxide semiconductor pattern SP1 may have a multilayer structure. For example, the first channel region A1 may include a first oxide semiconductor layer SL1 and a second oxide semiconductor layer SL2 on the first oxide semiconductor layer SL1.

[0150] The first oxide semiconductor layer SL1 and the second oxide semiconductor layer SL2 may comprise different metal oxide semiconductor materials. For example, the first oxide semiconductor layer SL1 may comprise an oxide of a metal (such as zinc (Zn), indium (In), gallium (Ga), titanium (Ti)) or a mixture thereof.

[0151] According to an embodiment, the first oxide semiconductor layer SL1 may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), zinc indium oxide (ZIO), indium oxide (In2O3), or titanium oxide (TiO2).

[0152] The second oxide semiconductor layer SL2 may include oxides of metals (such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti)) or mixtures thereof.

[0153] According to embodiments, the second oxide semiconductor layer SL2 may include indium tin oxide (ITO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), or indium tin gallium zinc oxide (ITGZO). In the ITGZO of the second oxide semiconductor layer SL2, indium may have a composition ratio ranging from about 60 wt% to about 80 wt%, tin may have a composition ratio ranging from about 0.5 wt% to about 8 wt%, gallium may have a composition ratio ranging from about 5 wt% to about 15 wt%, and zinc may have a composition ratio ranging from about 10 wt% to about 30 wt%, but the disclosure is not limited thereto. The second oxide semiconductor layer SL2 may include oxides having various compositions as long as the second oxide semiconductor layer SL2 has a high mobility, and the disclosure is not limited to any one embodiment.

[0154] A first gate G1 may be disposed on a semiconductor pattern of a first transistor TR1. The first gate G1 may be stacked with a first channel region A1 in a planar view. A first insulating pattern 31 may be disposed between the first gate G1 and the semiconductor pattern. The first insulating pattern 31 may be patterned into a shape aligned with the first gate G1. The first insulating pattern 31 may be a gate insulating layer, and the first transistor TR1 may have a top-gate structure. However, the disclosure is not limited thereto. The first insulating pattern 31 may be configured as a layer with an integral shape to cover the entire area of ​​the substrate layer BS, and the first transistor TR1 may have a bottom-gate structure, but the disclosure is not limited thereto.

[0155] The second transistor TR2 may include a second oxide semiconductor pattern SP2 and a second gate G2. The second transistor TR2 may be a switching transistor for applying a data voltage to the first transistor TR1 in response to a scan signal applied to a scan line, but the disclosure is not limited thereto. The second oxide semiconductor pattern SP2 may include a second source region S2, a second drain region D2, and a second channel region A2.

[0156] According to an embodiment, the second channel region A2 of the second oxide semiconductor pattern SP2 may have a single-layer structure. For example, the second channel region A2 may include a single-layer oxide semiconductor layer SSL.

[0157] According to an embodiment, the second oxide semiconductor pattern SP2 and the second oxide semiconductor layer SL2 of the first oxide semiconductor pattern SP1 can be formed using the same process. Therefore, the single-layer oxide semiconductor layer SSL of the second oxide semiconductor pattern SP2 and the second oxide semiconductor layer SL2 can include the same material. For example, the single-layer oxide semiconductor layer SSL of the second oxide semiconductor pattern SP2 can include indium tin gallium zinc oxide (ITGZO) and can have the same component ratio as the second oxide semiconductor layer SL2. Details of components in the second oxide semiconductor pattern SP2 that perform the same function as the first oxide semiconductor pattern SP1 can be omitted to avoid redundancy.

[0158] The second gate G2 may be spaced apart from the second oxide semiconductor pattern SP2, while the second insulating pattern 32 is disposed between the second gate G2 and the second oxide semiconductor pattern SP2, and the second gate G2 may be disposed on the second oxide semiconductor pattern SP2. The second gate G2 may be stacked with the second channel region A2 in a planar view. Although similar to the first transistor TR1, the second transistor TR2 is shown with a top-gate structure, the disclosure is not limited thereto, and in another embodiment, the second transistor TR2 may have a bottom-gate structure.

[0159] According to an embodiment, the thickness of the first oxide semiconductor pattern SP1 can be greater than the thickness of the second oxide semiconductor pattern SP2. For example, the thickness of the first oxide semiconductor pattern SP1 can be greater than or equal to about 250 Å. When the thickness of the first oxide semiconductor pattern SP1 is less than a certain range, the edge portion of the first oxide semiconductor pattern SP1 may short-circuit due to the step difference with the underlying metal layer BML. Therefore, since the first oxide semiconductor pattern SP1 is formed to be thicker than a certain thickness range, the first oxide semiconductor pattern SP1 can be structurally stable.

[0160] According to an embodiment, the thickness of the second oxide semiconductor pattern SP2 can be less than or equal to about 200 Å. When the thickness of the second oxide semiconductor pattern SP2 exceeds a certain range, the ability to control charge movement may deteriorate. In other words, when the second oxide semiconductor pattern SP2 is formed with a thickness greater than a certain range, the charge mobility may increase excessively, leading to leakage current. Because the second oxide semiconductor pattern SP2 is formed with a thickness thinner than the certain range, the second transistor TR2 can have short-channel characteristics while significantly suppressing leakage current. Therefore, improved switching characteristics can be exhibited, and a display panel DP with higher resolution can be provided.

[0161] Used as Figures 5A to 5CThe first transistor TR1 of the driving transistors T1, T11, and T12 shown can have a higher efficiency than that used for driving transistors T1, T12, and T12. Figures 5A to 5C The second transistor TR2 of the switching transistors T2, T21, and T22 shown has a wide driving range. The first channel region A1 of the first transistor TR1 can have a multilayer structure in which different materials are stacked on top of each other. Therefore, the driving range of the first channel region A1 can be greater than the driving range of the second channel region A2, which has a single-layer structure. According to an embodiment, the first channel region A1 can have a driving range of up to 0.39V. Therefore, the pixel PX (see Figure 4 It can easily express various gray levels.

[0162] As described above, the first insulating pattern 31 and the second insulating pattern 32 can be connected to each other to form a layer with an integral shape. In other words, the third insulating layer 30 can be formed as a single insulating layer with an integral shape, rather than as multiple split insulating patterns 31 and 32, but the disclosure is not limited thereto.

[0163] The fourth insulating layer 40 may cover transistors TR1 and TR2. The fourth insulating layer 40 may comprise silicon oxide, silicon nitride, or silicon oxynitride stacked sequentially on top of each other. The fourth insulating layer 40 may cover the top surfaces of the first gate G1 and the second gate G2, and may also cover the top surfaces of the first oxide semiconductor pattern SP1 and the second oxide semiconductor pattern SP2.

[0164] The circuit element layer DP-CL may also include multiple connection electrodes CN1, CN2, CN3, and CN4. The first connection electrode CN1 may be connected to the first source region S1 of the first transistor TR1, and the second connection electrode CN2 may be connected to the first drain region D1 of the first transistor TR1. The third connection electrode CN3 may be connected to the second source region S2 of the second transistor TR2, and the fourth connection electrode CN4 may be connected to the second drain region D2 of the second transistor TR2.

[0165] The lower metal layer BML can be electrically connected to the first source region S1. In other words, the first connection electrode CN1 can be connected to the first source region S1 of the first transistor TR1 and the lower metal layer BML. Therefore, the driving range of the first channel region A1 can be widened. However, the disclosure is not limited thereto. In another embodiment, the lower metal layer BML can be connected to the first gate G1 or the first drain region D1 of the first transistor TR1, can be electrically floated to receive a constant voltage, or can be omitted.

[0166] The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 and cover the connecting electrodes CN1, CN2, CN3, and CN4. The light-emitting element OLED can be connected to the circuit element layer DP-CL through contact holes formed through the fifth insulating layer 50.

[0167] According to embodiments, each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may include an inorganic layer and / or an organic layer. For example, the first insulating layer 10 and the second insulating layer 20 may include silicon nitride and / or silicon oxide, and each of the first insulating patterns 31 to the second insulating patterns 32 constituting the third insulating layer 30 may include silicon oxide. The fourth insulating layer 40 may include a silicon oxynitride layer and a silicon nitride layer sequentially stacked on top of each other, and the fifth insulating layer 50 may include an organic layer. However, the disclosure is not limited thereto. For example, the material or stacking configuration of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be varied.

[0168] The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light-emitting element OLED and a pixel-defining layer PDL. The light-emitting element OLED may include a first electrode E1, a hole control layer HCL, a light-emitting layer EML, an electronic control layer ECL, and a second electrode E2.

[0169] The first electrode E1 can be disposed on the fifth insulating layer 50. The first electrode E1 can be connected to the third connection electrode CN3 through the fifth insulating layer 50. However, the disclosure is not limited thereto. In another embodiment, the first electrode E1 can be connected by a separate additional connection electrode and can be directly connected to the second source region S2 of the second transistor TR2.

[0170] A pixel defining layer (PDL) may be disposed on the fifth insulating layer 50. The pixel defining layer (PDL) may expose at least a portion of the first electrode E1. In other words, an opening may be defined in the pixel defining layer (PDL) to expose a specific portion of the first electrode E1.

[0171] A hole control layer (HCL) can be disposed on the first electrode (E1) and the pixel definition layer (PDL). The hole control layer (HCL) can be commonly disposed in both the light-emitting and non-light-emitting regions. The hole control layer (HCL) may include layers with high hole mobility to facilitate the movement of holes from the first electrode (E1) to the light-emitting layer (EML). For example, the hole control layer (HCL) may include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0172] The emissive layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening of the pixel limiting layer (PDL). The EML can include organic and / or inorganic materials. The EML can generate one of red, green, and blue light.

[0173] An electron control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can be commonly disposed in both the light-emitting and non-light-emitting regions. The ECL may include layers with high electron mobility to facilitate electron movement from the second electrode E2 to the light-emitting layer EML. For example, the ECL may include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0174] The second electrode E2 can be disposed on the electronic control layer ECL. The second electrode E2 can be commonly disposed in the pixel PX. In other words, the second electrode E2 can have a unified shape commonly on the light-emitting layer EML of the pixel PX. However, the disclosure is not limited thereto. In another embodiment, the second electrode E2 can be disposed in each of the pixels PX in a split pattern. The second electrode E2 can have semi-transmissive or transmissive properties. For example, the second electrode E2 can be disposed in various forms, such as a transparent conductive oxide layer, a metal layer with thin film thickness and transmissive properties, or a layer with a stacked structure of metal / oxide layers. In the case where the light-emitting element OLED has a bottom-emitting structure, the second electrode E2 can be a reflective electrode.

[0175] The thin-film encapsulation layer TFE can be disposed on the display element layer DP-OLED. The thin-film encapsulation layer TFE may include inorganic layers and organic layers. Although the thin-film encapsulation layer TFE is shown in the form of a stacked structure in which a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 are stacked in sequence, the disclosure is not limited thereto, and the stacked structure of the layers forming the thin-film encapsulation layer TFE may be varied.

[0176] The first inorganic layer IL1 and the second inorganic layer IL2 may comprise inorganic materials and protect the pixels from moisture / oxygen. The first inorganic layer IL1 and the second inorganic layer IL2 may comprise the same or different materials. The organic layer OL may comprise organic materials and protect the display element layer DP-OLED or the circuit element layer DP-CL from foreign matter.

[0177] Figure 8A and Figure 8B It is a secondary ion mass spectrometry (SIMS) curve showing the variation of hydrogen content in the first channel region A1 of the first transistor TR1 and the second channel region A2 of the second transistor TR2, according to the disclosure.

[0178] Figure 8A This is a SIMS curve showing the thickness of the first channel region A1 in the multilayer structure of the first transistor TR1 as a function of its thickness. Figure 8BThis is a SIMS graph showing the thickness of the second channel region A2 as a function of the single-layer structure of the second transistor TR2. (Referring to...) Figure 8A and Figure 8B The description is public.

[0179] Reference Figure 8A It can be recognized that, due to the formation of the first channel region A1, which has a multilayer structure including a first oxide semiconductor layer SL1 and a second oxide semiconductor layer SL2, a hydrogen (H) peak is formed at the interface between the first oxide semiconductor layer SL1 and the second oxide semiconductor layer SL2. Since hydrogen is present at the interface, defects can be passivated. Therefore, a wider voltage drive range can be exhibited by improving the stability of the threshold voltage of the first transistor TR1.

[0180] Reference Figure 8B It can be recognized that, due to the formation of the second channel region A2, which includes a single-layer oxide semiconductor layer SSL, the hydrogen content was continuously measured without hydrogen peaks. In other words, the second channel region A2 can be formed continuously without hydrogen peaks. Therefore, charge mobility can be improved. Thus, the short-channel characteristics of the second transistor TR2 can be ensured.

[0181] Figures 9A to 9K This is a schematic cross-sectional view illustrating a method for manufacturing a display panel according to a disclosed embodiment. In the following, reference will be made to... Figures 9A to 9K The description is public. (Referencing) Figures 1 to 8B Components that are the same as those described will be assigned to the reference. Figures 1 to 8B The components described will use the same reference numerals, and repeated descriptions will be omitted to avoid redundancy.

[0182] Reference Figure 9A A first insulating layer 10, a second insulating layer 20, and a lower metal layer BML can be formed on a substrate layer BS. The first insulating layer 10 can be formed by depositing or coating an insulating material on the substrate layer BS. The lower metal layer BML can be formed by depositing a conductive material on the first insulating layer 10 and patterning the resulting structure. However, the disclosure is not limited thereto. In another embodiment, the lower metal layer BML can be formed from an insulating material such as a black matrix or by a solution process such as a coating process, in addition to a deposition process. Subsequently, a second insulating layer 20 can be formed by depositing or coating an insulating material to cover the lower metal layer BML. The second insulating layer 20 may include a barrier layer or a buffer layer. In an embodiment, the second insulating layer 20 may also include a buffer layer to cover the substrate layer BS and the first insulating layer 10.

[0183] Reference Figure 9B and Figure 9CA first initial semiconductor pattern SP1-I can be formed on the second insulating layer 20. After forming a preliminary first oxide semiconductor layer SML1 on the second insulating layer 20, a first mask MSK1 can be used to pattern the preliminary first oxide semiconductor layer SML1 into the first initial semiconductor pattern SP1-I. The preliminary first oxide semiconductor layer SML1 may include indium gallium zinc oxide (IGZO). The preliminary first oxide semiconductor layer SML1 can be deposited with a surface area greater than or equal to about 50 nm. The thickness.

[0184] In the initial first oxide semiconductor layer SML1, the portion corresponding to the blocking region BA of the first mask MSK1 can be retained to form the first initial semiconductor pattern SP1-I, and the portion corresponding to the transmissive region TA of the first mask MSK1 can be removed. For example, the thickness of the first initial semiconductor pattern SP1-I can be greater than or equal to about 50 nm. The first initial semiconductor pattern SP1-I can be formed in a planar view in a region superimposed with the lower metal layer BML. However, the disclosure is not limited thereto. For example, the first initial semiconductor pattern SP1-I can be obtained by various patterning methods, and the disclosure is not limited to any one embodiment.

[0185] Reference Figure 9D A preliminary second oxide semiconductor layer SML2 can be formed. The preliminary second oxide semiconductor layer SML2 and the preliminary first oxide semiconductor layer SML1 can include different oxides. In an embodiment, the preliminary second oxide semiconductor layer SML2 can include indium tin gallium zinc oxide (ITGZO). The preliminary second oxide semiconductor layer SML2 can be deposited with a surface area of ​​less than or equal to about 200 nm. The thickness.

[0186] A preliminary second oxide semiconductor layer SML2 can be formed on the second insulating layer 20 and the first initial semiconductor pattern SP1-I by a deposition process. In other words, the preliminary second oxide semiconductor layer SML2 can be formed simultaneously with the first initial semiconductor pattern SP1-I.

[0187] Reference Figure 9E and Figure 9FThe second initial semiconductor pattern SMP2 may include a first region SP1-II superimposed on the first initial semiconductor pattern SP1-I and a second region SP2-I not superimposed on the first initial semiconductor pattern SP1-I in the planar view. After forming the preliminary second oxide semiconductor layer SML2, the second initial semiconductor pattern SMP2 can be obtained using a second mask MSK2. In the second initial semiconductor pattern SMP2, the portion corresponding to the first blocking region BA1 of the second mask MSK2 can be retained, and the portion superimposed on the first initial semiconductor pattern SP1-I can be formed as the first region SP1-II. In the second initial semiconductor pattern SMP2, the portion corresponding to the second blocking region BA2 of the second mask MSK2 can be retained, and the portion not superimposed on the first initial semiconductor pattern SP1-I can be formed as the second region SP2-I. The portion corresponding to the transmission region TA of the second mask MSK2 can be removed. For example, the thickness of the second initial semiconductor pattern SMP2 can be less than or equal to about 200 nm. .

[0188] According to an embodiment, the first region SP1-II and the second region SP2-I of the second initial semiconductor pattern SMP2 can be formed simultaneously using a mask MSK2. Therefore, the first region SP1-II and the second region SP2-I of the second initial semiconductor pattern SMP2 can be formed from the same material.

[0189] Reference Figure 9G , Figure 9H and Figure 9I Subsequently, gates G1 and G2, as well as insulating patterns 31 and 32, can be formed. An initial third insulating layer 30-I and a metal layer ML can be sequentially formed on the second insulating layer 20 to cover the first initial semiconductor pattern SP1-I and the second initial semiconductor pattern SMP2. The initial third insulating layer 30-I can be formed by depositing or coating an insulating material, and the metal layer ML can be formed by depositing or coating a metal material. In addition to metal, the metal layer ML can also be formed of a conductive material, but the disclosure is not limited thereto.

[0190] The initial third insulating layer 30-I and the metal layer ML can undergo a processing step-reaction (TRT) to form a first insulating pattern 31, a second insulating pattern 32, a first gate G1, and a second gate G2. According to an embodiment, the TRT can be an etching process. The first gate G1 and the second gate G2 can be formed from the metal layer ML using a mask (not shown). Subsequently, the first insulating pattern 31 and the second insulating pattern 32 can be formed by using each of the first gate G1 and the second gate G2 as a mask. Therefore, the first insulating pattern 31 and the second insulating pattern 32 can have a form aligned with the first gate G1 and the second gate G2.

[0191] The first initial semiconductor pattern SP1-I and the second initial semiconductor pattern SMP2 can be reduced to the first oxide semiconductor pattern SP1 and the second oxide semiconductor pattern SP2 using a processing technology called TRT. The exposed portions of the first initial semiconductor pattern SP1-I and the second initial semiconductor pattern SMP2 that are not covered by the first insulating pattern 31 and the second insulating pattern 32, as well as the first gate G1 and the second gate G2, can be reduced using the TRT process, resulting in metal deposition. Therefore, sources S1 and S2 and drains D1 and D2 with high conductivity can be formed. Each of the sources S1 and S2 and the drains D1 and D2 can be formed from a region with an N-type dopant.

[0192] The first initial semiconductor pattern SP1-I and the first region SP1-II can be formed as a first oxide semiconductor pattern SP1 including a first source region S1, a first drain region D1, and a first channel region A1, and the second region SP2-I can be formed as a second oxide semiconductor pattern SP2 including a second source region S2, a second drain region D2, and a second channel region A2. The channels A1 and A2 of the first oxide semiconductor pattern SP1 and the second oxide semiconductor pattern SP2 can be self-aligned with the gates G1 and G2 and the insulating patterns 31 and 32.

[0193] According to the disclosed embodiments, the first transistor TR1 and the second transistor TR2 can be formed in the same layer comprising oxide semiconductor patterns SP1 and SP2. However, the disclosure is not limited thereto. The position or structure of the first transistor TR1 and the second transistor TR2 can be varied, and the disclosure is not limited to any one embodiment.

[0194] Subsequently, refer to Figure 9J A fourth insulating layer 40 can be formed. The fourth insulating layer 40 can be formed by depositing or coating an insulating material. Although not shown, the fourth insulating layer 40 can be formed by sequentially stacking multiple insulating layers. The fourth insulating layer 40 can be formed to cover transistors TR1 and TR2.

[0195] Subsequently, refer to Figure 9KConnection electrodes CN1, CN2, CN3, and CN4 can be formed. Contact holes CH1, CH2, CH3, and CH4 can be formed in the fourth insulating layer 40, and the connection electrodes CN1, CN2, CN3, and CN4 can be connected to the corresponding transistors TR1 and TR2 through the contact holes CH1, CH2, CH3, and CH4, respectively. According to the disclosed embodiment, a contact hole CH5 can also be formed through the second insulating layer 20 and the fourth insulating layer 40. The first connection electrode CN1 can be further connected to the lower metal layer BML through the contact hole CH5. Therefore, the first source region S1 of the first transistor TR1 and the lower metal layer BML can be electrically connected to each other. However, the disclosure is not limited thereto. For example, the arrangement of the connection electrodes CN1, CN2, CN3, and CN4 can be varied depending on the structure of the transistors TR1 and TR2, and at least a portion of the arrangement can be omitted or further added.

[0196] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device, and may also include modules or devices with additional functions in addition to the display device.

[0197] Figure 10 This is a block diagram of an electronic device ED according to a disclosed embodiment. (Refer to...) Figure 10 Electronic devices (EDs) may include a display module (DM), a processor (PR), a memory (MR), and a power module (PM).

[0198] The processor PR may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0199] The memory MR can store the data information required for the operation of the processor PR or the display module DM. When the processor PR executes the application stored in the memory MR, image data signals and / or input control signals can be sent to the display module DM, and the display module DM can process the received signals to output image information through the display screen.

[0200] The power module PM may include a power module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device ED.

[0201] At least one of the components of the electronic device ED may be included in the display device according to the embodiment. Additionally, among the various modules functionally included within the electronic device ED, some modules may be included in the display device, while others may be provided separately from the display device. As an example, the display device may include a display module DM, and the processor PR, memory MR, and power module PM may be provided as separate devices within the electronic device ED and may not be included in the display device.

[0202] Figure 11 This is a view illustrating an electronic device according to a disclosed embodiment.

[0203] Reference Figure 11 Various electronic devices that apply the display device according to the embodiments may include electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, desktop monitors 10_1e, etc.), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.), or vehicle electronic devices 10_3 including display modules (such as center console panels, central instrument panels, instrument panel-mounted central information displays (CID), interior mirror displays, etc.).

[0204] As described above, the oxide semiconductor pattern of the first transistor can be formed as a multilayer oxide semiconductor layer, and the oxide semiconductor pattern of the second transistor can be formed as a single-layer oxide semiconductor layer. The first transistor may include a multilayer oxide semiconductor layer to reduce the risk of disconnection caused by the step difference with the metal layer disposed in the lower end portion of the first transistor. The first transistor may include different materials in the multilayer structure to increase the driving voltage range of the first transistor. The single-layer oxide semiconductor layer of the second transistor may have a higher mobility and may be formed with a thickness for controlling the carriers in the channel region.

[0205] In other words, a first transistor with a wide driving voltage range and a second transistor with high mobility can be simultaneously configured. Therefore, lower grayscale levels can be stably represented, and higher resolution display panels can be easily designed. Furthermore, the reliability of the manufacturing process for the display panel can be improved.

[0206] The above description is an example of the disclosed technical features, and those skilled in the art will be able to make various modifications and variations. Therefore, the disclosed embodiments described above can be implemented individually or in combination with each other.

[0207] Therefore, the embodiments disclosed herein are not intended to limit the spirit of the disclosed technology, but rather to describe it, and the scope of the disclosed spirit of the technology is not limited by these embodiments. The scope of protection of the disclosure should be interpreted by the appended claims, and should be construed as including all technical spirit within the equivalent scope within the scope of the disclosure.

Claims

1. A display panel comprising: a light emitting element over a base layer; and a pixel drive circuit electrically connected to the light emitting element, the pixel drive circuit including: a first transistor including a first oxide semiconductor pattern; and a second transistor including a second oxide semiconductor pattern, the first oxide semiconductor pattern including a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer over the first oxide semiconductor layer, and the second oxide semiconductor pattern including a second channel region including a single-layer oxide semiconductor layer. the first transistor further including:

2. The display panel of claim 1, wherein, a first gate provided over the second oxide semiconductor layer and overlapping with the first channel region in a plan view; and a first gate insulating layer interposed between the first gate and the second oxide semiconductor layer. the second oxide semiconductor layer and the single-layer oxide semiconductor layer include the same semiconductor material.

3. The display panel of claim 1, wherein, 4. The display panel according to claim 1, wherein the second transistor outputs a data voltage, and the first transistor controls a drive current of the light emitting element to correspond to the data voltage.

5. The display panel according to claim 1, wherein the first oxide semiconductor pattern has a thickness greater than or equal to 250 A, and the second oxide semiconductor pattern has a thickness less than or equal to 200 A.

6. The display panel according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include different oxide semiconductors, and the first oxide semiconductor layer includes indium gallium zinc oxide. the second oxide semiconductor layer includes indium tin gallium zinc oxide.

7. The display panel of claim 6, wherein, in the second oxide semiconductor layer, 8. The display panel of claim 7, wherein, an indium of the indium tin gallium zinc oxide has a composition ratio in a range of 60 wt% to 80 wt%, a tin of the indium tin gallium zinc oxide has a composition ratio in a range of 0.5 wt% to 8 wt%, a gallium of the indium tin gallium zinc oxide has a composition ratio in a range of 5 wt% to 15 wt%, and a zinc of the indium tin gallium zinc oxide has a composition ratio in a range of 10 wt% to 30 wt%.

9. The display panel according to claim 1, further comprising: a lower metal layer interposed between the base layer and the first transistor; and a buffer layer interposed between the lower metal layer and the first oxide semiconductor pattern, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern are provided over the buffer layer. a source of the first transistor is electrically connected to the lower metal layer. a first connection electrode connecting the source of the first transistor to the lower metal layer and a second connection electrode connecting to a source of the second transistor are provided in the same layer.

10. The display panel of claim 9, wherein, each of the first transistor and the second transistor has a top gate structure.

11. The display panel of claim 10, wherein, 13. An electronic device comprising:

12. The display panel of claim 1, wherein, a light emitting element over a base layer; and a pixel drive circuit electrically connected to the light emitting element, the pixel drive circuit including: a first transistor including a first oxide semiconductor pattern; and a second transistor including a second oxide semiconductor pattern, the first oxide semiconductor pattern including a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer over the first oxide semiconductor layer, and the second oxide semiconductor pattern including a second channel region including a single-layer oxide semiconductor layer. The pixel driving circuit includes a first transistor including a first oxide semiconductor pattern, and a second transistor including a second oxide semiconductor pattern, The first oxide semiconductor pattern includes a first channel region including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and The second oxide semiconductor pattern includes a second channel region including a single-layer oxide semiconductor layer.

14. The electronic device according to claim 13, wherein The first oxide semiconductor pattern has a thickness greater than or equal to 250 A, and The second oxide semiconductor pattern has a thickness less than or equal to 200 A.

15. The electronic device according to claim 13, wherein The first oxide semiconductor layer and the second oxide semiconductor layer include different oxide semiconductors, The first oxide semiconductor layer includes indium gallium zinc oxide, and The second oxide semiconductor layer includes indium tin gallium zinc oxide.

16. A method for manufacturing a display panel, the method comprising the steps of: forming a first oxide semiconductor layer on a base layer; forming a second oxide semiconductor layer on the base layer, the second oxide semiconductor layer including a first region superposed with the first oxide semiconductor layer in a plan view and a second region not superposed with the first oxide semiconductor layer in the plan view; forming a first gate electrode superposed with the first region of the second oxide semiconductor layer in the plan view; forming a second gate electrode superposed with the second region of the second oxide semiconductor layer in the plan view; and forming an insulating layer to cover the first gate electrode and the second gate electrode.

17. The method according to claim 16, wherein The first oxide semiconductor layer has a thickness greater than or equal to 50 A, and The second oxide semiconductor layer has a thickness less than or equal to 200 A.

18. The method according to claim 16, further comprising the steps of: forming a lower metal layer between the base layer and the first oxide semiconductor layer; and forming a buffer layer to cover the lower metal layer and the base layer. The step of forming the first gate electrode includes: forming a first channel region superposed with the first gate electrode in the plan view and a first source region and a first drain region provided at opposite sides of the first channel region from the second oxide semiconductor layer.

19. The method of claim 18, wherein, 20. The method according to claim 19, wherein The lower metal layer is superposed with the first region in the plan view, and The lower metal layer and the first source region are electrically connected to each other. ​ ​

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