Method for forming semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device and a method of forming the semiconductor device. The method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, forming a second mask layer over the plurality of spacers, and patterning the second mask layer to form a first opening, where a principal axis of the opening extends in a direction perpendicular to a principal axis of a spacer of the plurality of spacers in a plan view. The method further includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form a second opening in the target layer, and filling the second opening in the target layer with a conductive material.

Description

[0001] Case Analysis

[0002] This application is a divisional application of the first divisional application, filed on November 14, 2018, entitled "A patterning method for a semiconductor device and the resulting structure", with patent application number 202110786715.4 (first divisional application). The original application of the first divisional application was filed on November 14, 2018, entitled "A patterning method for a semiconductor device and the resulting structure", with patent application number 201811355245.0. Technical Field

[0003] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to methods for forming semiconductor devices. Background Technology

[0004] As semiconductor devices continue to shrink in size, various processing techniques (e.g., photolithography) are adapted to allow the fabrication of devices with increasingly smaller dimensions. For example, as gate density increases, the fabrication processes for various components within the device (e.g., the interconnect components above) are adapted to be compatible with the overall scaling down of device components. However, as semiconductor process windows become increasingly smaller, the fabrication of these devices has approached and even exceeded the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the desired spacing (i.e., pitch) between device elements is smaller than the pitch that can be fabricated using conventional optical masks and photolithography equipment. Summary of the Invention

[0005] According to one aspect of the present invention, a method of forming a semiconductor device is provided, comprising: forming a first mask layer over a target layer; forming a plurality of spacers over the first mask layer; forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, wherein, in a plan view, the main axis of the opening extends in a direction perpendicular to the main axis of one of the plurality of spacers; depositing a sacrificial material in the opening; patterning the sacrificial material; etching the first mask layer using the plurality of spacers and the patterned sacrificial material; etching the target layer using the etched first mask layer to form a second opening in the target layer; and filling the second opening located in the target layer with a conductive material.

[0006] According to another aspect of the present invention, a method of forming a semiconductor device is provided, comprising: forming a first capping layer over a second capping layer, the second capping layer being located over a first mask layer, the first mask layer being located over a dielectric layer; patterning an opening in the first capping layer, the opening having a target width; filling the opening with a first material to form a masking element; forming a second mask layer over the first capping layer and patterning the second mask layer to form a first mask, the first mask including a plurality of openings; etching the first capping layer and the second capping layer using the first mask and the masking element, wherein the masking element prevents portions of the second capping layer from being etched; patterning the first mask layer through the second capping layer to form a second mask; patterning the dielectric layer through the second mask, the patterning of the dielectric layer exposing conductive components located beneath the dielectric layer; and forming a wire in the dielectric layer, the wire contacting the conductive components.

[0007] According to another aspect of the present invention, a semiconductor device is provided, comprising: a dielectric layer; a power rail extending through the dielectric layer, wherein the sidewalls of the power rail include one or more kinks; a first set of interconnects located on a first side of the power rail and within the dielectric layer; and a second set of interconnects located on the first side of the power rail and within the dielectric layer, wherein a first kink of the one or more kinks is laterally positioned between the first set of interconnects and the second set of interconnects. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 and FIG. 11 Cross-sectional views are shown of various intermediate stages in the manufacture of a semiconductor device according to some embodiments.

[0010] FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A ,FIG. 15B , FIG. 16A , FIG. 16B , FIG. 17A , FIG. 17B , FIG. 18A , FIG. 18B , FIG. 19A , FIG. 19B , FIG. 20A , FIG. 20B , FIG. 21A , FIG. 21B , FIG. 22A and FIG. 22B Cross-sectional and plan views are shown of various intermediate stages in the manufacture of a semiconductor device according to some embodiments.

[0011] FIG. 23 and FIG. 24 Cross-sectional views are shown of various intermediate stages in the manufacture of a semiconductor device according to some embodiments;

[0012] FIG. 25A and FIG. 25B Cross-sectional and plan views are shown of intermediate stages in the manufacture of semiconductor devices according to some embodiments.

[0013] FIG. 26 This is a flowchart of a method according to some embodiments.

[0014] FIG. 27 , FIG. 28 , FIG. 29 and FIG. 30 A plan view of a semiconductor device according to some embodiments is shown.

[0015] FIG. 31 This is a block diagram of a processing system according to some embodiments.

[0016] FIG. 32 It is a plan view of a semiconductor device according to some embodiments.

[0017] FIG. 33A-FIG. 33B It is a virtual layout and plan view of semiconductor devices based on some embodiments.

[0018] FIG. 34 to FIG. 43 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device according to some embodiments.

[0019] FIG. 44A , FIG. 44B , FIG. 45A and FIG. 45B These are cross-sectional and plan views of intermediate stages in the manufacture of semiconductor devices according to some embodiments.

[0020] FIG. 46 and FIG. 47 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device according to some embodiments.

[0021] FIG. 48 This is a flowchart of a method according to some embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0024] A semiconductor device and a method of forming the semiconductor device are provided according to some embodiments. In some embodiments, a patterning process is performed to pattern lines located in a target layer of the semiconductor device. A dielectric layer is patterned using photolithography to form spacers. A patterned sacrificial material (sometimes referred to as a reverse material) is formed over the spacers. The patterned sacrificial material may include an inorganic material and is formed by patterning openings (openings exposing selected areas of the patterned lines) in a mask and depositing the inorganic material in the openings using a suitable film deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). After forming the sacrificial material, the sacrificial material is patterned by forming openings in the sacrificial material. The spacers and sacrificial material are used to pattern an underlying mask layer, which in turn is used to pattern the target layer. The underlying target layer may be a layer for various purposes. For example, the target layer may be a low-k dielectric layer, wherein the openings are patterned using the mask layer. Subsequently, conductive material may be filled in the openings of the low-k dielectric layer to define interconnects, wherein interconnects with line cuts are defined by the patterned sacrificial material. Interconnects can have fine pitch, and / or one or more wire cuts can have fine pitch, and / or interconnects and wire cuts with fine pitch can be formed using a simplified patterning process. For example, a target layer can be patterned using a single patterning process to form fine-pitch interconnects with one or more wire cuts to pattern the target layer. Because the target layer is patterned in a single patterning process, and / or using the simplified process described herein, improved patterning accuracy can be achieved and manufacturing costs can be reduced. For example, if the target layer 102 is etched in two or more different processes, the pattern actually etched into the target layer 102 may differ from the desired pattern, for example, due to the difficulty in precisely aligning the etching mask with the desired portion to be etched. Improved accuracy is possible when the target layer 102 is etched using a single etching step and / or a simplified patterning process as described herein. Thus, multiple interconnects with multiple wire cuts can be formed to have the same or substantially the same dimensions, which allows for better control of the interconnect resistance. Additionally, manufacturing costs may be reduced due to the simplified processing.

[0025] In some embodiments, the processes described herein can be used to form power rails and metal island structures with narrower power rails, the metal islands having generally similar dimensions and / or groups of metal islands well aligned with other groups of metal islands. Due to the processes used to form the power rails and metal islands, kinks may be present in the formed power rails. Kinks can reduce the reliability of the contacts to the power rails. To avoid kinks, contacts to the power rails can be formed outside of a "contactless area," where kinks may exist at the edges of the power rails.

[0026] In some embodiments, an interconnect may have one or more wire cuts, wherein a wire cut may refer to a physical separation between two adjacent portions of the interconnect. A wire cut can be formed by physically removing a portion of the interconnect after it has been formed. Alternatively, the interconnect can be formed such that a wire cut exists after its formation due to the process used to form the interconnect. In some devices, multiple adjacent interconnects may have wire cuts at the same location in the middle portion of the interconnect. Wire cuts can be prepared such that one or more undesired portions of the interconnect are left after the wire cut. For example, wire cuts can be formed at the same location in adjacent groups of interconnects. Interconnects in adjacent groups of interconnects may connect to vias, wherein the vias are located at a location greater than the minimum distance from the wire edge formed by the wire cut, and the portion of the interconnect between the wire edge formed by the wire cut and the via may not be necessary or desired in a particular design. Failure to remove unnecessary or undesirable interconnects from a semiconductor device may be disadvantageous, for example, because the RC performance of the device may be degraded, and / or the spacing consumed by unnecessary wire edges may undesirably increase the size or footprint of the semiconductor device. In some embodiments, wire ends can be removed from the semiconductor device being formed, thereby improving the RC performance of the semiconductor device and / or reducing the required size or footprint of the device.

[0027] FIG. 1 to FIG. 25B The diagram illustrates a cross-sectional and / or planar view of an intermediate stage in forming components in a target layer 102 located on a semiconductor device 100, according to some exemplary embodiments. The target layer 102 is the layer in which a pattern will be formed according to embodiments of the invention. In some embodiments, the semiconductor device 100 is processed as a portion of a larger wafer. In such embodiments, after the various components of the semiconductor device 100 (e.g., active devices, interconnect structures, etc.) are formed, a dicing process can be applied to the scribe lines located between the individual dies of the wafer to separate the individual semiconductor dies from the wafer (also referred to as dicing).

[0028] In some embodiments, target layer 102 is an intermetallic dielectric (IMD) layer. In this embodiment, target layer 102 comprises a low-k dielectric material, wherein, for example, the dielectric constant (k value) of the low-k dielectric material is less than 3.8, less than about 3.0, or less than about 2.5. In an alternative embodiment, target layer 102 is an IMD layer comprising a high-k dielectric material having a k value greater than 3.8. Openings can be patterned in target layer 102 using the process described herein, and conductors and / or vias can be formed in the openings, as described below.

[0029] In some embodiments, target layer 102 is a semiconductor substrate. The semiconductor substrate may be formed of a semiconductor material such as silicon, silicon germanium, etc. In some embodiments, the semiconductor substrate is a crystalline semiconductor substrate such as a crystalline silicon substrate, a crystalline silicon-carbon substrate, a crystalline silicon-germanium substrate, a group III-V compound semiconductor substrate, etc. The semiconductor substrate may be patterned using the processes described in the embodiments, and subsequent process steps may be used to form shallow trench isolation (STI) regions in the substrate. Semiconductor fins may protrude from between the formed STI regions. Source / drain regions may be formed in the semiconductor fins, and a gate dielectric layer and a gate electrode layer may be formed over the channel regions of the fins to form a semiconductor device such as a fin field-effect transistor (finFET).

[0030] In some embodiments, the target layer 102 is a conductive layer such as a metal layer or a polysilicon layer deposited using a blanket deposition process. The target layer 102 can be patterned using the embodiment patterning process to pattern the semiconductor gates and / or dummy gates of the FinFET. By using the embodiment process to pattern the conductive target layer 102, the spacing between adjacent gates can be reduced and the gate density can be increased.

[0031] exist FIG. 1 In this embodiment, a film stack including a target layer 102 is formed in a semiconductor device 100. In some embodiments, the target layer 102 may be formed over a semiconductor substrate 104. The semiconductor substrate 104 may be formed of a semiconductor material such as doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate as the active layer. The semiconductor substrate 104 may include other semiconductor materials, including: compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. (not shown) may be formed in and / or on the active surface of the semiconductor substrate 104. In other embodiments where the target layer 102 is a semiconductor substrate for forming a finFET, the semiconductor substrate 104 may be omitted.

[0032] although FIG. 1The target layer 102 is shown in physical contact with the semiconductor substrate 104, but any number of intermediate layers can be disposed between the target layer 102 and the semiconductor substrate 104. Such intermediate layers may include interlayer dielectric (ILD) layers (including low-k dielectrics and having contact plugs formed therein), other IMD layers (having wires and / or vias formed therein), one or more intermediate layers (e.g., etch stop layers, adhesive layers, etc.), combinations thereof, etc. For example, an optional etch stop layer (not shown) may be disposed directly below the target layer 102. The etch stop layer can serve as a stop for subsequent etching processes performed on the target layer 102. The materials and processes used to form the etch stop layer depend on the material of the target layer 102. In some embodiments, the etch stop layer may be made of silicon nitride, SiON, SiCON, SiC, SiOC, SiC x N y SiO x Other dielectrics, combinations thereof, etc., can be formed, and can be formed by plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), plasma vapor deposition (PVD), etc. Other materials and processes can also be used.

[0033] The film stack also includes an anti-reflective coating (ARC) 106 formed over the target layer 102. During the patterning of the photoresist layer, ARC 106 assists in the exposure and focusing of the overlying photoresist layer (discussed below). In some embodiments, ARC 106 may be formed from materials such as SiON, silicon carbide, or materials doped with oxygen (O) and nitrogen (N). In some embodiments, ARC 106 is substantially nitrogen-free and may be formed from oxides. In this embodiment, ARC 106 may also be referred to as nitrogen-free ARC (NFARC). In some embodiments, the material composition of ARC 106 may be selected to prevent reflection. ARC 106 can be formed by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma (HDP) deposition, etc. Other processes and materials may be used.

[0034] The film stack also includes a hard mask layer 108 formed over ARC 106 and target layer 102. The hard mask layer 108 may be formed of materials including metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, metal-doped carbides (e.g., tungsten carbide), etc.) and / or non-metals (e.g., silicon nitride, boron nitride, silicon carbide, etc.). In some embodiments, the material composition of the hard mask layer 108 may be determined to provide high etch selectivity relative to, for example, ARC 106 and / or target layer 102. The hard mask layer 108 may be formed by PVD, radio frequency PVD (RFPVD), atomic layer deposition (ALD), etc. Other processes and materials may be used. In a subsequent processing step, a pattern is formed on the hard mask layer 108 using an embodiment patterning process. The hard mask layer 108 is then used as an etch mask for etching the target layer 102, wherein the pattern of the hard mask layer 108 is transferred to the target layer 102.

[0035] In some embodiments, the film stack further includes a dielectric layer 110 formed over the hard mask layer 108. In subsequent processing, the dielectric layer 110 can be used to form a plurality of spacers for patterning the target layer (see [link]). FIG. 18A to FIG. 18B and FIG. 19A to FIG. 19B The dielectric layer 110 can be formed from silicon oxide such as borophosphosilicate tetraethyl orthosilicate (BPTEOS) or undoped tetraethyl orthosilicate (TEOS) oxide, and can be formed by CVD, ALD, spin coating, etc. Other processes and materials can be used.

[0036] A three-layer masking layer 120 is formed on a film stack located above the dielectric layer 110. The three-layer masking layer 120 includes a bottom layer 112, an intermediate layer 114 located above the bottom layer 112, and an upper layer 116 located above the intermediate layer 114. The upper layer 116 may be formed of a photoresist comprising organic materials (e.g., a photosensitive material) and may be a positive or negative photosensitive material. In some embodiments, the bottom layer 112 may be formed of a polymer. The bottom layer 112 may also be a bottom antireflective coating (BARC) layer or an ashed removable dielectric (ARD) layer (such as amorphous carbon). The intermediate layer 114 may include an inorganic material, wherein the inorganic material may be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 114 has high etch selectivity relative to the upper layer 116 and the bottom layer 112. The individual layers of the three-layer masking layer 120 may be sequentially carpet-deposited using, for example, a spin-coating process. Other processes and materials may be used. Although a three-layer masking layer 120 has been discussed herein, in other embodiments, the three-layer masking layer 120 may actually be a single-layer masking layer or a double-layer masking layer (e.g., consisting only of a bottom layer 112 and an upper layer 116 without an intermediate layer 114). The type of masking layer used (e.g., a single-layer masking layer, a double-layer masking layer, or a three-layer masking layer) may depend on the photolithography process used to pattern the dielectric layer 110. For example, in extreme ultraviolet (EUV) lithography processes, a single-layer masking layer or a double-layer masking layer may be used.

[0037] In some embodiments, the upper layer 116 is patterned using a photolithography process. Subsequently, the upper layer 116 is used as an etching mask for patterning the intermediate layer 114 (see [link]). FIG. 2 The intermediate layer 114 is then used as an etching mask to pattern the bottom layer 112, and the bottom layer 112 is then used to pattern the dielectric layer 110 (see...). FIG. 3 It has been observed that by using a three-layer photoresist (e.g., three-layer photoresist 120) to etch a target layer (e.g., dielectric layer 110), the accuracy of fine pitch patterns in the target layer (e.g., dielectric layer 110) can be improved.

[0038] The upper layer 116 is patterned using any suitable photolithography process to form openings 122 therein. As an example of patterning openings 122 in the upper layer 116, a photomask (not shown) can be placed above the upper layer 116. The upper layer 116 can then be exposed to radiation beams including ultraviolet (UV) or excimer lasers (such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, while the photomask masks areas of the upper layer 116. Immersion lithography or extreme ultraviolet lithography systems can be used to expose the top photoresist layer to improve resolution and reduce the minimum achievable pitch. One or more exposure steps can be performed. Baking or curing operations can be performed to harden the upper layer 116, and a developer can be used to remove exposed or unexposed portions of the upper layer 116, depending on whether a positive or negative resist is used. The opening 122 can have a strip shape in the plan view (not shown). The minimum width W1 of the opening 122 can be about 19 nm. Other widths of the opening 122 can also be considered.

[0039] refer to FIG. 2 After patterning the upper layer 116, the pattern of the upper layer 116 can be transferred to the intermediate layer 114 in an etching process. The etching process is anisotropic, causing the openings 122 in the upper layer 116 to extend through the intermediate layer 114 and have the same (or slightly smaller) dimensions in the intermediate layer 114 as they do in the upper layer 116. FIG. 2 The resulting structure is shown in the figure.

[0040] like FIG. 3 As shown, an etching process can be performed to transfer the pattern of the intermediate layer 114 to the bottom layer 112, thereby causing the opening 122 to extend through the bottom layer 112. The etching process of the bottom layer 112 is anisotropic, such that the opening 122 in the intermediate layer 114 extends through the bottom layer 112 and has approximately the same (or slightly smaller) size in the bottom layer 112 as in the intermediate layer 114. As part of etching the bottom layer 112, the upper layer 116 may be consumed.

[0041] exist FIG. 4In this process, an etching process is used to transfer the pattern of the base layer 112 to the dielectric layer 110. The etching process is anisotropic, causing the openings 122 in the base layer 112 to extend through the dielectric layer 110 and have the same (or slightly smaller) dimensions in the dielectric layer 110 as they do in the base layer 112. Therefore, the remaining portion of the dielectric layer 110 (e.g., the portion of the dielectric layer 110 located between the openings 122) defines spacers 124. During the etching of the dielectric layer 110, the intermediate layer 114 is consumed, and the base layer 112 may be consumed at least partially. In embodiments where the base layer 112 is not completely consumed when the dielectric layer 110 is etched, an ashing process may be performed to remove any remaining residue of the base layer 112. FIG. 5 The remaining structure is described below. In the plan view, the gaps between the spacers 124 define the region where wires will be formed in the target layer 102. The spacers 124 may have a line pitch P1 greater than or equal to 30 nm.

[0042] exist FIG. 6 In this process, a masking layer 130 is formed over a patterned dielectric layer 110. The masking layer 130 may include a bottom layer 126, an intermediate layer 128, and a top layer 132. The top layer 132 may be formed of a photoresist comprising organic materials (e.g., a photosensitive material). The top layer 132 may be a positive or negative photosensitive material. In some embodiments, the bottom layer 126 may be a polymer, a bottom anti-reflective coating (BARC), or an ashing removable dielectric (ARD) layer, etc. The intermediate layer 128 may include inorganic materials, wherein the inorganic material may be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 128 may have high etch selectivity relative to the top layer 132 and the bottom layer 126. The individual layers of the masking layer 130 may be sequentially carpet-deposited using, for example, a spin-coating process. Other processes and materials may be used. Although the three-layer masking layer 130 is discussed herein, in other embodiments, the masking layer 130 may be a single-layer masking layer or a double-layer masking layer (e.g., including only the bottom layer 126 and the top layer 132 without the middle layer 128).

[0043] exist FIG. 7 In this process, the upper layer 132 is patterned using a photolithography process to form the opening 134. Subsequently, the upper layer 132 is used as an etching mask, which is then used to pattern the intermediate layer 128 (see [link to image]). FIG. 7 The intermediate layer 128 is then used as an etching mask to pattern the underlying layer 126, and the underlying layer 126 is then used to define the periphery of the subsequently formed sacrificial material (see...). FIG. 10-FIG. 11 ).

[0044] refer to FIG. 7The upper layer 132 is patterned using any suitable photolithography process to form openings 134 therein. As an example of patterning openings 134 in the upper layer 132, a photomask (not shown) can be placed above the upper layer 132. The upper layer 132 can then be exposed to radiation beams including ultraviolet (UV) or excimer lasers (such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, while the photomask masks areas of the upper layer 132. Immersion lithography or extreme ultraviolet lithography systems can be used to perform the exposure of the top photoresist layer to improve resolution and reduce the minimum achievable pitch. A single exposure step or multiple exposure steps can be performed. Baking or curing operations can be performed to harden the upper layer 132, and depending on whether a positive or negative resist is used, a developer can be used to remove exposed or unexposed portions of the upper layer 132.

[0045] refer to FIG. 8 After patterning the upper layer 132, the pattern of the upper layer 132 can be transferred to the intermediate layer 128 in an etching process. The etching process is anisotropic, causing the openings 134 in the upper layer 132 to extend through the intermediate layer 128 and have approximately the same (or slightly smaller) dimensions in the intermediate layer 128 as they do in the upper layer 132. FIG. 8 The resulting structure is shown in the figure.

[0046] like FIG. 9 As shown, an etching process can be performed to transfer the pattern of the intermediate layer 128 to the bottom layer 126, thereby causing the opening 134 to extend through the bottom layer 126. The etching process of the bottom layer 126 is anisotropic, such that the opening 134 in the intermediate layer 128 extends through the bottom layer 126 and has approximately the same (or slightly smaller) size in the bottom layer 126 as in the intermediate layer 128. As part of etching the bottom layer 126, the upper layer 132 may be consumed. After patterning the bottom layer 126, the opening 134 may expose one or more spacers 124 formed by the remaining dielectric layer 110. The opening 134 may also expose portions of the hard mask layer 108 extending between adjacent spacers 124.

[0047] exist FIG. 10 In the process, sacrificial material 136 is formed in opening 134. As described in more detail below, in subsequent processing, the sacrificial material 136 will be further patterned, and the patterned sacrificial material can be used to define a line cut between two adjacent conductors to be formed in target layer 102. Although FIG. 10The description describes the formation of sacrificial material in a single opening 134; however, in some embodiments, more than one opening 134 may be present, and sacrificial material may be formed in more than one opening 134 (e.g., to form additional line cuts). In some embodiments, sacrificial material 136 may be deposited in an opening 134 located above spacer 124 and above an exposed portion of hard mask layer 108. Sacrificial material may be formed along the sidewalls of intermediate layer 128 and along its top surface (or, if intermediate layer 128 has been removed, along the top surface of bottom layer 126).

[0048] In various embodiments, the sacrificial material 136 comprises an inorganic material. For example, the sacrificial material 136 may be an inorganic oxide such as titanium oxide, tantalum oxide, silicon oxide, etc. Other materials such as silicon nitride, silicon carbide, metal nitride, metal oxide, etc., may be used. The sacrificial material 136 may be selected at least in part considering the etch selectivity between the material of the sacrificial material 136 and the materials used to form the hard mask layer 108, the intermediate layer 128, and / or the underlayer 126. In some embodiments, the inorganic material is a low-temperature oxide (LTO). As used herein, the term "LTO" refers to an oxide deposited using a relatively low process temperature (e.g., 200°C or lower). It has been observed that in this embodiment, the low-temperature deposition process does not cause significant damage to the underlayer 126. Other materials may also be used.

[0049] The sacrificial material 136 can be formed using semiconductor film deposition processes such as CVD, PVD, ALD, spin coating, etc. Other processes can also be used. The semiconductor film deposition process can be a conformal process, in which a semiconductor film is formed on the sidewalls and bottom surface of the opening 134. As deposition continues, portions of the sacrificial material 136 located on the opposite sidewalls of the opening 134 merge, thereby filling the opening. As a result of the semiconductor film deposition process, the top surface of the sacrificial material 136 may not be flat.

[0050] Next, in FIG. 11 In this process, a planarization process (e.g., chemical mechanical polishing (CMP), dry etching, combinations thereof, etc.) is performed to remove excess portions of the sacrificial material 136 located outside the opening 134. In some embodiments (not shown), the planarization process may continue until the intermediate layer 128 and the portions of the sacrificial material adjacent to the intermediate layer 128 are also removed.

[0051] Next, an ashing process is used to remove the intermediate layer 128 and the bottom layer 126. After removing the bottom layer 126, sacrificial material 136 remains and covers portions of the spacers 124 and the hard mask layer 108. Removing the bottom layer 126 exposes portions of the other spacers 124 and the hard mask layer 108. FIG. 12A (Cross-section view) and FIG. 12BThe remaining structure is shown in the (plan view). FIG. 12A The cross-sectional view along FIG. 12B The line A-A' shown in the plan view. For example... FIG. 12B As shown, in the plan view, the sacrificial material 136 is formed into a rectangle, wherein the rectangle has a main axis extending in a direction substantially perpendicular to the direction of the spacer 124. Thus, the line cut defined by the sacrificial material 136 is substantially perpendicular to the wire formed in the groove located between adjacent spacers 124, resulting in a wider coverage process window.

[0052] like FIG. 9 to FIG. 12A to FIG. 12B As shown, the thickness of the sacrificial material 136 can be determined at least in part based on the thickness of the underlying layer 126. For example, by reducing the thickness of the underlying layer 126, the thickness of the sacrificial material 136 also decreases. As described below, in some embodiments, if the sacrificial material 136 has a relatively thin thickness, subsequent planarization processes may not be necessary. This could potentially reduce manufacturing costs and time.

[0053] In some embodiments, it can be extended FIG. 12A and FIG. 12B The length of the strip of sacrificial material 136 shown is, for example, to extend the wire cut to an additional conductor. Although in FIG. 12B Only one sacrificial material 136 is shown, but in some embodiments, additional strips of sacrificial material 136 may be formed using the same or similar processes described above, for example, to form additional line cuts. In some embodiments, multiple sacrificial materials 136 may be formed, wherein each sacrificial material 136 extends in a direction parallel to the other sacrificial materials 136 and perpendicular to the direction in which the spacer 124 extends in the plan view.

[0054] refer to FIG. 13A to FIG. 13B A masking layer 140 is formed over spacer 124, hard mask layer 108, and sacrificial material 136. Masking layer 140 may include a bottom layer 142, an intermediate layer 144, and a top layer 148. Although a three-layer masking layer 140 is shown, in some embodiments, masking layer 140 may be a single-layer or double-layer masking layer as described above. In some embodiments, such as FIG. 14A As shown, the bottom layer 142 can completely cover the sacrificial material 136 and can extend along the exposed spacer 124 and hard mask layer 108.

[0055] In some embodiments, the upper layer 148 may be formed of a photoresist comprising an organic material (e.g., a photosensitive material). The upper layer 148 may be formed of a positive or negative photosensitive material. In some embodiments, the bottom layer 142 may be a polymer, a bottom anti-reflective coating (BARC), and / or an ashed removable dielectric (ARD) layer, etc. The intermediate layer 144 may comprise an inorganic material, wherein the inorganic material may be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 144 has high etch selectivity relative to the upper layer 148 and the bottom layer 142. The individual layers of the three masking layers 140 may be sequentially carpet-deposited using, for example, a spin-coating process. Other processes and materials may be used.

[0056] exist FIG. 14A to FIG. 14B In the process, the upper layer 148 is patterned using a photolithography process. Subsequently, the upper layer 148 is used as an etching mask, thereby being used to pattern the intermediate layer 144 (see [link to image]). FIG. 15A to FIG. 15B Then the intermediate layer 144 is used as an etching mask, which is then used to pattern the underlying layer 142 (see...). FIG. 16A to FIG. 16B ).

[0057] The upper layer 148 is patterned using any suitable photolithography process (such as the procedures discussed earlier) to form openings 146 therein. For example, a photomask (not shown) can be placed above the upper layer 148. The upper layer 148 can then be exposed to a radiation beam, including ultraviolet (UV) or excimer laser (such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, while the photomask masks areas of the upper layer 116. Immersion lithography or extreme ultraviolet lithography systems can be used to expose the top photoresist layer to improve resolution and reduce the minimum achievable pitch. One or more exposure steps can be performed. Baking or curing operations can be performed to harden the upper layer 148, and depending on whether a positive or negative resist is used, a developer can be used to remove exposed or unexposed portions of the upper layer 148. The opening 146 may have a width W2, wherein, in some embodiments, W2 is approximately 50 nm.

[0058] refer to FIG. 15A to FIG. 15B After patterning the upper layer 148, the pattern of the upper layer 148 can be transferred to the intermediate layer 144 in an etching process. The etching process is anisotropic, so that the openings 146 in the upper layer 148 extend through the intermediate layer 144 and have the same (or slightly smaller) size in the intermediate layer 144 as they do in the upper layer 148. FIG. 15A to FIG. 15B The resulting structure is shown in the figure.

[0059] like FIG. 16A to FIG. 16BAs shown, an etching process can be performed to transfer the pattern of the intermediate layer 144 to the underlayer 142 and the sacrificial material 136, whereby the opening 146 extends through the underlayer 142 and the sacrificial material 136. The etching process of the underlayer 142 is anisotropic, such that the opening 146 in the intermediate layer 144 extends through the underlayer 142 and has approximately the same (or slightly smaller) size in the underlayer 142 as in the intermediate layer 144. The etching process may include the use of CH4, Cl2, SF6, CH4, etc. x F y ,He,BCl3,N2,O2,H2,CF x CHF x Etching is performed using NF3, Ar, SiCl4, and combinations thereof.

[0060] As part of the etched bottom layer 142, the upper layer 148 may be consumed. After patterning the bottom layer 142, the opening 146 may expose the sidewalls of one or more spacers 124 formed by the remaining dielectric layer 110. The opening 146 may also expose portions of the hard mask layer 108 extending between adjacent spacers 124. In some embodiments, other portions of the spacers 124, such as the top surface, or other portions of the hard mask layer 108 may be exposed.

[0061] Next, refer to FIG. 17A to FIG. 17B For example, an ashing process can be used to remove any remaining portions of the bottom layer 142 and the intermediate layer 144. FIG. 17B As shown in the plan view, the sacrificial layer 136 has been patterned to form two discrete portions, each portion covering (at least partially) the gap between two adjacent spacers 124. Both discrete portions extend in a direction perpendicular to the direction in which the spacers 124 extend.

[0062] Next, refer to FIG. 18A to FIG. 18B A planarization process is performed to remove excess portions of the sacrificial material 136 and planarize the top surface of the sacrificial material 136 to be flush with the top surface of the spacer 124. In some embodiments, the planarization process includes one or more etching processes. For example, etching processes utilizing CH4, Cl2, SF6, CH4, etc., can be used. x F y ,He,SiCl4,HBr,N2,O2,H2,CF x CHF x Dry etching processes using NF3, Ar, NF3, etc. In some embodiments, wet etching processes using diluted hydrofluoric acid (DHF) as the etching chemical can be used. In other embodiments, polishing processes such as CMP can be used. FIG. 18A and FIG. 18B The resulting structure is shown. Along... FIG. 18B Obtain the line A-A' shown in the plan view.FIG. 18A A cross-sectional view. From FIG. 18A to FIG. 18B As can be seen, the planarization of the sacrificial material creates multiple discrete portions of the sacrificial material, each of which covers the gap between two adjacent spacers. In some embodiments, each discrete portion covers the area where a wire cut will be formed between two adjacent portions of the conductor.

[0063] In some embodiments, not implemented FIG. 18A to FIG. 18B The planarization process shown is not implemented therein. FIG. 18A to FIG. 18B In the embodiment of the planarization process shown, subsequent processes can continue, wherein the top surface of the sacrificial material 136 is offset from the top surface of the spacer 124. For example, as previously described... FIG. 9 to FIG. 12A to FIG. 12B In some embodiments, the thickness of the sacrificial material 136 can be controlled by controlling the thickness of the bottom layer 126 (e.g., ...). FIG. 9 to FIG. 12A to FIG. 12B (As shown). When the sacrificial material 136 is relatively thin, for example because the bottom layer 126 is formed to be relatively thin, FIG. 18A to FIG. 18B The planarization process described herein may be unnecessary. This could reduce manufacturing costs and / or manufacturing time.

[0064] FIG. 19A to FIG. 19B to FIG. 22A to FIG. 22B The patterning of hard mask layer 108 and target layer 102 is shown. FIG. 19A to FIG. 19B to FIG. 22A to FIG. 22B In each of the diagrams, a cross-sectional view of the diagram ending in "A" is obtained along line A-A' shown in the plan view of the corresponding diagram ending in "B".

[0065] refer to FIG. 19A to FIG. 19B The hard mask layer 108 is patterned using spacers 124 and sacrificial material 136 as etching masks to form openings 150. In this way, the pattern of spacers 124 and sacrificial material 136 is transferred to the hard mask layer 108. In some embodiments, etching the hard mask layer 108 includes anisotropic dry etching and / or wet etching. FIG. 19A and FIG. 19B The resulting structure is shown in the diagram. Along... FIG. 19A Obtain the line A-A' shown in the plan view. FIG. 19B Cross-sectional view.

[0066] like FIG. 19A and FIG. 19BAs shown, the remaining portion of the sacrificial material 136 prevents etching of the hard mask layer 108 located beneath the remaining portion of the sacrificial material 136, and effectively creates a break or "cutout" in the opening 150 when the sacrificial material is present, which would otherwise create a break or "cutout" in the hard mask layer 108 located between two adjacent spacers 124. As will be discussed in detail below, when the pattern of the hard mask layer 108 is subsequently transferred to the target layer 102 and conductive components are formed in the grooves, the sacrificial material 136 creates a gap or "line cutout" between two adjacent portions of the conductor.

[0067] After patterning the hard mask layer 108, wet cleaning can be performed to remove any remaining portion of the spacer 124 and sacrificial material 136. FIG. 20A and FIG. 20B The resulting structure is shown in the figure.

[0068] Subsequently, in FIG. 21A and FIG. 21B In this process, the hard mask layer 108 serves as an etching mask to extend the opening 150 into the target layer 102. Etching the target layer 102 may include an anisotropic dry etching process and / or a wet etching process, which sequentially etches through the ARC layer 106 to the target layer 102. The remaining portion of the target layer 102 may have a similar shape to... FIG. 19A to FIG. 19B The spacer 124 and the sacrificial material 136 have the same pattern. Thus, the target layer 102 is patterned in a single patterning step.

[0069] After patterning the opening 150, a wet cleaning process can be performed to remove any remaining portions of the hard mask layer 108 and the ARC layer 106. FIG. 22A to FIG. 22B The resulting structure is shown in the figure.

[0070] After patterning openings 150 in target layer 102, components can be formed within the openings. In this embodiment, target layer 102 is a low-k dielectric, and the patterned target layer 102 provides an interconnect structure IMD. Conductive components such as copper wires, copper vias, and / or cobalt plugs can be formed within the IMD.

[0071] refer to FIG. 23 One or more pads 162 can be formed along the sidewalls and bottom surface of the opening 150. The pads 162 may include TiO, TiN, TaO, TaN, Ru, Co, Ta, etc., and may provide a diffusion barrier layer, an adhesive layer, and / or a seed layer for conductive components. The pads can be deposited using any suitable process such as PVD, CVD, ALD, etc.

[0072] Next, as FIG. 24 As shown, the remaining portion of opening 150 can be filled with a conductive material 164, such as copper, using methods such as PVD or plating. FIG. 23(As shown in the diagram). Conductive material 164 can be initially deposited to fill the opening 150.

[0073] refer to FIG. 25A to FIG. 25B A planarization process is performed to remove the remaining portion of conductive material 164 located above target layer 102. Therefore, conductive components can be formed in target layer 102. In embodiments where the conductive component in target layer 102 is a wire, it is the region located below a portion of sacrificial material 136 when the hard mask 108 is patterned (see...). FIG. 19A to FIG. 19B () is the area where the conductor has gaps or "wire cuts".

[0074] As described above FIG. 12A and FIG. 12B As discussed, in some embodiments, the duration can be extended. FIG. 12A and FIG. 12B The length of the strip of sacrificial material 136 shown, or additional strips of sacrificial material 136 can be formed. If the length of sacrificial material 136 is extended, it can be extended... FIG. 25A and FIG. 25B The wire cut shown is such that additional conductors have the aforementioned wire cut. If multiple sacrificial materials 136 are formed, then... FIG. 25B The described conductor may have additional wire cuts offset from the illustrated wire cut. By employing the embodiments discussed herein, fine-pitch conductors with wire cut pitches of approximately 85.5 nm or greater can be formed. If an extreme ultraviolet lithography system is used in the patterning process discussed herein, for example, for the combination as described above... FIG. 7 The patterned upper layer 132 discussed can achieve a reduced line cut pitch. For example, a line cut pitch of about 30 nm or larger can be achieved.

[0075] If the process discussed in this paper is used repeatedly, wires with a line cut pitch of approximately 30 nm or 48 nm or larger can be formed with fewer manufacturing defects and increased yield. For example, the above combination can be repeated multiple times. FIG. 6 to FIG. 12A to FIG. 12B The discussed process involves forming multiple patterned sacrificial material lines (e.g., to form multiple adjacent line cuts in a subsequent processing), followed by... FIG. 13A to FIG. 13B to FIG. 25A to FIG. 25B The discussion focuses on additional processes to transfer conductors with multiple adjacent line cuts to the target layer. With this additional processing, line cut pitches of approximately 30nm, 48nm, or even larger can be achieved. However, this involves repeated processing... FIG. 6 to FIG. 12A to FIG. 12B The process discussed in the paper reduces the size of the interconnects, so the size of the resulting interconnects can vary slightly from the target size and / or alignment issues may occur.

[0076] refer to FIG. 26This provides a method 200 for forming interconnects in a target layer. In step 168, for example, as... FIG. 1 to FIG. 3 As shown, the photoresist is patterned to form a mask. In step 170, for example, as... FIG. 4 As shown, a mask is used as an etching mask to etch the dielectric layer. In step 172, for example, as... FIG. 6 to FIG. 9 As shown, another photoresist is formed and patterned to form another mask. In step 174, for example, as... FIG. 10 to FIG. 11 As shown, sacrificial material is formed in the opening of the mask. In step 176, for example, as... FIG. 12A to FIG. 12B As shown, the mask is removed. In some embodiments, steps 172 to 176 may be repeated multiple times, for example, to form a conductor with multiple wire cuts having a small wire cut pitch. In step 178, for example, as... FIG. 13A to FIG. 13B to FIG. 15A to FIG. 15B As shown, another photoresist is formed and patterned to form another mask. In step 180, for example, as... FIG. 16A to FIG. 16B As shown, a mask is used to pattern the sacrificial material. In step 182, for example, as... FIG. 17A to FIG. 17B As shown, the mask is removed. In step 184, for example, as... FIG. 18A to FIG. 18B As shown, the sacrificial material is thinned. In step 186, for example, as... FIG. 19A to FIG. 19B As shown, the metal hard mask layer is etched. In step 188, for example, as... FIG. 21A to FIG. 21B As shown, a hard metal mask layer is used to pattern the target layer. In step 190, for example, as... FIG. 23 to FIG. 25A to FIG. 25B As shown, a wire with one or more line cuts is formed in the opening of the target layer.

[0077] In some embodiments, such as FIG. 25A to FIG. 25B As shown, the patterning method described herein can be used to form interconnects in a target layer. Interconnects can be formed with fine pitch, and multiple wire cuts can be formed with small wire cut pitch. Simplified patterning processes can be used to form interconnects with improved accuracy. For example, a single patterning process can be used to pattern the target layer to form fine-pitch interconnects with one or more wire cuts. Because the target layer is patterned in a single patterning process (or a simplified patterning process), improved patterning accuracy can be achieved. For example, if the target layer 102 is etched in two or more different processes, the pattern actually etched into the target layer 102 may differ from the desired pattern, for example, due to the difficulty in precisely aligning the etch mask with the portion to be etched. Improved accuracy is possible when the target layer 102 is etched using a single etch step and / or a simplified patterning process as described herein. Thus, multiple interconnects with one or more wire cuts can be formed with the same or substantially the same dimensions, which allows for better control of the interconnect resistance.

[0078] In some embodiments, the above combination FIG. 1 to FIG. 25A to FIG. 25B The described process can be used to form power rails and / or metal island structures, such as FIG. 27 to FIG. 30 The power rail and metal island structure described above. For example, the combination described above can be used. FIG. 1 to 25A to FIG. 25B The described process is formed in target layer 102. FIG. 27 to FIG. 30 The power rail and metal island structure are described above. In some embodiments, as described above... FIG. 1 to FIG. 5 The method describes forming a plurality of spacers above the dielectric layer, wherein a gap between one or more of the spacers defines a groove formed in the target layer for forming a power rail, and wherein a gap between other spacers defines a groove formed in the target layer for forming a plurality of conductors adjacent to the power rail, wherein the conductors extend in a direction parallel to the main axis of the power rail. A sacrificial material (such as a bonding agent) can be formed and patterned above the dielectric layer. FIG. 6 to FIG. 18A to FIG. 18B (As discussed), wherein the sacrificial material is defined by multiple wire cuts extending in a direction perpendicular to the direction of the power rail and the conductor. The combination of the spacer and the sacrificial material can define FIG. 27 to FIG. 30 The structure shown. For example, as shown in the example. FIG. 19A to FIG. 19B to FIG. 22A to FIG. 22B As shown, the patterns of the sacrificial material and spacers are transferred to the target layer. (See diagram) FIG. 23 to FIG. 25A to FIG. 25B As shown, conductors are formed in the patterned target layer to form FIG. 27 to FIG. 30 The structure shown.

[0079] In some embodiments, this document combines FIG. 1 to FIG. 25A to FIG. 25B The described process can be used to form narrow power rails and / or groups of metal islands well aligned with other groups of metal islands. Due to the process used to form the power rails and metal islands, kinks may be present in the formed power rails. Kinks can reduce the reliability of the contacts to the power rails. To avoid kinks, the contacts to the power rails may be restricted to portions of the power rails outside of "contactless areas," where kinks may exist at the edges of the power rails.

[0080] FIG. 27 This illustrates a power rail and metal island structure 2300 that can be formed in target layer 2316 using the processes described herein. In some embodiments, target layer 2316 is coupled with... FIG. 1 to FIG. 25A to FIG. 25BThe target layer 102 described herein is the same as or similar. The power rail and metal island structure 2300 includes a power rail 2302. In some embodiments, the power rail 2302 facilitates the distribution of power such as Vdd or ground power within the device. For example, the power rail 2302 may be electrically connected to a power or ground node, and contacts (not shown) may be formed at different locations along the power rail 2302, electrically connected to the power rail 2302, and thereby connecting the power rail 2302 to a power or ground node. The processes described herein can be used to form the power rail 2302 with relatively small dimensions. For example, in some embodiments, the power rail 2302 may have a thickness T4 of about 55 nm or less.

[0081] The power rail and metal island structure 2300 may further include a metal island 2312. In some embodiments, the metal island 2312 may be used to distribute power and / or signals within the device. FIG. 27 As shown, the process described herein can be used to form an array of metal islands 2312 having a line pitch P2 greater than or equal to about 85.5 nm and a line pitch P5 greater than or equal to about 30 nm. Because the process described herein allows the array of metal islands 2312 to be formed with a fine line pitch and a fine line pitch, a greater number of metal islands 2312 can be formed in the spacing adjacent to the power rail 2302. Additionally, the process described herein can be used to form a group 2304 of metal islands 2312 that is well aligned with another group 2306 of metal islands 2312. In some embodiments, the group 2304 of metal islands is well aligned with another group 2306 of metal islands 2302, for example, because the same line pitch (i.e., the same sacrificial material 136 of the same strip) can be used to form the group 2304 and the group 2306 of metal islands. The sidewalls of the metal islands 2312 of the group 2304 of metal islands can be aligned with the sidewalls of the metal islands 2312 of the group 2306 of metal islands. Furthermore, as FIG. 27 As shown, the process described herein can be used to form a group of metal islands 2312 with a fine-line notch pitch P2 (such as greater than or equal to about 85.5 nm), wherein each metal island 2312 has the same or substantially the same dimensions as the other metal islands 2312 in the group. For example, in some embodiments, each metal island 2312 may have a length L1 of about 45 nm to about 60 nm.

[0082] In some embodiments, such as FIG. 28 As shown, the process described herein can be used to form a power rail and metal island structure 2400 in target layer 2416. In some embodiments, target layer 2416 is combined with... FIG. 1 to FIG. 25A to FIG. 25BThe target layer 102 described is the same as or similar to the one described above. The power rail and metal island structure 2400 includes a power rail 2402. In some embodiments, the power rail 2402 facilitates the distribution of power such as Vdd or ground within the device. The power rail 2402 can be similar to the combination described above. FIG. 27 The power rail 2302 is discussed. For example, in some embodiments, the power rail 2402 may have a thickness T5 of about 55 nm or less. The power rail and metal island structure 2400 may also include a metal island 2412. As described above... FIG. 27 The metal island 2412 may be similar to or the same as the metal island 2312. The metal island 2412 may have a line-cut pitch P3, wherein the line-cut pitch P3 may be associated with the bonding... FIG. 27 The line cut pitch P2 discussed is the same or similar.

[0083] like FIG. 28 As shown, the process described herein for forming the power rail and metal island structure 2400 can also form a kink 2414 extending into the power rail 2402. For example, the process for forming the power rail and metal island structure may have inherent accuracy limitations, such as limiting the ability to align an etch mask with a specific portion of the underlying layer to be etched. The processing equipment used to form the power rail and metal island structure 2400 may have inaccuracies or defects. Thus, the process described herein may result in the formation of a kink at the edge of the power rail 2402. The kink 2414 can reduce the reliability of any physical or electrical connections to the power rail 2402 formed in the edge region of the power rail 2402, where the kink 2414 can be formed in the edge region of the power rail 2402. In some embodiments, the kink 2414 may extend a distance D1 in the power rail 2402, where D1 is about 5 nm to about 8 nm.

[0084] In some embodiments, to avoid forming contacts that may be affected by one or more kinks 2414 and thus have reduced reliability, one or more contactless regions 2408 may be included along the edge of the power rail 2402 forming the kinks 2414. For example, semiconductor devices may be designed and formed such that physical and / or electrical connections to the power rail 2402 are formed outside the contactless regions 2408 of the power rail 2402. In some manufacturing processes, a computer-based processing system (e.g., ...) may be used prior to formation. FIG. 31The computer-based processing system 300 (discussed in detail below) is used to design semiconductor devices. This system enables the use of one or more design rules to guide designers in routing electrical connections within a virtual semiconductor device layout, for example, to ensure adherence to minimum distances specified by a particular processing technique in a given design. In some embodiments, a contactless region 2408 may be included as a design rule to prevent the formation of physical and / or electrical connections to the power rail 2402 within the contactless region 2408. Thus, when the design is completed and the semiconductor device is formed according to the planned design, all contacts to the power rail 2402 can be formed outside the contactless region 2408 according to the design rules.

[0085] In some embodiments, the contactless region 2408 may extend a distance D2 into the power rail 2402, wherein D2 is approximately 5 nm to approximately 10 nm. In embodiments, a plurality of contactless regions 2408 may be included (e.g., located on opposite sides of the power rail 2402), or only a single contactless region 2408 may be included.

[0086] FIG. 29 The diagram illustrates the formation of a power rail and metal island structure 2500 in a target layer 2516 according to some embodiments. In some embodiments, the target layer 2516 is combined with... FIG. 1 to FIG. 25A to FIG. 25B The target layer 102 described is the same as or similar to this. The above combination can be used. FIG. 1 to FIG. 25A to FIG. 25B The described process forms a power rail and metal island structure 2500. The power rail and metal island structure 2500 may include a power rail 2502 and a metal island 2512. The power rail 2502 may be the same as or similar to the power rail 2402, and the metal island 2512 may be the same as or similar to the metal island 2412.

[0087] In some embodiments, the combination can be used multiple times. FIG. 1 to FIG. 25A to FIG. 25B The specific process described, such as the combination above FIG. 6 to FIG. 12A to FIG. 12B The process described. In the 10nm technology node, the metal island 2512 may have a line-cut pitch P4 of approximately 30nm to 48nm. In some embodiments, inaccuracies that may occur during manufacturing (examples of which have been discussed above) may become more problematic as the pitch decreases. In some embodiments, it may be more difficult to manufacture multiple metal islands 2512 with the same or substantially similar dimensions when the pitch of the metal island (e.g., metal island 2512) decreases. Thus, when the pitch P4 of the metal island 2512 is approximately 30nm to 48nm, the dimensions of the metal island 2512 can be varied. For example, the length L2 of a particular metal island 2512 and the bonding... FIG. 27The metal islands 2312 described are of the same length L1. Other metal islands 2512 may have a length L3 of about 10 nm to about 35 nm.

[0088] As described above, in some embodiments, the above combination is used. FIG. 1 to FIG. 25A to FIG. 25B The accuracy of the pattern formed in target layer 102 by the described process depends on the accuracy of different processing steps (e.g., the accuracy with which the patterning mask used in the patterning process is formed and / or the accuracy achievable in the etching process where the upper mask transfers its pattern to the lower layer). In particular, when the target pitch of the metal islands 2512 is reduced to, for example, a pitch P4 of about 30 nm to 48 nm, slight deviations may occur in the desired pattern. These slight deviations may result in slight misalignment of the groups of metal islands. For example, as... Figure 29 As shown, metal island group 2504 is offset from metal island group 2506. As mentioned above, this offset can also lead to the formation of kinks 2514. Kinks 2514 are related to the bonding... Figure 27 The described kink 2414 is the same as or similar. Therefore, a contactless area 2508 may be required. The contactless element 2508 can be coupled with... Figure 28 The contactless area 2408 discussed is the same as or similar to that discussed.

[0089] In some embodiments, the above combinations may be formed. Figures 27 to 29 The single power rail and metal island structure are discussed for some or all of the features. Figure 30 The power supply rail and metal island structure 2900 are shown. The metal structure 2900 may include various parts formed in different sizes. For example, as shown above... Figure 27 In the first part of the discussion, the power rail and metal island structure 2900 are formed as a component including the power rail and metal island structure 2300. As discussed above... Figure 28 As discussed in the second part, the power rail and metal island structure 2900 are formed as a component including the power rail and metal island structure 2400. (As described above...) Figure 29 In the third part of the discussion, the power rail and metal island structure 2900 are formed as a component including the power rail and metal island structure 2500.

[0090] As described above, processing systems such as computers can be used to design and optimize the virtual layout of semiconductor devices to be formed. After the virtual layout is optimized on the processing system, the optimized layout can be used as a guide for subsequent semiconductor chip formation.

[0091] refer to Figure 31The diagram illustrates a block diagram of the components of a processing system 300, which can be used to generate a diagram showing a virtual layout of a semiconductor chip to be formed. The processing system 300 may include a processor 302 equipped with one or more input / output devices such as a video adapter / graphics processing unit (“GPU”). The processor 302 may include a central processing unit (“CPU”) / DSP, memory, and hardware accelerators connected to a bus 304.

[0092] Bus 304 can be one or more of any bus architectures, including a memory bus or memory controller, a peripheral bus or video bus, etc. The CPU can be formed by any type of electronic data processor. The memory can be formed by any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), non-volatile random access memory (“NVRAM”), combinations thereof, etc. In embodiments, the memory may include ROM used at startup and DRAM used for data storage during program execution. The memory may store programs that enable users to view, modify, and / or optimize the virtual layout of the semiconductor chip to be formed. The memory may store parameters, rules, etc., to help users design, modify, and / or optimize the virtual layout of the semiconductor chip to be formed. For example, the memory may store one or more design rules that can be used to ensure that the minimum distance required for a specific technology or process is met, thereby optimizing the virtual layout of the semiconductor chip to be formed.

[0093] The video adapter / GPU provides an interface to connect external inputs and outputs from the display 306 to the processor. The display 306 can display a virtual layout of the semiconductor chips to be formed. Other devices can be connected to the processor 302, and additional or individual interface cards can be used. For example, a serial interface card (not shown) can be used to provide a serial interface for use with a printer.

[0094] The processor 302 may also include a network interface (not shown), which may be a wired link such as an Ethernet cable and / or a wireless link to enable communication with a network such as a cellular communication network. The network interface allows the processor to communicate with remote units over a network. In embodiments, the processor 302 is connected to a local area network (LAN) or a wide area network (WAN) to provide communication to remote devices such as other processors, the Internet, remote storage facilities, etc.

[0095] It should be noted that the processing system 300 may include other components. For example, the processing system 300 may include a power supply, cables, a motherboard, a removable storage medium, a casing, etc. Although not shown, these other components can be considered as part of the processing system 300.

[0096] In some embodiments, the planned semiconductor device may include wires, interconnects, and the layout of the resulting semiconductor chip can be optimized by removing unwanted portions of the wires. For example, multiple wires may have one or more wire cuts, and in some embodiments, the above combination can be used. Figures 1 to 25B The methods discussed form wire cuts. Wire cuts can be formed in the middle section of a conductor. After forming multiple conductors with one or more wire cuts, portions of one or more conductors may be unnecessary or undesirable. For example, as... Figure 32 As shown, wire 308 can be used to form an electrical connection between a first end 312 of wire 308 and a through hole 316, and between a second end 323 of wire 308 and a through hole 318. A wire cut 320 can be formed between through holes 316 and 318. From Figure 32 As can be seen, the portion 322 extending between the in-line cutout 320 and the via 316 of the conductor 308 may be unused (e.g., this portion 322 of the conductor may not be required for any desired electrical connection in a given layout). In some devices, unnecessary or undesirable metal lines can be detrimental in semiconductor devices. For example, unnecessary or undesirable metal lines may degrade the RC performance of the semiconductor device and / or may adversely increase the size and / or footprint of the semiconductor device.

[0097] In some embodiments, wires can be formed in a manner that avoids forming unnecessary or unwanted wire ends, which can improve the RC performance of the semiconductor device and / or reduce the size or footprint of the semiconductor device. Figure 33A A comparison is shown between virtual layouts (e.g., 324, 330) and physical conductive components formed using virtual layouts as guidelines (e.g., 326, 332). Figure 33A Also shown are parameters that can be used to calculate the target cut width of the wire cut that can be used during the formation of physical conductors (see [reference]). Figures 34 to 47 This will allow unnecessary or undesirable wire ends to be omitted in the formed semiconductor device, thereby improving the RC constant of the device and / or reducing the size or footprint of the semiconductor device.

[0098] Figure 33A A virtual layout 324 is shown over the physical conductor 326, wherein the virtual layout 324 can be used as a guide to form the physical conductor 326. Figure 33AA virtual layout 330 is also shown over the physical conductor 332, which can be used as a guide for forming the physical conductor 332. In the physical conductor 326, the portion extending between the via 328 and the line end 338 is unused, and it would be advantageous to remove or not form it in the semiconductor device being manufactured. In the physical conductor 332, the portion extending between the via 334 and the line end 336 is unused, and it would be advantageous to remove or not form it in the semiconductor chip being manufactured.

[0099] In each of physical conductors 326 and 332, EN is the width of the target virtual conductor cutout in the virtual layout, and W is the minimum distance between the edge of a virtual via in the virtual layout (e.g., 328 or 334) and the nearest edge of the target virtual conductor cutout EN. In some embodiments, W is a parameter defined by design rules of a specific technology, for example, to ensure that physical conductors 326 above via 328 and physical conductors above via 334 are not removed, for example, due to inaccuracies introduced by the processing techniques used to form the semiconductor device when using the virtual layout as a guide for forming a semiconductor device.

[0100] like Figure 33A As shown, for example, due to inaccuracies introduced by various processing techniques or imperfections or deviations in the equipment used in the processing, the physical guides formed using a virtual layout as a guide can differ from the virtual layout in various aspects. Figure 33A In this configuration, a physical conductor 326 is formed such that the line end 338 does not reach the planned line end of the virtual layout 324 (the virtual layout 324 is used as a guide for formation). In some embodiments, the distance between the line end 338 of the physical conductor 326 and the planned line end of the virtual layout 324 can vary within a maximum distance S. On the other hand, the physical conductor 332 can be formed such that the line end 336 extends beyond the planned line end of the virtual layout 330 by a maximum distance S. In other words, there may be a variation of + / -S or 2S between the planned line end of the planned conductor and the actual line end of the actual conductor, wherein the actual line end can be formed to extend the maximum distance S to the farthest point on either side of the planned line end. Thus, the actual line end can be formed within a 2S offset range of the planned line end. In some embodiments, S can be from about 0 nm to about 5 nm.

[0101] In some embodiments, during the formation of a semiconductor device, it may be desirable to align the planned line cut with specific locations on the conductor. For example, it may be desirable to position the central axis of the planned line cut so that it intersects the center point of line EN. However, the ability to achieve precise alignment may be limited due to the processing constraints discussed herein, and some variations may occur during normal processing. Figure 33BThis illustrates that, during the formation of the actual device, the planned center axis 341 of the planned line cut 343 is offset from the center axis 345 of the actual line cut 347, which is formed using the planned line cut 343 as a guide. A coverage distance V can be defined, where V is the distance the line cut moves along the X-axis between the actual and planned positions. Figure 33B (As shown in the image). See again. Figure 33A This shows the actual line cut 340 that has been offset, causing the central axis 342 to deviate from the center point of the dashed line EN. (Reference) Figure 33B In the actual manufacturing process, the wire cut 347 can actually be located at a distance V along the x-axis from a first side of the planned wire cut 343, or at a distance V along the x-axis from a second side, where the second side is opposite to the first side. In some embodiments, V can be from about 0 nm to about 6 nm. The value of V depends on the processing equipment used to form the wire cut 340 and / or the wires 326 and 332, and any processing limitations or inaccuracies introduced by the equipment.

[0102] Variations in the target cut width CD can also be considered. For example, in some embodiments, a wire cut 340 with the desired target cut width CD can be determined (e.g., using a virtual layout) to remove unwanted ends of a particular conductor. However, due to limitations in the accuracy of the processing technique or variations in the processing equipment, when the wire cut 340 is used in forming the physical conductor, the wire cut 340 may have an actual cut width that is slightly different from the target cut width CD. In some embodiments, the actual cut width may be an amount Z (not shown) wider than the target cut width CD. In some embodiments, the actual cut width may be an amount Z narrower than the target cut width CD. Therefore, a cut width variation of + / - Z or 2Z can be considered. In some embodiments, Z can be about 0 nm to about 1 nm.

[0103] In some embodiments, the optimal cut width CD can be determined based on the parameters described above. The optimal cut width CD can be determined based on the following relationship:

[0104] The cut CD = 2X + S + 2 × (Z^2 + V^2)^0.5,

[0105] Where 2X is EN, the target length of the virtual wire to be removed in the virtual layout, S is half of the offset range 2S, Z is half of the cut width variation 2Z, and V is the distance the wire cut can move between the actual and planned positions. The determined optimal cut width CD can be used to form a wire with removed unused wire ends, as described below (see...). Figures 34 to 47 Conductors formed using a wire cut with a cut width CD determined by this relationship can have a wider process window during conductor formation.

[0106] Figures 34 to 47 The diagram illustrates the formation of wires according to some embodiments. Figure 34 In this process, a film stack 415 is formed over a semiconductor substrate 402. The film stack 415 includes a dielectric layer 404 formed over the semiconductor substrate 402, a dielectric layer 406 formed over the dielectric layer 404, a hard mask layer 408 formed over the dielectric layer 406, a second capping layer 410 formed over the hard mask layer 408, an etch stop layer 412 formed over the second capping layer 410, and a first capping layer 414 formed over the etch stop layer 412. Each layer is discussed in detail below.

[0107] like Figure 34 As shown, a film stack 415 is formed over a semiconductor substrate 402. The semiconductor substrate 402 may be formed of a semiconductor material such as doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate as the active layer. The semiconductor substrate 402 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. (not shown) may be formed in and / or on the active surface of the semiconductor substrate 402. One or more interconnects and / or vias (not shown) may be included in the semiconductor substrate 402. For example, vias 416 are electrically connected to one or more devices (not shown) located in the semiconductor substrate 402 using one or more wires (not shown) and / or one or more conductive vias (not shown).

[0108] A dielectric layer 404 is formed over a semiconductor substrate 402. In some embodiments, the dielectric layer 404 is an inter-metal dielectric (IMD) layer. In this embodiment, the dielectric layer 404 comprises a low-k dielectric material having a dielectric constant (k value) less than 3.8, less than about 3.0, or less than about 2.5. In an alternative embodiment, the dielectric layer 404 is an IMD layer comprising a high-k dielectric material having a k value greater than 3.8. Other materials may also be used.

[0109] like Figure 34 As shown, a via 416 is formed in dielectric layer 404. In some embodiments, via 416 can provide access from the dielectric layer 406 (see Figure 404). Figure 47Electrical connections are made between the conductors in the dielectric layer 404 and devices located in the semiconductor substrate 402 (not shown). Vias 416 can be formed, for example, using an acceptable photolithography process (such as the one described herein) by forming openings in the dielectric layer 404. One or more pads can be deposited in the openings. A conductive material can then be deposited in the openings above the one or more pads, for example, using a plating process. After the plating process is complete, excess conductive material can be left to fill the openings and extend along the top surface (not shown) of the dielectric layer 404. Figure 34 As shown, a planarization process such as chemical mechanical polishing can be used to remove excess conductive material and make the top surface of via 416 flush with the top surface of dielectric layer 404. Other processes can also be used.

[0110] A dielectric layer 406 is formed over dielectric layer 404. In some embodiments, conductors are formed in dielectric layer 404. The conductors can be formed in a manner that does not form undesirable wire ends. Dielectric layer 406 can be formed using the same or similar processes described in connection with dielectric layer 404. In some embodiments, dielectric layer 404 has the same material composition as dielectric layer 406. In other embodiments, dielectric layer 404 has a different material composition than dielectric layer 406.

[0111] A hard mask layer 408 is formed over the dielectric layer 406. The hard mask layer 408 can be formed of materials including metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, metal-doped carbides (e.g., tungsten carbide)) and / or non-metals (e.g., silicon nitride, boron nitride, silicon carbide, etc.) and can be formed by PVD, radio frequency PVD (RFPVD), atomic layer deposition (ALD), etc. Other processes and materials can be used. In subsequent processing steps, a pattern is formed on the hard mask layer 408 (see...). Figures 44A to 44B Then the hard mask layer 408 is used as an etching mask for etching the dielectric layer 406.

[0112] A second capping layer 410 is formed over the hard mask layer 408. The second capping layer 410 can be formed using silicon oxide such as borophosphosilicate tetraethyl orthosilicate (BPTEOS) or undoped tetraethyl orthosilicate (TEOS) oxide. In some embodiments, the second capping layer 410 is a low-temperature oxide (LTO). As used herein, the term "LTO" refers to an oxide deposited using a relatively low process temperature (e.g., 200°C or lower). The second capping layer 410 can be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials can be used.

[0113] An etch stop layer 412 is formed over the second cover layer 410. In some embodiments, SiC or SiOC can be used. x SiN, SiON xAn etch stop layer is formed. The etch stop layer 412 can be formed from a suitable material that has high etch selectivity relative to the first cover layer 414. The etch stop layer 412 can be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials can also be used.

[0114] A first capping layer 414 is formed over the etch stop layer 412. The first capping layer 414 can be formed using silicon oxide such as BPTEOS or undoped TEOS oxide. In some embodiments, the first capping layer 414 is LTO. The first capping layer 414 can be formed using the same material as the second capping layer 410. In other embodiments, the first capping layer 414 is formed of a different material than the second capping layer 410. The second capping layer 410 can be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials can be used.

[0115] exist Figure 35 In this process, the first capping layer 414 is patterned to form an opening 418. The opening 418 covers the dielectric layer 406, where a mask 420 will be formed (see [link]). Figure 37 The area of ​​) opening 418. The opening 418 can have the above-described combination. Figures 33A to 33B The target width CD is defined as described herein. The aperture 418 can be formed using, for example, an acceptable photolithography process as described herein.

[0116] exist Figure 36 In this process, a mask material 421 is disposed above the first cover layer 414 and in the opening 418, thereby filling the opening 418 with the mask material 421. In some embodiments, the mask material 421 comprises SiO2. x SiN x SiC x Metal oxides, metal nitrides, etc. In some embodiments, mask material 421 may comprise any suitable inorganic material having high etch selectivity relative to the material of hard mask layer 408. Mask material 421 may be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials may be used.

[0117] exist Figure 37 In this process, excess portions of mask material 421 are removed to form mask 420. In some embodiments, a polishing process such as chemical mechanical polishing can be used to remove excess portions of the mask material 420. In other embodiments, an etching process can be used to remove excess portions of the mask material 420. After removing excess portions of the mask material 420, the upper and lower surfaces of the mask 420 are flush with the upper and lower surfaces of the first cover layer 414. Other processes and materials can be used.

[0118] like Figure 37As shown, the first cover layer 414 and the mask 420 have a thickness T1, and the etch stop layer 412 has a thickness T2. In some embodiments, T1 is greater than or equal to half the cut width CD, wherein, as combined Figures 33A to 33B As described, the slit width CD is determined. In other words, in some embodiments, T1 ≥ 0.5 × CD. In some embodiments, the combined thickness of T1 and T2 satisfies the following relationship:

[0119] T1+T2=T3×(1+TargetOE% / sel(Hard Mask Layer 408 / Etching Stop Layer 412)).

[0120] Where T1 is the thickness of the first capping layer 414, T2 is the thickness of the etch stop layer 412, T3 is the thickness of the hard mask layer 408, the target OE% is the target over-etch percentage used in manufacturing semiconductor devices, and sel(hard mask layer 408 / etch stop layer 412) is the etch selectivity of the hard mask layer 408 relative to the etch stop layer 412. When the above relationship is satisfied, when etching the hard mask layer (see...) Figures 44A to 44B During etching, mask layer 420, etch stop layer 412, and first cover layer 414 are consumed. Due to the consumption of mask layer 420, etch stop layer 412, and first cover layer 414, the hard mask layer 408 and second cover layer 410 have approximately uniform heights after the etching process terminates. This allows subsequent etching of dielectric layer 406 to form conductors therein to be performed more reliably with fewer failures, and / or the etch window can be maintained without undesirably shrinking, which could lead to difficulties filling openings in dielectric layer 406 with conductive material.

[0121] exist Figure 38 In this embodiment, three masking layers are formed over the first capping layer 414 and the mask 420. The three layers include a bottom layer (sometimes also called a lower layer) 422, an intermediate layer 424 above the bottom layer 422, and an upper layer 426 above the intermediate layer 424. According to some embodiments, the upper layer 426 may be formed of photoresist. Positive or negative photosensitive materials can be used. The intermediate layer 424 may be formed of an inorganic material, wherein the inorganic material may be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The bottom layer 422 may be a polymer or an anti-reflective material. The intermediate layer 424 may have high etch selectivity relative to the upper layer 426 and the bottom layer 422. Therefore, the upper layer 426 can be used as an etch mask for patterning the intermediate layer 424, and the intermediate layer 424 can be used as an etch mask for patterning the bottom layer 422. Other materials may also be used.

[0122] exist Figure 39In this process, the upper layer 426 is patterned to form openings 428 and 429. Opening 429 has a conductor pattern that will be formed in the dielectric layer 406. Opening 428, together with the mask 420, has a pattern for another conductor that will be formed in the dielectric layer 406. Figure 39 As shown, for example, due to limitations in the accuracy of the processing technology or variations in the equipment used to form the semiconductor device, the sidewall of the opening 428 may be offset from the sidewall of the mask 420.

[0123] Next, refer to Figure 40 The patterned upper layer 426 is used as an etching mask to etch the middle layer 424, thereby transferring the pattern of the upper layer 426 to the middle layer 424.

[0124] refer to Figure 41 After etching the intermediate layer 424, the bottom layer 422 is patterned, wherein the intermediate layer 424 serves as an etching mask. During the patterning of the bottom layer 422, the upper layer 426 may be consumed. The patterning of the bottom layer 422 exposes a portion of the top surface of the mask 420 and a portion of the top surface of the first overlay layer 414. After patterning the bottom layer 422, any remaining portions of the intermediate layer 424 may be removed.

[0125] exist Figure 42 In the middle, the bottom layer 422 is then used as an etching mask to etch the underlying first cover layer 414, etch stop layer 412, and second cover layer 410. Any suitable etching process, such as wet etching or dry etching, can be used. In some embodiments, the etching process is anisotropic. Figure 42 As shown, the mask 420 prevents the portion 440 of the etch stop layer 412 and the second cover layer 410 located below the mask 420 from being etched. Thus, the size of the wires subsequently formed in the opening 428 is smaller than the size would be without the mask 420. Therefore, no wire ends (e.g., unused wire ends) are formed.

[0126] refer to Figure 43 After patterning the first cover layer 414, etch stop layer 412, and second cover layer 410, the remaining portion of the underlying layer 422 is removed, for example, in an ashing process. In some embodiments, the patterning of the first cover layer 414, etch stop layer 412, and second cover layer 410 consumes the underlying layer, and the separate step of removing the underlying layer 422 may be omitted.

[0127] Next, the hard mask layer 408 is etched to extend the openings 428 and 429 into the hard mask layer 408. Figure 44A and Figure 44B Plan and cross-sectional views of the semiconductor device 400 after etching the hard mask layer 408 are depicted. Along... Figure 44B Obtain the line A-A' shown in the plan view. Figure 44AA cross-sectional view. Any suitable etching process, such as wet etching or dry etching, can be used for the hard mask layer 408. In some embodiments, the etching process is anisotropic. During etching of the hard mask layer 408, the mask layer 420, the etch stop layer 412, and the first capping layer 414 are consumed. Due to the consumption of the mask layer 420, the etch stop layer 412, and the first capping layer 414, the hard mask layer 408 and the second capping layer 410 have a substantially uniform height after the etching process terminates. Thus, subsequent etching of the dielectric layer 406 to form wires therein can be carried out more reliably with fewer failures, and / or the etch window can be maintained and will not undesirably shrink, which could lead to difficulty in filling the openings in the dielectric layer 406 with conductive material.

[0128] exist Figure 45A and Figure 45B In this process, a hard mask layer 408 is used as an etching mask to etch the dielectric layer 406. The etching process extends openings 428 and 429 into the dielectric layer 406. Any suitable etching process can be used. In some embodiments, the etching process is anisotropic. The etching of the dielectric layer 406 exposes the top surface of the dielectric layer 404 and the via 416. Although the via 416 is in Figure 45B While the top view is rectangular, in other embodiments, the through-hole 416 may have any suitable shape, including circles, ellipses, polygons, squares, etc.

[0129] exist Figure 46 In the via 416, openings 428 and 429 are filled with conductive material 430. For example, in some embodiments, one or more pads (not shown) may be deposited in openings 428 and 429 and on the top surface of hard mask layer 408. The pads may include TiO, TiN, TaO, TaN, etc., and may provide a diffusion barrier layer, an adhesive layer, and / or a seed layer. The pads may be deposited using any suitable process such as PVD, CVD, ALD, etc. The remaining portions of openings 428 and 429 may then be filled with conductive material 430, for example, using a plating process. The pads and / or conductive material 430 contact via 416. Any suitable conductive material 430, such as copper or another metal, may be used. Figure 46 The resulting structure is shown in the figure.

[0130] exist Figure 47In this process, for example, a polishing process such as chemical mechanical polishing is used to remove excess conductive material 430. The polishing process can also remove the remainder of the hard mask layer 408. After the polishing process is completed, a conductor 444 has been formed in the dielectric layer 406. The top surface of the conductor 444 is flush with the top surface of the dielectric layer 406. Due to the use of the mask 420, the length of the conductor 444A is reduced compared to the length of the conductor 444A without the mask 420. Region 442 represents the section of the conductor 444A that should have been formed but has not yet been formed in the semiconductor device 400 without the mask 420.

[0131] In subsequent processing, an additional dielectric layer, with or without conductors, may be formed over dielectric layer 406. External contacts may be formed over semiconductor device 400, enabling semiconductor device 400 to be electrically connected and / or physically connected to additional devices.

[0132] Figure 48 A method according to some embodiments is shown. In step 502, for example, as in combination Figures 33A to 33B The discussion revolves around determining the optimal width of the line cut. In step 504, for example, as... Figure 35 As shown, an opening with an optimal width is patterned in the first overlay layer. In step 506, for example, as... Figure 36 As shown, the opening is filled with mask material. In step 508, for example, as... Figure 37 As shown, the mask material is planarized. In step 510, for example, as... Figures 38 to 41 As shown, photoresist is deposited and patterned to form openings. In step 512, for example, as... Figure 42 As shown, an etching process is performed using a mask. In step 514, for example, as... Figure 44A and Figure 44B As shown, a patterned hard mask layer. In step 516, for example, as... Figure 45A and Figure 45B As shown, a patterned hard mask is used to pattern the dielectric layer. In step 518, for example, as... Figure 46 As shown, the openings in the dielectric layer are filled with a conductive material. In step 520, for example, as... Figure 47 As shown, the conductive material is planarized.

[0133] As described herein, semiconductor devices and methods for forming semiconductor devices are provided according to some embodiments. A patterning process is performed to pattern lines in a target layer of the semiconductor device. In some embodiments, a dielectric layer is patterned using photolithography, and a patterned sacrificial material (sometimes referred to as a reverse material) is formed over the patterned dielectric layer. After the sacrificial material is formed, it is patterned by forming openings in the sacrificial material. The patterned dielectric layer and sacrificial material are used to pattern an underlying mask layer, which in turn is used to pattern the target layer using a single patterning step. Subsequently, conductive material can be filled into the openings in the low-k dielectric layer to define interconnects having line cuts defined by the patterned sacrificial material. The conductors can have finer pitches than those achievable using other similar patterning processes, and / or simplified patterning processes can be used to form interconnects with finer pitches. For example, a single patterning process can be used to pattern the target layer to form fine-pitch conductors with one or more line cuts. Because the target layer is patterned in a single patterning process and / or using simplified processes as described herein, improved patterning accuracy can be achieved. In this way, multiple interconnects can be formed to have the same or approximately the same size, which allows for better control over the resistance of the interconnects.

[0134] In some embodiments, the target width of the line cut at the line end can be determined, for example, using a virtual layout as described herein. The determined optimal width can be used to form a mask during the formation of the semiconductor device. The mask can prevent the patterned dielectric layer from being located in areas beneath it, thereby preventing the formation of line ends in the dielectric layer during subsequent processing. As described herein, this can improve the RC performance of the semiconductor device and / or reduce the required size or footprint of the device.

[0135] A method is provided according to some embodiments. The method includes forming a first mask layer over a target layer. The method further includes forming a plurality of spacers over the first mask layer. The method further includes forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, wherein, in a plan view, the main axis of the opening extends in a direction perpendicular to the main axis of the spacers among the plurality of spacers. The method further includes depositing a sacrificial material in the opening. The method further includes patterning the sacrificial material. The method further includes etching the first mask layer using the plurality of spacers and the patterned sacrificial material. The method further includes etching the target layer using the etched first mask layer to form a second opening in the target layer. The method further includes filling the second opening in the target layer with a conductive material. In embodiments, the patterned sacrificial material includes a sacrificial material patterned using extreme ultraviolet lithography. In embodiments, the gap between adjacent spacers among the plurality of spacers has a pitch of 85.5 nm or less. In embodiments, the sacrificial material includes an inorganic material having high etch selectivity relative to the material used to form the first mask layer. In embodiments, the sacrificial material is a metal oxide or a metal nitride. In an embodiment, the method further includes planarizing a sacrificial material, wherein after planarization, the top surface of the sacrificial material is flush with the top surfaces of a plurality of spacers. In an embodiment, after patterning the sacrificial material, the sacrificial material covers one or more gaps between adjacent spacers. In an embodiment, forming a plurality of spacers over a target layer includes: forming three layers on a spacer layer; using photolithography to pattern the top layer of the three layers; etching the middle layer of the three layers through the patterned top layer; etching the bottom layer of the three layers through the middle layer; and etching the spacer layer through the bottom layer to form a plurality of spacers. In an embodiment, the method further includes planarizing a conductive material to form a plurality of interconnects, wherein two adjacent interconnects among the plurality of interconnects have a physical gap separating the two adjacent interconnects, the gap being disposed in a region located below a portion of the sacrificial material, wherein this portion is left after patterning the sacrificial material.

[0136] A method is provided according to some embodiments. The method includes forming a first overlay layer over a second overlay layer, the second overlay layer being located over a first mask layer, and the first mask layer being located over a dielectric layer. The method further includes patterning openings in the first overlay layer, the openings having a target width. The method further includes filling the openings with a first material to form a masking element. The method further includes forming a second mask layer over the first overlay layer and patterning the second mask layer to form a first mask, the first mask including a plurality of openings. The method further includes etching the first and second overlay layers using the first mask and the masking element, wherein the masking element prevents portions of the second overlay layer from being etched. The method further includes patterning the first mask layer through the second overlay layer to form a second mask. The method further includes patterning a dielectric layer through the second mask, the patterning of the dielectric layer exposing conductive components located beneath the dielectric layer. The method further includes forming wires in the dielectric layer, wherein the wires contact the conductive components. In this embodiment, the target width of the opening is equal to: 2X + S + 2 × (Z^2 + V^2)^0.5; where 2X is the target width of the opening in the virtual layout, S is half of the bias range 2S, Z is half of the cut width variation 2Z, and V is the distance the line cut can move between the actual and planned positions. In this embodiment, the target width of the opening is determined by virtually designing the semiconductor device to be formed using a processing system. In this embodiment, the masking element is formed of an inorganic material, wherein the inorganic material has high etch selectivity relative to the material of the second mask layer. In this embodiment, the thickness of the first capping layer is greater than or equal to half the target width of the opening. In an embodiment, an etch stop layer is disposed between a first capping layer and a second capping layer, and the combined thickness of the first capping layer and the etch stop layer satisfies the following relationship: T1 + T2 = T3 × (1 + target OE% / SEL); where T1 is the thickness of the first capping layer, T2 is the thickness of the etch stop layer, T3 is the thickness of the second mask layer, target OE% is the target over-etch percentage for the processing technique, and SEL is the etch selectivity of the second mask layer relative to the etch stop layer. In an embodiment, masking elements are consumed during patterning of the second mask layer.

[0137] A device is provided according to some embodiments. The device includes a dielectric layer. The device also includes a power rail extending through the dielectric layer, wherein the sidewalls of the power rail include one or more kinks. The device further includes a first set of interconnects in the dielectric layer on a first side of the power rail. The device also includes a second set of interconnects in the dielectric layer on the first side of the power rail, wherein a first kink of the one or more kinks is laterally positioned between the first and second sets of interconnects. In an embodiment, the spacing between the first and second sets of interconnects is 85.5 nm or less. In an embodiment, the device also includes a third set of interconnects in the dielectric layer on a second side of the power rail, opposite the first side, wherein the interconnects in the first set of interconnects are the same size as the interconnects in the second set of interconnects, and wherein the sidewalls of the first set of interconnects are aligned with the sidewalls of the second set of interconnects. In an embodiment, all contacts to the power rail are formed at a minimum distance from the edge of the power rail.

[0138] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a semiconductor device, comprising: forming a first mask layer over a target layer; forming a plurality of spacers over the first mask layer; forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, wherein, in plan view, a major axis of the first opening extends in a direction perpendicular to a major axis of a spacer of the plurality of spacers; depositing a sacrificial material in the first opening; patterning the sacrificial material; etching the first mask layer using the plurality of spacers and the patterned sacrificial material; etching the target layer using the etched first mask layer to form a second opening in the target layer; and filling the second opening in the target layer with a conductive material.

2. The method of claim 1, wherein, Patterning the sacrificial material includes patterning the sacrificial material using an extreme ultraviolet lithography process or an immersion exposure process.

3. The method of claim 1, wherein, Gaps between adjacent spacers of the plurality of spacers have a pitch of 85.5 nm or less.

4. A method of forming a semiconductor device, comprising: forming a first patterned mask layer over a target layer; forming a second patterned mask layer over the first patterned mask layer, the second patterned mask layer overlapping a first component and a second component of the first patterned mask layer; patterning the patterned mask layers to form a third patterned mask layer, the third patterned mask layer overlapping the first component and the second component of the first patterned mask layer; etching the target layer using the first patterned mask layer and the third patterned mask layer as masks to form an opening in the target layer; and filling the opening in the target layer with a conductive material.

5. The method of claim 4, wherein, The second patterned mask layer has a longitudinal axis that is perpendicular to longitudinal axes of the first component and the third component.

6. The method of claim 4, wherein, Patterning the second patterned mask layer to form the third patterned mask divides the first mask component into a second mask component and a third mask component.

7. A method of forming a semiconductor device, comprising: forming a first mask layer over a target layer; patterning the first mask layer to form a plurality of line patterns; forming a second mask layer over the plurality of line patterns; patterning the second mask layer to form a first opening, wherein the first opening exposes a first line pattern, a second line pattern, and a third line pattern of the plurality of line patterns; depositing a sacrificial material in the first opening, wherein the sacrificial material is embedded between the first line pattern and the second line pattern and between the second line pattern and the third line pattern; patterning the sacrificial material, wherein, after patterning the sacrificial material, a first portion of the sacrificial material remains between the first line pattern and the second line pattern, wherein patterning the sacrificial material removes the sacrificial material between the second line pattern and the third line pattern; etching the target layer using the first line pattern, the second line pattern, the third line pattern, and the first portion of the material as masks to form a second opening in the layer; and filling the second opening in the target layer with a conductive material.

8. The method of claim 7, wherein, After deposition of the sacrificial material and before top patterning of the sacrificial material, the sacrificial material extends only partially over the width of the first line pattern.

9. The method of claim 8, wherein, After deposition of the sacrificial material and before top patterning of the sacrificial material, the sacrificial material extends completely over the width of the second line pattern.

10. The method of claim 9, wherein, After patterning of the sacrificial material, sidewalls of the second and third line patterns are exposed.

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