Wafer level module integration method

Abstract

The invention discloses a wafer-level module integration method, which comprises the steps of providing a first wafer, forming a plurality of first bare core particles in the first wafer, and dividing the surface of each first bare core particle into a bonding area and an interconnection area; providing a second bare core particle, wherein the surface of the second bare core particle is divided into a bonding area and an interconnection area; forming a bonding body in the bonding area of the first bare chip particle and / or the bonding area of the second bare chip particle; the second bare chip particles are bonded to the first wafer through bonding bodies, the bonding areas of the first bare chip particles and the bonding areas of the second bare chip particles vertically correspond to each other, and the bonding bodies are connected between the first bare chip particles and the second bare chip particles; the electrodes of the second metal electrode array and the first metal electrode array are in one-to-one correspondence; and simultaneously growing metal on the surface of each metal electrode of the first metal electrode array and the second metal electrode array until the first metal electrode and the second metal electrode which are opposite to each other are interconnected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip manufacturing, and more particularly to a wafer-level module integration method. Background Technology

[0002] With the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink, and the requirements for integrated circuit packaging technology are also constantly increasing. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), 3D packaging, and system in package (SiP).

[0003] Currently, to meet the goals of lower cost, higher reliability, faster speed, and higher density in integrated circuit packaging, advanced packaging methods mainly employ wafer-level package system-in-package (WLPSIP) in a three-dimensional stacked configuration. Compared to traditional system packaging, WLPSIP completes the packaging integration process on the wafer, offering advantages such as significantly reduced package area, lower manufacturing costs, optimized electrical performance, and batch manufacturing, while also noticeably reducing workload and equipment requirements. Existing system-in-package systems suffer from the following problems: 1. Complex processes leading to low packaging efficiency; 2. Poor conductivity of the package structure resulting in low yield; 3. Large package size, complex processes, and high costs.

[0004] Therefore, with the increasing demands of AI for computing power, there is a growing expectation for a new system-level module integration method that can solve technical problems such as high process difficulty, large package size, low integration, and poor packaging effect. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide a wafer-level module integration method comprising the following steps: A first wafer is provided, and a plurality of first bare dies are formed inside the first wafer. The surface of the first bare dies is divided into a bonding region and an interconnect region, and the interconnect region has at least two columns and two rows of first metal electrode arrays. A second bare die is provided, the surface of which is divided into a bonding region and an interconnection region, and the interconnection region has a second metal electrode array of at least 2 columns and 2 rows; The second bare core is bonded to the first wafer, and the bonding regions of the first and second bare cores are perpendicularly aligned; the electrodes of the second metal electrode array and the first metal electrode array are in one-to-one correspondence. Metals are simultaneously grown on the surface of each metal electrode in the first and second metal electrode arrays until the opposing first and second metal electrodes are interconnected.

[0006] This invention solves the problem that chips with different process technologies cannot be produced on the same production line by three-dimensional chip stacking, as well as the problem of increased size caused by packaging chips with different process technologies. This results in larger computing chips with higher integration, lower power consumption, and faster speed. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a flowchart of a wafer-level module integration method according to an embodiment of the present invention; Figures 2-8 This is a cross-sectional schematic diagram of a wafer-level module integration method according to an embodiment of the present invention; Figure 9 This is a cross-sectional schematic diagram of the manufacturing method of a wafer-level module integration method according to another embodiment of the present invention; Figure 10 This is a cross-sectional schematic diagram of the manufacturing method of a wafer-level module integration method according to another embodiment of the present invention. Detailed Implementation

[0009] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0010] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connection and interconnection both refer to conductive interconnection. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.

[0011] This invention provides a wafer-level module integration method, comprising the steps of: providing a first wafer, wherein a plurality of first bare dies are formed inside the first wafer, the surface of the first bare dies is divided into a bonding region and an interconnect region, and the interconnect region has at least two columns and two rows of first metal electrode arrays; A second bare die is provided, the surface of which is divided into a bonding region and an interconnection region, and the interconnection region has a second metal electrode array of at least 2 columns and 2 rows; The second bare core is bonded to the first wafer, and the bonding regions of the first and second bare cores are perpendicularly aligned; the electrodes of the second metal electrode array and the first metal electrode array are in one-to-one correspondence. Metals are simultaneously grown on the surface of each metal electrode in the first and second metal electrode arrays until the opposing first and second metal electrodes are interconnected.

[0012] The embodiments will now be described in detail with reference to the accompanying drawings. Please refer to them. Figures 1 to 3 An embodiment of the present invention provides a wafer-level module integration method, comprising the following steps: S10: Provide a first wafer 100, in which a plurality of first bare dies 110 are formed, the surface of the first bare die 110 is divided into a bonding region 111 and an interconnect region 112, and the interconnect region has at least two columns and two rows of first metal electrode array 113. In one embodiment, the method for forming the first metal electrode array includes the steps of: S11: Provide a first wafer 100, wherein a plurality of first bare dies 110 are formed inside the first wafer 100, and the first bare dies 110 include through silicon vias 114 communicating with the surface; Specifically, in this embodiment, such as Figure 1 As shown, wafer 100 includes a semiconductor substrate, which is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. In this embodiment, a silicon substrate is used, and an epitaxial layer is formed on the silicon substrate. A plurality of first bare dies 110, arranged in an array to form semiconductor devices, are formed in the epitaxial layer and the silicon substrate. Due to limitations in the drawings, [the remaining text is incomplete and requires further context]. Figure 2 The image only shows two first dies of the first wafer; in reality, the dies are arrayed on the wafer. Semiconductor devices, such as MOSFETs, MEMS, or other functional devices, are fabricated within the dies. Therefore, to enable signal input and output, signals are transmitted to the surface through through-silicon vias (TSVs) at the device ports. During manufacturing or packaging, pads or other electrode structures can be formed on the TSVs to interconnect the signals.

[0013] S12: Form a metal layer 310 on the wafer surface; In this embodiment, as Figure 2 As shown, the wafer with the manufactured device has through-silicon vias (TSVs) for the device and interconnects, but no electrodes. Therefore, in this step, the TSVs 114 are embedded in the insulating layer during the semiconductor manufacturing process. Thus, this step directly forms a metal layer 310 on the wafer 100. For example, the metal layer can be deposited by chemical vapor deposition or physical vapor deposition. In this embodiment, a layer of aluminum is deposited with a thickness of 0.5 micrometers to 15 micrometers.

[0014] S13: A photoresist layer 311 is coated on the surface of the metal layer 310, and a uniformly distributed photoresist pattern 312 is obtained by photolithography exposure through a mask. Specifically, such as Figure 3 and Figure 4 As shown, a positive chemical amplification photoresist layer is uniformly coated on an aluminum layer, and a patterned photoresist pattern is formed by photolithography with a mask, ultraviolet exposure, post-baking, and development. For example, in this embodiment, the photoresist pattern is a circular array or a polygonal array corresponding to the metal electrodes.

[0015] S14: High-temperature curing of the photoresist pattern 312 array to make its upper surface curved 313; Specifically, such as Figure 5 As shown, the photoresist pattern 312 is thermally baked, for example, by re-exposure to ultraviolet light without a mask, followed by another post-baking, to form a modified photoresist pattern with altered viscosity and / or surface tension; thus, a photoresist pattern 313 with a curved upper surface is formed after a thermal reflow process. In this embodiment, the exposure metering is 200–2000 mJ / cm²; the heating temperature used in the thermal reflow process is 145°C–175°C, and the time is not less than 5 minutes.

[0016] S15: Using the curved photoresist pattern 313 as a mask, dry etching is performed to form discrete curved metal electrodes 113.

[0017] Specifically, such as Figure 6 As shown, plasma etching can be used to etch perpendicular to the surface of the bare chip, thereby transferring the curved photoresist pattern into the aluminum layer to form individual curved aluminum electrodes. The etching stops at the surface of the bare chip, penetrating the aluminum layer.

[0018] In one embodiment, the metal electrodes in the first and second metal electrode arrays include electrodes located on top of vias within the bare die and support electrodes located on the dielectric layer. That is, not only are electrodes formed on top of the vias for external conductive interconnection, but the metal electrodes are also uniformly distributed in an array, thus including some electrodes that are not interconnected. These electrodes can serve to support the electrode and reduce stress to maintain balance.

[0019] In one embodiment, the electrodes in the first metal electrode array and the second metal electrode array are hemispherical, specifically hemispherical with curved surfaces.

[0020] In one embodiment, the spacing between the metal electrodes in the first and second metal electrode arrays is 0.5 micrometers to 300 micrometers; the width of the metal electrodes is 0.5 micrometers to 100 micrometers; and the height of the metal electrodes is 0.5 micrometers to 15 micrometers. This size ensures interconnection while preventing short circuits or open circuits during subsequent connection processes.

[0021] In one embodiment, the bonding region is located in the central region of the bare core, and the interconnect region is located around the bonding region. For module integration, the metal electrodes are concentrated in one region of the bare core, while another region allows bonding without affecting or obscuring the metal electrodes. Therefore, the surface is divided into a bonding region and an interconnect region. In this embodiment, the central region of the bare core is the bonding region 111, while the peripheral region is used to house the metal electrodes, i.e., the interconnect region 112.

[0022] S20: As Figure 7 As shown, a second bare die 210 is provided. The surface of the second bare die 210 is divided into a bonding region 211 and an interconnect region 212. The interconnect region 212 has at least two columns and two rows of second metal electrode arrays 213. The position and formation method of the second metal electrode array can be the same as the formation method of the first metal electrode array, and will not be described again. The difference is that the second bare die 210 is a die with a different function than the first bare die 110, and its size is usually different as well. For example, in another embodiment, the area of ​​the first bare die 110 is much larger than that of the second bare die. Therefore, multiple first bare die 110s can be bonded to one first bare die 110, or a third bare die can be bonded on top of it. The metal electrode array of the third bare die can be the same as that of the second bare die.

[0023] In another embodiment, the first metal electrode is hemispherical; the second metal electrode is planar.

[0024] S30: A bonded body 310 is formed in the bonding region of the first bare core 110 and / or the bonding region of the second bare core 210; Specifically, such as Figure 8As shown, in this embodiment, a bonding body is formed in the bonding region of the first bare die 110 and the second bare chip 210. The bonding body is silicon dioxide, and bonding is achieved through a silicon dioxide melt bonding process. Melt bonding is a process that mainly utilizes interfacial chemical forces to complete bonding. During the melt bonding process, the surface activity of the first oxide layer and the second oxide layer is improved, thereby forming covalent bonds between the contact surfaces of the first oxide layer and the second oxide layer and achieving bonding in a covalent manner. Furthermore, the first oxide layer and the second oxide layer have high bonding strength, thereby improving the packaging yield of the wafer-level system packaging. In other embodiments, bonding can also be achieved through other methods, such as epoxy resin or solder adhesive bonding, glass dielectric bonding, metal bonding, or metal compound bonding, etc.

[0025] In another embodiment, instead of forming a bonded body, electromagnetic bonding can be used to temporarily bond the second bare core to the first wafer, with the highest point of the hemispherical first metal electrode of the first wafer in contact with or having a gap with the planar second metal electrode of the second bare core.

[0026] S40: The second bare core is bonded to the first wafer using a bonding agent, and the bonding regions of the first and second bare cores are perpendicular to each other and connected by a bonding agent in the middle; the electrodes of the second metal electrode array and the first metal electrode array correspond one-to-one. Specifically, such as Figure 8 As shown in the figure, in this embodiment, the process of forming metal electrodes corresponds the first metal electrode and the second metal electrode one by one. Therefore, after bonding, the first metal electrode and the second metal electrode are opposite each other, and they may or may not be in contact, depending on the specific operation of the specific semiconductor process.

[0027] S50: Simultaneously grow metal on the surface of each metal electrode in the first metal electrode array and the second metal electrode array until the opposing first metal electrode and the second metal electrode are interconnected.

[0028] Specifically, such as Figure 8 As shown, a metal can be grown through an electroplating process. The characteristic of electroplating is that the metal adheres to the metal electrode, growing layer by layer until complete contact and tight bonding occur. For example, it can be placed in a solution containing metal ions (e.g., electroless silver plating, nickel plating, copper plating solutions), and based on the principle of redox reaction, a strong reducing agent is used to reduce the metal ions to metal, which is then deposited on the surfaces of the first metal electrode 110 and the second metal electrode 210, forming a metal coating. The grown metal material includes one or more of aluminum, titanium, tungsten, copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.

[0029] In embodiments utilizing electromagnetic bonding, a gap exists between the first wafer and the second bare die due to the contact between the spherical and planar surfaces. This allows liquid electroplating material to flow between the first and second metal electrodes, thereby growing metal on the surfaces of the first and second metal electrodes and making them electrically interconnected. In this way, even if the electrodes are loosely connected at some locations, it does not affect the electroplating process. After the electroplating process, the electrodes are completely interconnected.

[0030] In one embodiment, the grown metal includes electroplating or chemical plating, and the metal material is one or an alloy of aluminum, titanium, tungsten, copper, nickel, tin, cobalt, tantalum, silver, and gold.

[0031] In another embodiment, reference Figure 9 It also includes providing a third bare die 300, the surface 310 of which is divided into a bonding region and an interconnect region, and a third metal electrode array 315 with at least 2 columns and 2 rows in the interconnect region; A bond is formed in the bonding region of the first bare core and / or the bonding region of the third bare core; The third bare core is bonded to the first wafer using a bonding agent, and the bonding regions of the first and third bare cores are perpendicular to each other and connected by a bonding agent in the middle; the electrodes of the third metal electrode array and the first metal electrode array are one-to-one opposite each other. Metal is simultaneously grown on the surface of each metal electrode in the first and third metal electrode arrays until the opposing first and third metal electrodes are interconnected.

[0032] In one embodiment, at least one second bare core particle and at least one third bare core particle are bonded to the surface of the same first bare core particle.

[0033] In one embodiment, the metal electrodes of the second bare core and the third bare core are selectively interconnected during the metal growth step.

[0034] In another embodiment, reference Figure 10 It also includes providing a third bare die 300, the surface 310 of which is divided into a bonding region and an interconnect region, and a third metal electrode array 315 with at least 2 columns and 2 rows in the interconnect region; A bond is formed in the bonding region of the first bare core and / or the bonding region of the third bare core; The third bare core is bonded to the first wafer using a bonding agent, and the bonding regions of the first and third bare cores are perpendicular to each other and connected by a bonding agent in the middle; the electrodes of the third metal electrode array and the first metal electrode array are one-to-one opposite each other. Metal is simultaneously grown on the surface of each metal electrode in the first and third metal electrode arrays until the opposing first and third metal electrodes are interconnected.

[0035] In one embodiment, at least one of the first bare dies is bonded with a second bare die or a third bare die. For example, a second bare die and a third bare die can also be bonded alternately to two first bare dies with different functions and sizes.

[0036] In one embodiment, the metal electrodes of the second bare core and the third bare core are selectively interconnected during the metal growth step.

[0037] In another embodiment, the wafer-level module integration method includes the steps of: A first wafer is provided, wherein a plurality of first bare dies are formed inside the first wafer, and the surface of the first wafer is divided into a bonding region and an interconnect region, wherein the interconnect region has at least two columns and two rows of first metal electrode arrays; A second wafer is provided, wherein a plurality of second bare dies are formed inside the second wafer, and the surface of the second wafer is divided into a bonding region and an interconnect region, wherein the interconnect region has at least two columns and two rows of second metal electrode arrays; The second wafer is bonded to the first wafer, and the bonding regions of the first and second wafers are perpendicularly aligned; the electrodes of the second metal electrode array and the first metal electrode array are in one-to-one correspondence. Metals are simultaneously grown on the surface of each metal electrode in the first and second metal electrode arrays until the opposing first and second metal electrodes are interconnected.

[0038] In another embodiment, the wafer-level module integration method further includes the step of: A first wafer is provided, in which a plurality of first bare dies are formed, and the surface of the first bare dies has a first electrode, the first electrode being a hemispherical shape with a curved surface; A plurality of second bare core particles are provided, the surface of which has a second electrode; The first electrode is positioned opposite to the first electrode, such that the second bare die is bonded to the first wafer, and the first electrode and the second electrode are in contact. A fluid material containing metal ions is introduced into the gap between the first electrode and the second electrode, causing metal to be deposited on the surfaces of the first electrode and the second electrode to form an interconnect.

[0039] The step of forming the first electrode includes: A metal layer is formed on the surface of the first wafer; A photoresist layer is coated on the surface of the metal layer, and a uniformly distributed photoresist pattern is obtained by photolithography exposure using a mask. The photoresist pattern array is cured at high temperature to make its upper surface curved. Using a curved photoresist pattern as a mask, dry etching is performed to form discrete curved metal electrodes.

[0040] In another embodiment, the wafer-level module integration method further includes the step of: A first wafer is provided, in which a plurality of first bare dies are formed, and the surface of the first bare dies has a first electrode, the first electrode being a hemispherical shape with a curved surface; A second wafer is provided, in which a plurality of second bare dies are formed, and the surface of the second bare dies has a second electrode; The first electrode is positioned opposite to the first electrode, such that the second wafer is bonded to the first wafer, and the first electrode and the second electrode are in contact. A fluid material containing metal ions is introduced into the gap between the first electrode and the second electrode, causing metal to be deposited on the surfaces of the first electrode and the second electrode to form an interconnect.

[0041] The second electrode is a hemispherical shape with a curved surface.

[0042] The steps for forming the first electrode and / or the second electrode include: Form a metal layer; A photoresist layer is coated on the surface of the metal layer, and a uniformly distributed photoresist pattern is obtained by photolithography exposure using a mask. The photoresist pattern array is cured at high temperature to make its upper surface curved. Using a curved photoresist pattern as a mask, dry etching is performed to form discrete curved metal electrodes.

[0043] In this embodiment, the first and / or second electrodes are formed into curved hemispherical shapes. Combined with subsequent metal growth processes, even if the first and second electrodes are not precisely aligned, a good interconnect can still be formed through subsequent steps. Furthermore, since the electrodes are no longer planar, there is no need to reserve cavities after bonding. Even with curved surfaces in contact, gaps will still exist, allowing liquid or gaseous materials containing metal ions to flow and make good contact with the electrode surface, thereby growing metal on the electrode surface to form an interconnect. This further reduces the thickness and simplifies the manufacturing process by eliminating the need for bonding materials to form cavities.

[0044] This invention removes the metal pads formed during semiconductor manufacturing and forms corresponding metal electrodes according to the interconnection requirements of the functional modules of the first and second bare chips. Then, it employs a bonding-before-further metal growth interconnection method, reducing the difficulty of direct chip bonding or surface-activated bonding. Direct chip bonding or surface-activated bonding involves contacting the flat, clean surfaces of two electrodes at room temperature, relying on short-range forces (such as van der Waals forces) to achieve permanent bonding, and subsequently using heat treatment to enhance the bonding strength. This method has extremely high requirements for flatness and alignment. In particular, it creates conditions for the interconnection of multi-array electrodes, ensuring that the multi-array electrodes still have channels for introducing fluid material to each electrode after bonding.

[0045] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wafer level module integration method, comprising: The method comprises the steps of: providing a first wafer, which is internally formed with a plurality of first die particles, the surface of the first die particle is divided into a bonding area and an interconnection area, and the interconnection area is provided with at least two columns and two rows of first metal electrode arrays; providing a second die particle, which is divided into a bonding area and an interconnection area on the surface, and the interconnection area is provided with at least two columns and two rows of second metal electrode arrays; bonding the second die particle to the first wafer, and the bonding areas of the first die particle and the second die particle are vertically corresponding; the second metal electrode arrays and the first metal electrode arrays are one-to-one corresponding; growing metal on the surface of each metal electrode of the first metal electrode arrays and the second metal electrode arrays until the opposite first metal electrodes and second metal electrodes are interconnected.

2. The wafer level module integration method of claim 1, wherein, The metal electrodes in the first metal electrode arrays and the second metal electrode arrays include electrodes on the top of the through silicon vias in the die particles and support electrodes on the dielectric layer.

3. The wafer level module integration method of claim 1, wherein, The electrodes in the first metal electrode arrays and the second metal electrode arrays are hemispherical.

4. The wafer level module integration method of claim 1, wherein, The forming method of the first metal electrode arrays and / or the second metal electrode arrays comprises the steps of: providing a wafer, which is internally formed with a plurality of die particles, and the die particle includes a through silicon via in communication with the surface; forming a metal layer on the surface of the wafer; coating a photoresist layer on the surface of the metal layer, and performing photoetching exposure through a mask to obtain a uniform array of photoresist patterns; high-temperature curing the photoresist pattern array to make the upper surface thereof curved; performing dry etching using the curved photoresist pattern as a mask to form discrete curved metal electrodes, and the metal electrodes are interconnected with the through silicon vias.

5. The wafer level module integration method of claim 1, wherein, The spacing of the metal electrodes in the first metal electrode arrays and the second metal electrode arrays is 0.5-300 microns; the width of the metal electrodes is 0.5-100 microns; and the height of the metal electrodes is 0.5-15 microns.

6. The wafer level module integration method of claim 1, wherein, The method further comprises the steps of: providing a third die particle, which is divided into a bonding area and an interconnection area on the surface, and the interconnection area is provided with at least two columns and two rows of third metal electrode arrays; forming a bonding body in the bonding area of the first die particle and / or the bonding area of the third die particle; bonding the third die particle to the first wafer by using the bonding body, and the bonding areas of the first die particle and the third die particle are vertically opposite, and the bonding body is connected therebetween; the third metal electrode arrays and the first metal electrode arrays are one-to-one corresponding; 7. The wafer level module integration method of claim 6, wherein, growing metal on the surface of each metal electrode of the first metal electrode arrays and the third metal electrode arrays until the opposite first metal electrodes and third metal electrodes are interconnected.

8. The wafer level module integration method of claim 6, wherein, At least one of the second die particles and at least one of the third die particles are bonded on the surface of the same first die particle.

9. The wafer level module integration method of claim 8, wherein, At least one of the first die particles is bonded with one second die particle or one third die particle.

10. The wafer level module integration method of claim 1, wherein, The growing metal includes electroplating or chemical plating, and the metal material is one of metal aluminum, titanium, tungsten, copper, nickel, tin, cobalt, tantalum, silver, gold or an alloy. A bonding body is formed in the bonding area of the first die particle and / or the bonding area of the second die particle; the bonding area is located in the central region of the die particle, and the interconnection area is located in the periphery of the bonding area.

11. The wafer level module integration method of claim 1, wherein, The second die particle is bonded to the first wafer, and the bonding areas of the first and second die particles correspond vertically; the first metal electrode is hemispherical; and the second metal electrode is planar.

12. The wafer level module integration method of claim 11, wherein, The method for growing metal on each metal electrode surface of the first and second metal electrode arrays simultaneously comprises introducing a fluid material containing metal ions into the gaps of the first and second metal electrode arrays, the fluid material including gaseous and liquid states.

13. The wafer level module integration method of claim 12, wherein, The bonding method comprises electromagnetic adsorption bonding.

14. A wafer level module integration method, comprising: The method comprises the steps of: providing a first wafer, the first wafer having a plurality of first die particles formed therein, the surface of the first wafer being divided into a bonding area and an interconnection area, the interconnection area having at least two columns and two rows of first metal electrode arrays; providing a second wafer, the second wafer having a plurality of second die particles formed therein, the surface of the second wafer being divided into a bonding area and an interconnection area, the interconnection area having at least two columns and two rows of second metal electrode arrays; bonding the second wafer to the first wafer, and the bonding areas of the first and second wafers corresponding vertically; the second metal electrode arrays and the first metal electrode arrays correspond one-to-one; growing metal on each metal electrode surface of the first and second metal electrode arrays simultaneously until the opposite first and second metal electrodes are interconnected.

15. A wafer level module integration method, comprising: The method further comprises the steps of: providing a first wafer, the first wafer having a plurality of first die particles formed therein, the surface of the first die particles having first electrodes, the first electrodes being hemispherical with curved surfaces; providing a plurality of second die particles, the surface of the second die particles having second electrodes; bonding the first electrodes to the second die particles, the second die particles being arranged opposite the first electrodes, and the first and second electrodes being in contact; introducing a fluid material containing metal ions into the gaps of the first and second electrodes, and depositing metal on the surfaces of the first and second electrodes to form interconnections.

16. The wafer level module integration method of claim 15, wherein, The forming step of the first electrodes comprises: forming a metal layer on the surface of the first wafer; coating a photoresist layer on the surface of the metal layer, and exposing the photoresist layer to light through a mask to obtain a uniform array of photoresist patterns; high-temperature curing the photoresist pattern array to make the upper surface thereof curved; masking with the photoresist pattern array to perform dry etching, thereby forming discrete metal electrodes with curved surfaces.

17. A wafer level module integration method, comprising: The method further comprises the steps of: providing a first wafer, the first wafer having a plurality of first die particles formed therein, the surface of the first die particles having first electrodes, the first electrodes being hemispherical with curved surfaces; providing a second wafer, the second wafer having a plurality of second die particles formed therein, the surface of the second die particles having second electrodes; bonding the first electrodes to the second die particles, the second die particles being arranged opposite the first electrodes, and the first and second electrodes being in contact; introducing a fluid material containing metal ions into the gaps of the first and second electrodes, and depositing metal on the surfaces of the first and second electrodes to form interconnections.

18. The wafer level module integration method of claim 17, wherein, The second electrodes are hemispherical with curved surfaces.

19. The wafer level module integration method of claim 18, wherein, The forming step of the first and / or second electrodes comprises: forming a metal layer; A photoresist layer is coated on the surface of the metal layer, and the photoresist layer is exposed to light through a mask to obtain a uniform array of photoresist patterns; The photoresist pattern array is cured at high temperature to make the upper surface of the photoresist pattern array curved; Dry etching is performed using the curved photoresist pattern as a mask to form discrete curved metal electrodes.

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