Array substrate, preparation method thereof and display panel

Abstract

The invention discloses an array substrate, a preparation method of the array substrate and a display panel, and can solve the problem that the display effect is affected due to the fact that the load of a data line in an existing array substrate is large. The array substrate comprises a substrate (101), a first film layer, a first electrode, a second film layer and a second electrode, wherein the first film layer, the first electrode, the second film layer and the second electrode are located on the substrate (101); the array substrate (101) further comprises: a data line (106); the data line (106) is located on the side, away from the second electrode, of the first film layer; the first film layer comprises a first sub-layer and a second sub-layer, and the dielectric constant of the first sub-layer is smaller than that of the second sub-layer.

Description

Array substrate and manufacturing method thereof, and display panel Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Current LCD panels employ a variety of common electrode configurations. One approach involves placing both the common electrode and the pixel electrode on the array substrate, as exemplified by Advanced-Super Dimensional Switching (ADS) technology. ADS utilizes the electric field generated by the edges of slit electrodes within the same plane, as well as the electric field between the slit electrode layer and the planar electrode layer, to create a multi-dimensional electric field. This allows the rotation of all aligned liquid crystal molecules within the liquid crystal cell, between the slit electrodes and directly above them.

[0003] To further increase the aperture ratio and, in turn, the transmittance of the display panel, high aperture display (HADS) technology has been widely adopted. HADS technology swaps the positions of the common electrode and the pixel electrode based on ADS technology, meaning that the common electrode of a HADS-type liquid crystal display panel is above the pixel electrode. However, in current HADS-type liquid crystal display panels, parasitic capacitance is easily formed between the common electrode and the data line, increasing the load on the data line and reducing the charging rate of the pixel electrode, thus affecting the display quality of the display panel.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides an array substrate and a preparation method thereof, and a display panel.

[0006] In a first aspect, an embodiment of the present disclosure provides an array substrate, wherein the array substrate comprises: a substrate, a first film layer located on the substrate, a first electrode, a second film layer, and a second electrode; the array substrate further comprises: a data line; the data line is located on a side of the first film layer facing away from the second electrode;

[0007] The first film layer includes: a first sublayer and a second sublayer, and the dielectric constant of the first sublayer is smaller than the dielectric constant of the second sublayer.

[0008] Optionally, the dielectric constant of the first sublayer is less than or equal to 4.0 Farad / m, and the second sublayer is located on a side of the first sublayer facing away from the substrate and / or on a side of the first sublayer close to the substrate.

[0009] Optionally, the first film layer includes M layers of the first sub-layers and N layers of the second sub-layers, 1≤M≤5, 1≤N≤5;

[0010] The second sublayer is located between adjacent first sublayers.

[0011] Optionally, the array substrate further comprises: a thin film transistor located on a side of the first film layer facing away from the substrate; the thin film transistor comprises: a semiconductor layer; the semiconductor layer comprises: a first conductor portion, a second conductor portion, and a channel portion located between the first conductor portion and the second conductor portion;

[0012] The first conductor portion is electrically connected to the data line through a lap via hole; the lap via hole penetrates the first film layer and exposes a portion of the data line;

[0013] The second conductor portion is reused as the first electrode.

[0014] Optionally, the first conductor portion is electrically connected to the data line through a bonding electrode, and at least a portion of the bonding electrode falls into the bonding via.

[0015] Optionally, the thin film transistor further comprises: a gate located on a side of the semiconductor layer facing away from the substrate, and a gate insulating layer located between the semiconductor layer and the gate;

[0016] The gate insulating layer covers the channel portion.

[0017] Optionally, the thin film transistor further comprises: a gate located on a side of the semiconductor layer facing away from the substrate, and a gate insulating layer located between the semiconductor layer and the gate;

[0018] The gate insulating layer covers the first conductor portion, the second conductor portion, and the channel portion, and the overlapping via penetrates the gate insulating layer.

[0019] Optionally, at the overlapping via hole, the second sub-layer covers a side wall of the first sub-layer close to the overlapping via hole.

[0020] Optionally, a thickness of at least one of the first film layer and the second film layer is greater than or equal to 6000 angstroms.

[0021] Optionally, the overlapping electrode is provided in the same layer as the gate.

[0022] Optionally, the bonding electrode and the common electrode are arranged in the same layer.

[0023] Optionally, the first conductive portion is reused as the bonding electrode.

[0024] Optionally, the material of the dielectric sublayer includes at least one of an organic silicon material and a silicon fluoride material.

[0025] Optionally, the array substrate further comprises: a light shielding layer; the light shielding layer is located on a side of the semiconductor layer close to the substrate;

[0026] The orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the channel portion on the substrate.

[0027] Optionally, the light shielding layer and the data line are provided in the same layer.

[0028] Optionally, orthographic projections of the first electrode and the second electrode on the substrate at least partially overlap, one of the two has a slit opening structure, and the other has a planar structure.

[0029] In a second aspect, an embodiment of the present disclosure provides a display panel, wherein the display device includes the array substrate provided above.

[0030] In a third aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, wherein the method for preparing the display substrate includes:

[0031] forming a metal conductive layer on a substrate and patterning the layer using a first mask to form a data line;

[0032] A first film layer is formed on the side of the data line away from the substrate; the first film layer includes: a first sublayer and a second sublayer, the dielectric constant of the first sublayer is smaller than the dielectric constant of the second sublayer

[0033] forming a semiconductor layer on a side of the first film layer facing away from the substrate, and patterning the first film layer using a second mask to form a first electrode;

[0034] The semiconductor layer is processed to form a first conductive portion, a second conductive portion and a channel portion; the second conductive portion is reused as the pixel electrode;

[0035] forming a gate insulating layer on a side of the semiconductor layer facing away from the substrate, and patterning the layer using a third mask to expose the first conductive portion and the second conductive portion;

[0036] patterning the first film layer using a fourth mask to form a lap via hole exposing the data line;

[0037] A gate conductive layer is formed on a side of the gate insulating layer away from the substrate, and is patterned using a fifth mask to form a gate and a bonding electrode connecting the first conductive portion and the data line.

[0038] forming a second film layer on a side of the gate facing away from the substrate;

[0039] A transparent conductive layer is formed on the side of the second film layer facing away from the substrate, and is patterned using a sixth mask to form a second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of an exemplary array substrate.

[0041] FIG2 a is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present disclosure.

[0042] FIG2 is a schematic structural diagram of a first array substrate provided in an embodiment of the present disclosure.

[0043] FIG3 is a graph showing experimental results of the thickness of the first sub-layer in the array substrate and the parasitic capacitance and charging rate of the device.

[0044] FIG4 is a schematic structural diagram of a second array substrate provided in an embodiment of the present disclosure.

[0045] FIG5 is a schematic structural diagram of a third array substrate provided in an embodiment of the present disclosure.

[0046] FIG6 is a schematic structural diagram of a fourth array substrate provided in an embodiment of the present disclosure.

[0047] FIG7 is a schematic structural diagram of a fifth array substrate provided in an embodiment of the present disclosure.

[0048] FIG8 is a schematic structural diagram of a sixth array substrate provided in an embodiment of the present disclosure.

[0049] FIG9 is a schematic structural diagram of a seventh array substrate provided in an embodiment of the present disclosure.

[0050] FIG10 is a schematic structural diagram of an eighth array substrate provided in an embodiment of the present disclosure.

[0051] FIG11 is a schematic structural diagram of a ninth array substrate provided in an embodiment of the present disclosure.

[0052] FIG12 is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present disclosure.

[0053] 13a to 13j are schematic structural diagrams corresponding to the steps of the method for preparing an array substrate. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0056] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors. Due to the high mobility of oxide semiconductor thin film transistors, they are currently widely used. In the following description, oxide semiconductor thin film transistors will be used as an example. Each thin film transistor includes a first electrode, a second electrode and a control electrode; wherein the control electrode serves as the gate of the thin film transistor, one of the first electrode and the second electrode serves as the source of the thin film transistor, and the other serves as the drain of the transistor; and the source and drain of the thin film transistor may be symmetrical in structure, so the source and drain may be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate serving as the control electrode, the first electrode is directly described as the source and the second electrode as the drain, so the source and drain of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0057] FIG1 is a schematic structural diagram of an exemplary array substrate. As shown in FIG1 , the array substrate includes: a substrate 101; a first film layer, a first electrode, a second film layer, and a second electrode sequentially disposed on the substrate 101; wherein the first film layer may be a buffer layer 102, the first electrode may be a pixel electrode 103, the second film layer may be a passivation layer 104, and the second electrode may be a common electrode 105. The array substrate also includes: a thin film transistor 20 located on a side of the buffer layer 102 facing away from the substrate 101; the thin film transistor 20 includes: a semiconductor layer 201, a gate insulating layer 202, a gate 203, an interlayer insulating layer 204, a source electrode 205, and a drain electrode 206 sequentially disposed away from the substrate 101; the source electrode 205 and the drain electrode 206 are disposed in the same layer and are respectively connected to opposite ends of the semiconductor layer 201. The array substrate also includes: a data line 106; the data line 106 is disposed in the same layer as the source electrode 205 and the drain electrode 206. The source electrode 205 is connected to the data line 106, and the drain electrode 206 is connected to the pixel electrode 103. When a control signal (e.g., a high-level signal) is input to the gate electrode 203, the source electrode 205 and the drain electrode 206 can be conductive, so that the data signal on the data line 106 can be transmitted to the pixel electrode 103. The common signal on the common signal line (not shown) can be transmitted to the common electrode 105. An electric field can be formed between the pixel electrode 103 and the common electrode 105, driving the liquid crystal molecules to rotate to achieve the display function.

[0058] The current array substrate manufacturing process requires a large number of masks (8 masks), resulting in complex processes and high costs. Furthermore, the common electrode 105 covers the data line 106, which easily creates parasitic capacitance between the two. This increases the load on the data line 106 and reduces the charging rate of the pixel electrode 103, affecting the display quality of the array substrate.

[0059] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display panel. The array substrate, a preparation method thereof, and a display panel provided by the embodiments of the present disclosure will be further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0060] In a first aspect, embodiments of the present disclosure provide an array substrate. FIG2a is a schematic diagram of a planar structure of an array substrate provided by an embodiment of the present disclosure, and FIG2 is a schematic diagram of the structure of the first array substrate provided by an embodiment of the present disclosure (FIG. 2 is a cross-sectional structure taken along the AA' direction of FIG2a; the cross-sectional structure will be primarily used as an example in the following description). As shown in FIG2a and FIG2, the array substrate includes: a substrate 101; a first film layer located on the substrate 101; a first electrode; a second film layer; and a second electrode. The first film layer may be a buffer layer 102, the first electrode may be a pixel electrode 103, the second film layer may be a passivation layer 104, and the second electrode may be a common electrode 105. The array substrate also includes: a data line 106; the data line 106 is located on a side of the buffer layer 102 facing away from the common electrode 105; the buffer layer 102 includes a first sublayer and a second sublayer; the dielectric constant of the first sublayer is smaller than that of the second sublayer. The first sublayer may be a dielectric sublayer 1021, and the second sublayer may be a buffer sublayer 1022.

[0061] It should be noted here that, in the embodiments of the present disclosure and the subsequent description, the first film layer will be described as the buffer layer 102, the first electrode as the pixel electrode 103, the second film layer as the passivation layer 104, the second electrode as the common electrode 105, the first sublayer as the dielectric sublayer 1021, and the second sublayer as the buffer sublayer 1022. It can be understood that the above-mentioned film layers may also be other film layers in array substrates of other different structures, which will not be described in detail here.

[0062] The substrate 101 can be made of a rigid material such as glass to improve the substrate 101's ability to support other film layers thereon. Alternatively, the substrate 101 can be made of a flexible material such as polyimide (PI) to improve the overall bending and stretching resistance of the metal oxide thin film transistor, thereby preventing stress generated during bending, stretching, and twisting from causing the substrate 101 to break and cause a short circuit. In practical applications, the material of the substrate 101 can be appropriately selected based on actual needs to ensure good performance of the metal oxide thin film transistor.

[0063] The buffer layer 102 may have a multi-layer structure, wherein the buffer layer 102 includes: a dielectric sub-layer 1021 and a buffer sub-layer 1022. The dielectric sub-layer 1021 may be made of a material with a relatively low dielectric constant, for example, the dielectric constant of the material may be less than or equal to 4.0 Farads / meter, specifically 3.0 Farads / meter. Specifically, the material of the dielectric sub-layer 1021 includes: at least one of organic silicon material (SOG) and fluorinated silicate glass (FSG). Of course, the material of the dielectric sub-layer 1021 may also be other materials doped with a relatively low dielectric constant, which may be organic materials or inorganic materials, which are not listed here one by one. The buffer sub-layer 1022 may be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), which may prevent gases such as water and oxygen from invading from one side of the substrate 101 into other film layers thereon and causing damage to the array substrate. The dielectric sub-layer 1021 with a relatively low dielectric constant may prevent the flow of electrons between the conductive layers on both sides thereof, thereby shielding the conductive layers on both sides thereof from each other. The dielectric sublayer 1021 may have a thickness of 0.6 micrometers to 5.0 micrometers, and preferably, a thickness of 1.0 micrometers to 2.0 micrometers.

[0064] The pixel electrode 103 may be a planar electrode formed of a transparent conductive material such as indium tin oxide (ITO), so as to avoid the pixel electrode 103 blocking light and improve the overall light transmittance of the array substrate.

[0065] The passivation layer 104 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), and can be formed into a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The passivation layer 104 can prevent a short circuit between the pixel electrode 103 and the common electrode 105.

[0066] The common electrode 105 can be a slit electrode formed of a transparent conductive material such as indium tin oxide (ITO). This prevents the common electrode 105 from blocking light and improves the overall light transmittance of the array substrate. The orthographic projection of the common electrode 105 on the substrate 101 at least partially overlaps with the orthographic projection of the pixel electrode 103 on the substrate 101, allowing an electric field to be formed between the two, driving the liquid crystal to rotate.

[0067] The data line 106 is located on the side of the buffer layer 102 facing away from the substrate 101 and can be made of a metal material, such as one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), or an alloy of the above materials. It can be a single-layer structure or a multi-layer structure. It can be electrically connected to the pixel electrode 103 to provide a data signal to the pixel electrode 103.

[0068] In the array substrate provided by the disclosed embodiment, the common electrode 105 is located above the pixel electrode 103, forming a HADS mode. When combined with a color filter substrate to form a display panel, it is no longer necessary to use a large black matrix to shield the data line 106. This improves the pixel aperture ratio and thus the display effect of the array substrate. Furthermore, the data line 106 is located on the side of the buffer layer 102 facing away from the common electrode 105, which increases the distance between the data line 106 and the common electrode 105 and reduces the parasitic capacitance formed between the data line 106 and the common electrode 105. This reduces the load on the data line 106, increases the charging rate of the pixel electrode 103, and further improves the display effect of the array substrate. In addition, a dielectric sublayer 1021 is provided between the data line 106 and the common electrode 105. The dielectric sublayer 1021 has a small dielectric constant (less than or equal to 4.0 farads / meter), which can prevent the flow of electrons between the data line 106 and the common electrode 105, shielding the two, and reducing the parasitic capacitance formed between the data line 106 and the common electrode 105 (Figure 3 is an experimental result diagram of the thickness of the first sublayer in the array substrate and the parasitic capacitance and charging rate of the device, where the material of the dielectric sublayer is silicone material (SOG) as an example). Therefore, the load of the data line 106 can be reduced, the charging rate of the pixel electrode 103 can be improved, and the display effect of the array substrate can be further improved.

[0069] In some embodiments, Figure 4 is a structural schematic diagram of the second array substrate provided in an embodiment of the present disclosure, and Figure 5 is a structural schematic diagram of the third array substrate provided in an embodiment of the present disclosure. As shown in Figures 2, 4 and 5, the buffer sublayer 1022 is located on the side of the dielectric sublayer 1021 away from the substrate 101 and / or on the side of the dielectric sublayer 1021 close to the substrate 101.

[0070] The dielectric sub-layer 1021 can be made of a material with a relatively small dielectric constant, for example, the dielectric constant of the material can be less than or equal to 4.0 farads / meter, specifically 3.0 farads / meter. Specifically, the material of the dielectric sub-layer 1021 includes at least one of: organic silicon material (SOG) and fluorinated silicate glass (FSG). Of course, the material of the dielectric sub-layer 1021 can also be other materials doped with a relatively small dielectric constant, which can be organic materials or inorganic materials, which are not listed here one by one. The buffer sub-layer 1022 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2), which can prevent gases such as water and oxygen from invading from one side of the substrate 101 into other film layers thereon and causing damage to the array substrate. The dielectric sub-layer 1021 with a relatively small dielectric constant can prevent the flow of electrons between the conductive layers on both sides thereof, thereby shielding the conductive layers on both sides thereof from each other. At the same time, the dielectric sublayer 1021 and the buffer sublayer 1022 can increase the distance between the data line 106 and the common electrode 105, reducing the parasitic capacitance formed between the data line 106 and the common electrode 105. This can reduce the load on the data line 106, increase the charging rate of the pixel electrode 103, and further enhance the display effect of the array substrate. In actual applications, as shown in FIG2 , the number of dielectric sublayer 1021 is one, and the number of buffer sublayers 1022 is two, with the dielectric sublayer 1021 located between the two buffer sublayers 1022. As shown in FIG4 and FIG5 , the number of dielectric sublayer 1021 and the number of buffer sublayer 1022 are both one, and the dielectric sublayer 1021 can be located on the side of the buffer sublayer 1022 facing away from the substrate 101, or on the side of the buffer sublayer 1022 close to the substrate 101.

[0071] In some embodiments, Figure 6 is a structural schematic diagram of the fourth array substrate provided in an embodiment of the present disclosure. As shown in Figure 6, the buffer layer 102 includes M dielectric sub-layers 1021 and N buffer sub-layers 1022, 1≤M≤5, 1≤N≤5. In Figure 6, the number of dielectric sub-layers 1021 is 2, and the number of buffer sub-layers 1022 is 3; the buffer sub-layer 1022 is located between adjacent dielectric sub-layers 1021.

[0072] The dielectric sub-layer 1021 can be made of a material with a relatively small dielectric constant, for example, the dielectric constant of the material can be less than or equal to 4.0 farads / meter, specifically 3.0 farads / meter. Specifically, the material of the dielectric sub-layer 1021 includes at least one of: organic silicon material (SOG) and fluorinated silicate glass (FSG). Of course, the material of the dielectric sub-layer 1021 can also be other materials doped with a relatively small dielectric constant, which can be organic materials or inorganic materials, which are not listed here one by one. The buffer sub-layer 1022 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2), which can prevent gases such as water and oxygen from invading from one side of the substrate 101 into other film layers thereon and causing damage to the array substrate. The dielectric sub-layer 1021 with a relatively small dielectric constant can prevent the flow of electrons between the conductive layers on both sides thereof, thereby shielding the conductive layers on both sides thereof from each other. Adjacent dielectric sublayers 1021 can be separated by a buffer sublayer 1022. The multi-layer dielectric sublayer 1021 and the multi-layer buffer sublayer 102 can further increase the distance between the data line 106 and the common electrode 105, reduce the parasitic capacitance formed between the data line 106 and the common electrode 105, thereby reducing the load of the data line 106, improving the charging rate of the pixel electrode 103, and further improving the display effect of the array substrate.

[0073] It should be noted that in the structure shown in FIG2 , the number of dielectric sub-layers 1021 is one, and the number of buffer sub-layers 1022 is two. The buffer sub-layers 1022 can be located on both sides of the dielectric sub-layer 1021. In the structures shown in FIG4 and FIG5 , the number of dielectric sub-layers 1021 is one, and the number of buffer sub-layers 1022 is one. The buffer sub-layer 1022 can be located on the side of the dielectric sub-layer 1021 close to the substrate 101, or on the side of the dielectric sub-layer 1021 facing away from the substrate 101. In the structure shown in FIG6 , the number of dielectric sub-layers 1021 is two, and the number of buffer sub-layers 1022 is three. The buffer sub-layers can be located not only on the side of the dielectric sub-layer 1021 close to the substrate 101, but also on the side of the dielectric sub-layer 1021 facing away from the substrate 101, and can also be located between adjacent dielectric sub-layers 1021. In practical applications, the number and relative position relationship of the dielectric sub-layer 1021 and the buffer sub-layer 1022 can be set according to actual needs and will not be listed one by one here.

[0074] In some embodiments, as shown in Figures 2 and 4 to 6, the array substrate further includes: a thin film transistor 20 located on the side of the buffer layer 102 away from the substrate 101; the thin film transistor 20 includes: a semiconductor layer 201; the semiconductor layer 201 includes: a first conductor portion 2011, a second conductor portion 2012, and a channel portion 2013 located between the first conductor portion 2011 and the second conductor portion 2012; the first conductor portion 2011 is electrically connected to the data line 106 through a lap via V; the lap via V passes through the buffer layer 102 and exposes a portion of the data line 106; the second conductor portion 2012 is reused as the pixel electrode 103.

[0075] The semiconductor layer 201 can be made of one or more materials selected from the group consisting of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), and rare earth-doped oxide (Ln-OS). The semiconductor layer material can be amorphous, partially crystalline, single crystal, or polycrystalline, and the film layer can be a single-layer or multi-layer structure. This can result in the thin film transistor 20 having a lower leakage current and a higher mobility. Furthermore, the semiconductor layer 201 is a transparent structure, which can further enhance the display effect of the array substrate.

[0076] The two end regions of the semiconductor layer 201 are subjected to a conductorization treatment using a plasma treatment or a doping process, thereby forming a first conductor portion 2011 and a second conductor portion 2012. The first conductor portion 2011 can serve as the source of the thin-film transistor 20, and the second conductor portion 2012 can serve as the drain of the thin-film transistor 20 and the pixel electrode 103. Thus, the first conductor portion 2011, the second conductor portion 2012, and the channel portion 2013 can be formed using a single patterning process, utilizing only a single mask. This reduces the number of masks, process steps, and manufacturing costs. Furthermore, the first conductor portion 2011, the second conductor portion 2012, and the channel portion 2013 are provided in the same layer, which reduces the number of film layers and the thickness of the thin-film transistor 20, thereby facilitating a thinner array substrate.

[0077] The first conductor portion 2011 can be electrically connected to the data line 106 via a bonding via V. The bonding via V can penetrate the buffer layer 102 and expose a portion of the data line 106 to facilitate electrical connection between the first conductor portion 2011 and the data line 106. The second conductive portion 2012 can be reused as the pixel electrode 103. The data signal provided by the data line 106 can be transmitted from the first conductor portion 2011 and the channel portion 2013 to the second conductor portion 2012, i.e., the pixel electrode 103. In actual applications, the first conductor portion 2011 and the data line 106 can be electrically connected via a bonding electrode 2010, with at least a portion of the bonding electrode 2010 falling into the bonding via V.

[0078] In some embodiments, as shown in Figures 2 and 4 to 6, the thin film transistor 20 further includes: a gate 203 located on the side of the semiconductor layer 201 away from the substrate 101, and a gate insulating layer 202 located between the semiconductor layer 201 and the gate 203; the gate insulating layer 202 covers the channel portion 2023.

[0079] The gate 203 can input a gate signal, and the gate signal can control whether the channel portion 2023 in the semiconductor layer 201 is turned on or off. The gate 203 can be an integrally formed structure with the gate line in the array substrate. A gate insulating layer 202 is provided between the gate 203 and the semiconductor layer 201 to prevent a short circuit between the two. In the preparation process, the other portions of the gate insulating layer 202 covered by the gate 203 can be removed so that the gate insulating layer 202 can only cover the channel portion 2023. After the gate insulating layer 202 and the gate 203 are formed, the gate insulating layer 202 can be patterned using the gate 203 as a mask to remove the portion covering the channel portion 2023. In this way, it is not necessary to use a new mask for patterning, thereby saving the number of mask plates and saving preparation costs. Of course, a new mask can also be used for patterning.

[0080] In some embodiments, Figure 7 is a structural schematic diagram of the fifth array substrate provided in an embodiment of the present disclosure. As shown in Figure 7, the thin film transistor 20 also includes: a gate 203 located on the side of the semiconductor layer 201 away from the substrate 101, and a gate insulating layer 202 located between the semiconductor layer 201 and the gate 203; the gate insulating layer 202 covers the first conductor portion 2011, the second conductor portion 2012 and the channel portion 2013, and the overlapping via V passes through the gate insulating layer 202.

[0081] The gate 203 can input a gate signal, which can control whether the channel portion 2023 in the semiconductor layer 201 is conductive or inconductive. A gate insulating layer 202 is disposed between the gate 203 and the semiconductor layer 201 to prevent a short circuit between the two. The gate insulating layer 202 can cover the first conductor portion 2011, the second conductor portion 2012, and the channel portion 2013. During the manufacturing process, after the gate insulating layer 202 and the gate 203 are formed, patterning is no longer necessary. During the subsequent formation of the overlapping vias V, the corresponding regions of the gate insulating layer 202 are simultaneously etched. This reduces the number of patterning steps, the number of masks, the number of process steps, and the manufacturing cost.

[0082] In some embodiments, FIG8 is a schematic structural diagram of a sixth array substrate provided in an embodiment of the present disclosure. As shown in FIG8 , at the overlapping via V, the buffer sublayer 1022 covers the side wall of the dielectric sublayer 1021 close to the overlapping via V.

[0083] Photosensitive material can be added to the dielectric sublayer 1021 at the locations corresponding to the overlapping vias V. Simultaneously with the formation of the dielectric sublayer 1021, the locations corresponding to the overlapping vias V can be exposed to expose the data lines 106 they cover. After the buffer sublayer 1022 and other film layers are subsequently formed, etching of the dielectric sublayer 1021 is no longer necessary when patterning the overlapping vias V, thereby reducing etching time. Furthermore, at the locations of the overlapping vias V formed, the buffer sublayer 1022 can cover the sidewalls of the dielectric sublayer 1021 near the overlapping vias V. This allows the buffer sublayer 1022 to protect the sidewalls of the dielectric sublayer 1021, preventing gases such as water and oxygen from invading from one side of the substrate 101 into the other film layers thereon and causing damage to the array substrate.

[0084] In some embodiments, FIG9 is a schematic structural diagram of a seventh array substrate provided by an embodiment of the present disclosure. As shown in FIG9 , the thickness of at least one of the buffer layer 102 and the passivation layer 104 is greater than or equal to 6000 angstroms.

[0085] During the fabrication of the array substrate, a plasma enhanced chemical vapor deposition (PECVD) process can be used to thicken the buffer layer 102 and the passivation layer 104. For example, at least one of the two layers can be made thicker than or equal to 6000 angstroms. This increases the distance between the data line 106 and the common electrode 105, reducing the parasitic capacitance formed between the data line 106 and the common electrode 105. This reduces the load on the data line 106, increases the charging rate of the pixel electrode 103, and further enhances the display quality of the array substrate. Furthermore, due to the thicker thickness, the dielectric sublayer 1021 is no longer necessary to provide a shielding effect, thus reducing process steps and saving fabrication costs.

[0086] In some embodiments, as shown in FIG. 2 and FIG. 4 to FIG. 9 , the strapping electrode 2010 and the gate 203 are disposed in the same layer.

[0087] The strapping electrode 2010 can be provided in the same layer as the gate 203. During the preparation of the array substrate, the strapping electrode 2010 can be formed using the same material and the same process as the gate 203 to reduce process steps and save preparation costs.

[0088] In some embodiments, FIG10 is a schematic structural diagram of an eighth array substrate provided by an embodiment of the present disclosure. As shown in FIG10 , the bonding electrode 2010 and the common electrode 103 are provided in the same layer.

[0089] The strapping electrode 2010 can be provided in the same layer as the common electrode 103. During the preparation of the array substrate, the strapping electrode 2010 can be formed using the same material and process as the common electrode 103 to reduce process steps and save preparation costs.

[0090] In some embodiments, FIG11 is a schematic structural diagram of a ninth array substrate provided by an embodiment of the present disclosure. As shown in FIG11 , the first conductive portion 2011 is reused as a bonding electrode 2010 .

[0091] During the preparation of the array substrate, the first conductive portion 2011 can be directly extended to the overlapping via V, and the first conductive portion 2011 can be directly electrically connected to the data line 106. This eliminates the need for other film layers for overlapping, reduces overlapping resistance, and ensures the performance of the array substrate.

[0092] In some embodiments, as shown in Figures 2, 4 to 11, the array substrate further includes: a light-shielding layer 107; the light-shielding layer 107 is located on a side of the semiconductor layer 201 close to the substrate 101; the orthographic projection of the light-shielding layer 107 on the substrate 101 covers the orthographic projection of the channel portion 2013 on the substrate 101.

[0093] The light shielding layer 107 can be made of a metal material and can shield the channel portion 2013, preventing light from reaching the channel portion 2013, thereby ensuring the stability of the thin film transistor 20. Specifically, the light shielding layer 107 can be provided on the same layer as the data line 106. During the array substrate manufacturing process, the light shielding layer 107 can be formed using the same material and the same process as the data line 106, thereby reducing process steps and saving manufacturing costs.

[0094] In the second aspect, an embodiment of the present disclosure provides a display panel, which includes an array substrate provided in any of the above embodiments. The implementation principle and beneficial effects of the array substrate are similar to the implementation principle and beneficial effects of the above array substrate, and will not be repeated here.

[0095] In a third aspect, embodiments of the present disclosure provide a display device comprising an array substrate and a display panel as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, a mobile phone, a monitor, a laptop computer, a digital photo frame, or a navigation system. The implementation principles and beneficial effects of the display device are similar to those of the aforementioned array substrate and display panel, and are not further elaborated here.

[0096] Fourthly, embodiments of the present disclosure provide a method for manufacturing an array substrate. FIG12 is a schematic flow chart of the method for manufacturing an array substrate according to embodiments of the present disclosure. As shown in FIG12 , the method for manufacturing an array substrate includes steps S1201 to S1209. FIG13a to FIG13j are schematic structural diagrams corresponding to the steps of the method for manufacturing an array substrate. The following detailed description of the array substrate manufacturing process will be provided, taking the array substrate shown in FIG2 as an example, in conjunction with the accompanying drawings.

[0097] S1201, forming a metal conductive layer on a substrate, and patterning it using a first mask to form data lines.

[0098] As shown in FIG13a , a metal layer is deposited on substrate 101. The metal layer can be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), or an alloy thereof. The metal layer can be a single-layer or multi-layer structure. The metal layer is then patterned using a first mask to form data lines 106. Simultaneously, a light shielding layer 107 can be formed.

[0099] S1202 , forming a buffer layer on the side of the data line facing away from the substrate; the buffer layer includes: a dielectric sublayer and a buffer sublayer; the dielectric constant of the dielectric sublayer is smaller than the dielectric constant of the buffer sublayer 1022 .

[0100] As shown in FIG13b , a first buffer sublayer 1022 is deposited on the metal layer. The buffer sublayer 1022 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials.

[0101] As shown in FIG13c , a dielectric sub-layer 1021 is deposited on the first buffer sub-layer 1022. The dielectric sub-layer 1021 can be made of a material with a relatively low dielectric constant. For example, the dielectric constant of the material can be less than or equal to 4.0 farads / meter, specifically 3.0 farads / meter. Specifically, the material of the dielectric sub-layer 1021 includes at least one of an organic silicon material (SOG) and a fluorinated silicate glass (FSG). Of course, the material of the dielectric sub-layer 1021 can also be other materials with relatively low dielectric constants, which are not listed here one by one.

[0102] As shown in FIG13 d , a second buffer sub-layer 1022 is deposited on the dielectric sub-layer 1021 . The process and structure of the second buffer sub-layer 1022 are the same as those of the first buffer sub-layer 1022 , and are not described again here.

[0103] S1203 , forming a semiconductor layer on the side of the buffer layer facing away from the substrate, and patterning the layer using a second mask to form a pixel electrode.

[0104] S1204 , processing the semiconductor layer to form a first conductive portion, a second conductive portion, and a channel portion; the second conductive portion is reused as a pixel electrode.

[0105] As shown in Figure 13e, a semiconductor layer 201 is deposited on the second buffer sublayer 1022. The semiconductor layer is patterned using a second mask to remove unwanted portions. The two end regions of the semiconductor layer 201 are then conductively treated using a plasma treatment or doping process, forming a first conductive portion 2011 and a second conductive portion 2012. The second conductive portion 1022 is then reused as the pixel electrode 103.

[0106] S1205 , forming a gate insulating layer on a side of the semiconductor layer away from the substrate, and patterning the layer using a third mask to expose the first conductive portion and the second conductive portion.

[0107] As shown in FIG13f , a gate insulating layer 202 is deposited on the semiconductor layer 201. The gate insulating layer 202 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2). It can be a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The gate insulating layer 202 is patterned using a third mask to expose the first conductive portion 2011 and the second conductive portion 2012.

[0108] S1206 , patterning the buffer layer using a fourth mask plate to form overlapping vias exposing the data lines.

[0109] As shown in FIG. 13 g , the buffer layer 102 is patterned using a fourth mask to form overlapping vias V. The overlapping vias can penetrate through various film layers of the buffer layer 102 to expose the data lines 106 .

[0110] S1207 , forming a gate conductive layer on the side of the gate insulating layer facing away from the substrate, and patterning the layer using a fifth mask to form a gate and a bonding electrode connecting the first conductive portion and the data line.

[0111] As shown in FIG13h , a gate conductive layer is deposited on the gate insulating layer 202. The gate conductive layer can be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), or an alloy of these materials. It can be a single-layer structure or a multi-layer structure. The gate conductive layer is then patterned using a fifth mask to form the gate 203. A bonding electrode 2010 is also formed, connecting the data line 106 to the first conductor portion 2011 via the bonding electrode 2010.

[0112] S1208, forming a passivation layer on the side of the gate facing away from the substrate.

[0113] As shown in FIG13i , a passivation layer 104 is deposited on the pixel electrode 103 and the gate electrode 203. The passivation layer 104 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials.

[0114] S1209 , forming a transparent conductive layer on the side of the passivation layer facing away from the substrate, and patterning the layer using a sixth mask to form a common electrode.

[0115] As shown in FIG13 j , a transparent conductive layer is deposited on the passivation layer 104 . The transparent conductive layer can be formed of a conductive material such as ITO. The transparent conductive layer can be patterned using a sixth mask to form a common electrode 105 with a slit structure.

[0116] In the method for manufacturing an array substrate provided in the embodiments of the present disclosure, a mask plate can be used during the formation of the data line 106, the first conductive portion 2011 (the second conductive portion 2012 and the pixel electrode 103), the gate insulating layer 202, the gate 203, the overlapping via V, and the common electrode 105. The number of mask plates is six, which can reduce the number of mask plates and save manufacturing costs. When forming the gate insulating layer 202, it is not necessary to pattern the gate insulating layer 202, thus saving another mask plate. The number of mask plates is five, further saving manufacturing costs.

[0117] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An array substrate, wherein: The array substrate comprises: a substrate, a first film layer located on the substrate, a first electrode, a second film layer and a second electrode; the array substrate further comprises: a data line; the data line is located on a side of the first film layer away from the second electrode; The first film layer includes: a first sublayer and a second sublayer, and the dielectric constant of the first sublayer is smaller than the dielectric constant of the second sublayer.

2. The array substrate according to claim 1, wherein: The dielectric constant of the first sublayer is less than or equal to 4.0 Farad / meter, and the second sublayer is located on a side of the first sublayer facing away from the substrate and / or on a side of the first sublayer close to the substrate.

3. The array substrate according to claim 2, wherein: The first film layer includes M layers of the first sub-layers and N layers of the second sub-layers, 1≤M≤5, 1≤N≤5; The second sublayer is located between adjacent first sublayers.

4. The array substrate according to claim 1, wherein: The array substrate further comprises: a thin film transistor located on a side of the first film layer away from the substrate; the thin film transistor comprises: a semiconductor layer; the semiconductor layer comprises: a first conductor portion, a second conductor portion, and a channel portion located between the first conductor portion and the second conductor portion; The first conductor portion is electrically connected to the data line through a lap via hole; the lap via hole penetrates the first film layer and exposes a portion of the data line; The second conductor portion is multiplexed as the first electrode.

5. The array substrate according to claim 4, wherein: The first conductor portion is electrically connected to the data line through a bridging electrode, and at least a portion of the bridging electrode falls into the bridging via hole.

6. The array substrate according to claim 4, wherein: The thin film transistor further comprises: a gate located on a side of the semiconductor layer away from the substrate, and a gate insulating layer located between the semiconductor layer and the gate; The gate insulating layer covers the channel portion.

7. The array substrate according to claim 4, wherein: The thin film transistor further comprises: a gate located on a side of the semiconductor layer away from the substrate, and a gate insulating layer located between the semiconductor layer and the gate; The gate insulating layer covers the first conductor portion, the second conductor portion, and the channel portion, and the overlapping via penetrates the gate insulating layer.

8. The array substrate according to claim 4, wherein: At the overlapping via hole, the second sub-layer covers the side wall of the first sub-layer close to the overlapping via hole.

9. The array substrate according to claim 1, wherein: At least one of the first film layer and the second film layer has a thickness greater than or equal to 6000 angstroms.

10. The array substrate according to claim 4, wherein: The overlapping electrode is arranged in the same layer as the gate.

11. The array substrate according to claim 4, wherein: The overlapping electrode is arranged in the same layer as the common electrode.

12. The array substrate according to claim 4, wherein: The first conductive portion is reused as the bonding electrode.

13. The array substrate according to claim 1, wherein: The material of the dielectric sublayer includes at least one of an organic silicon material and a silicon fluoride material.

14. The array substrate according to any one of claims 5 to 7, wherein: The array substrate further comprises: a light shielding layer; the light shielding layer is located on a side of the semiconductor layer close to the substrate; The orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the channel portion on the substrate.

15. The array substrate according to claim 14, wherein: The light shielding layer is arranged on the same layer as the data line.

16. The array substrate according to claim 1, wherein: The orthographic projections of the first electrode and the second electrode on the substrate at least partially overlap, one of the two has a slit opening structure, and the other has a planar structure.

17. A display panel, wherein: The display device comprises the array substrate according to any one of claims 1 to 16.

18. A method for preparing an array substrate, wherein: The method for preparing the display substrate comprises: Forming a metal conductive layer on the substrate, and patterning it using a first mask to form a data line; A first film layer is formed on the side of the data line away from the substrate; the first film layer includes: a first sublayer and a second sublayer, the dielectric constant of the first sublayer is smaller than the dielectric constant of the second sublayer forming a semiconductor layer on a side of the first film layer away from the substrate, and patterning the first film layer using a second mask to form a first electrode; The semiconductor layer is processed to form a first conductive portion, a second conductive portion and a channel portion; the second conductive portion is reused as the pixel electrode; forming a gate insulating layer on a side of the semiconductor layer away from the substrate, and patterning the layer using a third mask to expose the first conductive portion and the second conductive portion; Using a fourth mask to pattern the first film layer to form a lapped via hole exposing the data line; A gate conductive layer is formed on a side of the gate insulating layer away from the substrate, and a fifth mask is used to perform patterning to form a gate and a bonding electrode connecting the first conductive portion and the data line. forming a second film layer on a side of the gate away from the substrate; A transparent conductive layer is formed on the side of the second film layer facing away from the substrate, and a sixth mask is used to perform patterning to form a second electrode.

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