Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of pixel driving circuits; a plurality of light emitting elements; a plurality of data lines configured to provide data signals to the plurality of pixel driving circuits; and a plurality of voltage supply lines extending in the display area of the array substrate and configured to supply voltage supply signals to the cathodes of the plurality of light emitting elements. The layer where the voltage supply lines are located is located on the side, close to the active layer of the pixel driving circuits, of the data lines, or the voltage supply lines and the data lines are located on the same layer.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently one of the hottest research areas in flat panel displays. OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate, including: a plurality of pixel driving circuits; a plurality of light-emitting elements; a plurality of data lines configured to provide data signals to the plurality of pixel driving circuits; and a plurality of voltage supply lines extending in a display area of ​​the array substrate and configured to provide voltage supply signals to the cathodes of the plurality of light-emitting elements; wherein the layer in which the plurality of voltage supply lines are located is located on the side of the plurality of data lines close to the active layer of the plurality of pixel driving circuits, or the plurality of voltage supply lines and the plurality of data lines are located on the same layer.

[0004] Optionally, the array substrate includes a second signal line layer; wherein the second signal line layer includes a plurality of third power signal lines configured to provide power signals, the power signals being the same as the signals provided to the light-emitting control transistors of the plurality of pixel driving circuits; the plurality of voltage supply lines and the plurality of third power signal lines are located on the same layer; and the plurality of voltage supply lines, the plurality of third power signal lines, and the plurality of data lines extend along a second direction.

[0005] Optionally, the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); the plurality of third power supply signal lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the (4k)th column, but not between the (4k-2)th column and the (4k-1)th column; and the plurality of voltage supply lines exist between the (4k-2)th column and the (4k-1)th column, but not between the (4k-3)th column and the (4k-2)th column, and not between the (4k-1)th column and the (4k)th column.

[0006] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines and a plurality of third power lines interconnected together; each of the plurality of first power lines extends along a first direction; each of the plurality of third power lines extends along a second direction; the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); and the plurality of third power signal lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the (4k)th column, and do not exist between the (4k-2)th column and the (4k-1)th column.

[0007] Optionally, the array substrate further includes a first reset signal network; wherein the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends along a first direction; each of the plurality of fifth reset signal lines extends along a second direction; the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); and the plurality of fifth reset signal lines exist between the (4k-2)th column and the (4k-3)th column, but not between the (4k-2)th column and the (4k-1)th column, and not between the (4k-1)th column and the (4k)th column.

[0008] Optionally, the array substrate further includes a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends along a first direction; each of the plurality of fourth reset signal lines extends along a second direction; the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); and the plurality of fourth reset signal lines exist between the (4k-1)th column and the (4k)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-3)th column and the (4k-2)th column.

[0009] Optionally, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1; and the ratio of the total number of data lines in the array substrate to the total number of the plurality of voltage supply lines is in the range of 3.5:1 to 4.5:1.

[0010] Optionally, the array substrate includes a third signal line layer; wherein the third signal line layer includes the plurality of data lines and the plurality of voltage supply lines; the plurality of data lines and the plurality of voltage supply lines extend along a second direction; the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4);

[0011] The plurality of pixel driving circuits are arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2); the plurality of voltage supply lines exist between the (4k-2)th column and the (4k-1)th column, but not between the (4k-3)th column and the (4k-2)th column, and not between the (4k-1)th column and the (4k)th column; two adjacent data lines of the plurality of data lines are located between two adjacent columns of pixel driving circuits in the K columns; the first adjacent data line of the two adjacent data lines between the two adjacent columns of pixel driving circuits in the K columns is configured to provide a data signal to the (2m-1)th row; and the second adjacent data line of the two adjacent data lines between the two adjacent columns of pixel driving circuits in the K columns is configured to provide a data signal to the (2m)th row.

[0012] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines and a plurality of third power lines interconnected together; each of the plurality of first power lines extends along a first direction; each of the plurality of third power lines extends along a second direction; the plurality of third power lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the (4k)th column; and the plurality of third power lines do not exist between the (4k-2)th column and the (4k-1)th column, do not exist between the (4k+1)th column and the (4k)th column, and do not exist between the (4k-4)th column and the (4k-3)th column.

[0013] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected together; each of the plurality of first power lines extends along a first direction; each of the plurality of second power lines extends along the first direction; each of the plurality of third power lines extends along a second direction; and the plurality of third power lines exist between the (4k-2)th column and the (4k-3)th column, between the (4k-2)th column and the (4k-1)th column, or between the (4k-1)th column and the (4k)th column.

[0014] Optionally, the array substrate further includes a first reset signal network; wherein the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends along a first direction; each of the plurality of fifth reset signal lines extends along a second direction; and the plurality of fifth reset signal lines exist between the (4k-2)th column and the (4k-3)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-1)th column and the (4k)th column.

[0015] Optionally, the array substrate further includes a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends along a first direction; each of the plurality of fourth reset signal lines extends along a second direction; the plurality of fourth reset signal lines exist between the (4k-1)th column and the (4k)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-3)th column and the (4k-2)th column.

[0016] Optionally, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1; and the ratio of the total number of data lines in the array substrate to the total number of the plurality of voltage supply lines is in the range of 3.5:1 to 4.5:1.

[0017] Optionally, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 1.8:1 to 2.2:1; and the ratio of the total number of data lines in the array substrate to the total number of the plurality of voltage supply lines is in the range of 3.5:1 to 4.5:1.

[0018] Optionally, the plurality of voltage supply lines include a plurality of first voltage supply lines and a plurality of second voltage supply lines interconnected; each of the plurality of first voltage supply lines extends along a first direction; each of the plurality of second voltage supply lines extends along a second direction; the plurality of pixel driving circuits are arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), and the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), and the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), and the (8j-3)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), and the (8j-3)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-3), and the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-3), and the (8j-3 ...3 The plurality of second voltage supply lines are located between the (8j-1)th column C(8j-1) and the (8j)th column C(8j) of the J columns, where J and j are positive integers, 1≤j≤(J / 8); the plurality of second voltage supply lines exist between the (8j)th column and the (8j-1)th column, or exist between the (8j-4)th column and the (8j-5)th column; and the plurality of second voltage supply lines do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-2)th column C(8j-2) and the (8j-3)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-5)th column and the (8j-6)th column, and do not exist between the (8j-6)th column and the (8j-7)th column.

[0019] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected together; each of the plurality of first power lines extends along a first direction; each of the plurality of second power lines extends along the first direction; each of the plurality of third power lines extends along a second direction; the plurality of third power lines exist between the (8j-1) column and the (8j-2) column, between the (8j-3) column and the (8j-4) column, or between the (8j-5) column and the (8j-6) column; and the plurality of third power lines do not exist between the (8j) column and the (8j-1) column, between the (8j-2) column and the (8j-3) column, between the (8j-4) column and the (8j-5) column, and between the (8j-6) column and the (8j-7) column.

[0020] Optionally, the array substrate further includes a first reset signal network; wherein the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends along a first direction; each of the plurality of fifth reset signal lines extends along a second direction; and the plurality of fifth reset signal lines exist between the (8j-6)th column and the (8j-7)th column, do not exist between the (8j)th column and the (8j-1)th column, do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-2)th column and the (8j-3)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-4)th column and the (8j-5)th column, and do not exist between the (8j-5)th column and the (8j-6)th column.

[0021] Optionally, the array substrate further includes a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends along a first direction; each of the plurality of fourth reset signal lines extends along a second direction; and the plurality of fourth reset signal lines exist between the (8j-2)th column and the (8j-3)th column, do not exist between the (8j)th column and the (8j-1)th column, do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-4)th column and the (8j-5)th column, do not exist between the (8j-5)th column and the (8j-6)th column, and do not exist between the (8j-6)th column and the (8j-7)th column.

[0022] Optionally, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 15.0:1 to 17.0:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 15.0:1 to 17.0:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1; and the ratio of the total number of data lines in the array substrate to the total number of the plurality of second voltage supply lines is in the range of 7.5:1 to 8.5:1.

[0023] Optionally, the array substrate further includes a plurality of first power lines and a plurality of fourth reset signal lines; wherein the plurality of first reset signal lines, the plurality of fourth reset signal lines, and the plurality of voltage supply lines are interconnected; each of the plurality of first reset signal lines extends along a first direction; each of the plurality of voltage supply lines extends along the first direction; each of the plurality of fourth reset signal lines extends along a second direction; the plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); the plurality of fourth reset signal lines exist in the array substrate. Between column (4k-1) and column (4k), there is no space between column (4k-2) and column (4k-1), and there is no space between column (4k-3) C(4k-3) and column (4k-2); each of the first reset signal lines is connected to at least a plurality of fourth reset signal lines; each of the fourth reset signal lines is connected to at least a plurality of first reset signal lines; the plurality of first reset signal lines, the plurality of fourth reset signal lines, and the plurality of voltage supply lines are configured to provide a voltage supply signal to the cathodes of the plurality of light-emitting elements and to provide a reset signal to the first reset transistors of the plurality of pixel driving circuits; and the voltage supply signal provided to the cathodes of the plurality of light-emitting elements and the reset signal provided to the first reset transistors of the plurality of pixel driving circuits are the same signal.

[0024] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected together; each of the plurality of first power lines extends along a first direction; each of the plurality of second power lines extends along the first direction; each of the plurality of third power lines extends along a second direction; and the plurality of third power lines exist between the (4k-1)th column and the (4k-2)th column, do not exist between the (4k)th column and the (4k-1)th column, and do not exist between the (4k-2)th column and the (4k-3)th column.

[0025] Optionally, the array substrate further includes a first reset signal network; wherein the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends along the first direction; each of the plurality of fifth reset signal lines extends along the second direction; and the plurality of fifth reset signal lines exist between the (4k-2)th column and the (4k-3)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-1)th column and the (4k)th column.

[0026] Optionally, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1; the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1; and the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.6:1 to 4.4:1.

[0027] On the other hand, this disclosure provides a display device including an array substrate described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0028] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0029] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0032] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0033] Figure 3B It is shown Figure 3A The diagram depicts the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0034] Figure 3C It is shown Figure 3A A schematic diagram depicting the arrangement of pixel driving circuits in an array substrate.

[0035] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted.

[0036] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0037] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0038] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted.

[0039] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0040] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure.

[0041] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0042] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0043] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0044] Figure 3M It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted.

[0045] Figure 3N It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0046] Figure 3O It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0047] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0048] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0049] Figure 5A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 5B It is shown Figure 5A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0051] Figure 5C It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0052] Figure 5D It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0053] Figure 5E It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0054] Figure 5F It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0055] Figure 5G It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0056] Figure 5H It is shown Figure 5A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0057] Figure 5I It is shown Figure 5AThe diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0058] Figure 5J It is shown Figure 5A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0059] Figure 5K It is shown Figure 5A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0060] Figure 6A It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0061] Figure 6B It is shown Figure 5A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0062] Figure 6C It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0063] Figure 6D It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0064] Figure 6E It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0065] Figure 7A It is shown Figure 5A A schematic diagram of the power network in the array substrate depicted in the figure.

[0066] Figure 7B It is shown Figure 5A A schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0067] Figure 7C It is shown Figure 5A A schematic diagram of the second reset signal network in the array substrate depicted in the figure.

[0068] Figure 8A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0069] Figure 8B It is shown Figure 8AThe diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0070] Figure 8C It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0071] Figure 8D It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0072] Figure 8E It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0073] Figure 8F It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0074] Figure 8G It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0075] Figure 8H It is shown Figure 8A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0076] Figure 8I It is shown Figure 8A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0077] Figure 8J It is shown Figure 8A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0078] Figure 8K It is shown Figure 8A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0079] Figure 9A It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0080] Figure 9B It is shown Figure 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0081] Figure 9C It is shown Figure 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0082] Figure 9D It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0083] Figure 9E It is shown Figure 8A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0084] Figure 10A It is shown Figure 8A A schematic diagram of the power network in the array substrate depicted in the figure.

[0085] Figure 10B It is shown Figure 8A A schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0086] Figure 10C It is shown Figure 8A A schematic diagram of the second reset signal network in the array substrate depicted in the figure.

[0087] Figure 11A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0088] Figure 11B It is shown Figure 11A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0089] Figure 11C It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0090] Figure 11D It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0091] Figure 11E It is shown Figure 11AThe diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0092] Figure 11F It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0093] Figure 11G It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0094] Figure 11H It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0095] Figure 11I It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0096] Figure 11G It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0097] Figure 11K It is shown Figure 11A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0098] Figure 12A It is shown Figure 11A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0099] Figure 12B It is shown Figure 11A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0100] Figure 12C It is shown Figure 11A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0101] Figure 12D It is shown Figure 11AA schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0102] Figure 12E It is shown Figure 11A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0103] Figure 13A It is shown Figure 11A A schematic diagram of the power network in the array substrate depicted in the figure.

[0104] Figure 13B It is shown Figure 11A A schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0105] Figure 13C It is shown Figure 11A A schematic diagram of the second reset signal network in the array substrate depicted in the figure.

[0106] Figure 14A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0107] Figure 14B It is shown Figure 14A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0108] Figure 14C It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0109] Figure 14D It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0110] Figure 14E It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0111] Figure 14F It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0112] Figure 14G It is shown Figure 14AThe diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0113] Figure 14H It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0114] Figure 14I It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0115] Figure 14J It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0116] Figure 14K It is shown Figure 14A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0117] Figure 15A It is shown Figure 14A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0118] Figure 15B It is shown Figure 14A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0119] Figure 15C It is shown Figure 14A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0120] Figure 15D It is shown Figure 14A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0121] Figure 15E It is shown Figure 14A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0122] Figure 16A It is shown Figure 14A A schematic diagram of the power network in the array substrate depicted in the figure.

[0123] Figure 16B It is shown Figure 14AA schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0124] Figure 16C It is shown Figure 14A A schematic diagram of the second reset signal network in the array substrate depicted in the figure.

[0125] Figure 17A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0126] Figure 17B It is shown Figure 17A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0127] Figure 17C It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0128] Figure 17D It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0129] Figure 17E It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0130] Figure 17F It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0131] Figure 17G It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0132] Figure 17H It is shown Figure 17A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0133] Figure 17I It is shown Figure 17AThe diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0134] Figure 17J It is shown Figure 17A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0135] Figure 17K It is shown Figure 17A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0136] Figure 18A It is shown Figure 17A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0137] Figure 18B It is shown Figure 17A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0138] Figure 18C It is shown Figure 17A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0139] Figure 18D It is shown Figure 17A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0140] Figure 18E It is shown Figure 17A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0141] Figure 19A It is shown Figure 17A A schematic diagram of the power network in the array substrate depicted in the figure.

[0142] Figure 19B It is shown Figure 17A A schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0143] Figure 19C It is shown Figure 17A A schematic diagram of the second reset signal network in the array substrate depicted in the figure.

[0144] Figure 19D It is shown Figure 17A A schematic diagram of the voltage supply network in the array substrate depicted in the figure.

[0145] Figure 20AThis is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure.

[0146] Figure 20B It is shown Figure 20A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate.

[0147] Figure 20C It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate.

[0148] Figure 20D It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0149] Figure 20E It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0150] Figure 20F It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0151] Figure 20G It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0152] Figure 20H It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0153] Figure 20I It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate.

[0154] Figure 20J It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0155] Figure 20K It is shown Figure 20A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0156] Figure 21A It is shown Figure 20A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0157] Figure 21B It is shown Figure 20A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0158] Figure 21C It is shown Figure 20A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0159] Figure 21D It is shown Figure 20A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0160] Figure 21E It is shown Figure 20A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure.

[0161] Figure 22A It is shown Figure 20A A schematic diagram of the power network in the array substrate depicted in the figure.

[0162] Figure 22B It is shown Figure 20A A schematic diagram of the first reset signal network in the array substrate depicted in the figure.

[0163] Figure 22C It is shown Figure 20A A schematic diagram of the second reset signal network in the array substrate depicted in the figure. Specific Implementation

[0164] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0165] This disclosure provides, in particular, an array substrate and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes: a plurality of pixel driving circuits; a plurality of light-emitting elements; a plurality of data lines configured to provide data signals to the plurality of pixel driving circuits; and a plurality of voltage supply lines extending in a display area of ​​the array substrate and configured to provide voltage supply signals to the cathodes of the plurality of light-emitting elements. Optionally, the layer containing the plurality of voltage supply lines is located on the side of the plurality of data lines adjacent to the active layer of the plurality of pixel driving circuits, or the plurality of voltage supply lines and the plurality of data lines are located on the same layer.

[0166] Various suitable pixel driving circuits can be used in the array substrate of this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate of this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0167] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components such as a light-emitting element. In one example, the light-emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of data lines (e.g., each data line DL), a plurality of power lines (e.g., each power line Vdd), and a plurality of voltage supply lines (e.g., each voltage supply line Vss). Each subpixel Sp is driven to emit light by the respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via each of the plurality of power lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via the voltage supply lines. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV that drives the light-emitting element to emit light.

[0168] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line among a plurality of second gate lines. The transistor comprises: a gate of line GL2; a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to a corresponding power line Vdd among a plurality of power lines; and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to the second electrode of the driving transistor Td and the second electrode of the second transistor T2; and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines; a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines; and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding power line and the first electrode of the third transistor T3.

[0169] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0170] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to the active layer of the transistor. The direction of current flow through the transistor can be configured from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flow through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0171] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0172] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes each first sub-pixel, each second sub-pixel, and each third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of the form S1-S2-S3, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 form is a C1-C2-C3 form, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 form is an RGB form, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0173] In another example, the array of multiple sub-pixels includes a repeating array of the form S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 form is C1-C2-C3-C4, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In yet another example, the S1-S2-S3-S4 form is C1-C2-C3-C2', where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C2' represents each fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' form is RGBG, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0174] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0175] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0176] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2AThe second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0177] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to turn off. In the initial sub-stage t0, a cutoff signal is provided to the corresponding first gate line GL1, therefore the first transistor T1 is turned off.

[0178] In reset phase t1, the turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, turning on the first reset transistor Tr1; this causes the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and then to node N4. The anode of the light-emitting element LE is initialized. The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1, turning on the third reset transistor Tr3; this causes the initialization voltage signal from the corresponding third reset signal line Vint3 to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding power supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During the reset phase t1, a cutoff signal is provided to the corresponding first gate line GL1, thus turning off the first transistor T1. A high voltage signal is provided to the corresponding light-emitting control signal line em, causing the third transistor T3 and the fourth transistor T4 to turn off.

[0179] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2, turning on the second reset transistor Tr2. This causes the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to its second electrode, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is then initialized.

[0180] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to be turned off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Because the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Because only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level of node N1 gradually increases to (Vdata + Vth) during the data write sub-stage t2, where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0181] In the light-emitting phase t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is also provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing both the first and third reset transistors Tr1 and Tr3 to turn off. Cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, thus turning off the first transistor T1 and the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em, causing the third transistor T3 and the fourth transistor T4 to turn on. In the light-emitting phase t3, the voltage level of node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0182] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A The diagram depicts the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the first signal line layer in the array substrate. Figure 3C It is shown Figure 3A A schematic diagram depicting the arrangement of pixel driving circuits in an array substrate. Figures 3A to 3C A portion of an array substrate with two adjacent pixel driving circuits (including PDC1 and PDC2) is depicted.

[0183] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0184] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 3I It is shown Figure 3A A schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 3M It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted. Figure 3N It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figure 3O It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate is depicted. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0185] Reference Figures 3A to 3N , Figure 4A and Figure 4BIn some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; and a second interlayer dielectric layer ILD2 located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1. A three-gate metal layer (Gate3) is located on the side of the second interlayer dielectric layer (ILD2) away from the second semiconductor material layer (SML2); a passivation layer (PVX) is located on the side of the third gate metal layer (Gate3) away from the second interlayer dielectric layer (ILD2); a first signal line layer (SD1) is located on the side of the passivation layer (PVX) away from the third gate metal layer (Gate3); a first planarization layer (PLN1) is located on the side of the first signal line layer (SD1) away from the passivation layer (PVX); and a second signal line layer (SD2) is located on the side of the first planarization layer (PLN1). The side of LN1 away from the first signal line layer SD1; the second planarization layer PLN2, which is located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; the third signal line layer SD3, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SD2; the third planarization layer PLN3, which is located on the side of the third signal line layer SD3 away from the second planarization layer PLN2; and the anode layer ADL, which is located on the side of the third planarization layer PLN3 away from the third signal line layer SD3.

[0186] Reference Figure 2A , Figure 3A , Figure 3D , Figure 4A and Figure 4BIn some embodiments, the first semiconductor material layer SML1 includes an active layer of at least a pixel driving circuit comprising a plurality of transistors including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit comprising the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit comprising the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode of a pixel driving circuit comprising a plurality of transistors including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0187] exist Figure 3D In, with Figure 3C The pixel driving circuit corresponding to PDC2 is labeled with markings indicating components of each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0188] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACTr3 and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3 and Sd), and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0189] In some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure. Optionally, in the same pixel driving circuit, the portion of the second reset transistor Tr2 located in the first semiconductor material layer (ACTr2, Sr2, Dr2) is spaced apart from the overall structure (T1, T3, T4, Tr1, Tr3, and Td). Figure 3D As shown, in some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of a plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in two adjacent pixel driving circuits, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure.

[0190] Reference Figure 2A , Figure 3A , Figure 3E , Figure 4A and Figure 4B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a first light emission control electrode pad emP1, a second light emission control electrode pad emP2, and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0191] In some embodiments, the first light-emitting control electrode pad emP1 includes the gate G3 of the third transistor T3. Optionally, the first light-emitting control electrode pad emP1 includes the gate of the third transistor of the first adjacent pixel driving circuit and the second adjacent pixel driving circuit in the same row. In some embodiments, the second light-emitting control electrode pad emP2 includes the gate G4 of the fourth transistor T4. Optionally, the second light-emitting control electrode pad emP2 includes the gate of the fourth transistor of the first adjacent pixel driving circuit and the third adjacent pixel driving circuit in the same row. The third adjacent pixel driving circuit, the first adjacent pixel driving circuit, and the second adjacent pixel driving circuit are arranged sequentially in the same row.

[0192] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a first light-emitting control electrode pad emP1, a second light-emitting control electrode pad emP2, and the first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0193] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines and first capacitor electrodes Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process on the same material layer. In another example, multiple first gate lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines and the steps of forming first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0194] In some embodiments, refer to Figure 3A , Figure 3B , Figure 3E , Figure 3J and Figure 4AThe first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are connected to corresponding light-emitting control signal lines em among a plurality of light-emitting control signal lines. Optionally, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are located in the first gate metal layer Gate1. Optionally, each light-emitting control signal line em is located in the first signal line layer SD1. In one example, each light-emitting control signal line em is connected to the first light-emitting control electrode pad emP1 via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, each light-emitting control signal line em is connected to the second light-emitting control electrode pad emP2 via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0195] Reference Figure 2A , Figure 3A , Figure 3F , Figure 4A and Figure 4B In some embodiments, the second gate metal layer Gate2 includes at least portions of a plurality of second gate lines (e.g., first branches GL2-1 of each second gate line), a plurality of second reset signal lines (e.g., each second reset signal line Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least portions of the plurality of second gate lines (e.g., first branches GL2-1 of each second gate line), the plurality of second reset signal lines (e.g., each second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0196] Reference Figure 2A , Figure 3A , Figure 3G , Figure 4A and Figure 4BIn some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2 of the second transistor T2, the first electrode S2, and the second electrode D2. In the array substrate of this disclosure, at least the active layer ACT2 of the second transistor T2 is located in a different layer than the active layers of at least other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.

[0197] exist Figure 3G In, with Figure 3C The pixel driving circuit corresponding to PDC2 is marked with labels indicating the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are located on the same layer.

[0198] Reference Figure 2A , Figure 3A , Figure 3H , Figure 4A and Figure 4B In some embodiments, the third gate metal layer Gate3 includes at least portions of a plurality of second gate lines (e.g., second branches GL2-2 of each second gate line), a plurality of first reset signal lines (e.g., each first reset signal line Vint1), and a plurality of third reset signal lines (e.g., each third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third gate metal layer Gate3. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0199] Figure 3I Show Figure 3A The image depicts vias extending through the passivation layer in an array substrate.

[0200] Reference Figure 2A, Figure 3A , Figure 3J , Figure 4A and Figure 4B In some embodiments, the first signal line layer SD1 includes a plurality of light emission control signal lines (e.g., each light emission control signal line em), a first voltage connection pad VCP1, a second voltage connection pad VCP2, a first data connection pad DCP1, a first node connection line Cln1, a third node connection line Cln3, a first relay electrode RE1, a first reset signal connection line Cli1, a second reset signal connection line Cli2, and a third reset signal connection line Cli3.

[0201] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on the substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple light emission control signal lines (e.g., each light emission control signal line em), a first voltage connection pad VCP1, a second voltage connection pad VCP2, a first data connection pad DCP1, a first node connection line Cln1, a third node connection line Cln3, a first relay electrode RE1, a first reset signal connection line Cli1, a second reset signal connection line Cli2, and a third reset signal connection line Cli3 are located on the same layer.

[0202] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (Refer to...) Figure 4A The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the first electrode S2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 is depicted in the diagram.

[0203] In some embodiments, the orthographic projection of the second electrode Dr3 of the third reset transistor Tr3 onto the substrate BS at least partially overlaps with the orthographic projection of the first voltage connection pad VCP1 onto the substrate BS. The inventors of this disclosure have found that this structure helps stabilize the voltage level at node N2 by having a constant voltage at the first voltage connection pad VCP1.

[0204] Reference Figure 2A , Figure 3A , Figure 3E , Figure 3F , Figure 4A and Figure 4B In some embodiments, the second capacitor electrode Ce2 is absent from the portion of the via region H. Optionally, except for the portion of the via H in which the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the via region H, and the insulating layer IN.

[0205] In some embodiments, the first node connection line Cln1 intersects with a corresponding second gate line among a plurality of second gate lines. For example... Figure 3A , Figure 3B and Figure 4A As shown, the first node connection line Cln1 intersects with the first branch GL2-1 of the corresponding second gate line located in the second gate metal layer Gate2, and intersects with the second branch GL2-2 of the corresponding second gate line located in the third gate metal layer Gate3.

[0206] In some embodiments, refer to Figure 4B The third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 through the third via v3, to the second electrode D2 of the second transistor T2 through the fourth via v4, and to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through the fifth via v5. Optionally, the third node connection line Cln3 corresponds to Figure 2A Node N3 is depicted in the diagram. Optionally, the third node connecting line Cln3 intersects with a corresponding second gate line among a plurality of second gate lines. For example... Figure 3A , Figure 3B and Figure 4B As shown, the third node connection line Cln3 intersects with the first branch GL2-1 of the corresponding second gate line located in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line located in the third gate metal layer Gate3.

[0207] In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) with the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate. Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the direction in which the active layer ACT2 of the second transistor T2 extends. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the first electrode S2 of the second transistor T2 on the substrate. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the second electrode D2 of the second transistor T2 on the substrate. As used herein, the term “substantially parallel” means an angle in the range of 0 to 45 degrees, for example, 0 to 5 degrees, 0 to 10 degrees, 0 to 15 degrees, 0 to 20 degrees, 0 to 25 degrees, and 0 to 30 degrees.

[0208] In the array substrate of this disclosure, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an overall structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more portions of the first semiconductor material layer SML1; for example, there are no connection lines in layers other than the first semiconductor material layer SML1.

[0209] In some embodiments, each of the plurality of light emission control signal lines em is connected to a first light emission control electrode pad emP1 and a second light emission control electrode pad emP2 located in the first gate metal layer Gate1.

[0210] Figure 3K Show Figure 3A The vias extending through the first planarization layer in the array substrate depicted in the figure.

[0211] Reference Figure 2A , Figure 3A , Figure 3B , Figure 3L , Figure 4A and Figure 4B In some embodiments, the second signal line layer SD2 includes a plurality of second power lines (e.g., individual second power lines Vdd2), a plurality of first voltage supply lines (e.g., individual first voltage supply lines Vss1), a second relay electrode RE2, and a second data connection pad DCP2. Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the plurality of second power lines (e.g., individual second power lines Vdd2), the second relay electrode RE2, and the second data connection pad DCP2 are located in the same layer.

[0212] Figure 3M Show Figure 3A The vias extending through the second planarization layer in the array substrate depicted in the figure.

[0213] Reference Figure 2A , Figure 3A , Figure 3N , Figure 4A and Figure 4B In some embodiments, the third signal line layer SD3 includes a plurality of third power lines (e.g., each third power line Vdd3), an anode contact pad ACP, a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), a plurality of fifth reset signal lines (e.g., each fifth reset signal line Vint5), a plurality of sixth reset signal lines (e.g., each sixth reset signal line Vint6), and a plurality of second voltage supply lines (e.g., each second voltage supply line Vss2). In some embodiments, each second power line Vdd2 and each third power line Vdd3 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, each voltage supply line Vss is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0214] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the third signal line layer SD3. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer SD3 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple third power lines (e.g., each third power line Vdd3), anode contact pads ACP, multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), multiple fifth reset signal lines (e.g., each fifth reset signal line Vint5), multiple sixth reset signal lines (e.g., each sixth reset signal line Vint6), and multiple second voltage supply lines (e.g., each second voltage supply line Vss2) are located on the same layer.

[0215] Reference Figure 2A , Figure 3A , Figure 3O , Figure 4A and Figure 4B In some embodiments, the anode layer ADL includes multiple anodes AD.

[0216] Reference Figure 2A , Figure 3A , Figure 3B , Figure 3J , Figure 3L , Figure 3N , Figure 4A and Figure 4B In some embodiments, a plurality of second power lines and a plurality of third power lines are interconnected to form a power network. Each of the plurality of second power lines, Vdd2, is connected to a first voltage connection pad, VCP1, which is connected to a first electrode of a third transistor T3, thereby providing a power signal to the first electrode of the third transistor T3. Each of the plurality of second power lines, Vdd2, is connected to a second voltage connection pad, VCP2, which is connected to a second capacitor electrode, Ce2, of the storage capacitor Cst, thereby providing a power signal to the second capacitor electrode, Ce2, of the storage capacitor Cst.

[0217] In some embodiments, a first reset signal connection line Cli1 connects a corresponding first reset signal line Vint1 among a plurality of first reset signal lines to a first electrode Sr1 of a first reset transistor Tr1. The first reset signal connection line Cli1 is configured to transmit a reset signal from the corresponding first reset signal line Vint1 to the first electrode Sr1 of the first reset transistor Tr1.

[0218] In some embodiments, the second reset signal connection line Cli2 connects a corresponding second reset signal line Vint2 among a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Cli2 is configured to transmit a reset signal from the corresponding second reset signal line Vint2 to the first electrode Sr1 of the second reset transistor Tr2.

[0219] In some embodiments, the third reset signal connection line Cli3 connects a corresponding third reset signal line Vint3 among a plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor Tr3. The third reset signal connection line Cli3 is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In one example, the third reset signal connection line Cli3 is connected to the first electrode of the third reset transistor of two adjacent pixel driving circuits in the same row, and is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode of the third reset transistor of the two adjacent pixel driving circuits in the same row.

[0220] In some embodiments, the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) and to the second relay electrode RE2. The second relay electrode is connected to the first relay electrode RE1 and to the anode contact pad ACP. In one example, the anode contact pad ACP is located on the third signal line layer SD3, the second relay electrode RE2 is located on the second signal line layer SD2, and the first relay electrode RE1 is located on the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the second relay electrode RE2 via a via extending through the second planarization layer PLN2, the second relay electrode RE2 is connected to the first relay electrode RE1 via a via extending through the first planarization layer PLN1, and the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0221] In some embodiments, a first data connection pad DCP1 is connected to a first electrode S1 of a first transistor T1 and to a second data connection pad DCP2. The second data connection pad DCP2 is connected to the first data connection pad DCP1 and to a corresponding data line DL among a plurality of data lines. In one example, the first data connection pad DCP1 is located on a first signal line layer SD1, the second data connection pad DCP2 is located on a second signal line layer SD2, and each data line DL is located on a third signal line layer SD3. In another example, each data line DL is connected to the second data connection pad DCP2 via a via extending through a second planarization layer PLN2, the second data connection pad DCP2 is connected to the first data connection pad DCP1 via a via extending through a first planarization layer PLN1, and the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 via a via extending through a passivation layer PVX, a second interlayer dielectric layer ILD2, a first interlayer dielectric layer ILD1, an insulating layer IN, and a gate insulating layer GI.

[0222] Reference Figure 3A , Figure 3B and Figure 3D The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an overall structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more portions of the first semiconductor material layer SML1; for example, there are no connection lines in layers other than the first semiconductor material layer SML1.

[0223] In some embodiments, refer to Figures 3A to 3N The first pixel driving circuits that are directly adjacent to each other and in the current level (e.g., in the same row) Figure 3C The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 3CThe corresponding layer of PDC2 in the array has, for example, a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines, and has a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical) mirror symmetry with respect to each other.

[0224] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a first signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third gate metal layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second gate metal layer.

[0225] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and at least one conductive layer of the second pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first semiconductor material layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first gate metal layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a second semiconductor material layer.

[0226] Various alternative implementations can be practiced in this disclosure. In particular, the first signal line layer, the second signal line layer, and the third signal line layer can be implemented in various alternative ways, as shown in the following embodiments.

[0227] Figure 5AThis is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 5B It is shown Figure 5A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 5C It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 5D It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 5E It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate. Figure 5F It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate. Figure 5G It is shown Figure 5A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 5H It is shown Figure 5A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate. Figure 5I It is shown Figure 5A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 5J It is shown Figure 5A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 5K It is shown Figure 5A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 6A It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 6B It is shown Figure 5A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 6C It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 6D It is shown Figure 5AA schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 6E It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 5A to 5K , Figures 6A to 6E A portion of an array substrate with eight adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The eight adjacent pixel driving circuits are arranged in four columns and two rows.

[0228] Figure 7A It is shown Figure 5A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 5A to 5K , Figures 6A to 6E and Figure 7A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of second power lines, Vdd2, extends along the first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0229] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0230] In some embodiments, the plurality of second power lines and the plurality of third power lines are part of an overall structure. Optionally, the plurality of second power lines and the plurality of third power lines are located on a second signal line layer. Each of the plurality of second power lines, Vdd2, is connected to the plurality of third power lines, and each of the plurality of third power lines, Vdd3, is connected to the plurality of second power lines.

[0231] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each second power line Vdd2 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each second power line Vdd2 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0232] Figure 7B It is shown Figure 5A A schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 5A to 5K , Figures 6A to 6E as well as Figure 7B In some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a first signal line layer.

[0233] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines. Optionally, each fifth reset signal line Vint5 extends through a via to connect to a second reset signal line, the via extending through at least one of a passivation layer, a second interlayer dielectric layer, or a first interlayer dielectric layer.

[0234] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0235] As used herein, the terms "column (4k-3)," "column (4k-2)," "column (4k-1)," and "column (4k)" are used in the context of K columns. The array substrate may or may not include additional columns preceding the first column of the K columns and / or additional columns following the last column of the K columns. In the context of the array substrate, the terms "column (4k-3)" or "column (4k-1)" do not necessarily indicate an odd-numbered column, and the terms "column (4k-2)" or "column (4k)" do not necessarily indicate an even-numbered column. In one example, column (4k-3) is an odd-numbered column in the context of K columns, but may be an even-numbered column in the context of the array substrate. In another example, column (4k-3) is an odd-numbered column in the context of K columns and also an odd-numbered column in the context of the array substrate. In one example, column (4k-2) is an even-numbered column in the context of K columns, but may be an odd-numbered column in the context of the array substrate. In another example, column (4k-2) is an even column against the background of the K columns, and also an even column against the background of the array substrate. In one example, column (4k-1) is an odd column against the background of the K columns, but can be an even column against the background of the array substrate. In another example, column (4k-1) is an odd column against the background of the K columns, and also an odd column against the background of the array substrate. In one example, column (4k) is an even column against the background of the K columns, but can be an odd column against the background of the array substrate. In another example, column (4k) is an even column against the background of the K columns, and also an even column against the background of the array substrate.

[0236] In some embodiments, a plurality of fifth reset signal lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0237] In some embodiments, refer to Figure 7A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), between column (4k-2) C(4k-2) and column (4k-1) C(4k-1), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0238] Figure 7C It is shown Figure 5A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 5A to 5K , Figures 6A to 6E as well as Figure 7CIn some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a first signal line layer.

[0239] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines. Optionally, each fourth reset signal line Vint4 extends through a via to connect to a first reset signal line, the via extending through at least a passivation layer.

[0240] In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2).

[0241] In some embodiments, refer to Figure 7A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), between column (4k-2) C(4k-2) and column (4k-1) C(4k-1), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0242] In some embodiments, refer to Figure 6B The array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0243] In some embodiments, refer to Figure 6E The array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0244] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m) of the M rows, where M and m are positive integers, 1≤m≤(M / 2). As used herein, the terms “(2m-1)th row” and “(2m)th row” are used in the context of M rows. The array substrate may or may not include additional rows preceding the first row of the M rows and / or additional rows following the last row of the M rows. In the context of the array substrate, the term “(2m-1)th row” does not necessarily mean an odd-numbered row, and the term “(2m)th row” does not necessarily mean an even-numbered row. In one example, the (2m-1)th row is an odd-numbered row in the context of M rows, but may be an even-numbered row in the context of the array substrate. In another example, the (2m-1)th row is an odd-numbered row in the context of M rows, and is also an odd-numbered row in the context of the array substrate. In one example, row (2m) is an even row against the background of rows M, but can be an odd row against the background of the array substrate. In another example, row (2m) is an even row against the background of rows M, and is also an even row against the background of the array substrate.

[0245] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0246] Reference Figure 6E In some embodiments, the first data line and the second data line are configured to provide data signals to pixel driving circuitry located in the same column and in rows (2m-1) and (2m) respectively. The first data line includes a first protrusion PT1 for connection to a first electrode of a first transistor located in the same column and in the (2m-1) row R(2m-1). The second data line includes a second protrusion PT2 for connection to a first electrode of a first transistor located in the same column and in the (2m) row R(2m). In some embodiments, the first protrusion PT1 has a first length along a first direction DR1; the second protrusion PT2 has a second length along the first direction DR1, the first length being different from the second length. In one example, the first length is greater than the second length. In an alternative example, the second length is greater than the first length.

[0247] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0248] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0249] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 1.8:1 to 2.2:1, for example, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, or 2.1:1 to 2.2:1.

[0250] Figure 8A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 8B It is shown Figure 8A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 8C It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 8D It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 8E It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate. Figure 8F It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate. Figure 8G It is shown Figure 8A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 8H It is shown Figure 8AThe diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate. Figure 8I It is shown Figure 8A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 8J It is shown Figure 8A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 8K It is shown Figure 8A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 9A It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 9B It is shown Figure 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 9C It is shown Figure 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 9D It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 9E It is shown Figure 8A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 8A to 8K , Figures 9A to 9E A portion of an array substrate with eight adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The eight adjacent pixel driving circuits are arranged in four columns and two rows.

[0251] Figure 10A It is shown Figure 8A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 8A to 8K , Figures 9A to 9E and Figure 10A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines and a plurality of third power lines interconnected together. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0252] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0253] In some embodiments, multiple third power lines exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), or between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, each third power line Vdd3 does not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, multiple third power lines do not exist between column (4k+1) and column (4k) C(4k). Optionally, multiple third power lines do not exist between column (4k-4) and column (4k-3) C(4k-3).

[0254] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0255] In some embodiments, a plurality of third power lines are located on the second signal line layer.

[0256] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each third power line Vdd3 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each third power line Vdd3 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0257] Figure 10B It is shown Figure 8A A schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 8A to 8K , Figures 9A to 9E as well as Figure 10BIn some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a first signal line layer.

[0258] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines. Optionally, each fifth reset signal line Vint5 extends through a via to connect to a second reset signal line, the via extending through at least one of a passivation layer, a second interlayer dielectric layer, or a first interlayer dielectric layer.

[0259] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0260] In some embodiments, a plurality of fifth reset signal lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0261] In some embodiments, refer to Figure 10A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0262] Figure 10C It is shown Figure 8A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 8A to 8K , Figures 9A to 9E as well as Figure 10CIn some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a first signal line layer.

[0263] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines. Optionally, each fourth reset signal line Vint4 extends through a via to connect to a first reset signal line, the via extending through at least a passivation layer.

[0264] In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2).

[0265] In some embodiments, refer to Figure 9B The array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0266] In some embodiments, refer to Figure 9D The array substrate also includes multiple voltage supply lines. Optionally, each of the multiple voltage supply lines, Vss, extends along a second direction DR2. Optionally, the multiple voltage supply lines are located on a second signal line layer.

[0267] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0268] In some embodiments, a plurality of third power lines exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), or between column (4k-1) C(4k-1) and column (4k) C(4k). In some embodiments, a plurality of voltage supply lines exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of third power lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of third power lines do not exist between column (4k+1) and column (4k) C(4k). Optionally, a plurality of third power lines do not exist between column (4k-4) and column (4k-3) C(4k-3). Optionally, multiple voltage supply lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), and do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0269] In some embodiments, refer to Figure 9E The array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0270] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2).

[0271] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0272] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0273] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0274] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0275] In some embodiments, the ratio of the total number of data lines to the total number of voltage supply lines in the array substrate is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0276] Figure 11A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 11B It is shown Figure 11A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 11C It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 11D It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 11E It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0277] Figure 11F It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0278] Figure 11G It is shown Figure 11A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 11H It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0279] Figure 11I It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 11J It is shown Figure 11A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 11K It is shown Figure 11A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 12A It is shown Figure 11A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 12B It is shown Figure 11A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 12C It is shown Figure 11A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 12D It is shown Figure 11A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 12E It is shown Figure 11A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 11A to 11K , Figures 12A to 12E A portion of an array substrate with eight adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The eight adjacent pixel driving circuits are arranged in four columns and two rows.

[0280] Figure 13A It is shown Figure 11A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 11A to 11K , Figures 12A to 12E and Figure 13A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines and a plurality of third power lines interconnected together. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0281] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0282] In some embodiments, a plurality of third power lines exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), or between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, the plurality of third power lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, the plurality of third power lines do not exist between column (4k+1) and column (4k) C(4k). Optionally, the plurality of third power lines do not exist between column (4k-4) and column (4k-3) C(4k-3).

[0283] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0284] In some embodiments, a plurality of third power lines are located on the second signal line layer.

[0285] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each third power line Vdd3 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each third power line Vdd3 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0286] Figure 13B It is shown Figure 11A A schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 11A to 11K , Figures 12A to 12E and Figure 13BIn some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a first signal line layer.

[0287] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines. Optionally, each fifth reset signal line Vint5 extends through a via to connect to a second reset signal line, the via extending through at least one of a passivation layer, a second interlayer dielectric layer, or a first interlayer dielectric layer.

[0288] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0289] In some embodiments, a plurality of fifth reset signal lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0290] Figure 13C It is shown Figure 11A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 11A to 11K , Figures 12A to 12E and Figure 13CIn some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a first signal line layer.

[0291] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines. Optionally, each fourth reset signal line Vint4 extends through a via to connect to a first reset signal line, the via extending through at least a passivation layer.

[0292] In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2).

[0293] In some embodiments, refer to Figure 13A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0294] In some embodiments, refer to Figure 12B The array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0295] In some embodiments, refer to Figure 12E The array substrate also includes multiple voltage supply lines. Optionally, each of the multiple voltage supply lines, Vss, extends along a second direction DR2. Optionally, the multiple voltage supply lines are located on a third signal line layer.

[0296] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0297] In some embodiments, multiple voltage supply lines exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, multiple voltage supply lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), and do not exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, multiple voltage supply lines exist between column (4k-3) C(4k-3) and column (4k-4). Optionally, multiple voltage supply lines exist between column (4k) C(4k) and column (4k+1).

[0298] In some embodiments, refer to Figure 12E The array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0299] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2).

[0300] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0301] In some embodiments, each voltage supply line Vss is located between two adjacent data lines.

[0302] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0303] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0304] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0305] In some embodiments, the ratio of the total number of data lines to the total number of voltage supply lines in the array substrate is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0306] Figure 14A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 14B It is shown Figure 14A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 14C It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 14D It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 14E It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0307] Figure 14F It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0308] Figure 14G It is shown Figure 14A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 14H It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0309] Figure 14I It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 14J It is shown Figure 14A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 14K It is shown Figure 14A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 15A It is shown Figure 14A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 15B It is shown Figure 14A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 15C It is shown Figure 14A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 15D It is shown Figure 14A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 15E It is shown Figure 14A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 14A to 14K , Figures 15A to 15E A portion of an array substrate with eight adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The eight adjacent pixel driving circuits are arranged in four columns and two rows.

[0310] Figure 16A It is shown Figure 14A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 14A to 14K , Figures 15A to 15E and Figure 16A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of second power lines, Vdd2, extends along the first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0311] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0312] In some embodiments, the plurality of second power lines and the plurality of third power lines are part of an overall structure. Optionally, the plurality of second power lines and the plurality of third power lines are located on a second signal line layer. Each of the plurality of second power lines, Vdd2, is connected to the plurality of third power lines, and each of the plurality of third power lines, Vdd3, is connected to the plurality of second power lines.

[0313] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each second power line Vdd2 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each second power line Vdd2 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0314] In some embodiments, refer to Figure 16A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), between column (4k-2) C(4k-2) and column (4k-1) C(4k-1), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0315] Figure 16B It is shown Figure 14A A schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 14A to 14K , Figures 15A to 15E and Figure 16B In some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a first signal line layer.

[0316] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines. Optionally, each fifth reset signal line Vint5 extends through a via to connect to a second reset signal line, the via extending through at least one of a passivation layer, a second interlayer dielectric layer, or a first interlayer dielectric layer.

[0317] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0318] In some embodiments, a plurality of fifth reset signal lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0319] Figure 16C It is shown Figure 14A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 14A to 14K , Figures 15A to 15E and Figure 16C In some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a first signal line layer.

[0320] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines. Optionally, each fourth reset signal line Vint4 extends through a via to connect to a first reset signal line, the via extending through at least a passivation layer.

[0321] In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2).

[0322] In some embodiments, refer to Figure 16A Multiple third power lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3), between column (4k-2) C(4k-2) and column (4k-1) C(4k-1), or between column (4k-1) C(4k-1) and column (4k) C(4k).

[0323] In some embodiments, refer to Figure 15B The array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0324] In some embodiments, refer to Figure 15E The array substrate also includes multiple voltage supply lines. Optionally, each of the multiple voltage supply lines, Vss, extends along a second direction DR2. Optionally, the multiple voltage supply lines are located on a third signal line layer.

[0325] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0326] In some embodiments, multiple voltage supply lines exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, multiple voltage supply lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2), and do not exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, multiple voltage supply lines exist between column (4k-3) C(4k-3) and column (4k-4). Optionally, multiple voltage supply lines exist between column (4k) C(4k) and column (4k+1).

[0327] In some embodiments, refer to Figure 15EThe array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0328] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2).

[0329] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0330] In some embodiments, each voltage supply line Vss is located between two adjacent data lines.

[0331] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0332] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0333] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 1.8:1 to 2.2:1, for example, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, or 2.1:1 to 2.2:1.

[0334] In some embodiments, the ratio of the total number of data lines to the total number of voltage supply lines in the array substrate is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0335] Figure 17AThis is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 17B It is shown Figure 17A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 17C It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 17D It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 17E It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0336] Figure 17F It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0337] Figure 17G It is shown Figure 17A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 17H It is shown Figure 17A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0338] Figure 17I It is shown Figure 17A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 17J It is shown Figure 17A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 17K It is shown Figure 17A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 18A It is shown Figure 17A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 18B It is shown Figure 17A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 18CIt is shown Figure 17A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 18D It is shown Figure 17A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 18E It is shown Figure 17A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 17A to 17K , Figures 18A to 18E A portion of an array substrate with sixteen adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, PDC12, PDC13, PDC14, PDC15, and PDC16. The sixteen adjacent pixel driving circuits are arranged in eight columns and two rows.

[0339] Figure 19A It is shown Figure 17A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 17A to 17K , Figures 18A to 18E and Figure 19A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of second power lines, Vdd2, extends along the first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0340] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0341] In some embodiments, the plurality of second power lines and the plurality of third power lines are part of an overall structure. Optionally, the plurality of second power lines and the plurality of third power lines are located on a second signal line layer. Each of the plurality of second power lines, Vdd2, is connected to the plurality of third power lines, and each of the plurality of third power lines, Vdd3, is connected to the plurality of second power lines.

[0342] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each second power line Vdd2 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each second power line Vdd2 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0343] In some embodiments, refer to Figure 19A The array substrate includes multiple pixel driving circuits arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-1)th column C(8j-1), and the (8j)th column C(8j) of the J columns, where J and j are positive integers, and 1≤j≤(J / 8).

[0344] As used herein, the terms "column (8j-7)," "column (8j-6)," "column (8j-5)," "column (8j-4)," "column (8j-3)," "column (8j-2)," "column (8j-1)," and "column (8j)" are used in the context of J columns. The array substrate may or may not include additional columns preceding the first column of the J columns and / or additional columns following the last column of the J columns. In the context of the array substrate, the terms "column (8j-7)," "column (8j-5)," "column (8j-3)," and "column (8j-1)" do not necessarily represent odd-numbered columns, and the terms "column (8j-6)," "column (8j-4)," "column (8j-2)," and "column (8j)" do not necessarily represent even-numbered columns. In one example, column (8j-7) is an odd-numbered column in the context of J columns, but may be an even-numbered column in the context of the array substrate. In another example, column (8j-7) is an odd column against the background of column J, and also an odd column against the background of the array substrate. In one example, column (8j-6) is an even column against the background of column J, but can be an odd column against the background of the array substrate. In another example, column (8j-6) is an even column against the background of column J, and also an even column against the background of the array substrate. In one example, column (8j-5) is an odd column against the background of column J, but can be an even column against the background of the array substrate. In another example, column (8j-5) is an odd column against the background of column J, and also an odd column against the background of the array substrate. In one example, column (8j-4) is an even column against the background of column J, but can be an odd column against the background of the array substrate. In another example, column (8j-4) is an even column against the background of column J, and also an even column against the background of the array substrate. In one example, column (8j-3) is an odd-numbered column against the background of column J, but can be an even-numbered column against the background of the array substrate. In another example, column (8j-3) is an odd-numbered column against the background of column J, and is also an odd-numbered column against the background of the array substrate. In one example, column (8j-2) is an even-numbered column against the background of column J, but can be an odd-numbered column against the background of the array substrate. In another example, column (8j-2) is an even-numbered column against the background of column J, and is also an even-numbered column against the background of the array substrate. In one example, column (8j-1) is an odd-numbered column against the background of column J, but can be an even-numbered column against the background of the array substrate. In another example, column (8j-1) is an odd-numbered column against the background of column J, and is also an odd-numbered column against the background of the array substrate. In one example, column (8j) is an even-numbered column against the background of column J, but can be an odd-numbered column against the background of the array substrate. In another example, column (8j) is an even column against the background of column J, and also an even column against the background of the array substrate.

[0345] In some embodiments, a plurality of third power lines exist between column (8j-1) C(8j-1) and column (8j-2) C(8j-2), between column (8j-3) C(8j-3) and column (8j-4) C(8j-4), or between column (8j-5) C(8j-5) and column (8j-6) C(8j-6). In some embodiments, a plurality of third power lines do not exist between column (8j) C(8j) and column (8j-1) C(8j-1), between column (8j-2) C(8j-2) and column (8j-3) C(8j-3), between column (8j-4) C(8j-4) and column (8j-5) C(8j-5), and between column (8j-6) C(8j-6) and column (8j-7) C(8j-7).

[0346] Figure 19B It is shown Figure 17A A schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 17A to 17K , Figures 18A to 18E and Figure 19B In some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a third signal line layer.

[0347] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines.

[0348] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-1)th column C(8j-1), and the (8j)th column C(8j) of the J columns, where J and j are positive integers, and 1≤j≤(J / 8).

[0349] In some embodiments, a plurality of fifth reset signal lines exist between column (8j-6) C(8j-6) and column (8j-7) C(8j-7). Optionally, multiple fifth reset signal lines are not present between column (8j) C(8j) and column (8j-1) C(8j-1), are not present between column (8j-1) C(8j-1) and column (8j-2) C(8j-2), are not present between column (8j-2) C(8j-2) and column (8j-3) C(8j-3), are not present between column (8j-3) C(8j-3) and column (8j-4) C(8j-4), are not present between column (8j-4) C(8j-4) and column (8j-5) C(8j-5), and are not present between column (8j-5) C(8j-5) and column (8j-6) C(8j-6).

[0350] In some embodiments, the array substrate includes a plurality of first reset signal connection pads ICP1. Optionally, the plurality of first reset signal connection pads ICP1 are located on a first signal line layer. In some embodiments, the array substrate includes a plurality of third reset signal connection pads ICP3. Optionally, the plurality of third reset signal connection pads ICP3 are located on a second signal line layer.

[0351] In some embodiments, each of the plurality of fifth reset signal lines Vint5 is connected to a third reset signal connection pad in a plurality of third reset signal connection pads ICP3; the third reset signal connection pad is connected to a first reset signal connection pad in a plurality of first reset signal connection pads ICP1; and the first reset signal connection pad is connected to a second reset signal line in a plurality of second reset signal lines.

[0352] Figure 19C It is shown Figure 17A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 17A to 17K , Figures 18A to 18E and Figure 19C In some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a third signal line layer.

[0353] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines.

[0354] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-1)th column C(8j-1), and the (8j)th column C(8j) of the J columns, where J and j are positive integers, and 1≤j≤(J / 8).

[0355] In some embodiments, a plurality of fourth reset signal lines exist between column (8j-2) C(8j-2) and column (8j-3) C(8j-3). Optionally, multiple fourth reset signal lines are not present between column (8j) C(8j) and column (8j-1) C(8j-1), are not present between column (8j-1) C(8j-1) and column (8j-2) C(8j-2), are not present between column (8j-3) C(8j-3) and column (8j-4) C(8j-4), are not present between column (8j-4) C(8j-4) and column (8j-5) C(8j-5), are not present between column (8j-5) C(8j-5) and column (8j-6) C(8j-6), and are not present between column (8j-6) C(8j-6) and column (8j-7) C(8j-7).

[0356] In some embodiments, the array substrate includes a plurality of second reset signal connection pads ICP2. Optionally, the plurality of second reset signal connection pads ICP2 are located on a first signal line layer. In some embodiments, the array substrate includes a plurality of fourth reset signal connection pads ICP4. Optionally, the plurality of fourth reset signal connection pads ICP4 are located on a second signal line layer.

[0357] In some embodiments, a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines is connected to a fourth reset signal connection pad among a plurality of fourth reset signal connection pads ICP4; the fourth reset signal connection pad is connected to a second reset signal connection pad among a plurality of second reset signal connection pads ICP2; and the second reset signal connection pad is connected to a first reset signal line among a plurality of first reset signal lines.

[0358] In some embodiments, refer to Figure 18BThe array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0359] Figure 19D It is shown Figure 17A A schematic diagram of the voltage supply network in the array substrate is depicted. (Refer to...) Figures 17A to 17K , Figures 18A to 18E and Figure 19D In some embodiments, the array substrate includes a voltage supply network. In some embodiments, the voltage supply network includes a plurality of first voltage supply lines and a plurality of second voltage supply lines interconnected together. Optionally, each of the plurality of first voltage supply lines, Vss1, extends along a first direction DR1. Optionally, each of the plurality of second voltage supply lines, Vss2, extends along a second direction DR2. Optionally, each of the first voltage supply lines, Vss1, is located on a first signal line layer. Optionally, each of the second voltage supply lines, Vss2, is located on a third signal line layer.

[0360] In some embodiments, each first voltage supply line Vss1 is connected to at least a plurality of second voltage supply lines, and each second voltage supply line Vss2 is connected to at least a plurality of first voltage supply lines.

[0361] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-1)th column C(8j-1), and the (8j)th column C(8j) of the J columns, where J and j are positive integers, and 1≤j≤(J / 8).

[0362] In some embodiments, a plurality of second voltage supply lines exist between column (8j) C(8j) and column (8j-1) C(8j-1), or between column (8j-4) C(8j-4) and column (8j-5) C(8j-5). Optionally, multiple second voltage supply lines do not exist between column (8j-1) C(8j-1) and column (8j-2) C(8j-2), do not exist between column (8j-2) C(8j-2) and column (8j-3) C(8j-3), do not exist between column (8j-3) C(8j-3) and column (8j-4) C(8j-4), do not exist between column (8j-5) C(8j-5) and column (8j-6) C(8j-6), and do not exist between column (8j-6) C(8j-6) and column (8j-7) C(8j-7).

[0363] In some embodiments, the array substrate includes a plurality of signal connection pads (SCPs). Optionally, the plurality of signal connection pads (SCPs) are located on a second signal line layer.

[0364] In some embodiments, each of the plurality of second voltage supply lines Vss2 is connected to a signal connection pad in a plurality of signal connection pads SCP; the signal connection pad is connected to a first voltage supply line in a plurality of first voltage supply lines.

[0365] In some embodiments, refer to Figure 18E The array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0366] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2).

[0367] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0368] In some embodiments, each second voltage supply line Vss2 is located between two adjacent data lines.

[0369] In some embodiments, each fourth reset signal line Vint4 is located between two adjacent data lines.

[0370] In some embodiments, each fifth reset signal line Vint5 is located between two adjacent data lines.

[0371] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 15.0:1 to 17.0:1, for example, 15.0:1 to 15.5:1, 15.5:1 to 16.0:1, 16.0:1 to 16.5:1, or 16.5:1 to 17.0:1.

[0372] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 15.0:1 to 17.0:1, for example, 15.0:1 to 15.5:1, 15.5:1 to 16.0:1, 16.0:1 to 16.5:1, or 16.5:1 to 17.0:1.

[0373] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.5:1 to 4.5:1, for example, 3.5:1 to 3.7:1, 3.7:1 to 3.9:1, 3.9:1 to 4.1:1, 4.1:1 to 4.3:1, or 4.3:1 to 4.5:1.

[0374] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of second voltage supply lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0375] Figure 20A This is a schematic diagram illustrating the arrangement of pixel driving circuitry in an array substrate according to some embodiments of the present disclosure. Figure 20B It is shown Figure 20A The diagram depicts the structure of the light-shielding layer and the first semiconductor material layer in the array substrate. Figure 20C It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, and the first gate metal layer in the array substrate. Figure 20D It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 20E It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the third gate metal layer in the array substrate.

[0376] Figure 20F It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the second semiconductor material layer in the array substrate.

[0377] Figure 20G It is shown Figure 20A The diagram depicts the structure of the light-shielding layer, the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the second semiconductor material layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 20H It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0378] Figure 20I It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, and the second signal line layer in the array substrate. Figure 20J It is shown Figure 20A The diagram depicts the structure of the second gate metal layer, the third gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 20K It is shown Figure 20A The diagram depicts the structure of the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figure 21A It is shown Figure 20A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 21B It is shown Figure 20A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 21C It is shown Figure 20A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 21D It is shown Figure 20A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 21E It is shown Figure 20A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in the figure. Figures 20A to 20K , Figures 21A to 21E A portion of an array substrate with eight adjacent pixel driving circuits is depicted, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The eight adjacent pixel driving circuits are arranged in four columns and two rows.

[0379] Figure 22A It is shown Figure 20A A schematic diagram of the power network in the array substrate is depicted. (Refer to...) Figures 20A to 20K , Figures 21A to 21E and Figure 22A In some embodiments, the array substrate includes a power network. In some embodiments, the power network includes a plurality of first power lines, a plurality of second power lines, and a plurality of third power lines interconnected. Optionally, each of the plurality of first power lines, Vdd1, extends along a first direction DR1. Optionally, each of the plurality of second power lines, Vdd2, extends along the first direction DR1. Optionally, each of the plurality of third power lines, Vdd3, extends along a second direction DR2.

[0380] In some embodiments, each first power line Vdd1 includes a second capacitor electrode of a storage capacitor in a row pixel driving circuit. Optionally, each first power line Vdd1 is located in a second gate metal layer.

[0381] In some embodiments, the plurality of second power lines and the plurality of third power lines are part of an overall structure. Optionally, the plurality of second power lines and the plurality of third power lines are located on a second signal line layer. Each of the plurality of second power lines, Vdd2, is connected to the plurality of third power lines, and each of the plurality of third power lines, Vdd3, is connected to the plurality of second power lines.

[0382] In some embodiments, the array substrate further includes a plurality of voltage connection pads VCP. Each second power line Vdd2 is connected to a corresponding voltage connection pad among the plurality of voltage connection pads VCP in the pixel driving circuit, and the corresponding voltage connection pad in the pixel driving circuit is connected to a first power line among a plurality of first power lines. Optionally, the corresponding voltage connection pad in the pixel driving circuit is connected to a second capacitor electrode in the pixel driving circuit. Optionally, each second power line Vdd2 is located in a second signal line layer, each voltage connection pad is located in a first signal line layer, and the plurality of first power lines are located in a second gate metal layer.

[0383] In some embodiments, refer to Figure 22A Multiple third power lines exist between column (4k-1) C(4k-1) and column (4k-2) C(4k-2). In some embodiments, multiple third power lines do not exist between column (4k) C(4k) and column (4k-1) C(4k-1), and do not exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, multiple third power lines exist between column (4k) C(4k) and column (4k+1), or between column (4k-3) C(4k-3) and column (4k-4).

[0384] Figure 22B It is shown Figure 20AA schematic diagram of the first reset signal network in the array substrate depicted in the image. (Refer to...) Figures 20A to 20K , Figures 21A to 21E as well as Figure 22B In some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together. Optionally, each of the plurality of second reset signal lines, Vint2, extends along a first direction DR1. Optionally, each of the plurality of fifth reset signal lines, Vint5, extends along a second direction DR2. Optionally, each of the second reset signal lines, Vint2, is located in a second gate metal layer. Optionally, each of the fifth reset signal lines, Vint5, is located in a third signal line layer.

[0385] In some embodiments, each second reset signal line Vint2 is connected to at least a plurality of fifth reset signal lines, and each fifth reset signal line Vint5 is connected to at least a plurality of second reset signal lines. Optionally, each fifth reset signal line Vint5 extends through a via to connect to a second reset signal line, the via extending through at least one of a second planarization layer, a first planarization layer, a passivation layer, a second interlayer dielectric layer, or a first interlayer dielectric layer.

[0386] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0387] In some embodiments, a plurality of fifth reset signal lines exist between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fifth reset signal lines do not exist between column (4k-1) C(4k-1) and column (4k) C(4k).

[0388] In some embodiments, the array substrate includes a plurality of first reset signal connection pads ICP1. Optionally, the plurality of first reset signal connection pads ICP1 are located on a first signal line layer. In some embodiments, the array substrate includes a plurality of third reset signal connection pads ICP3. Optionally, the plurality of third reset signal connection pads ICP3 are located on a second signal line layer.

[0389] In some embodiments, each of the plurality of fifth reset signal lines Vint5 is connected to a third reset signal connection pad in a plurality of third reset signal connection pads ICP3; the third reset signal connection pad is connected to a first reset signal connection pad in a plurality of first reset signal connection pads ICP1; and the first reset signal connection pad is connected to a second reset signal line in a plurality of second reset signal lines.

[0390] Figure 22C It is shown Figure 20A A schematic diagram of the second reset signal network in the array substrate depicted in the image. (Refer to...) Figures 20A to 20K , Figures 21A to 21E and Figure 22C In some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of first reset signal lines, a plurality of fourth reset signal lines, and a plurality of voltage supply lines interconnected. Optionally, each of the plurality of first reset signal lines, Vint1, extends along a first direction DR1. Optionally, each of the plurality of voltage supply lines, Vss, extends along the first direction DR1. Optionally, each of the plurality of fourth reset signal lines, Vint4, extends along a second direction DR2. Optionally, each of the first reset signal lines, Vint1, is located in a third gate metal layer. Optionally, each of the voltage supply lines, Vss, is located in a first signal line layer. Optionally, each of the fourth reset signal lines, Vint4, is located in a third signal line layer.

[0391] In some embodiments, each first reset signal line Vint1 is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of first reset signal lines. In some embodiments, each voltage supply line Vss is connected to at least a plurality of fourth reset signal lines, and each fourth reset signal line Vint4 is connected to at least a plurality of voltage supply lines. Optionally, each fourth reset signal line Vint4 extends through a via to connect to a voltage supply line, the via extending through at least a second planarization layer or a first planarization layer.

[0392] exist Figure 22C In the second reset signal network depicted, multiple voltage supply lines and reset signal lines are interconnected. The second reset signal network is configured to provide voltage supply signals to the cathodes of multiple light-emitting elements and reset signals to the first reset transistors of multiple pixel driving circuits. Figures 20A to 20K , Figures 21A to 21E and Figure 22CIn the array substrate depicted, the voltage supply signal provided to the cathodes of multiple light-emitting elements and the reset signal provided to the first reset transistors of multiple pixel driving circuits are the same signal. Multiple first reset signal lines, multiple fourth reset signal lines, and multiple voltage supply lines are configured to provide the same signal. In this sense, the multiple first reset signal lines and the multiple fourth reset signal lines can be considered as voltage supply lines.

[0393] In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k) C(4k). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-2) C(4k-2) and column (4k-1) C(4k-1). Optionally, a plurality of fourth reset signal lines do not exist between column (4k-3) C(4k-3) and column (4k-2) C(4k-2).

[0394] In some embodiments, the array substrate includes a plurality of second reset signal connection pads ICP2. Optionally, the plurality of second reset signal connection pads ICP2 are located on a first signal line layer. In some embodiments, the array substrate includes a plurality of fourth reset signal connection pads ICP4. Optionally, the plurality of fourth reset signal connection pads ICP4 are located on a second signal line layer.

[0395] In some embodiments, each of the plurality of fourth reset signal lines Vint4 is connected to the fourth reset signal connection pad in the plurality of fourth reset signal connection pads ICP4; the fourth reset signal connection pad is connected to the second reset signal connection pad in the plurality of second reset signal connection pads ICP2; and the second reset signal connection pad is connected to the first reset signal line in the plurality of first reset signal lines.

[0396] In some embodiments, refer to Figure 21B The array substrate also includes a plurality of third reset signal lines. Each of the plurality of third reset signal lines extends along a first direction DR1.

[0397] In some embodiments, refer to Figure 21E The array substrate includes multiple data lines DL. In some embodiments, the array substrate includes two adjacent data lines located between two adjacent columns of pixel driving circuits in K columns.

[0398] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​rows, the M rows including the (2m-1)th row R(2m-1) and the (2m)th row R(2m), where M and m are positive integers, 1≤m≤(M / 2).

[0399] In some embodiments, a first adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m-1) R(2m-1), and a second adjacent data line among two adjacent data lines between two adjacent pixel driving circuits in K columns is configured to provide a data signal to row (2m) R(2m).

[0400] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fifth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0401] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of fourth reset signal lines is in the range of 7.5:1 to 8.5:1, for example, 7.5:1 to 7.7:1, 7.7:1 to 7.9:1, 7.9:1 to 8.1:1, 8.1:1 to 8.3:1, or 8.3:1 to 8.5:1.

[0402] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of the plurality of third power lines is in the range of 3.6:1 to 4.4:1, for example, 3.6:1 to 3.8:1, 3.8:1 to 4.0:1, 4.0:1 to 4.2:1, or 4.2:1 to 4.4:1.

[0403] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0404] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel driving circuits; forming a plurality of light-emitting elements; forming a plurality of data lines configured to provide data signals to the plurality of pixel driving circuits; and forming a plurality of voltage supply lines extending in a display area of ​​the array substrate and configured to provide voltage supply signals to the cathodes of the plurality of light-emitting elements. Optionally, the layer containing the plurality of voltage supply lines is located on the side of the plurality of data lines close to the active layer of the plurality of pixel driving circuits, or the plurality of voltage supply lines and the plurality of data lines are located on the same layer.

[0405] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms 'the invention, the present invention,' etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of 'first,' 'second,' etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: a plurality of pixel driving circuits; a plurality of light emitting elements; a plurality of data lines configured to provide data signals to the plurality of pixel driving circuits; and a plurality of voltage supply lines extending in a display area of the array substrate and configured to provide voltage supply signals to cathodes of the plurality of light emitting elements; wherein a layer in which the plurality of voltage supply lines are located is located on a side of an active layer of the plurality of data lines close to the plurality of pixel driving circuits, or the plurality of voltage supply lines are located in a same layer as the plurality of data lines. 2.The array substrate of claim 1, comprising a second signal line layer; the second signal line layer comprises a plurality of third power supply signal lines configured to provide power supply signals, the power supply signals being the same as signals provided to light emitting control transistors of the plurality of pixel driving circuits; wherein the plurality of voltage supply lines are located in a same layer as the plurality of third power supply signal lines; and the plurality of voltage supply lines, the plurality of third power supply signal lines, and the plurality of data lines extend in a second direction. the plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns comprise a (4k-3)th column in the K columns, a (4k-2)th column in the K columns, a (4k-1)th column in the K columns, and a 4kth column in the K columns, k being a positive integer, 1≤k≤(K / 4); the plurality of third power supply signal lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the 4kth column, and do not exist between the (4k-2)th column and the (4k-1)th column; and 3. The array substrate according to claim 2, wherein, the plurality of voltage supply lines exist between the (4k-2)th column and the (4k-1)th column, do not exist between the (4k-3)th column and the (4k-2)th column, and do not exist between the (4k-1)th column and the 4kth column. 4.The array substrate of claim 2, further comprising a power supply network; the power supply network comprises a plurality of first power supply lines and a plurality of third power supply lines interconnected together; each of the plurality of first power supply lines extends in a first direction; wherein each of the plurality of third power supply lines extends in the second direction; the plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns comprise a (4k-3)th column in the K columns, a (4k-2)th column in the K columns, a (4k-1)th column in the K columns, and a 4kth column in the K columns, k being a positive integer, 1≤k≤(K / 4); and the plurality of third power supply signal lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the 4kth column, and do not exist between the (4k-2)th column and the (4k-1)th column. 5.The array substrate of claim 2, further comprising a first reset signal network. ​ ​ wherein, the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends in a first direction; each of the plurality of fifth reset signal lines extends in the second direction; the plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns include a (4k-3)th column among the K columns, a (4k-2)th column among the K columns, a (4k-1)th column among the K columns, and a 4kth column among the K columns, k being a positive integer, 1≤k≤(K / 4); and the plurality of fifth reset signal lines exist between the (4k-2)th column and the (4k-3)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-1)th column and the (4k)th column.

6. The array substrate of claim 2, further comprising a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends in a first direction; each of the plurality of fourth reset signal lines extends in the second direction; the plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns include a (4k-3)th column among the K columns, a (4k-2)th column among the K columns, a (4k-1)th column among the K columns, and a 4kth column among the K columns, k being a positive integer, 1≤k≤(K / 4); and the plurality of fourth reset signal lines exist between the (4k-1)th column and the (4k)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-3)th column and the (4k-2)th column.

7. The array substrate of claim 2, wherein, a ratio of a total number of data lines in the array substrate to a total number of the plurality of fifth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of the plurality of fourth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of the plurality of third power supply lines is in a range of 3.5:1 to 4.5:1; and a ratio of a total number of data lines in the array substrate to a total number of the plurality of voltage supply lines is in a range of 3.5:1 to 4.5:

1.

8. The array substrate of claim 1, comprising a third signal line layer; the third signal line layer includes the plurality of data lines and the plurality of voltage supply lines; wherein the plurality of data lines and the plurality of voltage supply lines extend in a second direction; and the plurality of data lines and the plurality of voltage supply lines extend in a second direction. the plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns include an (4k-3)th column among the K columns, an (4k-2)th column among the K columns, an (4k-1)th column among the K columns, and a 4kth column among the K columns, k being a positive integer, 1≤k≤(K / 4); the plurality of pixel driving circuits are arranged in M rows, the M rows including an (2m-1)th row R(2m-1) and an (2m)th row R(2m) among the M rows, M and m being positive integers, 1≤m≤(M / 2); the plurality of voltage supply lines exist between the (4k-2)th column and the (4k-1)th column, do not exist between the (4k-3)th column and the (4k-2)th column, and do not exist between the (4k-1)th column and the (4k)th column; two adjacent data lines among the plurality of data lines are located between adjacent two column pixel driving circuits among the K columns; a first adjacent data line among the two adjacent data lines between the adjacent two column pixel driving circuits among the K columns is configured to provide a data signal to the (2m-1)th row; and a second adjacent data line among the two adjacent data lines between the adjacent two column pixel driving circuits among the K columns is configured to provide a data signal to the (2m)th row.

9. The array substrate of claim 8, further comprising a power supply network; wherein the power supply network comprises a plurality of first power supply lines and a plurality of third power supply lines interconnected together; each first power supply line among the plurality of first power supply lines extends along a first direction; each third power supply line among the plurality of third power supply lines extends along the second direction; the plurality of third power supply lines exist between the (4k-3)th column and the (4k-2)th column, or exist between the (4k-1)th column and the (4k)th column; and the plurality of third power supply lines do not exist between the (4k-2)th column and the (4k-1)th column, do not exist between a (4k+1)th column and the (4k)th column, and do not exist between a (4k-4)th column and the (4k-3)th column.

10. The array substrate of claim 8, further comprising a power supply network; wherein, the power supply network comprises a plurality of first power supply lines, a plurality of second power supply lines, and a plurality of third power supply lines interconnected together; each first power supply line among the plurality of first power supply lines extends along a first direction; each second power supply line among the plurality of second power supply lines extends along the first direction; each third power supply line among the plurality of third power supply lines extends along the second direction; and the plurality of third power supply lines exist between the (4k-2)th column and the (4k-3)th column, between the (4k-2)th column and the (4k-1)th column, or between the (4k-1)th column and the (4k)th column.

11. The array substrate of claim 8, further comprising a first reset signal network; wherein the first reset signal network includes a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; each of the plurality of second reset signal lines extends in a first direction; each of the plurality of fifth reset signal lines extends in the second direction; and the plurality of fifth reset signal lines is present between the (4k-2)th column and the (4k-3)th column, is not present between the (4k-2)th column and the (4k-1)th column, and is not present between the (4k-1)th column and the (4k)th column.

12. The array substrate of claim 8, further comprising a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends in a first direction; each of the plurality of fourth reset signal lines extends in the second direction; the plurality of fourth reset signal lines is present between the (4k-1)th column and the (4k)th column, is not present between the (4k-2)th column and the (4k-1)th column, and is not present between the (4k-3)th column and the (4k-2)th column.

13. The array substrate of claim 8, wherein, a ratio of a total number of data lines in the array substrate to a total number of fifth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of fourth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of third power supply lines is in a range of 3.5:1 to 4.5:1; and a ratio of a total number of data lines in the array substrate to a total number of the plurality of voltage supply lines is in a range of 3.5:1 to 4.5:

1.

14. The array substrate of claim 8, wherein, a ratio of a total number of data lines in the array substrate to a total number of fifth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of fourth reset signal lines is in a range of 7.5:1 to 8.5:1; a ratio of a total number of data lines in the array substrate to a total number of third power supply lines is in a range of 1.8:1 to 2.2:1; and a ratio of a total number of data lines in the array substrate to a total number of the plurality of voltage supply lines is in a range of 3.5:1 to 4.5:

1.

15. The array substrate of claim 1, wherein, the plurality of voltage supply lines includes a plurality of first voltage supply lines and a plurality of second voltage supply lines interconnected together; each of the plurality of first voltage supply lines extends in a first direction; each of the plurality of second voltage supply lines extends in a second direction; The plurality of pixel driving circuits are arranged in J columns, J being a positive integer; the J columns include an (8j-7)th column C(8j-7) among the J columns, an (8j-6)th column C(8j-6) among the J columns, an (8j-5)th column C(8j-5) among the J columns, an (8j-4)th column C(8j-4) among the J columns, an (8j-3)th column C(8j-3) among the J columns, an (8j-2)th column C(8j-2) among the J columns, an (8j-1)th column C(8j-1) among the J columns, and an (8j)th column C(8j) among the J columns, J and j being positive integers, 1≤j≤(J / 8); The plurality of second voltage supply lines exist between the (8j)th column and the (8j-1)th column, or exist between the (8j-4)th column and the (8j-5)th column; and The plurality of second voltage supply lines do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-2)th column C(8j-2) and the (8j-3)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-5)th column and the (8j-6)th column, and do not exist between the (8j-6)th column and the (8j-7)th column.

16. The array substrate of claim 15, further comprising a power supply network; wherein The power supply network comprises a plurality of first power supply lines, a plurality of second power supply lines, and a plurality of third power supply lines interconnected together; Each first power supply line among the plurality of first power supply lines extends along the first direction; Each second power supply line among the plurality of second power supply lines extends along the first direction; Each third power supply line among the plurality of third power supply lines extends along the second direction; The plurality of third power supply lines exist between the (8j-1)th column and the (8j-2)th column, between the (8j-3)th column and the (8j-4)th column, or between the (8j-5)th column and the (8j-6)th column; and The plurality of third power supply lines do not exist between the (8j)th column and the (8j-1)th column, between the (8j-2)th column and the (8j-3)th column, between the (8j-4)th column and the (8j-5)th column, and between the (8j-6)th column and the (8j-7)th column.

17. The array substrate of claim 15, further comprising a first reset signal network; wherein, The first reset signal network comprises a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; Each second reset signal line among the plurality of second reset signal lines extends along the first direction; Each fifth reset signal line among the plurality of fifth reset signal lines extends along the second direction; and The plurality of fifth reset signal lines exist between the (8j-6)th column and the (8j-7)th column, do not exist between the (8j)th column and the (8j-1)th column, do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-2)th column and the (8j-3)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-4)th column and the (8j-5)th column, and do not exist between the (8j-5)th column and the (8j-6)th column.

18. The array substrate of claim 15, further comprising a second reset signal network; wherein the second reset signal network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; each of the plurality of first reset signal lines extends in the first direction; each of the plurality of fourth reset signal lines extends in the second direction; and the plurality of fourth reset signal lines exist between the (8j-2)th column and the (8j-3)th column, do not exist between the (8j)th column and the (8j-1)th column, do not exist between the (8j-1)th column and the (8j-2)th column, do not exist between the (8j-3)th column and the (8j-4)th column, do not exist between the (8j-4)th column and the (8j-5)th column, do not exist between the (8j-5)th column and the (8j-6)th column, and do not exist between the (8j-6)th column and the (8j-7)th column.

19. The array substrate of claim 15, wherein, a ratio of a total number of data lines in the array substrate to a total number of the plurality of fifth reset signal lines is in a range of 15.0:1 to 17.0:1; a ratio of a total number of data lines in the array substrate to a total number of the plurality of fourth reset signal lines is in a range of 15.0:1 to 17.0:1; a ratio of a total number of data lines in the array substrate to a total number of the plurality of third power supply lines is in a range of 3.5:1 to 4.5:1; and a ratio of a total number of data lines in the array substrate to a total number of the plurality of second voltage supply lines is in a range of 7.5:1 to 8.5:

1.

20. The array substrate of claim 1, further comprising a plurality of first power supply lines and a plurality of fourth reset signal lines; wherein, the plurality of first reset signal lines, the plurality of fourth reset signal lines, and the plurality of voltage supply lines are interconnected together; each of the plurality of first reset signal lines extends in a first direction; each of the plurality of voltage supply lines extends in the first direction; each of the plurality of fourth reset signal lines extends in a second direction; The plurality of pixel driving circuits are arranged in K columns, K being a positive integer; the K columns include a (4k-3)th column among the K columns, a (4k-2)th column among the K columns, a (4k-1)th column among the K columns, and a 4kth column among the K columns, k being a positive integer, 1≤k≤(K / 4); The plurality of fourth reset signal lines exist between the (4k-1)th column and the 4kth column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-3)th column and the (4k-2)th column; Each first reset signal line is connected to at least a plurality of fourth reset signal lines; Each fourth reset signal line is connected to at least a plurality of first reset signal lines; The plurality of first reset signal lines, the plurality of fourth reset signal lines, and the plurality of voltage supply lines are configured to provide a voltage supply signal to cathodes of the plurality of light emitting elements, and to provide a reset signal to first reset transistors of the plurality of pixel driving circuits; and The voltage supply signal provided to the cathodes of the plurality of light emitting elements and the reset signal provided to the first reset transistors of the plurality of pixel driving circuits are the same signal.

21. The array substrate of claim 20, further comprising a power supply network; wherein The power supply network comprises a plurality of first power supply lines, a plurality of second power supply lines, and a plurality of third power supply lines interconnected together; Each first power supply line among the plurality of first power supply lines extends along the first direction; Each second power supply line among the plurality of second power supply lines extends along the first direction; Each third power supply line among the plurality of third power supply lines extends along the second direction; and The plurality of third power supply lines exist between the (4k-1)th column and the (4k-2)th column, do not exist between the 4kth column and the (4k-1)th column, and do not exist between the (4k-2)th column and the (4k-3)th column.

22. The array substrate of claim 20, further comprising a first reset signal network; wherein The first reset signal network comprises a plurality of second reset signal lines and a plurality of fifth reset signal lines interconnected together; Each second reset signal line among the plurality of second reset signal lines extends along the first direction; Each fifth reset signal line among the plurality of fifth reset signal lines extends along the second direction; and The plurality of fifth reset signal lines exist between the (4k-2)th column and the (4k-3)th column, do not exist between the (4k-2)th column and the (4k-1)th column, and do not exist between the (4k-1)th column and the 4kth column.

23. The array substrate of claim 20, wherein, A ratio of a total number of data lines in the array substrate to a total number of fifth reset signal lines is in a range of 7.5:1 to 8.5:1; A ratio of a total number of data lines in the array substrate to a total number of fourth reset signal lines is in a range of 7.5:1 to 8.5:1; and A ratio of a total number of the data lines to a total number of the plurality of third power supply lines in the array substrate is in a range of 3.6:1 to 4.4:

1.

24. A display device comprising the array substrate according to any one of claims 1 to 23, and one or more integrated circuits connected to the array substrate.

Images