Test circuit, chip, test method, electronic equipment and medium

Abstract

The invention discloses a chip performance test circuit, a chip, a test method, electronic equipment and a medium. The test circuit comprises a control switch unit; and a plurality of cascaded delay units, the plurality of delay units are coupled with the control switch unit, each of the plurality of delay units comprises a plurality of first delay subunits which are connected in parallel and a plurality of second delay subunits which are connected in series, the control ends of the plurality of first delay subunits and the control ends of the plurality of second delay subunits are coupled to an input node, and the control ends of the plurality of first delay subunits and the control ends of the plurality of second delay subunits are coupled to an output node. The first ends of the plurality of first delay subunits and the first ends of the plurality of second delay subunits are coupled to the output node, for each delay unit located at the middle stage in the plurality of delay units, the input node is coupled with the output node of the delay unit at the upper stage, and the output node is coupled with the input node of the delay unit at the lower stage. The test circuit can distinguish the types of the process corners to which different types of devices in the chip belong under the condition of representing the real working state of the circuit in the chip.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a chip performance testing circuit, chip, and testing method. Background Technology

[0002] Chip manufacturing is a physical process subject to process variations (including doping concentration, diffusion depth, etching degree, etc.), resulting in differences between different batches, between different wafers within the same batch, and between different chips on the same wafer. This leads to significant variations in the parameters of semiconductor devices. Typically, device performance must be maintained within a certain range, which is given in the form of "process corners." Summary of the Invention

[0003] Currently, testing of devices within a chip makes it difficult to distinguish the process corner type of different types of devices within the chip, while still representing the actual operating state of the circuitry within the chip.

[0004] At least one embodiment of this disclosure provides a chip performance testing circuit, including: a control switch unit; and a plurality of cascaded delay units, wherein the plurality of delay units are coupled to the control switch unit, wherein each of the plurality of delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series, the plurality of first delay sub-units being of a first type and the plurality of second delay sub-units being of a second type, the first type and the second type having opposite activation methods, wherein the control terminals of the plurality of first delay sub-units and the plurality of second delay sub-units are coupled to an input node, the first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to an output node, and for each of the plurality of delay units located in an intermediate stage, the input node is coupled to the output node of the previous stage delay unit, and the output node is coupled to the input node of the next stage delay unit.

[0005] At least one embodiment of this disclosure provides a chip including a first test circuit, wherein the first test circuit includes: a first control switch unit; and a plurality of cascaded first delay units, wherein the plurality of first delay units are coupled to the first control switch unit, wherein each of the plurality of first delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series, the plurality of first delay sub-units being of a first type and the plurality of second delay sub-units being of a second type, the first type and the second type having opposite activation methods, wherein the control terminals of the plurality of first delay sub-units and the control terminals of the plurality of second delay sub-units are coupled to an input node, the first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to an output node, for each of the plurality of first delay units located in an intermediate level, the input node is coupled to the output node of the previous level first delay unit, and the output node is coupled to the input node of the next level first delay unit.

[0006] At least one embodiment of this disclosure provides a method for testing chip performance, applied to a test circuit provided in any embodiment of this disclosure. The method includes: providing an enable signal to a control switch unit, the control switch unit responding to the enable signal by providing a control signal to a plurality of delay units; acquiring output signals output by the plurality of delay units in response to the control signals; and obtaining test results of the chip performance based on the output signals.

[0007] At least one embodiment of this disclosure provides a chip performance testing method, applied to a chip provided in any embodiment of this disclosure. The method includes: providing enable signals to a first control switch unit and a second control switch unit respectively; the first control switch unit responding to the enable signal providing a control signal to a plurality of first delay units; the second control switch unit responding to the enable signal providing the control signal to a plurality of second delay units; acquiring a first output signal output by a plurality of first delay units in the first test circuit in response to the control signal and a second output signal output by a plurality of second delay units in the second test circuit in response to the control signal; and obtaining a test result of the chip performance based on the first output signal and the second output signal.

[0008] At least one embodiment of this disclosure provides an electronic device, including: a processor; a memory including one or more computer program instructions; wherein the one or more computer program instructions are stored in the memory and, when executed by the processor, implement the test method provided in any embodiment of this disclosure.

[0009] At least one embodiment of this disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, they implement the test method provided in any embodiment of this disclosure. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same reference numerals denote the same elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0011] Figure 1A A schematic diagram of a process angle is shown;

[0012] Figure 1B A circuit diagram of a ring oscillator is shown;

[0013] Figure 1C It shows Figure 1B The timing diagram of the ring oscillator shown is as follows;

[0014] Figure 2 A schematic diagram of a chip performance testing circuit provided in at least one embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic diagram of the circuit structure of a delay unit provided in at least one embodiment of the present disclosure is shown;

[0016] Figure 4 A schematic diagram of the circuit structure of another delay unit provided in at least one embodiment of the present disclosure is shown;

[0017] Figure 5 A schematic diagram of a chip provided in at least one embodiment of the present disclosure is shown;

[0018] Figure 6 A flowchart illustrating a chip performance testing method provided in at least one embodiment of this disclosure is shown;

[0019] Figure 7 A flowchart illustrating another chip performance testing method provided in at least one embodiment of this disclosure is shown;

[0020] Figure 8 A schematic block diagram of an electronic device provided for some embodiments of this disclosure;

[0021] Figure 9 A schematic block diagram of another electronic device provided for some embodiments of this disclosure; and

[0022] Figure 10 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. Detailed Implementation

[0023] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0024] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0025] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0026] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0027] It should be noted that the terms "one" and "more" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0028] Process corners refer to the rectangular area defined by four corners that restrict the speed fluctuations of NMOS and PMOS transistors. These four corners are: fast NFET and fast PFET (FF), slow NFET and slow PFET (SS), fast NFET and slow PFET (FS), and slow NFET and fast PFET (SF). NFET refers to an N-type field-effect transistor (e.g., an NMOS transistor), and PFET refers to a P-type field-effect transistor (e.g., a PMOS transistor). F-type indicates that the drive current is at its maximum value, while S-type indicates that the drive current is at its minimum value (Ids current). This can also be understood as F being faster and S being slower. For example, fast NFET and fast PFET are FF type, slow NFET and slow PFET are SS type, fast NFET and slow PFET are FS type, and slow NFET and fast PFET are SF type.

[0029] Figure 1A A schematic diagram of a process angle is shown.

[0030] like Figure 1A As shown, the process corner refers to the range of transistor speed fluctuation within the rectangle 100 defined by the rectangle. The four corners of rectangle 100 are FS, FF, SS, and SF. FS is the top-left vertex of rectangle 100, where NMOS is the fastest and PMOS is the slowest. Similarly, FF is when both NMOS and PMOS speeds are at their maximum values, SS is when both NMOS and PMOS speeds are at their minimum values, and SF is when NMOS speed is at its minimum and PMOS speed is at its maximum value. Here, speed refers, for example, the speed at which the transistor turns from on to off or from off to on, or the transistor's conduction speed.

[0031] During chip manufacturing, the speed fluctuation range of transistors in the chip should be limited to the range defined by rectangle 100.

[0032] Ring oscillator circuits are generally used to detect the aforementioned process changes during wafer fabrication. They typically employ a complementary metal-oxide-semiconductor (CMOS) logic architecture.

[0033] Figure 1B A circuit diagram of a ring oscillator 10 is shown; Figure 1C It shows Figure 1B The timing diagram of the ring oscillator is shown.

[0034] like Figure 1B As shown, the circuit of the ring oscillator 10 includes multiple inverters 11. Each inverter 11 includes a PMOS transistor and an NMOS transistor. The inverter 11 formed by the PMOS transistor and the NMOS transistor inverts the signal.

[0035] Assuming the delay of the NMOS transistor is Tdn, the delay of the PMOS transistor is Tdp, and the number of inverter stages is N, then the period of the output signal OUT is Td = (Tdn + Tdp) * N, as shown in Figure C. By measuring Td and comparing the simulation results, we can determine whether the device's manufacturing process falls within the process corners. The simulation results may include, for example, the four corners FS, FF, SS, and SF, and may also include the center TT of rectangle 100, where TT represents the average value of the PMOS process range and the average value of the NMOS process range. For example, the period of the output signal OUT can be compared with the threshold range Td. If the period of the output signal is greater than the upper limit of the threshold range, the MOSFET is determined to be in a slow NMOS / slow PMOS process corner, indicating that the MOSFET has a thicker gate oxide layer and a higher threshold voltage. If the period of the output signal OUT is less than the lower limit of the threshold range Td, the MOSFET is determined to be in a fast NMOS / fast PMOS process corner, indicating that the MOSFET has a thinner gate oxide layer and a lower threshold voltage. If the period Td of the output signal OUT falls within the threshold range, the MOSFET is determined to be in a standard NMOS / standard PMOS process corner, indicating that the MOSFET's gate oxide layer and threshold voltage are both moderate.

[0036] Figure 1B The ring oscillator shown contains both NMOS and PMOS, so it is not possible to independently distinguish the process variations of NMOS or PMOS during manufacturing (such as the difference between SF and FS process angles).

[0037] In other technologies, only NMOS or PMOS transistors are used as delay modules, followed by an output sense amplifier (SA). The SA is used to detect and amplify the data in the memory cell. Since the signals on the data bit lines are typically very weak, the SA is needed to sense and amplify these signals for correct data reading. This is because NMOS and PMOS transistors have threshold voltage drops when transmitting data 1 and 0, respectively, causing their oscillations to deviate from the full-swing voltage of normal digital circuits (e.g., the normal operating voltage is 0V–1V, but the circuit can only oscillate in the range of 0.3V–0.7V). Therefore, an amplifier is needed to convert the output to a full swing. This oscillation pattern does not represent the true operating state of the circuit, and when testing NMOS or PMOS transistors with higher threshold voltages, the large threshold voltage drop, low signal swing, and significant impact of process variations on the SA amplifier's function may render it inoperable.

[0038] Some embodiments of this disclosure provide a chip performance testing circuit, including: a control switch unit; and a plurality of cascaded delay units coupled to the control switch unit. Each of the plurality of delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series. The plurality of first delay sub-units are of a first type, and the plurality of second delay sub-units are of a second type, with the first type and the second type having opposite activation methods. The control terminals of the plurality of first delay sub-units and the plurality of second delay sub-units are coupled to an input node. The first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to an output node. For each delay unit located in an intermediate stage of the plurality of delay units, the input node is coupled to the output node of the previous stage delay unit, and the output node is coupled to the input node of the next stage delay unit. This testing circuit can distinguish the process corner type of different types of devices in a chip, representing the actual operating state of the circuits in the chip.

[0039] Some embodiments of this disclosure provide a chip including a first test circuit. The first test circuit includes: a first control switch unit; and a plurality of cascaded first delay units coupled to the first control switch unit. Each of the plurality of first delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series. The plurality of first delay sub-units are of a first type, and the plurality of second delay sub-units are of a second type, with the first type and the second type having opposite activation methods. The control terminals of the plurality of first delay sub-units and the plurality of second delay sub-units are coupled to an input node. The first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to an output node. For each of the plurality of first delay units located in an intermediate stage, the input node is coupled to the output node of the previous stage first delay unit, and the output node is coupled to the input node of the next stage first delay unit. This chip enables the differentiation of the process corner type of different types of devices in the chip under actual operating conditions.

[0040] Some embodiments of this disclosure provide a method for testing chip performance, applied to the test circuit provided in any embodiment of this disclosure. The method includes: providing an enable signal to the control switch unit, the control switch unit responding to the enable signal by providing a control signal to the plurality of delay units; acquiring output signals output by the plurality of delay units in response to the control signals; and obtaining a test result of the chip performance based on the output signals. This method can distinguish the process corner type to which different types of devices in the chip belong, representing the chip's actual operating state.

[0041] Some embodiments of this disclosure provide a chip performance testing method, applied to the test circuit provided in any embodiment of this disclosure. The testing method includes: providing enable signals to a first control switch unit and a second control switch unit respectively; the first control switch unit responding to the enable signal providing a control signal to a plurality of first delay units; the second control switch unit responding to the enable signal providing the control signal to a plurality of second delay units; acquiring a first output signal output by the plurality of first delay units in the first test circuit in response to the control signal and a second output signal output by the plurality of second delay units in the second test circuit in response to the control signal; and obtaining a test result of the chip performance based on the first output signal and the second output signal. This testing method can distinguish the process corner type to which different types of devices in the chip belong, representing the actual operating state of the chip.

[0042] Figure 2 A schematic diagram of a chip performance testing circuit provided in at least one embodiment of the present disclosure is shown.

[0043] like Figure 2 As shown, the test circuit 200 includes a control switch unit 201 and multiple cascaded delay units 202. The multiple delay units 202 are coupled to the control switch unit 201.

[0044] Figure 3 A schematic diagram of the circuit structure of a delay unit provided in at least one embodiment of the present disclosure is shown.

[0045] The circuit structure of each delay unit in the multiple delay units 202 can be... Figure 3 The circuit structure shown is shown.

[0046] like Figure 3 As shown, the delay unit 202 includes multiple first delay sub-units 101 connected in parallel and multiple second delay sub-units 102 connected in series. The multiple first delay sub-units are of a first type, and the multiple second delay sub-units are of a second type, with the activation methods of the first type and the second type being opposite. For example, in Figure 3 In the example, each of the multiple first delay sub-units is a PMOS transistor, and each of the multiple second delay sub-units is an NMOS transistor.

[0047] The control terminals of multiple first delay sub-units 101 and multiple second delay sub-units 102 are coupled to the input node P1, and the first terminals of the multiple first delay sub-units 101 and multiple second delay sub-units 102 are coupled to the output node P2. For example, the control terminal of each of the multiple delay sub-units 101 is the gate of a transistor, and the first terminal of each first delay sub-unit is the drain or source of a transistor.

[0048] In some embodiments of this disclosure, multiple first delay sub-units 101 include multiple first transistors, and multiple second delay sub-units 102 include multiple second transistors, with the first and second transistors having opposite transistor types. The gate of each of the multiple first transistors and the gate of each of the multiple second transistors are coupled to an input node P1, and the first electrode of each of the multiple first transistors and the first electrode of a first target transistor T1 among the multiple second transistors are coupled to an output node P2. For example, the first target transistor is the transistor among the multiple second transistors closest to the multiple first transistors, and the first electrode of the first target transistor is coupled to the first electrodes of the multiple first transistors. The first electrode of a second transistor other than the first target transistor is coupled to the first electrode of another second transistor. The second electrode of each of the multiple first transistors is coupled to a first voltage terminal, and the second electrode of the second target transistor T2 among the multiple second transistors is coupled to a second voltage terminal. The second target transistor is the transistor among the multiple second transistors coupled to the second voltage terminal.

[0049] For example, the control terminal of the first delay sub-unit and the control terminal of the second delay sub-unit are the gate of the transistor, and the first terminal is the source or drain of the transistor. For example, in Figure 3 In the example, the plurality of first transistors include a plurality of P-type transistors (i.e., PMOS transistors), and the plurality of second transistors include a plurality of N-type transistors (i.e., NMOS transistors).

[0050] like Figure 3 As shown, the gates of multiple PMOS transistors are coupled to the gates of multiple NMOS transistors at the input node P1, and the drains of the multiple PMOS transistors are coupled to and coupled to the drain of one of the multiple NMOS transistors at the output node P2. The drain of this NMOS transistor serves as the first terminal of multiple second delay sub-units. Figure 3 In the example, the first voltage terminal is the power supply voltage terminal VDD, which provides a high level for multiple first transistors, and the second voltage terminal is the low level VSS, which provides a low level for multiple second transistors, for example, the second voltage terminal is grounded.

[0051] For each of the multiple delay units located in the intermediate level, the input node is coupled to the output node of the previous level delay unit, and the output node is coupled to the input node of the next level delay unit.

[0052] The delay unit located in the intermediate stage is, for example, a delay unit other than the first-stage delay unit and the last-stage delay unit among multiple delay units.

[0053] For example, input node P1 is coupled to output node P2 of the previous delay unit, and output node P2 is coupled to input node P1 of the next delay unit.

[0054] exist Figure 3 In the example, multiple PMOS transistors of the delay unit (also called an "inverter") are connected in parallel to increase their size and reduce the delay (the larger the size, the smaller the delay). Simultaneously, multiple NMOS transistors are connected in series to further increase the delay. Thus, the NMOS delay time included in the period T of the output signal OUT will be much greater than that of the PMOS transistors. Therefore, the performance deviation of the NMOS transistors can be determined by testing the period T of the output signal OUT. Figure 3 The illustrated embodiment can test the process deviation of a certain type of device individually, thereby distinguishing the process corner type to which different types of devices belong. Furthermore, since the circuit uses PMOS to transmit high levels and NMOS to transmit low levels, there is no threshold voltage loss, allowing for full-amplitude oscillation and thus representing the true operating state of the chip.

[0055] Figure 4 A schematic diagram of the circuit structure of another delay unit provided in at least one embodiment of the present disclosure is shown.

[0056] The circuit structure of each delay unit in the multiple delay units 202 can be... Figure 4 The circuit structure shown is 300.

[0057] like Figure 4 As shown, the delay unit includes multiple first delay sub-units 103 connected in parallel and multiple second delay sub-units 104 connected in series. The multiple first delay sub-units are of a first type, and the multiple second delay sub-units are of a second type, with the activation methods of the first type and the second type being opposite. For example, in Figure 4 In the example, each of the multiple first delay sub-units is an NMOS transistor, and each of the multiple second delay sub-units is a PMOS transistor.

[0058] The control terminals of multiple first delay sub-units 103 and multiple second delay sub-units 104 are coupled to the input node P3, and the first terminals of the multiple first delay sub-units 103 and multiple second delay sub-units 104 are coupled to the output node P4. For example, the control terminal of each of the multiple delay sub-units 103 is the gate of a transistor, and the first terminal of each first delay sub-unit is the drain or source of a transistor.

[0059] For example, the control terminal of the first delay sub-unit and the control terminal of the second delay sub-unit are the gate of the transistor, and the first terminal is the source or drain of the transistor. For example, in Figure 4 In the example, the plurality of first transistors include a plurality of P-type transistors (i.e., PMOS transistors), and the plurality of second transistors include a plurality of N-type transistors (i.e., NMOS transistors).

[0060] like Figure 4As shown, the gates of multiple PMOS transistors are coupled to the gates of multiple NMOS transistors at the input node P3, the drains of the multiple NMOS transistors are coupled, and the drain of one of the multiple PMOS transistors is coupled to the output node P4. The drain of this PMOS transistor serves as the first terminal of multiple second delay sub-units. Figure 4 In the example, the source of multiple PMOS transistors is the second terminal and coupled to the first voltage terminal, and the source of the second target transistor T3 among multiple second transistors is the second terminal and coupled to the second voltage terminal.

[0061] For example, the first voltage terminal is the power supply voltage terminal VDD, which provides a high level to multiple first transistors, and the second voltage terminal is the low level VSS, which provides a low level to multiple second transistors, for example, the second voltage terminal is grounded.

[0062] Figure 4 The embodiment shown, except for the structure of each delay unit and Figure 3 Except for the structure of the delay unit in the illustrated embodiment, all other structures are the same as those in the example. Figure 3 The implementation examples are similar.

[0063] Figure 4 This circuit, used for PMOS transistor performance testing, connects multiple PMOS transistors in series and multiple NMOS transistors in parallel, increasing the PMOS delay. By adjusting the number of PMOS and NMOS transistors connected in series and parallel, the delay of the NMOS and PMOS transistors can be controlled within an acceptable range.

[0064] exist Figure 3 and Figure 4 In the example, the source of the PMOS transistor is coupled to a first voltage terminal to provide a first voltage level, and the source of the NMOS transistor is coupled to a second voltage terminal to provide a second voltage level. The first voltage level is higher than the second voltage level, so that there is no threshold voltage loss, allowing the inverter to oscillate at full swing.

[0065] In some embodiments of this disclosure, the control switch unit 201 includes an output terminal and a first input terminal. The input node of the first-stage delay unit is coupled to the output terminal of the control switch unit 201, and the output node of the last-stage delay unit is coupled to the first input terminal of the control switch unit.

[0066] like Figure 2 and 3 As shown, the control switch unit 201 includes an output terminal P5 and a first input terminal P6. The input node P1 of the first-stage delay unit is coupled to the output terminal P5 of the control switch unit 201, and the output node P2 of the last-stage delay unit is coupled to the first input terminal P6 of the control switch unit 201.

[0067] For example, such as Figure 2 and 4 As shown, the control switch unit 201 includes an output terminal P5 and a first input terminal P6. The input node P3 of the first-stage delay unit is coupled to the output terminal P5 of the control switch unit 201, and the output node P4 of the last-stage delay unit is coupled to the first input terminal P6 of the control switch unit 201.

[0068] The control switch unit 201 acts as the control switch for the test circuit 200, controlling the test circuit 200 to start oscillation.

[0069] In some embodiments of this disclosure, the control switch unit 201 further includes a second input terminal P7, which is connected to an enable signal terminal EN to control the operating state of the plurality of delay units 202 in response to an enable signal provided by the enable signal terminal EN.

[0070] For example, the control switch unit 201 includes a NAND gate. According to the working principle of the NAND gate, the test circuit 200 starts oscillating when the enable signal changes from low to high. For example, when the enable signal is 0, the test circuit 200 does not work; when the enable signal is 1, the test circuit 200 starts oscillating.

[0071] In embodiments of this disclosure, the proportions of PMOS and NMOS delays in the overall circuit delay are varied using parallel and series connections, and then the output period (e.g., Figure 2 The output cycle OUT0 shown can distinguish the process corner types of PMOS and NMOS respectively. Process corner types include, for example: fast NFET and fast PFET (FF), slow NFET and slow PFET (SS), fast NFET and slow PFET (FS), slow NFET and fast PFET (SF), etc.

[0072] In some embodiments of this disclosure, for example, the delays of PMOS and NMOS are changed so that the proportion of the PMOS delay in the overall test circuit delay can be ignored. Thus, the output signal OUT of the test circuit is used as the NMOS test result. The NMOS test result is compared with the simulated delay of NMOS to obtain the process deviation of the NMOS transistor. The NMOS simulation result and the NMOS test result are for the same test circuit. For example, for... Figure 2 The test circuit shown is used for testing and simulation to obtain the test results and simulation delay of the NMOS. Figure 2 The delay unit in the test circuit shown is Figure 3The circuit structure shown. For example, if the NMOS test result > the simulation delay of the NMOS, then this NMOS is a slow NMOS; if the NMOS test result < the simulation delay of the NMOS, then this NMOS is a fast NMOS. Similarly, it is also possible to test and simulate the test circuit including Figure 4 the circuit structure described above, so as to obtain the process corner type to which the PMOS belongs. In some embodiments of the present disclosure, for example, simulation tools such as hspice, spectre, xa, finesim, etc. can be used to perform simulation to obtain the simulation delay.

[0073] In some embodiments of the present disclosure, for example, when the delay ratio of a certain type of transistor in the test circuit is not greater than 10%, the delay of this type of transistor to the entire test circuit can be ignored.

[0074] Some embodiments of the present disclosure provide a chip. The chip includes a first test circuit, and the structure of the first test circuit is, for example, Figure 2 the structure shown. The first test circuit includes a first control switch unit and a plurality of cascaded first delay units, and the plurality of first delay units are coupled to the first control switch unit. For example, the control switch unit 201 is an example of the first control switch unit, and the plurality of delay units 202 are examples of the plurality of first delay units.

[0075] Each of the plurality of first delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series. The plurality of first delay sub-units are of the first type, the plurality of second delay sub-units are of the second type, and the opening methods of the first type and the second type are opposite. The control ends of the plurality of first delay sub-units and the control ends of the plurality of second delay sub-units are coupled to an input node, and the first ends of the plurality of first delay sub-units and the first ends of the plurality of second delay sub-units are coupled to an output node. For each of the first delay units in the middle stage among the plurality of first delay units, the input node is coupled to the output node of the previous-stage first delay unit, and the output node is coupled to the input node of the next-stage first delay unit. For example, the first delay sub-unit is Figure 3 the delay sub-unit 101 in, and the second delay sub-unit is Figure 3 the delay sub-unit 102 in. The input node is the Figure 3 node P shown, and the output node is the Figure 3 node P2 shown.

[0076] Regarding the first control switch unit and the plurality of first delay units, please refer to the description of the control switch unit 201 and the plurality of delay units 202 above.

[0077] For example, the plurality of first delay sub-units include a plurality of P-type transistors, and the plurality of second delay sub-units include a plurality of N-type transistors.

[0078] Figure 5 A schematic diagram of a chip provided in at least one embodiment of the present disclosure is shown.

[0079] like Figure 5 As shown, chip 500 includes a first test circuit 501, which is, for example, a... Figure 2 The circuit structure shown, and Figure 2 The delay unit in the circuit structure shown is Figure 3 The circuit structure shown is shown.

[0080] In some embodiments of this disclosure, such as Figure 5 As shown, in addition to the first test circuit 501, chip 500 may also include a second test circuit 502. The second test circuit 502 includes a second control switch unit and a plurality of cascaded second delay units. The plurality of second delay units are coupled to the second control switch unit. Each of the plurality of second delay units includes a plurality of third delay sub-units connected in parallel and a plurality of fourth delay sub-units connected in series. The plurality of third delay sub-units include a plurality of N-type transistors, and the plurality of fourth delay sub-units include a plurality of P-type transistors. The control terminals of the plurality of third delay sub-units and the plurality of fourth delay sub-units are coupled to an input node. The first terminals of the plurality of third delay sub-units and the plurality of fourth delay sub-units are coupled to an output node. For each of the plurality of second delay units located in an intermediate stage, the input node is coupled to the output node of the previous stage second delay unit, and the output node is coupled to the input node of the next stage second delay unit. For example, the third delay sub-unit is... Figure 4 The delay subunit 103, the fourth delay subunit is Figure 4 The delay subunit 104 in the middle. The input node is Figure 4 The node P3 shown has an output node of... Figure 4 The node shown is P4.

[0081] In some embodiments of this disclosure, for example, the circuit structure of each of the plurality of second delay units is as follows: Figure 4 The circuit structure shown is as follows. The circuit structure of each first delay unit in the first test circuit 501 is as follows: Figure 3 The circuit structure shown is such that the circuit structure of each second delay unit in the second test circuit 502 is as follows: Figure 4 The circuit structure shown is similar to that of the first and second test circuits, except that the first test circuit is similar in structure.

[0082] In this embodiment, the chip includes a first test circuit and a second test circuit, thereby obtaining the test results of the NMOS transistor and the PMOS transistor. By comparing the test results of the NMOS transistor and the PMOS transistor, the process corner deviation of the transistors in the chip can be obtained. For example, if the test result of the NMOS transistor is greater than the NMOS simulation delay (i.e., TT), and the test result of the PMOS transistor is less than the PMOS simulation delay (i.e., TT), then the process corner of the chip is SF.

[0083] Some embodiments of this disclosure provide a method for testing chip performance, which can be applied to the test circuit provided in any embodiment of this disclosure.

[0084] Figure 6 A flowchart is shown of a chip performance testing method provided in at least one embodiment of this disclosure.

[0085] like Figure 6 As shown, the test method includes steps S601 to S603.

[0086] Step S601: Provide an enable signal to the control switch unit. In response to the enable signal, the control switch unit provides control signals to multiple delay units.

[0087] Step S602: Obtain the output signals of multiple delay units in response to the control signal.

[0088] Step S603: Based on the output signal, obtain the test results of the chip performance.

[0089] This testing method is applied to a test circuit that includes multiple first delay sub-units connected in parallel and multiple second delay sub-units connected in series, thereby enabling the differentiation of the process corner type of different types of devices in the chip while representing the chip's actual operating state.

[0090] For step S601, for example in Figure 2 In the chip performance test circuit shown, an enable signal is provided to the control switch unit 201. In response to the enable signal, the control switch unit 201 provides control signals to multiple delay units 202.

[0091] For step S602, the output signal OUT of the multiple delay units in response to the control signal is obtained.

[0092] exist Figure 2 In the test circuit shown, the delay unit is Figure 3 The circuit structure is shown. The period Td of the output signal OUT0 can be obtained through the output signal OUT0, and the period Td of the output signal OUT0 is the NMOS test result.

[0093] For step S603, obtain the test result of the chip performance according to the output signal OUT0.

[0094] For example, step S603 includes: obtaining the cycle length of the output signal; obtaining the simulation delay of the test circuit; determining the process corner type to which multiple second delay sub-units belong based on the cycle length and the simulation delay of the test circuit.

[0095] For example, Figure 2 The shown test circuit includes Figure 3 the shown delay unit, perform simulation on Figure 2 the shown test circuit to obtain the simulation delay, and compare the cycle length Td with the simulation delay. For example, if the NMOS test result > the simulation delay of NMOS, the process corner type to which this NMOS belongs is slow NMOS; if the NMOS test result < the simulation delay of NMOS, the process corner type to which this NMOS belongs is fast NMOS.

[0096] Similarly, for example Figure 2 the shown test circuit includes Figure 4 the shown delay unit, then the process corner type to which PMOS belongs can be obtained.

[0097] In some other embodiments of the present disclosure, the process deviation can be further refined according to the ratio of PMOS transistors and NMOS transistors in the delay unit. For example, in [[ID=!]] Figure 3 the example of, 2 first delay sub-units are in parallel, and 2 second delay sub-units are in series, then the proportion of the delay of multiple second delay sub-units in the entire test circuit is 4Td / 5, and the specific data of the delay of multiple second delay sub-units can be obtained according to Td. For example, the simulation delay time of NMOS transistors includes the maximum value, the minimum value, and the average value of NMOS transistors in the process corner. Compare the cycle Td of the output signal OUT0 with the simulation delay time of NMOS transistors to obtain whether the process deviation of NMOS transistors is within the process corner range.

[0098] In some embodiments of the present disclosure, the ratio of the delay of the first delay sub-unit to the delay of the second delay sub-unit can be obtained through simulation.

[0099] Figure 7 The flowchart shows another test method for chip performance provided by at least one embodiment of the present disclosure. Figure 7 The shown test method is applied to a chip including a first test circuit and a second test circuit provided by some embodiments of the present disclosure, for example Figure 5 the shown chip.

[0100] As Figure 7 shown, this test method includes steps S701 to S703. It should be noted that there seems to be an issue with the placeholder at line 24 where the content in Figure 3 is missing in the provided text. I have left it as it is in the translation. If you can provide the complete content for that placeholder, I can further improve the translation.

[0101] Step S701: Provide enable signals to the first control switch unit and the second control switch unit respectively. In response to the enable signal, the first control switch unit provides control signals to a plurality of first delay units. In response to the enable signal, the second control switch unit provides control signals to a plurality of second delay units.

[0102] Step S702: Obtain the first output signal of the plurality of first delay units in the first test circuit in response to the control signal and the second output signal of the plurality of second delay units in the second test circuit in response to the control signal.

[0103] Step S703: Based on the first output signal and the second output signal, obtain the test results of the chip performance.

[0104] For example, the first test unit 501 includes a first control switch unit, and the second test unit 502 includes a second control switch unit. In step S701, enable signals are provided to the first control switch unit and the second control switch unit, respectively. In response to the enable signal, the first control switch unit provides control signals to a plurality of first delay units, and the second control switch unit, in response to the enable signal, provides control signals to a plurality of second delay units. Please refer to the description above for information on the enable signal.

[0105] For step S702, the first output signal OUT1 of the plurality of first delay units in the first test circuit 501 in response to the control signal output and the second output signal OUT2 of the plurality of second delay units in the second test circuit 502 in response to the control signal output are obtained.

[0106] For step S703, for example, the first output signal and the second output signal are compared with the simulation delay to determine the process corner type of the chip performance.

[0107] For example, the delay unit included in the first test circuit 501 is: Figure 3 In the circuit structure shown, the first output signal OUT1 represents the test result of the NMOS transistor; the second test circuit 502 includes a delay unit. Figure 4 In the circuit structure shown, the second output signal OUT2 represents the test result of the PMOS transistor.

[0108] If the test result of the NMOS transistor is greater than the NMOS simulation delay (i.e., TT), and the test result of the PMOS transistor is less than the PMOS simulation delay (i.e., TT), then the process corner of the chip is SF.

[0109] It should be noted that in the embodiments of this disclosure, each step of the test method corresponds to each unit of the aforementioned test circuit. For the specific steps of the test method, please refer to the relevant description of the test circuit above, which will not be repeated here. Figure 2 The components and structure of the test circuit shown are merely exemplary and not limiting; the test circuit may include other components and structures as needed.

[0110] Figure 8 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. Figure 8 The electronic device shown is used to perform the test method provided in at least one embodiment of this disclosure.

[0111] like Figure 8 As shown, the electronic device 800 includes a processor 810 and a memory 820. The memory 820 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 810 executes the non-transitory computer-readable instructions, which, when executed by the processor 810, can perform one or more steps of the test method described above. The memory 820 and the processor 810 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0112] For example, processor 810 may be a central processing unit (CPU), a digital signal processor (DSP), or other processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 810 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 800 to perform desired functions.

[0113] For example, memory 820 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 810 may run one or more computer program modules to implement various functions of electronic device 800. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0114] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 800 can be referred to the description of the test method above, and will not be repeated here.

[0115] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of this disclosure. The electronic device 300 is, for example, suitable for implementing the testing methods provided in the embodiments of this disclosure. The electronic device 300 may be a user terminal, etc. It should be noted that... Figure 9 The illustrated electronic device 300 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0116] like Figure 9 As shown, electronic device 300 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 310, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 320 or a program loaded from storage device 380 into random access memory (RAM) 330. The RAM 330 also stores various programs and data required for the operation of electronic device 300. The processing device 310, ROM 320, and RAM 330 are interconnected via bus 340. Input / output (I / O) interface 350 is also connected to bus 340.

[0117] Typically, the following devices can be connected to I / O interface 350: input devices 360 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 370 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 380 including, for example, magnetic tapes, hard disks, etc.; and communication devices 390. Communication device 390 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 9 An electronic device 300 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 300 may alternatively implement or have more or fewer devices.

[0118] For example, according to embodiments of this disclosure, Figure 6 The test method shown in Figure 7 can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the test method described above. In such an embodiment, the computer program can be downloaded and installed from a network via communication device 390, or installed from storage device 380, or installed from ROM 320. When the computer program is executed by processing device 310, it can perform the functions defined in the test method provided in embodiments of this disclosure.

[0119] At least one embodiment of this disclosure also provides a storage medium for storing non-transitory computer-readable instructions, which, when executed by a computer, can implement the test method described in any embodiment of this disclosure. Using this storage medium, the impedance parameters of the actual traces of the signal lines can be obtained, improving the accuracy of the test.

[0120] Figure 10 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 10 As shown, storage medium 400 is used to store non-transitory computer-readable instructions 410. For example, when the non-transitory computer-readable instructions 410 are executed by a computer, one or more steps in the test method described above can be performed.

[0121] For example, the storage medium 400 can be used in the aforementioned electronic device 800. For example, the storage medium 400 can be... Figure 8 The memory 820 in the illustrated electronic device 800. For example, a description of the storage medium 400 can be found here. Figure 8 The corresponding description of the memory 820 in the illustrated electronic device 800 will not be repeated here.

[0122] The testing method, apparatus, electronic device, and storage medium provided in the embodiments of this disclosure have been described above with reference to the accompanying drawings. The testing method provided in the embodiments of this disclosure can distinguish the process corner type of different types of devices in a chip, while representing the actual operating state of the circuit in the chip.

[0123] It should be noted that the storage medium (computer-readable medium) described above in this disclosure can be a computer-readable signal medium or a non-transitory computer-readable storage medium, or any combination of the two. A non-transitory computer-readable storage medium can be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a non-transitory computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a non-transitory computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. The transmitted data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a non-transitory computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0124] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol, such as Hypertext Transfer Protocol (HTTP), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0125] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0126] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to perform one or more steps according to the test method described above. Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or combinations thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, such as a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0127] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0128] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0129] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), etc.

[0130] In this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0131] The above description is merely a partial embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0132] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0133] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A chip performance testing circuit, comprising: Control switch unit; as well as Multiple cascaded delay units, wherein the multiple delay units are coupled to the control switch unit. Each of the plurality of delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series. The plurality of first delay sub-units are of a first type, and the plurality of second delay sub-units are of a second type. The activation methods of the first type and the second type are opposite. The control terminals of the multiple first delay subunits and the multiple second delay subunits are coupled to the input node. The first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to the output node. For each of the multiple delay units located in the intermediate level, the input node is coupled to the output node of the previous level delay unit, and the output node is coupled to the input node of the next level delay unit.

2. The test circuit according to claim 1, wherein, The plurality of first delay sub-units include a plurality of first transistors, and the plurality of second delay sub-units include a plurality of second transistors. The gate of each of the plurality of first transistors and the gate of each of the plurality of second transistors are coupled to the input node. The first terminal of each of the plurality of first transistors is coupled to the first terminal of the first target transistor among the plurality of second transistors to the output node. The second terminal of each of the plurality of first transistors is coupled to a first voltage terminal, and the second terminal of the second target transistor among the plurality of second transistors is coupled to a second voltage terminal.

3. The test circuit according to claim 2, wherein, The plurality of first transistors include a plurality of P-type transistors, and the plurality of second transistors include a plurality of N-type transistors.

4. The test circuit according to claim 2, wherein, The plurality of first transistors include a plurality of N-type transistors, and the plurality of second transistors include a plurality of P-type transistors.

5. The test circuit according to claim 3 or 4, wherein, The first voltage terminal provides a first voltage level, and the second voltage terminal provides a second voltage level, wherein the first voltage level is higher than the second voltage level.

6. The test circuit according to claim 1, wherein, The intermediate-level delay unit includes all delay units except for the first-level and last-level delay units. The control switch unit includes an output terminal and a first input terminal. The input node of the first-stage delay unit is coupled to the output terminal of the control switch unit. The output node of the last stage delay unit is coupled to the first input terminal of the control switch unit.

7. The test circuit according to claim 6, wherein, The control switch unit also includes a second input terminal. The second input terminal is connected to the enable signal terminal to control the operating state of the plurality of delay units in response to the enable signal provided by the enable signal terminal.

8. The test circuit according to claim 7, wherein, The control switch unit includes NAND gates.

9. A chip, comprising a first test circuit, wherein, The first test circuit includes: First control switch unit; and A plurality of cascaded first delay units, wherein the plurality of first delay units are coupled to the first control switch unit. Each of the plurality of first delay units includes a plurality of first delay sub-units connected in parallel and a plurality of second delay sub-units connected in series. The plurality of first delay sub-units are of a first type, and the plurality of second delay sub-units are of a second type. The activation methods of the first type and the second type are opposite. The control terminals of the multiple first delay subunits and the multiple second delay subunits are coupled to the input node. The first terminals of the plurality of first delay sub-units and the first terminals of the plurality of second delay sub-units are coupled to the output node. For each of the plurality of first delay units located in the intermediate level, the input node is coupled to the output node of the previous level first delay unit, and the output node is coupled to the input node of the next level first delay unit.

10. The chip according to claim 9, wherein, The plurality of first delay sub-units include a plurality of P-type transistors, and the plurality of second delay sub-units include a plurality of N-type transistors. The chip further includes a second test circuit, wherein the second test circuit includes: Second control switch unit; and A plurality of cascaded second delay units, wherein the plurality of second delay units are coupled to the second control switch unit. Each of the plurality of second delay units includes a plurality of third delay sub-units connected in parallel and a plurality of fourth delay sub-units connected in series. The plurality of third delay sub-units include a plurality of N-type transistors, and the plurality of fourth delay sub-units include a plurality of P-type transistors. The control terminals of the multiple third delay subunits and the multiple fourth delay subunits are coupled to the input node. The first terminals of the plurality of third delay sub-units and the first terminals of the plurality of fourth delay sub-units are coupled to the output node. For each of the plurality of second delay units located in the intermediate level, the input node is coupled to the output node of the previous level second delay unit, and the output node is coupled to the input node of the next level second delay unit.

11. A method for testing chip performance, applied to the test circuit according to any one of claims 1-8, the method comprising: An enable signal is provided to the control switch unit, and the control switch unit, in response to the enable signal, provides a control signal to the plurality of delay units; Obtain the output signals of the plurality of delay units in response to the control signal; as well as Based on the output signal, the test results of the chip performance are obtained.

12. The test method according to claim 11, wherein, Based on the output signal, the test results of the chip performance are obtained, including: Obtain the period length of the output signal; Obtain the simulation delay of the test circuit; Based on the cycle length and the simulation delay, the process corner type of the plurality of second delay sub-units is determined.

13. A method for testing chip performance, applied to the chip of claim 10, the method comprising: Enable signals are provided to the first control switch unit and the second control switch unit respectively. In response to the enable signal, the first control switch unit provides a control signal to the plurality of first delay units, and the second control switch unit provides the control signal to the plurality of second delay units in response to the enable signal. Acquire the first output signal of the plurality of first delay units in the first test circuit in response to the control signal and the second output signal of the plurality of second delay units in the second test circuit in response to the control signal; The test results of the chip performance are obtained based on the first output signal and the second output signal.

14. The method according to claim 13, wherein, Based on the first output signal and the second output signal, the test results of the chip performance are obtained, including: The first output signal and the second output signal are compared with the simulation delay to determine the process corner type of the chip performance.

15. An electronic device comprising: processor; Memory, which includes one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the test method according to any one of claims 11-14.

16. A computer-readable storage medium that non-transitoryly stores computer-readable instructions, wherein, The test method according to any one of claims 11-14 is implemented when the computer-readable instructions are executed by a processor.

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