Chip aging monitoring method and system, computer device, medium and product

Abstract

The invention discloses a chip aging monitoring method and system, a computer device, a medium and a product. The method comprises the following steps: determining a target ring oscillator path of a target chip comprising a plurality of real critical paths and a plurality of artificially constructed paths; according to the circuit unit configuration requirement of the chip, the copy number is determined, a target ring oscillator path is copied, an aging monitoring path is obtained, and a digital aging management unit is configured; calibrating the digital aging management unit put into use according to the calibration strategy after leaving the factory, and obtaining the digital aging management unit after the aging allowance is updated; and dynamically adjusting the working mode of the ring oscillator according to the load level of the use scene where the target chip is located, and monitoring the performance of the adjusted ring oscillator in real time according to the digital aging management unit with the updated aging allowance to obtain chip aging information. According to the method, the aging conditions of the chip in different stages can be accurately tracked, the aging allowance is effectively reduced, and the reliability and performance of the chip are improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip aging detection technology, and in particular to a chip aging monitoring method and system, computer device, medium, and product. Background Technology

[0002] Chip aging refers to the phenomenon that integrated circuits gradually degrade in performance or even fail in function due to electrical, thermal, and mechanical stress during long-term use. Currently, chip aging detection is usually based on the chip aging law for estimation. This method attempts to predict the aging of chips in actual use by studying and analyzing the general laws of chip aging. However, the workload of chips varies greatly in different actual use scenarios, which makes it difficult to keep parameters such as input signals and toggle rates on the critical path consistent.

[0003] Meanwhile, existing technologies that use ring oscillators (RO) for monitoring can only reflect the average degradation of process corners and cannot capture the actual aging behavior of critical paths, resulting in monitoring blind spots. Laboratory test conditions (such as fixed voltage / temperature) differ greatly from real-working scenarios. In order to ensure the reliability of different workload scenarios, a large amount of aging margin is often introduced, which is not only costly but also limits the maximum operating speed of the chip and affects the overall performance of the system.

[0004] Furthermore, Replication Logic also faces many problems in practical applications. For example, the area-first strategy can only replicate part of the path, making it difficult to cover critical paths in multiple scenarios. Even if it can reflect the critical path in a specific scenario, differences in workload will lead to different input signals and toggle rates on the path. At the same time, process / temperature variation will also affect its aging speed with ACTUAL LOGIC. These factors combine to make the analysis results obtained by chip aging monitoring through existing technologies inaccurate and unable to accurately reflect the aging state of the chip in actual use. Summary of the Invention

[0005] In view of this, the present disclosure provides a chip aging monitoring method and system, computer device, medium, and product, which can solve the problems of inaccurate chip aging monitoring in the prior art.

[0006] In a first aspect, embodiments of this disclosure provide a chip aging monitoring method, including: Based on the static timing analysis of the target chip and waveforms of typical real-world scenarios, the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, is determined. Based on the circuit unit configuration requirements of the target chip, determine the number of copies, and copy the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip, and configure a digital aging management unit on the aging monitoring path. The digital aging management unit in the target chip put into use is calibrated according to the post-factory calibration strategy to obtain the digital aging management unit after the aging margin is updated. Based on the load level of the target chip's usage scenario, the operating mode of the ring oscillator is dynamically adjusted, and the performance of the adjusted ring oscillator is monitored in real time by the digital aging management unit updated according to the aging margin to obtain chip aging information.

[0007] Secondly, embodiments of this disclosure also provide a chip aging monitoring system, comprising: The target ring oscillator path construction module is used to determine the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on the static timing analysis of the target chip and typical real-world waveforms. The aging monitoring path determination module is used to determine the number of copies based on the circuit unit configuration requirements of the target chip, and copy the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip, and configure a digital aging management unit on the aging monitoring path. The post-shipment calibration module is used to calibrate the digital aging management unit in the target chip to be put into use according to the post-shipment calibration strategy, and to obtain the digital aging management unit after the aging margin is updated. The dynamic working mode adjustment module is used to dynamically adjust the working mode of the ring oscillator according to the load level of the target chip's usage scenario, and to monitor the performance of the adjusted ring oscillator in real time based on the updated digital aging management unit according to the aging margin, so as to obtain chip aging information.

[0008] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform any of the chip aging monitoring methods described above.

[0009] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to perform any of the chip aging monitoring methods described above.

[0010] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0011] The chip aging monitoring method provided in this disclosure is a critical path-based aging monitoring method that senses real-world scenarios. By analyzing the static timing of the target chip and typical real-world waveforms, it determines a target ring oscillator path that includes several real critical paths and several artificially constructed paths, thus covering a wider range of scenarios and improving the comprehensiveness of aging monitoring. Next, based on the circuit unit configuration requirements of the target chip, it determines the number of copies and replicates the target ring oscillator path accordingly to obtain the aging monitoring path of the target chip. By setting multiple identical monitoring paths in different areas of the chip, it can more accurately reflect the aging status of various parts of the chip. A digital aging management unit is configured on the aging monitoring path to monitor the aging status of the entire chip. Unified monitoring improves monitoring efficiency. Secondly, the digital aging management unit (DRM) configured in the target chip is calibrated according to the factory calibration strategy. The updated DRM with aging margin can be used to update the calibration based on the specific working scenario of the chip, improving the accuracy of the DRM and ensuring that it can monitor chip aging more reliably. Finally, the working mode of the ring oscillator is dynamically adjusted according to the load level of the target chip's usage scenario. The performance of the adjusted ring oscillator is monitored in real time based on the updated DRM with aging margin to obtain chip aging information. The dynamic adjustment of the ring oscillator's working mode allows the monitoring scheme to be flexibly adjusted according to the actual usage of the chip, meeting monitoring requirements while optimizing power consumption.

[0012] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic flowchart of the chip aging monitoring method provided in the embodiments of this disclosure.

[0015] Figure 2 This is a flowchart illustrating a method for determining the path of a target ring oscillator provided in an embodiment of this disclosure.

[0016] Figure 3 This is a flowchart illustrating the method for obtaining the aging monitoring path of a target chip according to an embodiment of this disclosure.

[0017] Figure 4 This is a flowchart illustrating a method for configuring a digital aging management unit on an aging monitoring path, as provided in an embodiment of this disclosure.

[0018] Figure 5 This is a flowchart illustrating a method for calibrating a digital aging management unit according to a pre-shipment calibration strategy, as provided in an embodiment of this disclosure.

[0019] Figure 6 This is a flowchart illustrating the method for obtaining the updated digital aging management unit based on the aging margin provided in this embodiment of the disclosure.

[0020] Figure 7 This is a flowchart illustrating the method for obtaining aging margin update values ​​provided in an embodiment of the present disclosure.

[0021] Figure 8 This is a flowchart illustrating a method for obtaining chip aging information provided in an embodiment of this disclosure.

[0022] Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0024] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0028] Reference Figure 1 This application discloses a chip aging monitoring method, which is an aging monitoring method based on the critical path and sensing the real scene. The method specifically includes: S100 determines the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on the static timing analysis of the target chip and typical real-world waveforms.

[0029] S200 determines the number of copies based on the circuit unit configuration requirements of the target chip, and copies the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip.

[0030] The S300 is equipped with a digital aging management unit along the aging monitoring path.

[0031] S400 calibrates the digital aging management unit in the target chip to be put into use according to the factory calibration strategy, and obtains the digital aging management unit after the aging margin is updated.

[0032] The S500 dynamically adjusts the operating mode of the ring oscillator according to the load level of the target chip's usage scenario, and monitors the performance of the adjusted ring oscillator in real time based on the updated digital aging management unit according to the aging margin, thereby obtaining chip aging information.

[0033] The chip aging monitoring method disclosed in this application, by combining real critical paths and artificially constructed paths and replicating them, can cover a wide range of chip scenarios and different regions, improving the comprehensiveness of aging monitoring. The post-factory calibration strategy and the method of dynamically adjusting the working mode can fully consider the actual working scenarios and load changes of the chip, improving the accuracy of aging monitoring. The digital aging management unit can monitor the performance changes of the ring oscillator in real time, obtain the aging information of the chip at different stages in a timely manner, and facilitate timely measures to ensure the reliability and stability of the chip. The dynamic adjustment of the ring oscillator's working mode allows the monitoring scheme to be flexibly adjusted according to the actual use of the chip, accurately obtaining circuit aging information under the corresponding business scenario, which not only meets the monitoring requirements but also optimizes power consumption.

[0034] The method disclosed in this application can accurately track the aging of chips at different stages, effectively reduce aging margin, and achieve power saving with lower voltage at the same frequency, or performance improvement with higher frequency at the same voltage.

[0035] Reference Figure 2 The method for determining the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on the static timing analysis of the target chip and typical real-world waveforms, specifically includes the following: S110, based on the static timing analysis results of the target chip and the waveforms of typical real-world scenarios, identifies several real critical paths covering typical real-world scenarios.

[0036] For S110, the specific steps include: 1) Based on the static timing analysis results, obtaining the initial path whose path delay is less than the preset upper limit threshold difference within a preset range; 2) Analyzing the waveforms of all initial paths based on power analysis tools (such as PTPX tools) to obtain the signal flip rate within a preset period that is greater than the preset threshold, and then obtaining the corresponding path whose signal flip rate within a preset period is greater than the preset threshold, which is recorded as the real critical path covering typical real-world scenarios.

[0037] The static timing analysis results only consider placement and routing, excluding logic. This static timing analysis refers to a comprehensive analysis of the chip's circuit design using professional static timing analysis tools (such as Synopsys' PrimeTime). These tools calculate the delay of each signal propagation path based on information such as the delays of logic gates and interconnects. In this embodiment, the path delay includes line delay and cell delay.

[0038] Signal flip rate refers to the number of flips within a preset period, reflecting the activity level of a path in actual operation. Paths with high flip rates consume more power during chip operation and are more susceptible to factors such as aging. By selecting paths with flip rates greater than a preset threshold as true critical paths, we can accurately capture those paths that have a significant impact on chip performance and power consumption in typical real-world scenarios, making aging monitoring more targeted.

[0039] Among them, "obtaining a number of initial paths whose path delay is less than the preset upper limit threshold" can be dynamically adjusted according to the preset number to obtain the desired number of these paths, preferably no less than 100. The path delay of these paths is close to the preset upper limit threshold, so their performance is relatively poor. This step is to select the relatively poor paths.

[0040] S120, run under preset extreme conditions to obtain several target paths where the difference between the path delay and the preset upper limit threshold is less than a preset range.

[0041] The preset extreme conditions are unconventional scenarios, such as running under conditions such as upper limit bandwidth or upper limit computation. The specific conditions can be flexibly set according to actual needs. That is, the target path obtained in this embodiment is the path corresponding to the extreme scenario.

[0042] S130: Based on the power consumption analysis tool, analyze the waveforms of all target paths (i.e. extreme scenario waveforms) to obtain the flip rate within a preset period that is greater than a preset threshold, and then obtain the paths with a flip rate greater than the preset threshold within a preset period (i.e., filter out the paths with a relatively high flip rate), which are denoted as artificially constructed paths covering extreme scenarios. All the real critical paths and the artificially constructed paths constitute the target ring oscillator path.

[0043] Each artificially constructed path and each real critical path has a separate masking bit, and all real critical paths share the control logic with artificially constructed paths. In this embodiment, the paths selected by preset extreme conditions are extreme scenarios not covered by the previous "several real critical paths covering typical real scenarios".

[0044] Among these, some individuals construct paths to cover signal propagation paths under extreme conditions, or build special paths for some easily interfered areas in the chip, to make up for scenarios that the real critical path may not cover, so that the target ring oscillator path can cover a wider range of scenarios and improve the comprehensiveness of aging monitoring.

[0045] The method disclosed in this embodiment uses static timing analysis to screen initial paths with delays approaching the upper limit threshold, and then combines this with power analysis tools to screen paths with high flip-flop rates. This accurately identifies the real critical paths that significantly impact chip performance and power consumption in actual use. This allows subsequent aging monitoring to focus on these critical paths, improving the accuracy of aging monitoring. The solution fully considers the actual operating scenarios of the chip, using power analysis tools to screen initial paths and ensure that the selected real critical paths cover typical real-world scenarios. This allows for more targeted monitoring of these critical paths during aging monitoring, enabling timely detection of aging issues in actual use. Accurately identifying and monitoring real critical paths helps to identify potential aging risks in advance, allowing for timely adjustments or maintenance, improving chip reliability and stability, and reducing the probability of chip failure due to aging.

[0046] Reference Figure 3 The method S200, which "determines the number of copies based on the circuit unit configuration requirements of the target chip, and copies the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip," specifically includes the following methods for obtaining the aging monitoring path of the target chip: S210, packages the target ring oscillator path into a single circuit unit; S220, Determine the target module of the circuit unit to be copied; S230, based on the layout and routing information of all modules in the target chip, determines the available area of ​​each target module; S240, determine the target number of copies for each target module based on the available area.

[0047] For example, if the usable area of ​​a target module is 400 square millimeters and the preset coefficient is 20, then the number of copies is 400 ÷ 20 = 20.

[0048] S250: Based on the target number of copies, the circuit units are configured (i.e. placed) into each target module to obtain the aging monitoring path of the target chip.

[0049] Copying the target ring oscillator path can increase the number of monitoring points, making the probes more comprehensive. By setting multiple identical monitoring paths in different areas of the chip, the aging status of each part of the chip can be reflected more accurately, avoiding inaccurate aging information caused by local monitoring.

[0050] Reference Figure 4 The method for configuring a digital aging management unit on the aging monitoring path in S300 specifically includes: S310, calibrates the digital aging management unit according to the pre-shipment calibration strategy; S320 configures the calibrated digital aging management unit on the aging monitoring path.

[0051] By configuring the digital aging management unit (DAU) on the aging monitoring path—that is, electrically connecting the DAU to the aging monitoring path during chip manufacturing—accurate monitoring of the ring oscillator's performance on the aging monitoring path can be ensured. The DAU can monitor the ring oscillator's performance changes in real time and accurately, providing a crucial monitoring method for subsequently obtaining chip aging information. By configuring it on the aging monitoring path, the aging status of the entire chip can be monitored uniformly, improving monitoring efficiency.

[0052] Reference Figure 5 The method for S310 "calibrating the digital aging management unit according to the pre-shipment calibration strategy" specifically includes: S311 performs tests covering all functional paths in the target chip to obtain the first voltage frequency table.

[0053] The functional path refers to the part of the ring oscillator circuit where signals are actually transmitted and processed to achieve a specific function. In this step, the first voltage-frequency table is obtained by testing the actual functional path in the target chip.

[0054] S312, test the digital aging management unit to obtain a second voltage frequency table covering the aging monitoring path.

[0055] In this step, the second voltage frequency table includes the correspondence between different typical voltage points and the frequency of the ring oscillator; the second voltage frequency table is obtained by testing the functional path in the configured path (i.e., the aging monitoring path), and this step is not sequential with the previous step.

[0056] S313. Based on the first voltage frequency table and the second voltage frequency table, fit all frequencies under the same voltage to obtain the frequency curves of all typical voltage points and the fitting relationship of the weight coefficients of each path in the corresponding aging monitoring path, which is denoted as the frequency-weight fitting relationship.

[0057] Among them, the least squares method is preferably used to fit all frequencies under the same voltage in the first voltage frequency table and the second voltage frequency table. The obtained frequency-weight fitting relationship is presented in the form of an equation, which represents the relationship between frequency F and weight coefficient k. That is, each frequency corresponds to several weight coefficients k, and each weight coefficient k corresponds to a path in the aging monitoring path.

[0058] S314. Fit all typical voltage points and their corresponding weight coefficients to obtain the fitting relationship between each typical voltage point and its corresponding weight coefficient, which is denoted as the voltage-weight fitting relationship.

[0059] Specifically, the least squares method is preferred for fitting, and the obtained voltage-weighted fitting relationship is presented in the form of an equation, which represents the relationship between the weight coefficient K(v) and the voltage v.

[0060] The frequency-weighted fitting relationship and the voltage-weighted fitting relationship constitute the voltage-frequency fitting curve; S315 configures the voltage-frequency fitting curve to the digital aging management unit, resulting in a digital aging management unit calibrated before leaving the factory.

[0061] Specifically, the voltage-frequency fitting curve (including the corresponding equation) is stored in the storage unit within the circuit of the digital aging management unit.

[0062] Specifically, S312 includes: 1) sampling the oscillation signal of the ring oscillator at different typical voltage points and based on a sampling window with a preset sampling frequency to obtain the number of oscillation cycles of the ring oscillator; 2) determining the frequency of the ring oscillator based on the number of oscillation cycles.

[0063] The sampling window duration is: : , The preset sampling frequency is used; the frequency of the ring oscillator is... : , This represents the number of oscillation periods of the ring oscillator.

[0064] At each typical voltage point, when the sampling window is open, the counter starts counting the oscillation signal of the ring oscillator. When the sampling window is closed, the counter stops counting. The count value obtained at this time is the number of oscillation cycles of the ring oscillator under the voltage point and sampling window conditions.

[0065] During chip operation, different voltages affect the oscillation frequency of the ring oscillator. The typical voltage points in this application usually refer to voltage values ​​or nodes that have specific functions and significance in the chip design, testing, and practical application. They play a key role in the normal operation, performance, and stability of the chip, such as power supply voltage points (e.g., core power supply voltage, I / O power supply voltage), reference voltage points (e.g., bandgap reference voltage, bias voltage), threshold voltage points (e.g., transistor threshold voltage, logic threshold voltage), etc.

[0066] A ring oscillator typically consists of an odd number of inverters connected end-to-end to form a closed loop. The signal oscillates continuously within this loop. The functional path described in this application refers to the effective circuitry through which the signal completes this oscillation process. The functional path plays a decisive role in the ring oscillator's oscillation frequency, phase, and other characteristics. Component parameters along the functional path, such as the inverter's delay time and load capacitance, directly affect the signal's propagation speed within the path. For example, the longer the inverter's delay time, the longer it takes for the signal to complete one cycle, and the lower the oscillation frequency.

[0067] For the tests in S311 and S312, the SCAN test is preferred to obtain the corresponding tables, or MBIST, LBIST and SCAN tests can be used respectively.

[0068] Taking the S311 test as an example, the specific operational logic used in all three test methods is explained as follows: 1) SCAN test phase: First, the flip-flops in the ring oscillator are connected into a scan chain. Through the scan chain controller, test data is serially shifted into each flip-flop in the scan chain; a series of different test vectors are applied, which can simulate various signal states during normal operation. While applying the test vectors, the voltage applied to the ring oscillator is changed; a frequency measurement device (such as a frequency counter) is used to measure and record the oscillation frequency of the ring oscillator under different voltages. 2) LBIST test phase: The LBIST circuit generates a pseudo-random test sequence and applies it to the logic section of the ring oscillator; during the application of the test sequence, the voltage is gradually changed while the frequency of the ring oscillator is measured. Since LBIST can test the logic circuit more comprehensively, it can detect some faults that the SCAN test might miss; the frequency data under different voltages is recorded and integrated with the data from the SCAN test phase. 3) MBIST Testing Phase: If the ring oscillator is associated with memory cells, MBIST will test these cells by applying different test modes to check their read and write capabilities. During the MBIST test, the voltage is also varied, and the ring oscillator frequency is measured. Because memory cell failures can affect oscillator performance, the MBIST test can further supplement the results of the previous two tests. The voltage-frequency data obtained from the MBIST test is integrated with the data from the previous two phases to form a complete first voltage-frequency table. By using these three methods in combination, the functional path of the ring oscillator can be tested from different perspectives, ensuring that the obtained first voltage-frequency table accurately reflects the ring oscillator's performance under various voltages.

[0069] It should be noted that the startup time for "calibrating the digital aging management unit in the target chip according to the factory calibration strategy" in S400 can be when the system where the target chip is located starts up every time it is powered on (in response to whether the power button is pressed), or after the target chip exits the low power state, or a user-defined time.

[0070] Reference Figure 6 The method for obtaining the updated digital aging management unit after aging margin adjustment specifically includes: S410 performs the first functional self-test on the target chip based on the initial startup voltage and initial startup frequency corresponding to the target chip, and obtains the first test result.

[0071] Each type of target chip is configured with an initial startup voltage V0 and an initial startup frequency at the factory. The test results obtained in this step are the actual self-test results of the target chip. For specific test methods, please refer to the test methods in S311 and S312 above.

[0072] S420, if the first test result is passed, the limit frequency corresponding to the initial start-up voltage is confirmed according to the voltage-frequency fitting curve.

[0073] After the target chip passes the actual self-test, the limiting frequency F corresponding to the initial startup voltage V0 is obtained from the voltage-frequency fitting curve. max0 The frequency is a logical value.

[0074] S430 performs a second functional self-test on the target chip based on the initial startup voltage and the limit frequency, and obtains the second test result.

[0075] This step uses the functional self-test method commonly used in integrated circuit chips. For details, please refer to the test methods in S311 and S312 above. This step yields the test results of the actual path.

[0076] If the test passes, the digital aging management unit uses the frequency-voltage curve and weighting coefficients obtained from the factory test to monitor the chip aging in real time.

[0077] During use after leaving the factory, chips are subjected to electrical stress, thermal stress, mechanical stress, etc. for a long time. The physical structure of the internal transistors, metal interconnects, etc. may change. For example, metal interconnects may break due to electromigration, and the threshold voltage of transistors may drift. These changes in physical structure can cause abnormal chip function, making MBIST, LBIST, or SCAN tests fail, indicating that the chip has aging problems.

[0078] S440, if the second test result is not passed, the frequency is swept downward according to the preset gradient with the limit frequency as the reference frequency, and the target chip is subjected to a functional self-test at each reduced frequency point to obtain the new limit frequency corresponding to the initial start-up voltage when the test is passed.

[0079] Frequency sweeping refers to changing the frequency sequentially within a certain frequency range according to a specific pattern and performing tests. This step employs a common functional self-test method for integrated circuit chips; for details, please refer to the test methods in S311 and S312 above. The new limiting frequency F corresponding to the initial startup voltage obtained in this step is... a This is the actual value.

[0080] S450, obtain the limiting frequency F corresponding to the initial startup voltage. max0 With the new limiting frequency F a The difference is used to determine the aging margin update value.

[0081] S460 updates the voltage-frequency fitting curve based on the aging margin update value, and configures the updated voltage-frequency fitting curve to the digital aging management unit to obtain the digital aging management unit after the aging margin update.

[0082] Post-factory calibration can take into account the calibration updates for specific chip operating scenarios. Since chips are affected by various factors during actual use, such as temperature and voltage fluctuations, the initial settings at the factory may not accurately reflect the actual aging of the chip. Post-factory calibration can improve the accuracy of the digital aging management unit and ensure that it can monitor chip aging more reliably.

[0083] Reference Figure 7 The method for S450 to "obtain the difference between the limiting frequency corresponding to the initial start-up voltage and the new limiting frequency to determine the aging margin update value" specifically includes the following: S451, obtain the frequency difference between the limiting frequency corresponding to the initial start-up voltage and the new limiting frequency; S452, if the frequency difference is less than the preset threshold, select the minimum value between the limit frequency corresponding to the initial start-up voltage and the new limit frequency as the frequency Fage after chip aging.

[0084] The preset threshold is usually based on empirical parameters obtained from testing previous or current generation products. If the frequency difference is less than the preset threshold, it is considered that RO and its weighting coefficient can well reflect the aging condition of the actual circuit and no adjustment is required.

[0085] S453 determines the target voltage corresponding to the frequency after chip aging based on the voltage-frequency fitting curve. S454, obtain the difference between the target voltage and the start-up voltage, and record it as the aging margin update value.

[0086] Among them, the aging margin update value △V represents the voltage increment that needs to be introduced due to aging.

[0087] S455, if the frequency difference is not less than the preset threshold, the new limit frequency will be used as the frequency after aging.

[0088] S456, by fitting the aged frequency with the limiting frequency corresponding to the initial start-up voltage, a new weighting coefficient for the ring oscillator is obtained.

[0089] If the difference between the limit frequency corresponding to the initial startup voltage (i.e., the frequency that the RO can reach under a specific initial startup voltage before the chip leaves the factory) and the frequency after aging (i.e., as the chip is used for longer, the performance of the RO will change, and its oscillation frequency will also change accordingly, i.e., the changed frequency) exceeds the threshold, it is considered that the RO cannot reflect the aging of the real circuit well, and the weighting coefficient of the RO needs to be adjusted.

[0090] By refitting the limiting frequency corresponding to the initial startup voltage with the frequency after aging to obtain new weighting coefficients, the performance changes of RO after aging can be reflected more accurately, thereby allowing for more reasonable adjustments to the chip's operating parameters. In this embodiment, the least squares method is preferred for fitting. Based on the chip's design and application requirements, and combined with the fitted coefficients, new weighting coefficients are calculated. The specific calculation method needs to be determined according to the specific circumstances of the chip.

[0091] S457: Determine the target voltage corresponding to the frequency after aging based on the voltage-frequency fitting curve, and obtain the difference between the target voltage and the starting voltage, which is recorded as the aging margin update value.

[0092] It should be noted that the order of S452-S454 and S455-S457 is not important, and they are all within the scope of protection of this application.

[0093] The S460's "updating the voltage-frequency fitting curve based on the aging margin update value, configuring the updated voltage-frequency fitting curve to the digital aging management unit, and obtaining the digital aging management unit with the updated aging margin" specifically includes: When the frequency difference is less than the preset threshold, the aging margin update value is added to each voltage in the voltage-frequency fitting curve to obtain the updated voltage-frequency fitting curve. The updated voltage-frequency fitting curve is then configured to the digital aging management unit to obtain the digital aging management unit with the updated aging margin.

[0094] When the frequency difference is not less than the preset threshold, each voltage in the voltage-frequency fitting curve is increased by the aging margin update value to obtain the updated voltage-frequency fitting curve; the updated voltage-frequency fitting curve and the new weight coefficient of the ring oscillator are configured to the digital aging management unit to obtain the digital aging management unit with the updated aging margin.

[0095] The voltage-frequency fitting curve in the digital aging management unit after the aging margin update is used until the next curve update.

[0096] After a chip leaves the factory, the aging speed can vary greatly due to significant differences in the programs run by different customers and even by the same customer at different times. The post-factory calibration method disclosed in this embodiment can better release the aging margin by accurately tracking the actual usage of the customer. That is, it can dynamically adjust the chip's operating parameters according to the actual operating conditions of the chip, make full use of the pre-set aging margin, and improve the chip's performance as much as possible while ensuring chip reliability.

[0097] By appropriately releasing the aging margin, excessive performance redundancy can be avoided, ensuring the chip maintains a reasonable performance level throughout its lifespan. This satisfies the needs of different customers and operating scenarios while effectively extending the chip's lifespan. For example, if too much aging margin is reserved during design but not fully utilized in actual use, the chip's performance will not be fully realized, resulting in wasted resources. Conversely, by better releasing the aging margin according to actual conditions, the chip can maintain good performance for a longer period without affecting its reliability. For chip manufacturers and customers, better releasing the aging margin improves the chip's cost-effectiveness. Manufacturers can reduce unnecessary performance redundancy during design, lowering manufacturing costs; customers can fully utilize the chip's performance during use, improving production efficiency and thus reducing operating costs.

[0098] Reference Figure 8 The S500 method of "dynamically adjusting the operating mode of the ring oscillator according to the load level of the chip's usage scenario, and monitoring the performance of the adjusted ring oscillator in real time according to the updated digital aging management unit based on the aging margin to obtain chip aging information," i.e., the method for obtaining chip aging information, includes: S510 uses a millisecond-level circuit event counter to acquire event data within a preset counting period; S520: Obtain the actual difference between the event data and the preset event threshold, and determine the actual scene level corresponding to the actual difference based on the preset difference threshold range.

[0099] The S530 dynamically adjusts the operating mode (i.e., oscillation state) of the ring oscillator according to the actual scenario level.

[0100] The S540, based on the updated digital aging margin, monitors the performance of the ring oscillator after the working mode adjustment in real time to obtain chip aging information.

[0101] In this embodiment, the behavior of the digital aging management unit is adjusted based on actual scenarios to facilitate better tracking. Dynamically adjusting the ring oscillator's operating mode can be optimized according to the chip's actual usage, reducing power consumption under low load and accurately monitoring chip aging under high load. By monitoring the adjusted ring oscillator performance in real time, aging trends of the chip can be detected promptly, facilitating appropriate measures such as adjusting chip operating parameters and performing preventative maintenance.

[0102] For the S510, the event counter based on the millisecond level acquires event data within a preset counting period. The event counter is a sequential logic device in digital circuits used to record the number of pulse signals or the time interval. It is mainly composed of flip-flops and can output a count value corresponding to the number or time of the input pulses.

[0103] Specifically, when the actual difference is within the first preset range, the corresponding actual scenario level is determined to be heavy load, and the working mode of the ring oscillator is dynamically adjusted to continuous oscillation; when the actual difference is within the second preset range, the corresponding actual scenario level is determined to be medium load, and the working mode of the ring oscillator is dynamically adjusted to oscillate according to a preset ratio; when the actual difference is within the third preset range, the corresponding actual scenario level is determined to be light load, and the working mode of the ring oscillator is dynamically adjusted to continuous non-oscillation.

[0104] If the corresponding scenario level is heavy load, it means the chip needs to handle a large number of tasks, placing high demands on performance. In this case, continuous oscillation of the ring oscillator provides the chip with a stable and continuous clock signal or other necessary periodic signals, ensuring that each module of the chip can operate efficiently and stably, meeting the processing requirements of heavy load tasks. For example, in a graphics processing chip, when rendering large-scale game graphics, the system is in a heavy load state. The continuous oscillation of the ring oscillator provides a stable clock signal to the graphics processing unit (GPU), enabling the GPU to quickly process large amounts of graphics data and ensuring the smoothness of the game graphics.

[0105] If the corresponding actual scenario level is medium load, the ring oscillator is configured to oscillate at a certain ratio. Specifically, when a medium load occurs, the system load is at a moderate level, and it does not need to continuously provide high-intensity signal support as it does under heavy load, but it cannot completely stop oscillating either. Therefore, configuring the ring oscillator to oscillate at a certain ratio can both meet the basic requirements of the system under medium load conditions and reduce power consumption to a certain extent.

[0106] The method for determining the ratio can be based on historical data statistical analysis or dynamically and adaptively adjusted. For the method based on historical data statistics: by analyzing a large amount of historical medium-load operation data, the optimal balance point between the ring oscillator oscillation ratio and performance and power consumption under medium-load conditions can be found. For example, after multiple experiments and data statistics, it was found that when the ring oscillator oscillation ratio is 60%, the system can meet the processing requirements of medium-load tasks and control the power consumption within a reasonable range.

[0107] For dynamic adaptive adjustment: the chip can dynamically adjust the oscillation ratio of the ring oscillator according to the real-time characteristics of the medium-load task and the system status; for example, when it is detected that there are some parts of the medium-load task that have high requirements for clock signal accuracy, the oscillation ratio is appropriately increased; while for some parts that have less stringent requirements for clock signal, the oscillation ratio is decreased.

[0108] If the corresponding scenario level is light load, the ring oscillator will remain quiescent. This means that when the system is under light load, the chip handles fewer tasks and has lower demand for periodic signals such as clock signals. In this case, keeping the ring oscillator quiescent can significantly reduce power consumption, extend the chip's battery life, reduce heat generation, and improve system stability. For example, in a smartphone chip, when the phone is in standby mode, the system is under light load, and the ring oscillator remains quiescent, thus reducing chip power consumption and extending the phone's battery life.

[0109] The chip aging monitoring method disclosed in this application effectively solves the problems of inaccurate chip aging monitoring and difficulty in covering multiple scenarios in existing technologies through a series of technical means. Specifically, existing methods are difficult to cope with the differences in input signals and toggle rates on critical paths under different actual use scenarios. This application, through static timing analysis, can identify potential paths in the chip with large signal propagation delays that have a critical impact on performance. At the same time, by collecting waveforms of typical real scenarios and combining the two, the true critical paths under different actual scenarios can be accurately determined, making the monitoring more in line with actual use and solving the monitoring problem caused by inconsistent critical path parameters. In order to further cover a wider range of scenarios, this application constructs several artificial paths. These artificial paths can simulate various extreme cases and special signal propagation conditions, making up for scenarios that the true critical paths may not cover, ensuring that there are corresponding paths for aging monitoring regardless of the chip's workload state, and reducing monitoring errors caused by workload differences.

[0110] Traditional ring oscillator monitoring can only reflect the average degradation at process corners and cannot capture the actual aging behavior of critical paths. The target ring oscillator path identified in this application includes several real critical paths and artificially constructed paths. The real critical paths directly correspond to the key performance parts of the chip in actual use, while the artificially constructed paths expand the monitoring scope. This design allows the ring oscillator to more comprehensively monitor the aging of the chip's critical paths and reduce monitoring blind spots. The operating mode of the ring oscillator is dynamically adjusted according to the load level of the target chip's usage scenario. This dynamic adjustment allows the ring oscillator to better adapt to different workloads and capture the aging behavior of critical paths in real time, solving the problem that traditional ring oscillator monitoring cannot adapt to different workloads.

[0111] Laboratory testing conditions differ significantly from real-world workloads. Existing methods introduce substantial aging margins to ensure reliability, leading to high costs and limited performance. This application employs a post-shipment calibration strategy. After the chip leaves the factory, the digital aging management unit is calibrated according to its specific operating scenario. Considering that chips are affected by factors such as temperature and voltage fluctuations during actual use, calibration allows the digital aging management unit to more accurately reflect the chip's aging status, reducing unnecessary aging margins, lowering costs, and simultaneously improving the chip's maximum operating speed and overall system performance.

[0112] Existing replication logic has problems such as only being able to replicate a portion of the path and being unable to cover critical paths in multiple scenarios. This application determines the number of replications based on the circuit unit configuration requirements of the target chip, and obtains the aging monitoring path by replicating the target ring oscillator path. This increases the number of monitoring points, making the probe deployment more comprehensive and covering critical paths in multiple scenarios. At the same time, the aging monitoring path is reasonably distributed in various areas of the chip, reducing the impact of workload differences on the monitoring results and improving the accuracy of monitoring.

[0113] In summary, the chip aging monitoring method of this application comprehensively solves the problems existing in the prior art through the integrated application of multiple technical means, and can more accurately reflect the aging state of the chip in actual use, thereby improving the reliability and performance of the chip.

[0114] Secondly, this application discloses a chip aging monitoring system for performing the chip aging monitoring method disclosed in the first aspect of this application. The system includes: The target ring oscillator path construction module is used to determine the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on the static timing analysis of the target chip and typical real-world waveforms. The aging monitoring path determination module is used to determine the number of copies based on the circuit unit configuration requirements of the target chip, and copy the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip, and configure a digital aging management unit on the aging monitoring path. The post-shipment calibration module is used to calibrate the digital aging management unit in the target chip to be put into use according to the post-shipment calibration strategy, and to obtain the digital aging management unit after the aging margin is updated. The dynamic working mode adjustment module is used to dynamically adjust the working mode of the ring oscillator according to the load level of the target chip's usage scenario, and to monitor the performance of the adjusted ring oscillator in real time based on the updated digital aging management unit according to the aging margin, so as to obtain chip aging information.

[0115] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0116] The processor may be a central processing unit (CPU) or other processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the chip aging monitoring methods of the foregoing embodiments of this disclosure.

[0117] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0118] like Figure 9 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 9 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0119] like Figure 9 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0120] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 9 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0121] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from ROM. When the computer program is executed by a processor, all or part of the steps of the chip aging monitoring method of embodiments of this disclosure are performed.

[0122] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0123] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the chip aging monitoring methods described in the foregoing embodiments of the present disclosure are performed.

[0124] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0125] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0126] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0127] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0128] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0129] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0130] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0131] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0132] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A chip aging monitoring method, characterized in that, include: Based on the static timing analysis of the target chip and waveforms of typical real-world scenarios, the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, is determined. Based on the circuit unit configuration requirements of the target chip, determine the number of copies, and copy the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip, and configure a digital aging management unit on the aging monitoring path. The digital aging management unit in the target chip put into use is calibrated according to the post-factory calibration strategy to obtain the digital aging management unit after the aging margin is updated. Based on the load level of the target chip's usage scenario, the operating mode of the ring oscillator is dynamically adjusted, and the performance of the adjusted ring oscillator is monitored in real time by the digital aging management unit updated according to the aging margin to obtain chip aging information.

2. The chip aging monitoring method according to claim 1, characterized in that, The process involves determining the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on static timing analysis of the target chip and typical real-world waveforms. Based on the static time series analysis results, several initial paths are obtained whose path delay is less than a preset range compared to the preset upper limit threshold. Based on the power consumption analysis tool, all the initial paths are analyzed to obtain the paths with a flip rate greater than a preset threshold within a preset period, which are recorded as the real critical paths covering typical real-world scenarios. Run under preset extreme conditions to obtain several target paths where the difference between the path delay and the preset upper limit threshold is less than a preset range; Based on the power consumption analysis tool, all the target paths are analyzed to obtain the paths with a flip rate greater than a preset threshold within a preset period, which are recorded as artificially constructed paths covering extreme scenarios. All the real critical paths and the artificially constructed paths constitute the target ring oscillator path; wherein, each of the artificially constructed paths and the real critical paths has a separate mask bit, and all the real critical paths and the artificially constructed paths share the control logic.

3. The chip aging monitoring method according to claim 2, characterized in that, The step of determining the number of copies based on the circuit unit configuration requirements of the target chip, and copying the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip includes: The target ring oscillator path is packaged into a single circuit unit; Identify the target module of the circuit unit to be copied; Based on the layout and wiring information of all modules in the target chip, determine the available area of ​​each target module; The target number of copies for each target module is determined based on the available area. The circuit units are configured into each target module according to the target number of copies to obtain the aging monitoring path of the target chip.

4. The chip aging monitoring method according to claim 1, characterized in that, The configuration of a digital aging management unit on the aging monitoring path includes: The digital aging management unit is calibrated according to the pre-shipment calibration strategy; Configure the calibrated digital aging management unit on the aging monitoring path; The calibration of the digital aging management unit according to the pre-shipment calibration strategy includes: A test covering all functional paths in the target chip is performed to obtain a first voltage frequency table; The digital aging management unit was tested to obtain a second voltage frequency table covering the aging monitoring path; Based on the first voltage frequency table and the second voltage frequency table, the fitting relationship between the frequency curves of all typical voltage points and the weight coefficients of each path is obtained, which is denoted as the frequency-weight fitting relationship. Fit all typical voltage points and their corresponding weight coefficients to obtain the fitting relationship between each typical voltage point and its corresponding weight coefficient, which is denoted as the voltage-weight fitting relationship. The frequency-weighted fitting relationship and the voltage-weighted fitting relationship constitute a voltage-frequency fitting curve; The voltage-frequency fitting curve is configured for the digital aging management unit to obtain a calibrated digital aging management unit.

5. The chip aging monitoring method according to claim 4, characterized in that, The step of calibrating the digital aging management unit in the target chip put into use according to the post-factory calibration strategy to obtain the digital aging management unit after aging margin update includes: The first functional self-test is performed on the target chip based on the initial startup voltage and initial startup frequency corresponding to the target chip, and the first test result is obtained. If the first test result is passed, the limiting frequency corresponding to the initial start-up voltage is confirmed according to the voltage-frequency fitting curve. A second functional self-test is performed on the target chip based on the initial startup voltage and the limiting frequency to obtain a second test result. If the second test result is not passed, the frequency is swept downward according to the preset gradient with the limit frequency as the reference frequency, and the target chip is subjected to a functional self-test at each reduced frequency point to obtain a new limit frequency corresponding to the initial start-up voltage when the test is passed; Obtain the difference between the limiting frequency corresponding to the initial start-up voltage and the new limiting frequency, and determine the aging margin update value; The voltage-frequency fitting curve is updated based on the aging margin update value, and the updated voltage-frequency fitting curve is configured to the digital aging management unit to obtain the digital aging management unit with updated aging margin.

6. The chip aging monitoring method according to claim 5, characterized in that, The step of obtaining the difference between the limiting frequency corresponding to the initial start-up voltage and the new limiting frequency, and determining the aging margin update value, includes: Obtain the frequency difference between the limiting frequency corresponding to the initial start-up voltage and the new limiting frequency; If the frequency difference is less than a preset threshold, the minimum value between the limit frequency corresponding to the initial start-up voltage and the new limit frequency is selected as the frequency after chip aging. The target voltage corresponding to the frequency after chip aging is determined based on the voltage-frequency fitting curve. The difference between the target voltage and the start-up voltage is obtained and recorded as the aging margin update value.

7. The chip aging monitoring method according to claim 6, characterized in that, If the frequency difference is not less than a preset threshold, the new limiting frequency will be used as the frequency after aging. The aging frequency is fitted with the limiting frequency corresponding to the initial start-up voltage to obtain a new weighting coefficient for the ring oscillator. The target voltage corresponding to the frequency after aging is determined based on the voltage-frequency fitting curve, and the difference between the target voltage and the starting voltage is obtained and recorded as the aging margin update value.

8. The chip aging monitoring method according to claim 6, characterized in that, The step of updating the voltage-frequency fitting curve based on the aging margin update value, configuring the updated voltage-frequency fitting curve to the digital aging management unit, and obtaining the digital aging management unit with the updated aging margin includes: When the frequency difference is less than a preset threshold, the aging margin update value is added to each voltage in the voltage-frequency fitting curve to obtain an updated voltage-frequency fitting curve. The updated voltage-frequency fitting curve is then configured to the digital aging management unit to obtain the digital aging management unit with the updated aging margin.

9. The chip aging monitoring method according to claim 7, characterized in that, The step of updating the voltage-frequency fitting curve based on the aging margin update value, configuring the updated voltage-frequency fitting curve to the digital aging management unit, and obtaining the digital aging management unit with the updated aging margin includes: When the frequency difference is not less than a preset threshold, the aging margin update value is added to each voltage in the voltage frequency fitting curve to obtain an updated voltage frequency fitting curve. The updated voltage-frequency fitting curve and the new weighting coefficients of the ring oscillator are configured to the digital aging management unit to obtain the digital aging management unit with updated aging margin.

10. The chip aging monitoring method according to claim 1, characterized in that, The process of dynamically adjusting the operating mode of the ring oscillator based on the load level of the target chip's usage scenario, and obtaining chip aging information by real-time monitoring of the adjusted ring oscillator performance by the digital aging management unit updated according to the aging margin, includes: The event data within a preset counting period is obtained based on the circuit event counter; The actual difference between the event data and the preset event threshold is obtained, the actual scene level corresponding to the actual difference is determined according to the preset difference threshold range, and the working mode of the ring oscillator is dynamically adjusted according to the actual scene level. Based on the updated aging margin, the digital aging management unit monitors the performance of the ring oscillator after the working mode adjustment in real time to obtain chip aging information.

11. The chip aging monitoring method according to claim 10, characterized in that, The step of obtaining the actual difference between the event data and a preset event threshold, determining the actual scene level corresponding to the actual difference based on the preset difference threshold range, and dynamically adjusting the working mode of the ring oscillator based on the actual scene level includes: When the actual difference is within the first preset range, the corresponding actual scenario level is determined to be heavy load, and the working mode of the ring oscillator is dynamically adjusted to continuous oscillation. When the actual difference is within the second preset range, the corresponding actual scenario level is determined to be medium load, and the working mode of the ring oscillator is dynamically adjusted to oscillate according to the preset ratio. When the actual difference is within the third preset range, the corresponding actual scenario level is determined to be light load, and the working mode of the ring oscillator is dynamically adjusted to continuous non-oscillation.

12. A chip aging monitoring system, characterized in that, include: The target ring oscillator path construction module is used to determine the target ring oscillator path, which includes several real critical paths and several artificially constructed paths, based on the static timing analysis of the target chip and typical real-world waveforms. The aging monitoring path determination module is used to determine the number of copies based on the circuit unit configuration requirements of the target chip, and copy the target ring oscillator path according to the number of copies to obtain the aging monitoring path of the target chip, and configure a digital aging management unit on the aging monitoring path. The post-shipment calibration module is used to calibrate the digital aging management unit in the target chip to be put into use according to the post-shipment calibration strategy, and to obtain the digital aging management unit after the aging margin is updated. The dynamic working mode adjustment module is used to dynamically adjust the working mode of the ring oscillator according to the load level of the target chip's usage scenario, and to monitor the performance of the adjusted ring oscillator in real time based on the updated digital aging management unit according to the aging margin, so as to obtain chip aging information.

13. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform the chip aging monitoring method according to any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the chip aging monitoring method according to any one of claims 1-11.

15. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the method according to any one of claims 1-11.

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