Field programmable gate array (FPGA) in-situ upgrading system and method for avionics equipment

Abstract

The invention provides an FPGA in-situ upgrading system and method for avionics equipment, and the system comprises an FPGA minimum system which comprises an FPGA chip, a clock circuit, a reset circuit, and a debugging interface circuit; the storage circuit is connected with the FPGA chip and is used for storing a configuration file; the input end of the signal driving circuit is connected to a JTAG pin of the FPGA chip, and the signal driving circuit is used for performing driving enhancement on the JTAG signal; the output end of the signal driving circuit is connected to a pair of external connectors to form an external debugging interface for in-situ upgrading; the impedance matching circuit is used for performing impedance matching on the wiring of the JTAG signal; and the power supply circuit is used for supplying power to the FPGA minimum system, the storage circuit and the signal driving circuit. The system effectively solves the reliability problem of long-distance transmission of the JTAG interface on the premise of keeping the design conciseness of hardware and software. And efficient and convenient in-situ upgrading and debugging of the FPGA in the avionics equipment are realized.

Description

Technical Field

[0001] This application relates to the field of avionics technology, specifically to an FPGA in-situ upgrade system and method for avionics equipment. Background Technology

[0002] With the development of avionics technology, more and more airborne avionics equipment is using FPGA (Field-Programmable Gate Array) as the core controller for equipment control circuits. FPGA needs to load pre-compiled program files from the configuration chip to work properly. FPGA software upgrades are the process of erasing, modifying, and rewriting the program files stored inside the configuration chip to enable it to run according to the new program files.

[0003] FPGA upgrade methods can be divided into two categories. One category utilizes the FPGA's internal soft core, MicroBlaze, or other controller chips (such as MCUs, DSPs, etc.). The FPGA's program upgrade file is sent to the soft core or controller chip via a dedicated program upgrade port (such as a Universal Serial Bus interface, Ethernet interface, etc.), and then written into the configuration chip via a two-to-one selector, thus achieving the FPGA software upgrade. This approach enables long-distance FPGA upgrades, but it significantly increases circuit design costs and software design complexity. The other category uses the FPGA's built-in JTAG (Joint Test Action Group) interface. Using a dedicated FPGA emulator and software, the program file is directly burned into the configuration chip. This method is simple to implement, but due to the poor driving capability of the JTAG signal processor, its signal quality and integrity are easily affected by factors such as transmission distance, transmission line loss, and transmission path. Therefore, JTAG is often used for board-level debugging.

[0004] In the development and maintenance of avionics products, it is often necessary to perform in-situ upgrades and maintenance without opening or moving the chassis. The two methods mentioned above cannot simultaneously meet the requirements of avionics equipment for efficient, convenient, and low-complexity in-situ upgrades. Therefore, there is an urgent need for a simple, efficient, and convenient FPGA in-situ upgrade method. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide an FPGA in-situ upgrade system and method for avionics equipment.

[0006] In a first aspect, this application proposes an in-situ FPGA upgrade system for avionics equipment, comprising: The minimum FPGA system includes the FPGA chip, clock circuit, reset circuit, and debug interface circuit. A storage circuit, connected to the FPGA chip, is used to store configuration files; The signal driving circuit has its input terminal connected to the JTAG pin of the FPGA chip for driving and enhancing the JTAG signal; the output terminal of the signal driving circuit is connected to an external connector to form an external debugging interface for in-situ upgrades. Impedance matching circuit, used to perform impedance matching on the traces of the JTAG signal; A power supply circuit is used to supply power to the FPGA minimum system, the storage circuit, and the signal driving circuit.

[0007] According to the technical solution provided in the embodiments of this application, the storage circuit includes a FLASH chip and a matching resistor connected to the FLASH chip; the FLASH chip communicates with the FPGA chip through an SPI bus; each signal line of the SPI bus is provided with a pull-up resistor, and each signal line is connected in series with a terminating resistor for signal integrity matching.

[0008] According to the technical solution provided in the embodiments of this application, the signal driving circuit includes a driving chip. The input terminal of the driving chip is connected to the JTAG pin of the FPGA chip, and the output terminal is connected to the external connector. The operating voltage of the driving chip is 3.3V, and its key timing parameters meet the following conditions: the average transmission delay time is less than 3 nanoseconds, the output enable time is less than 4 nanoseconds, and the output disable time is less than 7 nanoseconds.

[0009] According to the technical solution provided in the embodiments of this application, the impedance matching circuit controls the characteristic impedance of the PCB trace to match the trace impedance of the JTAG signal to 50 ohms; a pull-up resistor is also connected to the power supply at the JTAG pin lead-out terminal of the FPGA chip to maintain a certain level state of the JTAG signal terminal when there is no external cable connection.

[0010] According to the technical solution provided in the embodiments of this application, the power supply circuit includes a voltage conversion module, which is used to convert a single external input voltage into multiple different stable DC voltages, providing the required operating voltages for the FPGA chip and peripheral circuits in the FPGA minimum system, the FLASH chip in the storage circuit, and the driver chip in the signal driving circuit.

[0011] According to the technical solution provided in the embodiments of this application, the pull-up resistor has a resistance of 4.7 kΩ and the terminating resistor has a resistance of 33 Ω.

[0012] According to the technical solution provided in the embodiments of this application, the resistance value of the pull-up resistor is 10 kΩ.

[0013] According to the technical solution provided in the embodiments of this application, the driver chip is positioned close to the external connector in the circuit board layout.

[0014] According to the technical solution provided in the embodiments of this application, the input voltage of the voltage conversion module is 5V, and the output voltage includes at least 3.3V, 1.8V and 1V, so as to meet the operating voltage requirements of the signal driving circuit, the storage circuit and the FPGA minimum system respectively.

[0015] Secondly, this application proposes an in-situ FPGA upgrade method, employing the FPGA in-situ upgrade system described above, comprising the following steps: Connect one end of the FPGA downloader to the external debugging interface and the other end to the host computer; The host computer runs FPGA programming software and establishes JTAG communication with the FPGA chip via the FPGA downloader and the external debugging interface. The FPGA programming software is used to perform erase and write operations on the configuration file in the FPGA chip or the storage circuit to achieve in-situ debugging or upgrade of the FPGA.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: First, while maintaining the simplicity of hardware and software design, the reliability problem of long-distance transmission of JTAG interface is effectively solved: by setting up an independent signal driving circuit to enhance the JTAG signal and configuring an impedance matching circuit to ensure signal integrity, the driving capability and anti-interference of JTAG signal are effectively improved without introducing additional complex controllers or increasing the burden of FPGA internal logic design, enabling it to adapt to longer-distance transmission and providing a reliable physical basis for in-situ upgrades.

[0017] Second, it enables efficient and convenient in-situ upgrades and debugging of FPGAs within avionics equipment: By leading the enhanced JTAG signal to the outside of the device via an external connector, a dedicated external debugging interface is formed. This allows maintenance personnel to directly access the JTAG chain of the internal FPGA and perform operations such as erasing and programming configuration files without disassembling the equipment; they only need to connect a standard FPGA programmer through the external interface. This system perfectly meets the core requirements of the aviation industry for efficient, convenient, and low-complexity in-situ maintenance.

[0018] Third, it provides complete, reliable, and self-contained upgrade system hardware support: The system is a fully functional hardware module that integrates the FPGA minimum system, non-volatile memory circuitry, drive and impedance matching circuitry required for signal conditioning, and a unified power supply circuit. This integrated design ensures that the upgrade function does not depend on specific resources of other parts of the equipment. The system itself has complete configuration, storage, and upgrade interface capabilities, high reliability, and is easy to integrate as an independent functional module into various avionics devices, with strong environmental adaptability.

[0019] In summary, this technical solution overcomes the challenge of signal quality degradation in traditional JTAG interfaces over long distances and complex paths by employing a pure hardware signal conditioning path of driver enhancement and impedance matching. It successfully transforms the JTAG interface, originally only suitable for board-level debugging, into a reliable channel capable of meeting the stringent in-situ upgrade requirements of avionics equipment. This solution achieves an excellent balance between circuit design complexity, implementation cost, and the reliability of upgrade functions. Attached Figure Description

[0020] Figure 1 A system schematic diagram of an FPGA in-situ upgrade system for avionics equipment provided in an embodiment of this application; Figure 2 The schematic diagram of the FPGA minimum system and memory circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the signal driving circuit provided in an embodiment of this application; Figure 4 A schematic diagram of a power module provided for an embodiment of this application; Figure 5 This is a schematic diagram of the FPGA in-situ upgrade method provided in an embodiment of this application. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Example 1 As mentioned in the background section, in view of the problems in the prior art, this application proposes an FPGA in-situ upgrade system for avionics equipment, such as... Figure 1 As shown, it includes: The minimum FPGA system includes the FPGA chip, clock circuit, reset circuit, and debug interface circuit. A storage circuit, connected to the FPGA chip, is used to store configuration files; The signal driving circuit has its input terminal connected to the JTAG pin of the FPGA chip for driving and enhancing the JTAG signal; the output terminal of the signal driving circuit is connected to an external connector to form an external debugging interface for in-situ upgrades. Impedance matching circuit, used to perform impedance matching on the traces of the JTAG signal; A power supply circuit is used to supply power to the FPGA minimum system, the storage circuit, and the signal driving circuit.

[0024] In a preferred embodiment, the storage circuit includes a FLASH chip and a matching resistor connected to the FLASH chip; the FLASH chip communicates with the FPGA chip via an SPI bus; each signal line of the SPI bus is provided with a pull-up resistor, and each signal line is connected in series with a terminating resistor for signal integrity matching.

[0025] In a preferred embodiment, the signal driving circuit includes a driver chip, the input terminal of which is connected to the JTAG pin of the FPGA chip, and the output terminal is connected to the external connector; the operating voltage of the driver chip is 3.3V, and its key timing parameters meet the following conditions: average transmission delay time is less than 3 nanoseconds, output enable time is less than 4 nanoseconds, and output disable time is less than 7 nanoseconds.

[0026] In a preferred embodiment, the impedance matching circuit controls the characteristic impedance of the PCB traces to match the trace impedance of the JTAG signal to 50 ohms; a pull-up resistor is also connected to the power supply at the JTAG pin of the FPGA chip to maintain a certain level of the JTAG signal when there is no external cable connection.

[0027] In a preferred embodiment, the power supply circuit includes a voltage conversion module for converting a single externally input voltage into multiple different stable DC voltages, providing the required operating voltages for the FPGA chip and peripheral circuits in the FPGA minimum system, the FLASH chip in the storage circuit, and the driver chip in the signal driving circuit.

[0028] In a preferred embodiment, the pull-up resistor has a resistance of 4.7 kΩ and the terminating resistor has a resistance of 33 Ω.

[0029] In a preferred embodiment, the pull-up resistor has a resistance of 10 kilohms.

[0030] In a preferred embodiment, the driver chip is positioned close to the external connector on the circuit board layout.

[0031] In a preferred embodiment, the input voltage of the voltage conversion module is 5V, and the output voltage includes at least 3.3V, 1.8V and 1V, so as to meet the operating voltage requirements of the signal driving circuit, the storage circuit and the FPGA minimum system, respectively.

[0032] Specifically, such as Figure 1 As shown, this embodiment provides an FPGA in-situ upgrade system for avionics equipment. This system aims to address the problem that traditional JTAG interfaces, due to their weak signal driving capability and poor integrity, cannot meet the in-situ upgrade requirements of aviation equipment. Through hardware circuit enhancement and optimization, it achieves reliable and convenient remote JTAG debugging and upgrades.

[0033] Overall system composition: The FPGA in-situ upgrade system mainly consists of five parts: the FPGA minimum system, the storage circuit, the signal driving circuit, the impedance matching circuit, and the power supply circuit. These parts work together to form a complete hardware module that can independently complete FPGA configuration and accept remote programming through an enhanced external interface.

[0034] Specific implementation methods for each component: FPGA Minimum System: Reference Figure 2 The FPGA minimum system is the core control unit of the upgrade system, and its core is an FPGA chip. In this embodiment, the JFMK50 series chip (specifically model JFMK50T4-AS) from Fudan Microelectronics Co., Ltd. is used as an example for illustration, but the present invention is not limited to this model, and other FPGA chips with JTAG interface and SPI controller functions can also be applied.

[0035] Clock circuit: Provides a stable operating clock for the FPGA chip, typically consisting of a crystal oscillator, load capacitors, and possibly matching resistors (such as...). Figure 2 It consists of a resistor R2 (typically 20 ohms) to ensure clock signal quality.

[0036] Reset circuit: Provides power-on reset and manual reset signals for the FPGA chip to ensure reliable system startup.

[0037] Debugging interface circuit: This part mainly refers to the JTAG logic interface integrated inside the FPGA chip, which conforms to the IEEE 1149.1 standard. Its physical pins (including TMS, TCK, TDI, TDO, etc.) will be brought out to the outside for subsequent signal driving.

[0038] Storage circuitry: Storage circuitry is used to non-volatilely store the FPGA's configuration file (bit file). For example... Figure 2 As shown, the core of this circuit is a FLASH chip. This embodiment uses the EFM25QL256 SPI NORFLASH from Fudan Microelectronics as an example, which has a storage capacity of 256Mb.

[0039] Communication method: The FLASH chip communicates with the FPGA chip via a serial peripheral interface (SPI bus). The FPGA acts as the SPI master controller, responsible for sending commands and addresses to the FLASH chip and reading and writing configuration data.

[0040] Signal integrity design: To ensure communication reliability in the complex electromagnetic environment of avionics, special processing was performed on the SPI bus signals: Pull-up design: All SPI signal lines (such as CS#, CLK, DI / O0, DI / O1, etc.) are connected to the 3.3V power supply through a 4.7kΩ pull-up resistor R3 to ensure that the bus is in a defined logic high level when idle, preventing false triggering due to interference.

[0041] Termination Matching: A 33-ohm termination matching resistor R1 is connected in series on each SPI signal path. The main function of this resistor is to dampen signal reflection, especially at higher frequencies or with longer traces, effectively improving signal waveform, enhancing signal integrity, and ensuring the accuracy of configuration data loading. Signal driving circuit: such as Figure 3 As shown, the signal driving circuit is the key to improving the JTAG signal transmission capability of this invention.

[0042] Circuit Structure and Connections: The core of this circuit is a dedicated bus driver chip. The input terminals of the driver chip are directly connected to the JTAG pins (TMS, TCK, TDI, and TDO for receiving output) of the FPGA chip. The output terminals of the driver chip are directly connected to an external connector (such as a board-to-board connector or a high-speed cable connector). This external connector constitutes the externally visible upgrade and debugging interface of the device.

[0043] Chip selection requirements: The selected driver chip must meet specific electrical and timing performance requirements to ensure transparent, low-latency driving of high-speed JTAG signals.

[0044] Operating voltage: 3.3V single power supply, compatible with FPGA I / O voltage.

[0045] Timing parameters: To avoid significantly increasing the timing overhead of the JTAG chain, the average transmission delay of the driver chip should be less than 3 nanoseconds. Simultaneously, its switching performance must meet the following requirements: output enable time less than 4 nanoseconds, and output disable time less than 7 nanoseconds. In this embodiment, a high-speed, low-power bus driver such as the 54LVC244 is selected, which can meet the above requirements.

[0046] Layout requirements: To minimize path loss and radiation interference between the drive output and the interface, the signal drive circuit (driver chip) should be placed as close as possible to the external connector during the layout of the printed circuit board (PCB).

[0047] Impedance matching circuit: The impedance matching circuit is used to control the characteristic impedance of high-speed JTAG signals in the PCB transmission path to prevent distortion caused by signal reflection.

[0048] Trace impedance control: During the PCB design phase, the characteristic impedance of JTAG signal traces is designed to be 50 ohms by precisely calculating and controlling the trace width, spacing between the trace and the reference layer, and dielectric material. This is a standard impedance value commonly used in high-speed digital signal transmission and can form a good match with most test cables and interfaces.

[0049] Anti-floating design: At the JTAG pin exit points of the FPGA chip (i.e., before the signal enters the driver chip), each JTAG signal line is connected to a 3.3V power supply through a 10kΩ pull-up resistor R4. The main purpose of this design is to ensure that these signal pins are pulled high and in a defined non-floating state when no external JTAG download cable is connected, thus avoiding internal logic abnormalities or unnecessary power consumption caused by floating pins.

[0050] Power supply circuit: such as Figure 4 As shown, the power supply circuit provides a stable and clean DC operating voltage for the entire upgrade system. At the core of the power supply circuit is a voltage conversion module (such as a DC-DC converter or a low-dropout linear regulator). Its function is to efficiently and reliably convert a single input voltage (5V in this embodiment) introduced from the avionics backplane or external source into multiple voltages required by the various chips within the system. Output voltages: Typically, this module needs to generate at least three output voltages: 3.3V: Powers the driver chip of the signal drive circuit, the FLASH chip of the storage circuit, and part of the I / O bank of the FPGA chip. 1.8V: Powers the auxiliary voltage of the FPGA chip core or part of the bank in the FPGA minimum system. 1.0V: Powers the core logic voltage of the FPGA chip in the FPGA minimum system. By providing these precise voltages, the power supply circuit ensures that critical components such as the FPGA, FLASH, and driver chips operate stably at their respective nominal voltages.

[0051] The FPGA in-situ upgrade system of this invention can be integrated as a standard functional module into any avionics equipment (such as radar processing units, communication controllers, display controllers, etc.) with this requirement. During integration, the external connector of this system is interconnected with the connectors of other internal boards of the equipment. Finally, through cascading, the JTAG upgrade signal path is routed to the external connector of the avionics equipment (such as the maintenance port on the equipment chassis). This design allows the internal FPGA to be accessed through external ports even when the equipment is completely sealed and the chassis is not opened.

[0052] Example 2 Based on Example 1, this example proposes an in-situ FPGA upgrade method, which uses the FPGA in-situ upgrade system described above and includes the following steps: Connect one end of the FPGA downloader to the external debugging interface and the other end to the host computer; The host computer runs FPGA programming software and establishes JTAG communication with the FPGA chip via the FPGA downloader and the external debugging interface. The FPGA programming software is used to perform erase and write operations on the configuration file in the FPGA chip or the storage circuit to achieve in-situ debugging or upgrade of the FPGA.

[0053] like Figure 5 As shown, based on the above-described FPGA in-situ upgrade system, this invention also provides an FPGA in-situ upgrade method. The implementation steps of this method are as follows: Step S1: Hardware Connection: Reliably connect the interface of a standard FPGA emulator (such as a USB Blaster, Xilinx PlatformCable, etc.) to the upgrade and debugging interface (i.e., the final extension of the external connector of this system) on the avionics equipment via an adapter cable. Connect the other end of the FPGA emulator (usually a USB interface) to a host computer (such as a portable computer) running FPGA development software.

[0054] Step S2: Establish Communication: Launch the dedicated programming software provided by the FPGA manufacturer (e.g., Intel's Quartus Prime, AMD / Xilinx's Vivado, or ISE) on the host computer. This software will automatically or manually identify the connected FPGA downloader. The user selects the corresponding FPGA device model (e.g., JFMK50T4-AS) through the software interface. The software will establish a stable communication link with the JTAG interface of the target FPGA chip via the downloader, the device's external interface, internal cables, and finally the signal drive circuit in this invention. Thanks to signal drive and impedance matching, communication remains reliable even on long paths (proven to exceed 1 meter and pass through multiple connectors).

[0055] Step S3: Perform the upgrade operation: After communication is established, the user can perform the following operations in the host computer software: Debugging: The new configuration file can be directly downloaded to the SRAM of the FPGA chip for execution and functional verification. This process is called in-situ debugging.

[0056] Firmware Upgrade: Select the configuration file (.bit or .mcs file) to be programmed, and use software commands to erase and program the FLASH chip in the storage circuit. After programming is complete, the FPGA can be instructed to reload the configuration from the FLASH, and the new program will start running, thus completing a full in-situ upgrade. Throughout the process, users do not need to disassemble the avionics equipment, achieving efficient and convenient remote maintenance.

[0057] Actual testing showed that the avionics system using this embodiment maintained stable and reliable JTAG communication even after connecting cables longer than 1 meter and passing through multiple plug-in connectors inside and outside the equipment. This successfully completed multiple debugging and program firmware upgrades of the internal FPGA. This demonstrates that the system effectively enhances the driving capability and integrity of the JTAG signal, solving the problem of unreliable long-distance transmission using traditional methods. Without increasing the complexity of the FPGA's internal logic or adding extra controller costs, it perfectly meets the in-situ upgrade requirements of aviation equipment.

[0058] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. An in-situ FPGA upgrade system for avionics equipment, characterized in that, include: The minimum FPGA system includes the FPGA chip, clock circuit, reset circuit, and debug interface circuit. A storage circuit, connected to the FPGA chip, is used to store configuration files; A signal driving circuit, whose input terminal is connected to the JTAG pin of the FPGA chip, is used to drive and enhance the JTAG signal; The output of the signal driving circuit is connected to an external connector to form an external debugging interface for in-situ upgrades. Impedance matching circuit, used to perform impedance matching on the traces of the JTAG signal; A power supply circuit is used to supply power to the FPGA minimum system, the storage circuit, and the signal driving circuit.

2. The FPGA in-situ upgrade system for avionics equipment according to claim 1, characterized in that: The storage circuit includes a FLASH chip and a matching resistor connected to the FLASH chip; the FLASH chip communicates with the FPGA chip via an SPI bus; each signal line of the SPI bus is equipped with a pull-up resistor, and each signal line is connected in series with a terminating resistor for signal integrity matching.

3. The FPGA in-situ upgrade system for avionics equipment according to claim 1, characterized in that: The signal driving circuit includes a driver chip. The input terminal of the driver chip is connected to the JTAG pin of the FPGA chip, and the output terminal is connected to the external connector. The operating voltage of the driver chip is 3.3V, and its key timing parameters meet the following conditions: average transmission delay time is less than 3 nanoseconds, output enable time is less than 4 nanoseconds, and output disable time is less than 7 nanoseconds.

4. The FPGA in-situ upgrade system for avionics equipment according to claim 1, characterized in that: The impedance matching circuit controls the characteristic impedance of the PCB traces to match the JTAG signal trace impedance to 50 ohms; a pull-up resistor is also connected to the power supply at the JTAG pin of the FPGA chip to maintain a fixed level of the JTAG signal when there is no external cable connection.

5. The FPGA in-situ upgrade system for avionics equipment according to claim 1, characterized in that: The power supply circuit includes a voltage conversion module, which converts a single externally input voltage into multiple different stable DC voltages to provide the required operating voltages for the FPGA chip and peripheral circuits in the FPGA minimum system, the FLASH chip in the storage circuit, and the driver chip in the signal driving circuit.

6. The FPGA in-situ upgrade system for avionics equipment according to claim 2, characterized in that: The pull-up resistor has a resistance of 4.7 kΩ and the terminating resistor has a resistance of 33 Ω.

7. The FPGA in-situ upgrade system for avionics equipment according to claim 4, characterized in that: The pull-up resistor has a resistance of 10 kΩ.

8. The FPGA in-situ upgrade system for avionics equipment according to claim 3, characterized in that: The driver chip is positioned close to the external connector in the circuit board layout.

9. The FPGA in-situ upgrade system for avionics equipment according to claim 5, characterized in that: The voltage conversion module has an input voltage of 5V and an output voltage of at least 3.3V, 1.8V, and 1V to meet the operating voltage requirements of the signal driving circuit, the storage circuit, and the FPGA minimum system, respectively.

10. An in-situ FPGA upgrade method, characterized in that, The FPGA in-situ upgrade system as described in any one of claims 1 to 9 includes the following steps: Connect one end of the FPGA downloader to the external debugging interface and the other end to the host computer; The host computer runs FPGA programming software and establishes JTAG communication with the FPGA chip via the FPGA downloader and the external debugging interface. The FPGA programming software is used to perform erase and write operations on the configuration file in the FPGA chip or the storage circuit to achieve in-situ debugging or upgrade of the FPGA.

Images