SRAM memory computing anti-radiation test method and system based on running state injection

Abstract

The application relates to the technical field of SRAM storage and calculation anti-radiation test, and discloses an SRAM storage and calculation anti-radiation test method and system based on running state injection, which comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; model quantization compilation, sensitivity analysis and physical bit candidate generation; running state injection plan generation and test case loading; running state execution, disturbance injection and synchronous monitoring collection; multi-source triggering, weight reading back and fault decoupling decision; anti-radiation performance quantitative evaluation, degradation curve construction and report output. The system and the method correspond to each other. The application constructs a hardware-in-the-loop running state injection and online evaluation technology, and realizes the technical problems of a guided disturbance / equivalent radiation injection based on weight bit level sensitivity and logic-physical mapping.

Description

Technical Field

[0001] This application relates to the field of SRAM in-memory radiation resistance testing technology, specifically a method and system for SRAM in-memory radiation resistance testing based on runtime injection. Background Technology

[0002] Existing radiation resistance testing techniques for SRAM in-memory computing chips mainly include static data retention testing and pure software fault injection simulation. The former requires the chip to maintain its storage state without performing analog operations. Although it can accurately detect static bit flips (SEUs) in memory cells, its test state is severely disconnected from the chip's actual "running state" of performing neural network inference, failing to activate the dynamic operating states of the sensitive amplifier, ADC, and bit line current convergence path. As a result, transient interference (SET) caused by radiated particles to the analog computing circuit and the risk of single-event lock-up (SEL) induced under dynamic current cannot be captured, leading to low test coverage and seriously overlooking critical functional vulnerabilities of the chip under real dynamic computing scenarios.

[0003] On the other hand, while fault injection methods using pure software simulation can simulate error propagation at the algorithm level, they rely on idealized digital fault models and completely ignore the unique analog nonlinear characteristics of in-memory computing chips and the charge sharing effect at the physical layout level. Furthermore, existing simplified dynamic testing schemes typically use idealized digital results as the gold standard for comparison, without considering the inherent quantization noise and process deviations in analog in-memory computing. Due to the lack of online calibration criteria based on perturbation-free reference output and current fingerprint baselines, and the absence of hardware evidence such as weighted readback consistency verification for decoupling "memory" and "computing" faults, these methods are significantly deficient in fault location accuracy and decision accuracy. They are prone to misjudging inherent analog computing errors / noise as irradiation faults (high misjudgment rate) or failing to distinguish whether the source of the error is data flipping in the memory cell or transient deviations in the runtime computing link.

[0004] In summary, existing technologies generally suffer from technical deficiencies such as static testing modes, lack of physical realism, inability to decouple fault mechanisms, high false positive rates due to simulation noise, and a lack of targeted testing for critical weights. These problems are particularly pronounced when in-memory computing chips are applied to high-reliability aerospace and nuclear industries, limiting their widespread application in radiation hardening design verification, screening, and on-orbit health assessment.

[0005] To address the aforementioned technical deficiencies, there is an urgent need for a new technical solution for testing the radiation resistance performance of SRAM in-memory computing chips based on runtime injection. Summary of the Invention

[0006] The purpose of this application is to provide a method and system for testing the radiation resistance of SRAM computing based on runtime injection, so as to solve the technical problem of how to construct a hardware-in-the-loop runtime injection and online evaluation technology during the runtime process of SRAM-CIM chip performing neural network inference tasks, and realize the technical problem of guidance and position-constrained disturbance / equivalent radiation injection based on weight bit-level sensitivity and logic-physical mapping.

[0007] To achieve the above objectives, this application provides a method for testing the radiation resistance of SRAM memory based on runtime injection, the method comprising:

[0008] S10: System initialization, mapping preparation, and timing baseline establishment; used to complete the following before the test begins: system power-on self-test and communication establishment, working point configuration of the SRAM-type in-memory computing chip under test, availability confirmation of logical-physical address mapping relationship, timing calibration and delay compensation of injection / sampling links, establishment of normal operating current fingerprint baseline, and traceability registration of key versions and parameters; after completing S10, the system enters the ready state for executable model mapping and sensitivity analysis;

[0009] S20: Model quantization compilation, sensitivity analysis, and physical bit candidate generation; used to complete the fixed-point processing of the neural network model, the organization and mapping of logical weights on the memory array, the sensitivity calculation and sorting at the quantization bit level before test execution, and to generate a set of physical sensitive bit candidates for subsequent runtime injection based on the logical-physical mapping relationship; after completing S20, the following are obtained: quantized model parameters, logical storage layout, sensitivity map, physical sensitive bit candidate set and its confidence and version traceability information, providing input for the runtime injection plan generation of S30;

[0010] S30: Runtime Injection Plan Generation and Test Case Loading; used to generate a deterministic runtime injection plan based on the obtained physical sensitive bit candidate set; the injection plan takes the physical injection location, runtime window, trigger condition, injection parameters, sampling strategy, and readback strategy as core elements to form a set of structured test cases, and completes loading and traceability registration; after completing S30, all the necessary control information for executing runtime injection and synchronous monitoring is available in real time;

[0011] S40: Run-state execution, disturbance injection, and synchronous monitoring and acquisition; used to inject disturbances into specified physical locations according to the run-state injection plan when the tested SRAM-type in-memory computing chip is performing real inference / in-memory computing tasks, and to perform synchronous data acquisition and event association labeling before and after the injection event occurs; the synchronously acquired data includes at least: calculation output data, chip running state data, and power domain current / voltage transient data, and evidence features are formed based on the current transient data; the acquisition and labeling results are written for fault decoupling decision of S50;

[0012] S50: Multi-source triggering, weighted readback, and fault decoupling decision; used to trigger and execute the fault decoupling decision process based on computational output anomaly evidence, current fingerprint anomaly evidence, and readback consistency evidence after each running-state injection event; this process distinguishes between single-event latch-up, stored soft errors, and computational soft errors in the same test closed loop, and outputs fault labels, confidence levels, and traceable evidence sets, providing structured input for the quantitative evaluation of S60's radiation resistance performance;

[0013] S60: Quantitative assessment of radiation resistance performance, construction of degradation curves and report output; used to summarize and statistically analyze the injection event data, fault tags and evidence vectors formed from S40 to S50, obtain the occurrence characteristics of stored soft errors, computational soft errors and single-event latch-up under different injection conditions, and construct the mapping relationship between injection intensity and computational correctness at the application level, forming a computational correctness degradation curve and a multi-dimensional radiation resistance assessment index set, generating a traceable assessment report and outputting it.

[0014] To achieve the above objectives, this application also provides a radiation resistance testing system for SRAM memory based on runtime injection, applying the radiation resistance testing method for SRAM memory based on runtime injection as described above. The system includes a host computer control subsystem, a real-time main control unit, a radiation resistance injection and monitoring interface module, a tested SRAM-type memory chip, a fault judgment and evaluation processing unit, an address translation and physical mapping verification unit, a timing calibration and delay compensation unit, a current fingerprint feature extraction and spectrum analysis unit, and a test data and version traceability management unit. The host computer control subsystem is responsible for test task planning and algorithm-side processing. The real-time main control unit is responsible for timing execution and trigger control; the radiation-resistant injection and monitoring interface module is responsible for disturbance injection and power status monitoring; the SRAM-type in-memory computing chip under test performs in-memory calculations in the running state as the test object; the fault judgment and evaluation processing unit makes judgments and evaluations on multi-source data; the address translation and physical mapping verification unit provides logical-physical coordinate bridging; the timing calibration and delay compensation unit provides nanosecond-level alignment support; the current fingerprint feature extraction and spectrum analysis unit provides latch-up / transient / flip current evidence; and the test data and version traceability management unit is used to ensure the reproducibility and traceability of the test process and results.

[0015] Beneficial effects: The SRAM in-memory computing radiation resistance testing method and system based on runtime injection achieves runtime window alignment between injection triggering and sampling through runtime window identification, timing calibration, and delay compensation; under the condition of no power interruption and recoverable operation process, it collects computation output and power supply current transient information online, and performs readback consistency verification of relevant weights / addresses after abnormal triggering; it integrates multi-source evidence such as "current fingerprint - storage readback - computation output" to establish calibration criteria, reducing misjudgments caused by inherent simulation errors / noise, thereby decoupling and quantitatively evaluating failure mechanisms such as SEU, runtime computing link transient faults (SET / computational soft errors) and SEL, so as to meet the requirements of accurate quantification and self-diagnosis of dual failure mechanisms of "storage" and "computation" in complex radiation environment for SRAM in-memory computing chips. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 System module connection diagram of the SRAM in-memory radiation resistance test system based on runtime injection provided for the implementation of this application;

[0018] Figure 2 The diagram shows the internal connections of key modules provided in the embodiments of this application; in the diagram: (a) is the internal structure of the host computer control subsystem 1; (b) is the internal structure of the real-time main control unit 2; (c) is the internal structure of the radiation-resistant injection and monitoring interface module 3; (d) is the internal structure of the fault judgment and evaluation processing unit 5; (e) is a simplified block diagram of the supporting modules of the address translation and physical mapping verification unit 6, the timing calibration and delay compensation unit 7, the current fingerprint feature extraction and spectrum analysis unit 8, and the test data and version traceability management unit 9;

[0019] Figure 3 The overall flowchart of the SRAM in-memory radiation resistance testing method based on runtime injection provided in the embodiments of this application;

[0020] Figure 4 A schematic diagram illustrating the guidance-sensitive bit filtering and runtime injection plan generation provided in this application embodiment;

[0021] Figure 5 This is a schematic diagram of the runtime window alignment, injection, and sampling timing provided in the embodiments of this application;

[0022] Figure 6This is a schematic diagram illustrating the readback range positioning and address list generation provided in an embodiment of this application.

[0023] Figure 7 A schematic diagram illustrating fault decoupling decision-making based on multi-source evidence fusion provided in an embodiment of this application;

[0024] In the diagram: 1. Host computer control subsystem; 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. SRAM-type in-memory computing chip under test; 5. Fault judgment and evaluation processing unit; 6. Address translation and physical mapping verification unit; 7. Timing calibration and delay compensation unit; 8. Current fingerprint feature extraction and spectrum analysis unit; 9. Test data and version traceability management unit; 11. Neural network model quantization and compilation module; 12. In-memory array physical address mapping module; 13. Weight sensitivity analysis module; 14. Running state injection plan generation module; 15. Test data analysis and report generation module; 21. Injection control state machine; 22. Dual clock domain synchronization control module; 23. Running state window recognition module; 24. Data caching and forwarding module; 31. Programmable perturbation injection circuit. 32. High-bandwidth current monitoring circuit; 33. Voltage and current protection unit; 34. Analog signal acquisition interface; 51. Weight readback and consistency verification module; 52. Calculation output error analysis module; 53. Current transient characteristic analysis module; 54. Fault type judgment module; 61. Logical-physical address translation module; 62. Mapping table loading and parsing module; 63. Mapping consistency verification module; 71. Injection link delay measurement module; 72. IO delay compensation parameter generation module; 73. Clock phase alignment and jitter evaluation module; 81. Current waveform feature extraction module; 82. Spectrum / time-frequency analysis module; 83. Fingerprint database matching and threshold determination module; 91. Test metadata registration module; 92. Mapping table and threshold version management module; 93. Injection parameter and log storage module.

[0025] The implementation, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0027] In this document, the term "comprising" is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] The following is a summary of the technical features and effects of the SRAM in-memory radiation resistance testing method and system based on runtime injection in this embodiment.

[0029] This embodiment injects spatiotemporally coordinated guided perturbations within the runtime window of the chip performing neural network inference tasks. Combined with runtime window identification, timing calibration, and delay compensation, it achieves precise alignment between injection triggering and synchronous sampling. Simultaneously, it establishes a baseline of unperturbed reference output and normal operating current fingerprint. Upon abnormal triggering, it performs weight / address readback consistency verification, fusing multi-source evidence from "current fingerprint—memory readback—computation output" to form an online decision. This enables decoupled decision-making, independent characterization, and quantitative evaluation of failure mechanisms such as SEU, runtime computing link transient faults (SET / computational soft errors), and SEL. This approach avoids the omissions of dynamic computing faults in traditional static testing and the distortion of physical effects in pure software evaluation. It balances dynamic realism, high fault location accuracy, low false positive rate, and high testing efficiency, providing hardware-level testing support for radiation hardening design verification, reliability screening, and on-orbit health assessment of in-memory computing chips.

[0030] The following explains the terminology of the SRAM in-memory radiation resistance testing method and system based on runtime injection in this embodiment.

[0031] SRAM Compute-in-Memory (SRAM-CIM) refers to a new chip architecture that breaks through the "memory wall" bottleneck of the traditional von Neumann architecture. It utilizes the analog circuit characteristics of SRAM memory cells (usually using the superposition principle of bit line current or charge) to directly perform logical operations such as matrix multiplication and addition (MAC) within the memory array, realizing "computation in memory" rather than moving data to the processor for computation.

[0032] Operational State / Runtime: In this embodiment, it specifically refers to the working state where the SRAM in-memory computing chip has loaded neural network model weights and is continuously executing inference tasks. In this state, the chip's word lines are frequently turned on, the sensor amplifier (SA) and analog-to-digital converter (ADC) are in active working mode, and there is analog computing current on the bit lines, which is different from the "static storage state" that only maintains data retention.

[0033] Single Event Effects (SEE): These are the various radiation effects triggered when a single high-energy particle (such as a heavy ion, proton, or neutron) enters the sensitive region of a semiconductor device, generating electron-hole pairs through ionizing radiation. This embodiment focuses on the following three types:

[0034] Single-event upset (SEU): refers to a change in the logical state of an SRAM memory cell caused by a particle bombardment (such as 0 becoming 1). It is a soft error that can be recovered by rewriting and corresponds to the "memory error" in this embodiment.

[0035] Single-event transient (SET): refers to a transient voltage / current pulse generated by a particle bombardment simulation circuit (such as a sensitive amplifier or bit line), which causes quantization errors in the simulation calculation results, but does not change the weight data in the storage unit. This corresponds to the "computational error" in this embodiment.

[0036] ③ Single Event Lockout (SEL): This refers to the phenomenon where a particle bombardment triggers the parasitic thyristor structure in a CMOS circuit, resulting in a low-resistance path between the power supply and ground, generating a continuous large current, which is a potential hard damage.

[0037] Sensitivity Map: This refers to the mapping between the weight importance at the neural network algorithm level and the memory address at the chip physical level. This map quantifies the impact of each physical memory bit flipping on the final neural network inference accuracy, and is used to guide the selection of "targets" for fault injection.

[0038] Spatiotemporal Synergistic Injection: This embodiment proposes a fault injection strategy. "Spatial" refers to controlling the radiation source or injection logic to precisely target highly sensitive physical regions of the chip based on the sensitivity map; "temporal" refers to using FPGA synchronization technology to precisely trigger the injection within the time window (i.e., the running state window) when the chip is performing simulated MAC operations, in order to maximize the excitation of computational faults.

[0039] Fault decoupling refers to the process of accurately classifying chip output errors into "storage cell flip (SEU)," "analog computation interference (SET)," or "device lock-in (SEL)" through specific testing procedures and decision logic. This is the core technology that distinguishes this embodiment from traditional testing, which generally categorizes errors as "soft errors."

[0040] Current fingerprint: refers to the transient current waveform characteristics of the chip's power domain (VDD) acquired through a high-bandwidth sampling circuit during testing. In this embodiment, the current fingerprint is used to identify single-event lockout (current surge) in real time and to analyze abnormal transient fluctuations during simulation calculations.

[0041] MAC (Multiply-Accumulate Operation): This is the most fundamental operator in Convolutional Neural Networks (CNNs). In SRAM-CIM, this operation is typically implemented by enabling multiple word lines simultaneously, utilizing the current flowing across the bit lines in the analog domain.

[0042] Fingerprint Deviation: In this embodiment, it refers to the difference measure (such as Euclidean distance or correlation coefficient) between the real-time acquired transient current waveform and the preset reference current waveform (Golden Waveform) under normal operating conditions, which is used to help determine whether there is non-destructive analog domain radiation interference.

[0043] Golden Model: Refers to a high-precision reference model running in an FPGA or host computer, used to generate the expected correct inference results. In this invention, the Golden Model specifically refers to a calibrated reference model that includes compensation for simulation non-ideals, used for real-time comparison with the actual simulation calculation results of the SRAM-CIM chip.

[0044] Top-K Selection Strategy: In the injection target selection step of this embodiment, this refers to a selection algorithm based on sensitivity ranking. Specifically, based on the sensitivity map, only the top K physical storage bits or top K word lines that have the greatest impact on the neural network inference accuracy are selected as the target set for fault injection. This strategy aims to prioritize the evaluation of the system's weakest link within a limited testing time.

[0045] Runtime window / gating refers to a specific time segment (typically on the nanosecond scale) during a full clock cycle of an SRAM-based in-memory computing chip when it actually performs analog current pooling and sensor amplifier (SA) sampling. "Gating" means that the FPGA uses this time window signal as a mask to ensure that fault injection or radiation triggering is only effective within this time period, thereby accurately simulating computational faults.

[0046] Evidence Chain: This refers to a set of causally related data formed during the testing process in this embodiment, including: the time and location coordinates of injection / irradiation, the power supply current fingerprint characteristics at that moment, the corresponding SRAM readback data status, and the final calculation output error. This evidence chain is used in later analysis to logically and rigorously prove that a certain calculation failure was caused by a specific type of fault (such as SET or SEU).

[0047] CCVLE (Computation Voltage Linear Error): refers to the deviation between the actual output voltage and the ideal linearly superimposed voltage caused by factors such as bit line resistance and transistor nonlinearity when an SRAM in-memory computing chip performs multi-line data accumulation in the analog domain. In this embodiment, this term is used to explain why the Golden model requires "non-ideal calibration".

[0048] Injection Intensity: In this embodiment, it is a comprehensive physical quantity. For laser injection, it refers to the energy (nJ) and pulse width of the laser pulse; for radiation sources, it refers to the linear energy transfer (LET) value or flux rate of the particles. This parameter is used to construct a degradation curve between injection intensity and calculation accuracy to evaluate the chip's radiation safety margin.

[0049] Storage-to-Computation Failure Ratio: This embodiment proposes a quantitative evaluation metric, defined as the ratio of the number of "storage errors (data flips)" to the number of "computation errors (only incorrect calculation results)" occurring in a chip under the same radiation environment. This metric reflects the imbalance in radiation resistance between the chip's memory cells and peripheral analog computing circuits at the manufacturing process level.

[0050] The following is a general description of the overall technical solution of the SRAM in-memory radiation resistance testing method and system based on runtime injection in this embodiment.

[0051] This embodiment proposes a radiation resistance testing method and system for SRAM in-memory computing based on runtime injection. This technical solution targets SRAM-type in-memory computing chips operating in space radiation environments, high-energy particle environments, or other strong radiation application scenarios. By constructing a hardware-in-the-loop (HIL) testing system, timing-controlled and location-restricted perturbation injections are applied to the memory cells and their related simulated computing paths while the chip is executing real in-memory computing tasks. The resulting memory failure behavior and computing performance degradation are then monitored, classified, and quantitatively evaluated online.

[0052] Specifically, this embodiment does not perform simple irradiation or equivalent disturbance tests on SRAM cells in the traditional static hold state or no-load test state. Instead, it performs injection operations within the operating state window formed by word line opening, bit line dynamic discharge, and simulated accumulated current. This allows the test process to truly reproduce the electrical stress conditions and timing sensitivity distribution of in-memory computing chips in typical application scenarios such as neural network inference and matrix-vector multiplication.

[0053] Unlike existing radiation resistance testing methods that rely solely on Single Event Upset (SEU) statistics, this embodiment does not use single-bit error statistics as an evaluation metric. Instead, it introduces a multi-source joint decision mechanism that considers computational output consistency, current transient characteristics, and weighted readback results. This mechanism further maps storage-type soft errors, computational soft errors, and latch-up-like abnormal behaviors caused by irradiation or equivalent disturbances at the microscopic level into computational correctness degradation curves and reliability indicators at the storage and computation result level.

[0054] This embodiment enables a refined, quantitative, and application-aware evaluation of the radiation resistance performance of SRAM-type in-memory computing chips without disrupting the normal operation of the chip. This allows for a more realistic and comprehensive reflection of the reliability performance of such chips in practical engineering applications.

[0055] Reference Figure 1 , Figure 1 System module connection diagram of the SRAM-based radiation resistance testing system based on runtime injection provided for the implementation of this application.

[0056] like Figure 1As shown, this embodiment discloses a radiation resistance testing system for SRAM in-memory computing based on runtime injection, including a host computer control subsystem 1, a real-time main control unit 2, a radiation resistance injection and monitoring interface module 3, a SRAM-type in-memory computing chip under test 4, a fault judgment and evaluation processing unit 5, an address translation and physical mapping verification unit 6, a timing calibration and delay compensation unit 7, a current fingerprint feature extraction and spectrum analysis unit 8, and a test data and version traceability management unit 9; wherein, the host computer control subsystem 1 is responsible for test task planning and algorithm-side processing; the real-time main control unit 2 is responsible for timing execution and trigger control. The system includes: a radiation-resistant injection and monitoring interface module 3 responsible for disturbance injection and power status monitoring; a SRAM-type in-memory computing chip 4 serving as the test object performing in-memory calculations in runtime; a fault judgment and evaluation processing unit 5 judging and evaluating multi-source data; an address translation and physical mapping verification unit 6 providing logical-physical coordinate bridging; a timing calibration and delay compensation unit 7 providing nanosecond-level alignment support; a current fingerprint feature extraction and spectrum analysis unit 8 providing latch-up / transient / flip current evidence; and a test data and version traceability management unit 9 ensuring the reproducibility and traceability of the test process and results.

[0057] In the specific application of this embodiment, the above-mentioned components constitute a closed-loop test system through a high-speed communication interface, a power interface, and a debugging interface.

[0058] The host computer control subsystem 1 is used to complete the planning, model processing, and result evaluation of test tasks. It includes at least the following functional modules: neural network model quantization and compilation module 11, in-memory array physical address mapping module 12, weight sensitivity analysis module 13, runtime injection plan generation module 14, and test data analysis and report generation module 15. The host computer control subsystem 1 outputs key configuration data and control commands for the test process, including: model quantization results, weight and address related information, sensitivity ranking information, injection plan parameter set, and test result analysis and report data.

[0059] The real-time master control unit 2 is composed of a field-programmable gate array (FPGA) or equivalent programmable logic device, and is mainly used to implement timing control and injection triggering with nanosecond-level precision. This unit includes at least: an injection control state machine 21, a dual-clock domain synchronization control module 22, a running-state window identification module 23, and a data buffering and forwarding module 24. The real-time master control unit 2 receives control commands and injection plans from the host computer control subsystem 1, and completes the timing organization of running-state window control, injection triggering coordination, and data acquisition and forwarding during the testing process.

[0060] The radiation-resistant injection and monitoring interface module 3 is located between the real-time main control unit 2 and the SRAM-type in-memory computing chip under test 4, and is used to realize disturbance injection, power supply monitoring and protection functions. This module includes at least: a programmable disturbance injection circuit 31, a high-bandwidth current monitoring circuit 32, a voltage and current protection unit 33, and an analog signal acquisition interface 34. The radiation-resistant injection and monitoring interface module 3 is used to implement disturbance injection under control triggering, while simultaneously monitoring and acquiring power domain current, voltage and related analog signals, and providing a protection action interface when abnormal electrical characteristics occur.

[0061] The SRAM-type in-memory computing chip under test 4 includes at least: an SRAM in-memory array, storage mode and in-memory mode switching control logic, sensing amplification and analog computing circuitry, and data output and debugging interface. During the test, the SRAM-type in-memory computing chip under test operates under a real neural network inference task load and performs in-memory computation operations such as matrix-vector multiplication in in-memory mode, thereby providing a radiation-resistant testable object and a computation output data channel under operating conditions.

[0062] The fault judgment and evaluation processing unit 5 is used to analyze the data collected during the test. It includes at least: a weight readback and consistency verification module 51, a calculation output error analysis module 52, a current transient characteristic analysis module 53, and a fault type judgment module 54. This unit is used to decouple the judgment of stored soft errors and computational soft errors, and generate a comprehensive evaluation result output for radiation resistance performance.

[0063] The address translation and physical mapping verification unit 6 provides bridging capabilities between logical and physical information during the testing process. It includes at least: a logical-to-physical address translation module 61, a mapping table loading and parsing module 62, and a mapping consistency verification module 63. This unit outputs physical bit coordinates, physical area location information, and mapping consistency verification results, providing support for targeted injection and readback positioning.

[0064] The timing calibration and delay compensation unit 7 supports precise alignment of the running window and control of the injection trigger time. It includes at least: an injection link delay measurement module 71, an IO delay compensation parameter generation module 72, and a clock phase alignment and jitter evaluation module 73. This unit outputs delay compensation parameters, phase alignment status, and timing stability evaluation results, providing a prerequisite for nanosecond-level injection and synchronous acquisition.

[0065] The current fingerprint feature extraction and spectrum analysis unit 8 is used to process and analyze the dynamic characteristics of the power domain current. It includes at least: a current waveform feature extraction module 81, a spectrum / time-frequency analysis module 82, and a fingerprint database matching and threshold determination module 83. This unit is used to output current fingerprint features and anomaly criteria results, providing auxiliary evidence input for fault type determination and improving the reliability and stability of latch-up anomaly identification.

[0066] The Test Data and Version Traceability Management Unit 9 is used for traceability management of key data and configurations throughout the entire testing process. It includes at least: a test metadata registration module 91, a mapping table and threshold version management module 92, and an injection parameter and log storage module 93. This unit records and manages model versions, mapping table versions, injection plan parameters, threshold configurations, and key log information during the testing process, ensuring the reproducibility and traceability of test results. (Refer to...) Figure 2 , Figure 2 This is a diagram showing the internal connections of key modules provided in the embodiments of this application.

[0067] Reference Figure 3 , Figure 3 The overall flowchart of the SRAM in-memory radiation resistance testing method based on runtime injection provided in the embodiments of this application is shown.

[0068] like Figure 3 As shown, this embodiment discloses a method for testing the radiation resistance of SRAM memory based on runtime injection. The method includes:

[0069] S10: System initialization, mapping preparation and timing baseline establishment.

[0070] Specifically, S10 includes:

[0071] S101: Power-on initialization, self-test, and basic communication handshake. Components involved: 1. Host computer control subsystem; 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. Fault judgment and assessment processing unit; 5. Test data and version traceability management unit.

[0072] After the system is powered on, the host computer control subsystem 1 sequentially initiates self-test commands to the real-time main control unit 2, the radiation-resistant injection and monitoring interface module 3, and the fault judgment and evaluation processing unit 5, and establishes a basic communication link.

[0073] In the specific application of this embodiment, the first The time when the handshake request is sent is The corresponding response reception time is Then the first The round-trip delay for each communication is defined as:

[0074]

[0075] For continuous The handshake is measured once, and the average round-trip delay is calculated. With delay jitter The calculation formula is as follows:

[0076]

[0077]

[0078] Once the communication link is established, the host computer control subsystem 1 writes the self-test status words returned by each component into the test data and version traceability management unit 9 to form an initialization event record.

[0079] S101 enables the confirmation of basic communication availability and archiving of self-test status between the core components of the system, providing a prerequisite for subsequent configuration and synchronization processes.

[0080] S102: Confirmation of the working point loading and running status of the SRAM-type in-memory computing chip under test. Components involved: 1. Host computer control subsystem; 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. SRAM-type in-memory computing chip under test; 5. Test data and version traceability management unit.

[0081] The host computer control subsystem 1 loads the array structure parameters, working voltage and operating frequency configuration of the SRAM-type in-memory computing chip 4 under test, and sends them to the SRAM-type in-memory computing chip 4 under test through the real-time main control unit 2 to enter the predetermined working state.

[0082] In the specific application of this embodiment, the operating voltage setting value of the tested SRAM-type in-memory computing chip is... The operating clock frequency setting value is After configuration, the radiation-resistant injection and monitoring interface module 3 monitors the power domain, with a data acquisition time window of [time window value missing]. Obtain voltage sampling sequence And calculate the average voltage. With voltage fluctuation standard deviation The calculation formula is as follows:

[0083]

[0084]

[0085] The real-time main control unit 2 simultaneously reads the status flags of the tested SRAM-type in-memory computing chip 4 to confirm that the chip is in a running state capable of executing in-memory computing tasks (including mode status and interface handshake status). The host computer control subsystem 1 then processes the operating point parameters for this step. Recorded in Test Data and Version Tracking Management Unit 9.

[0086] Through S102, the loading and power supply stability of the tested SRAM-type in-memory computing chip at four working points were quantitatively recorded, providing a consistent electrical benchmark for subsequent operational state injection and monitoring.

[0087] S103: Logical-Physical Address Mapping Loading and Consistency Verification. Components involved: Host computer control subsystem 1, Address Translation and Physical Mapping Verification Unit 6, SRAM-type In-Memory Computing Chip Under Test 4, Real-Time Main Control Unit 2, Test Data and Version Traceability Management Unit 9. This step is used to establish and confirm the logical-physical address mapping relationship required for subsequent injection and readback. Host computer control subsystem 1 loads the mapping table or mapping configuration data into the Address Translation and Physical Mapping Verification Unit 6, and the logical-physical address translation module 61 generates the mapping relationship.

[0088] In the specific application of this embodiment, the logical bit coordinates are defined as follows: Physical position coordinates are The mapping function is denoted as:

[0089]

[0090] Where: logical bit coordinates Logical locations such as layers, indices, and bits used to describe model weights; physical bit coordinates. Used to describe the physical location in a chip array, such as array rows and columns and bit offsets; This represents a logical-to-physical address mapping function.

[0091] Mapping consistency verification module 63 generates a set of verification addresses. The real-time main control unit 2 coordinates the tested SRAM-type in-memory computing chip 4 to perform write / readback verification at the corresponding positions, and obtains the consistency indicator of each verification point. The corresponding mathematical expression is:

[0092]

[0093] in: This represents the number of mapping verification points; For the first Each verification point indicates consistency. Based on this, the mapping consistency coefficient is defined. The range of values ​​is The corresponding mathematical expression is:

[0094]

[0095] Address translation and physical mapping verification unit 6 will The version identifier and verification result are provided to the host computer control subsystem 1, and then written into the test data and version traceability management unit 9 by the host computer control subsystem 1.

[0096] S103 enables the confirmation of the availability of the mapping relationship on which injection positioning and readback positioning depend, and forms a traceable mapping consistency record.

[0097] S104: Timing calibration and delay compensation loading for runtime window alignment. Components involved: Timing calibration and delay compensation unit 7, real-time main control unit 2, radiation-resistant injection and monitoring interface module 3, SRAM-type in-memory computing chip under test 4, and test data and version traceability management unit 9. This step is used to establish the alignment relationship between the disturbance injection trigger time and the runtime window of the SRAM-type in-memory computing chip under test 4, and to determine the delay compensation parameters of the injection link and the sampling link.

[0098] In the specific application of this embodiment, the total delay of the injection trigger output from the real-time main control unit 2 to the radiation-resistant injection and monitoring interface module 3 and acting on the tested SRAM-type in-memory computing chip 4 is: The total latency of the sampling link from the radiation-resistant injection and monitoring interface module 3 to the real-time main control unit 2 buffer is: The latency measurement module 71 of the timing calibration and delay compensation unit 7 and the clock phase alignment and jitter evaluation module 73 measure the latency of the injected link. and The compensation parameters are generated by the IO latency compensation parameter generation module 72. Specifically:

[0099] Define the injection trigger advance as It is used to ensure that the actual arrival time of the injection falls within the running state window:

[0100]

[0101] in: A safety margin is provided to cover delay drift and jitter.

[0102] Meanwhile, to ensure that the sampled data and the injected events are correlated on the timeline, the sampling time alignment compensation is defined as follows: ,and .

[0103] Real-time main control unit 2 will and The data is loaded into the dual-clock domain synchronization control module 22 and injected into the control state machine 21, and the phase alignment status and compensation parameters are written into the test data and version traceability management unit 9.

[0104] S104 enables the loading of alignment support parameters between injection trigger and runtime window, as well as the establishment of a time correlation benchmark between injection events and sampled data.

[0105] S105: Establishment and registration of normal operating current fingerprint baseline and threshold configuration. Components involved: Radiation-resistant injection and monitoring interface module 3, current fingerprint feature extraction and spectrum analysis unit 8, SRAM-type in-memory computing chip under test 4, real-time main control unit 2, test data and version traceability management unit 9. This step is used to establish a power domain current baseline fingerprint under undisturbed conditions, serving as a reference input for subsequent anomaly identification and evidence fusion.

[0106] In the specific application of this embodiment, during the execution of a predetermined memory computing task load by the SRAM-type in-memory computing chip 4 under test, the power supply current waveform is collected by the high-bandwidth current monitoring circuit 32. The sampling time window is The signal is then sent to the current fingerprint feature extraction and spectrum analysis unit 8 via the analog signal acquisition interface 34. Specifically:

[0107] Define the mean current With current fluctuation standard deviation :

[0108]

[0109]

[0110] Current waveform feature extraction module 81 pairs Extracting temporal feature sets This includes peak value, current rise time duration, energy, etc.; 82 pairs of spectrum / time-frequency analysis modules. Perform frequency domain or time-frequency domain transformation to obtain the frequency domain feature set. The fingerprint database matching and threshold determination module 83 will... It is registered together with the current test threshold configuration as the "normal operating current fingerprint baseline".

[0111] In this step, the real-time main control unit 2 adds an empty injection event identifier to the current sampling data and writes the baseline fingerprint version number and threshold version number into the test data and version traceability management unit 9.

[0112] S105 enables the establishment of current baseline evidence and traceable registration of threshold configuration required for subsequent SEL / SET / abnormal electrical behavior decisions.

[0113] S106: Initialize parameter vector registration and set system ready flag. Components involved: Host computer control subsystem 1, fault judgment and evaluation processing unit 5, test data and version traceability management unit 9.

[0114] After steps S101 to S105 are completed, the host computer control subsystem 1 summarizes the key configuration and verification results generated in this step to form an initialization parameter vector. This data is then written into the test data and version traceability management unit 9. The initialization parameter vector is defined as follows:

[0115]

[0116] The meanings of the variables are consistent with those in the steps described above.

[0117] At the same time, the host computer control subsystem 1 generates a test batch identifier. And recorded by the test data and version traceability management unit 9. and The binding relationship. Finally, the host computer control subsystem 1 sets the system ready flag:

[0118]

[0119] After receiving the ready flag, the fault judgment and evaluation processing unit 5 enters the pending judgment state and waits for the input of subsequent steps (i.e., S20–S60).

[0120] S106 enables unified registration of key parameters during the initialization phase, establishment of batch-level traceability information, and setting of ready conditions for the system to enter the next phase.

[0121] S20: Model Quantization Compilation, Sensitivity Analysis, and Physical Bit Candidate Generation. Components involved: Host computer control subsystem 1, SRAM-type in-memory computing chip under test 4, Address Translation and Physical Mapping Verification Unit 6, Test Data and Version Traceability Management Unit 9. This step is used to complete the fixed-point processing of the neural network model, the organization and mapping of logical weights on the in-memory array, the sensitivity calculation and sorting at the quantization bit level, and generate a "physical sensitive bit candidate set" that can be used for subsequent runtime injection, based on the logical-physical mapping relationship. After completing this step, the system obtains: quantized model parameters, logical storage layout, sensitivity map, physical bit candidate set and its confidence and version traceability information, providing input for the subsequent runtime injection plan generation in S30.

[0122] Specifically, S20 includes:

[0123] S201: Model fixed-point quantization and compilation processing. Components involved: Host computer control subsystem 1, test data and version traceability management unit 9.

[0124] In this specific application, the neural network model quantization and compilation module 11 of the host computer control subsystem 1 performs fixed-point quantization and compilation processing on the neural network model to be tested, converts floating-point weights into fixed-point weight representations, and outputs the quantization scale and bit width configuration. Specifically:

[0125] Define floating-point weights and fixed-point weights, and let the model's... Layer (or first) The floating-point weight matrix of the parameter tensor is as follows: , where the element is After quantization, a fixed-point weight matrix is ​​obtained. , where the element is .

[0126] Define the quantization scale and quantization mapping, and define the quantization scale coefficient for each layer. (Used to map floating-point to fixed-point), bit width is (Unit: bits). When using symmetric saturated fixed-point quantization, the fixed-point representation range is:

[0127]

[0128] The quantization mapping from floating point to fixed point is defined as follows:

[0129]

[0130] in: This indicates rounding to the nearest integer. This represents a saturation cutoff function that restricts the result to a fixed-point range.

[0131] Quantization error and consistency records provide a benchmark for subsequent sensitivity analysis. The host computer control subsystem 1 records the quantization error matrix.

[0132]

[0133] in, This represents the quantization error.

[0134] The host computer control subsystem 1 will As a quantitative output, the quantitative configuration (bit width, scale, and quantitative method identifier) ​​is written into the test data and version traceability management unit 9 to form a quantitative version record.

[0135] S201 enables an executable conversion of the model from the floating-point domain to the fixed-point domain and establishes the quantization weights and quantization parameter benchmarks required for subsequent "bit-level sensitivity evaluation".

[0136] S202: Logical storage layout generation and physical bit coordinate set acquisition. Components involved: Host computer control subsystem 1, address translation and physical mapping verification unit 6, test data and version traceability management unit 9. This step organizes the quantized logical weights into a logical storage layout that can be mapped to the SRAM storage array, and obtains the corresponding physical bit coordinate set through the address translation and physical mapping verification unit 6, providing a foundation for subsequent "directional injection and positioning". Specifically:

[0137] Logical bit coordinate definition for quantization weights any element Define its first Bits (counted from least significant bit to most significant bit) The corresponding logical bit coordinates are:

[0138]

[0139] in: Presentation layer index; Indicates the index within the weight matrix; Indicates bit index; Represents the logical bit coordinates.

[0140] Logical memory layout generation: The physical address mapping module 12 of the in-memory computing array in the host computer control subsystem 1 generates the logical memory layout based on the array organization parameters of the SRAM-type in-memory computing chip 4 under test (such as array partitioning, memory word width, bank organization, and other structural parameters, all of which are derived from the parameter loading record of S10). The logical storage layout is defined by the mathematical expression of a set of logical bit coordinates:

[0141]

[0142] in: The total number of logical bits involved in the mapping; Indicates the first Each logical bit coordinate.

[0143] The logical-physical mapping and physical bit coordinate set output are used by the host computer control subsystem 1 to output the logical bit set. The data is sent to the address translation and physical mapping verification unit 6. The logical-to-physical address translation module 61 then uses the available mapping function confirmed in S10. Converting logical bit coordinates to physical bit coordinates is:

[0144]

[0145] in: For the first The physical bit coordinates corresponding to each logical bit; This is the logical-to-physical address mapping function (same as S10). This forms the set of physical bit coordinates:

[0146]

[0147] The host computer control subsystem 1 will and The mapping relationship index, mapping version number, and mapping consistency coefficient (From S10) Write test data and version traceability management unit 9.

[0148] S202 enables the logical layout construction of quantization weight bits and the acquisition of physical location information, providing the necessary coordinate system for the subsequent sensitivity results to "fall into physical positions".

[0149] S203: Bit-level sensitivity index calculation and sensitivity map generation. Components involved: Host computer control subsystem 1, Test data and version traceability management unit 9. This step is used to calculate the coordinates of each logical bit. The degree of influence on the correctness of the model output is used to form a sensitivity index, and a sensitivity ranking set and sensitivity map are generated. Specifically:

[0150] Referring to the definitions of the reference output and loss function, the input sample set used for sensitivity evaluation is: ,in This represents the sample size. The model applies weights to the sample size under quantized weight parameters. The output is The reference output is The loss function is defined as follows: The average loss under the current quantization model is... for:

[0151]

[0152] The bit-flip perturbation operator is defined for any logical bit coordinate. Define the bit-flipping perturbation operator Quantize weights The Bit flipping yields the perturbed weights The disturbance is defined as:

[0153]

[0154] in: This indicates a bitwise XOR operation; For the first Bit mask of bits.

[0155] The sensitivity metric is defined as follows (incremental loss form): the average loss of the model after flipping only this bit is denoted as... The sensitivity index of this logic bit is defined as the loss increment. Its mathematical expression is: .

[0156] To facilitate cross-level comparisons, the sensitivity can also be normalized, and a normalized sensitivity can be defined. Its mathematical expression is: ,in, To avoid positive constants with a denominator of zero.

[0157] Sensitivity ranking set and sensitivity map, host computer control subsystem 1 pair Calculate all logical bits or This forms a sensitivity set, the mathematical expression of which is: And press Sort the data in descending order to obtain the sensitivity-sorted set. Simultaneously, a sensitivity map is generated. It stores sensitivity values ​​using layers / array blocks / bit planes as indices for subsequent physical domain projection and filtering.

[0158] The host computer control subsystem 1 writes the sensitivity calculation configuration (sample set identifier, loss function identifier, disturbance operator identifier, sensitivity version number) into the test data and version traceability management unit 9.

[0159] S203 enables a quantifiable description and ranking output of the influence of quantization bits on model output, providing a basis for subsequent "limited injection to cover the worst case".

[0160] S204: Physical domain projection, candidate screening, and traceability registration of the sensitivity map. Components involved: Address translation and physical mapping verification unit 6, host computer control subsystem 1, test data and version traceability management unit 9. This step is used to project the sensitivity map from the logical domain to the physical domain and based on the mapping consistency coefficient... A candidate set of physically sensitive bits is generated based on the filtering threshold. Specifically:

[0161] Physical domain sensitivity assignment; for each logical bit Its physical position coordinates are , logical sensitivity Projecting onto physical bits to define physical sensitivity ,in, For physical position The sensitivity value, For the corresponding logical bit sensitivity.

[0162] Mapping consistency weighted and confidence level definition. To reflect the impact of mapping consistency on the reliability of physical location, physical location confidence level is defined. ,in, For physical position Confidence level, The mapping consistency coefficient (from S10, with values...) ), Normalization sensitivity (from S203).

[0163] Candidate filtering and candidate set output. Let the candidate filtering threshold be... (Set and version managed by the host computer control subsystem 1), then the candidate set of physical sensitive bits is defined as:

[0164]

[0165] At the same time, a set of candidate entries is formed:

[0166]

[0167] in: The candidate selection threshold; A candidate set of physically sensitive bits; The set of candidate items includes sensitivity and confidence.

[0168] Address translation and physical mapping verification unit 6 will and The output is sent to the host computer control subsystem 1. The host computer control subsystem 1 will then send the candidate set, threshold version number, mapping version number, sensitivity version number, and... Write test data and version traceability management unit 9.

[0169] S204 enables the conversion from "logically sensitive bits" to "physically injectable bits", generates physical candidate inputs for subsequent runtime injection plans, and completes versioned traceability registration of the candidate set.

[0170] S30: Runtime Injection Plan Generation and Test Case Loading. Components involved: Host computer control subsystem 1, real-time main control unit 2, SRAM-type in-memory computing chip under test 4, address translation and physical mapping verification unit 6, timing calibration and delay compensation unit 7, test data and version traceability management unit 9. This step generates a runtime injection plan that can be deterministically executed by the real-time main control unit 2 based on the obtained physical sensitive bit candidate set. The injection plan uses "physical injection location - runtime window - trigger condition - injection parameters - sampling strategy - readback strategy" as its core elements to form a structured test case set, and completes loading and traceability registration. After completing this step, the real-time main control unit 2 has all the necessary control information to perform runtime injection and synchronous monitoring.

[0171] Specifically, S30 includes:

[0172] S301: Injection target set filtering and injection sequence generation. Components involved: Host computer control subsystem 1, address translation and physical mapping verification unit 6, test data and version traceability management unit 9.

[0173] In the specific application of this embodiment, the host computer control subsystem 1 is based on the physical sensitive bit candidate set output by S20. and candidate item set Generate an injection target set and form an injection sequence. Define the injection target entries as follows:

[0174]

[0175] in: For the first One injection target entry; Physical position coordinates; For physical sensitivity; For physical confidence level (same as S20).

[0176] Let the upper limit of the number of injection targets be Candidate entries are sorted by Sort the sequence from largest to smallest. And select an injection target set that meets the target number constraint. .

[0177] To ensure spatial coverage and avoid target clustering, the host computer control subsystem 1 defines a physical distance function. Used to measure the distance between two physical coordinates and to set a minimum spacing threshold. This ensures that the target set for injection satisfies:

[0178]

[0179] For candidate entries that do not meet the constraint, the host computer control subsystem 1 skips them according to the sorting order and selects subsequent entries until a result that meets the constraint is formed. .

[0180] The injection sequence is defined as an ordered arrangement of the injection targets. , ,in, This is a sequence index mapping function used to represent the execution order.

[0181] The host computer control subsystem 1 will , , , Configuration parameters are written into the test data and version traceability management unit 9 to form a traceability record of the injection target and sequence.

[0182] S301 enables the structured generation of a candidate set of physically sensitive bits into a set of executable injection targets and an injection sequence. (See reference...) Figure 4 , Figure 4 This is a schematic diagram of the guidance-sensitive bit screening and runtime injection plan generation provided in the embodiments of this application.

[0183] S302: Determining the runtime injection time window and constructing trigger conditions. Components involved: Real-time main control unit 2, SRAM-type in-memory computing chip under test 4, timing calibration and delay compensation unit 7, host computer control subsystem 1. This step is used to determine the runtime injection time window for each injection target during the inference / in-memory computing task execution process of the SRAM-type in-memory computing chip under test 4, and to construct the trigger conditions that the real-time main control unit 2 can determine. Specifically:

[0184] For the first Injection target Define the running window as ,in: For the first One injection window; The start time of the window; This is the time when the window ends.

[0185] The running state window recognition module 23 of the real-time main control unit 2 generates a window flag signal by reading the status signal of the tested SRAM-type in-memory computing chip 4. ,in, Used to indicate whether the running window is open.

[0186] Definition of the first The set of triggering conditions for each target is ,in, The number of trigger condition entries; For the first There are 10 trigger condition entries, and each trigger condition entry is described by a state criterion and a time offset. The corresponding mathematical expression is:

[0187]

[0188] in: The operating status criterion for the tested SRAM-type in-memory computing chip 4 is defined by a combination of status signals; This is the trigger offset relative to the start of the window.

[0189] To ensure that the injection actually acts within the running window, the real-time main control unit 2 uses the injection trigger advance amount loaded in S10 when triggering the output. (Variables are the same as in S10). Regarding the target... The trigger output time is defined as ,in: This refers to the trigger moment output by the real-time main control unit 2. The reference time (located within the running window) is the time when the injection effect is expected to be applied to the SRAM-type in-memory computing chip under test. This is the injection trigger advance (from S10).

[0190] The host computer control subsystem 1 will display the running state window of each target. With trigger condition set The organization triggers the description item and sends it to the real-time main control unit 2.

[0191] S302 enables the description of the association between the injection target and the running window, as well as the construction of real-time triggering conditions.

[0192] S303: Runtime Injection Plan Generation and Loading. Components involved: Host computer control subsystem 1, real-time main control unit 2, timing calibration and delay compensation unit 7, address translation and physical mapping verification unit 6. This step generates a structured runtime injection plan and loads it to the real-time main control unit 2 for subsequent execution. Specifically:

[0193] For the There are injection targets, and the injection parameter vector is defined as follows: ,in: For the disturbance amplitude parameter; This is the duration parameter of the disturbance; The parameter is the number of times the perturbation is repeated.

[0194] Define the sampling strategy associated with the injection event as follows: ,in: This is the length of the sampling window before injection; This is the length of the sampling window after injection; This is a configuration item for the sampling frequency.

[0195] Define the readback strategy as follows ,in: Description of the readback address range; This is the trigger condition for readback; Configuration item for readback consistency check mode.

[0196] Considering the injection location, runtime window, triggering conditions, injection parameters, sampling strategy, and readback strategy, define the first... The injection plan entries are: ,in: To inject physical position coordinates; This is a running window; For the set of triggering conditions; Inject parameter vector; Sampling strategy; This is a readback strategy.

[0197] Define the complete runtime injection plan as follows ,in: The target quantity is to be injected (same as S301).

[0198] The host computer control subsystem 1 will The data is sent to the real-time master control unit 2, which then parses the plan and loads it into the injection control state machine 21, the dual-clock domain synchronization control module 22, the running state window identification module 23, and the data cache and forwarding module 24.

[0199] S303 enables the structured generation and real-time loading of runtime injection plans, ensuring deterministic execution conditions for subsequent runtime injections.

[0200] S304: Injection plan and configuration version are written to the traceability management unit. Components involved: Test data and version traceability management unit 9, host computer control subsystem 1, real-time main control unit 2. This step is used to version-register the runtime injection plan and related configurations, ensuring that the data and decision results generated during execution correspond one-to-one with specific plans, specific thresholds, and specific sampling and readback strategies. Specifically:

[0201] The host computer control subsystem 1 generates a version identifier for the injection plan. And generate summary values ​​for the plan content. Used to uniquely identify the content of the plan, and Write test data and version traceability management unit 9.

[0202] Test data and version traceability management unit 9 will include the following configuration items with Binding Registration: Candidate Filtering Threshold (From S20), Target number of injections Spatial constraint threshold (From S301), Injection Trigger Advance Compensation amount aligned with sampling time (From S10), and each program entry Sampling strategy With readback strategy The real-time main control unit 2 writes a loading confirmation flag to the test data and version traceability management unit 9. , used to indicate Loading is complete and execution is ready.

[0203] S304 enables the traceability registration and loading confirmation of injection plans and critical configurations, providing a plan version baseline for subsequent execution phases.

[0204] S40: Run-state execution, disturbance injection, and synchronous monitoring and acquisition. Components involved: 1. Host computer control subsystem; 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. SRAM-type in-memory computing chip under test; 5. Fault judgment and evaluation processing unit; 6. Timing calibration and delay compensation unit; 7. Current fingerprint feature extraction and spectrum analysis unit; 8. Test data and version traceability management unit; 9. This step is used to perform the actual inference / in-memory computing task on the SRAM-type in-memory computing chip under test 4, according to the run-state injection plan. (From S30) A disturbance injection is performed at a designated physical location, and synchronous data acquisition and event association labeling are carried out before and after the injection event. The synchronously acquired data includes at least: calculation output data, chip operating status data, and power domain current / voltage transient data. The current transient data is sent to the current fingerprint feature extraction and spectrum analysis unit 8 to form evidence features. The acquisition and labeling results are written into the test data and version traceability management unit 9 for subsequent fault decoupling decision-making in S50.

[0205] Specifically, S40 includes:

[0206] S401: Initiates the running task of the SRAM-type in-memory computing chip under test and enters the running state monitoring. Components involved: 1. Host computer control subsystem; 2. Real-time main control unit; 4. SRAM-type in-memory computing chip under test; 9. Test data and version traceability management unit. Specifically:

[0207] The host computer control subsystem 1 sends a task start command to the real-time main control unit 2 according to the task configuration of the neural network under test, and coordinates the tested SRAM-type in-memory computing chip 4 to enter the in-memory computing mode and execute the inference / in-memory computing task through the real-time main control unit 2. The task number is The task start timestamp is The real-time master control unit 2 sets the global event counter to zero and generates a task event flag at the start of the task. .

[0208] The real-time main control unit 2 continuously monitors the operating status signal of the tested SRAM-type in-memory computing chip 4 through the running state window recognition module 23, and generates a running state window gating flag. (Same as S30) so that subsequent injection entries can be made. Trigger control is executed within the corresponding running window. Real-time main control unit 2 will... The task start confirmation information is written into the test data and version traceability management unit 9 to form a task-level traceability record.

[0209] The S401 was used to start the running task of the SRAM-type in-memory computing chip under test, open the running state window recognition channel, and establish the task-level event identifier.

[0210] S402: Disturbance injection triggering and execution within the running window. Components involved: 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. SRAM-type in-memory computing chip under test; 7. Timing calibration and delay compensation unit; 9. Test data and version traceability management unit. Specifically:

[0211] Real-time main control unit 2 injects the plan according to the running state. The injection entries are executed sequentially, among which, And the meaning of the variables is the same as in S30. For the first... Each injection entry, the real-time main control unit 2, satisfies the running window gating... And the set of triggering conditions When any one of the conditions is met, an injection trigger output is generated. Let the reference time for meeting the trigger condition be... Then the real-time main control unit (2) outputs the trigger time as follows: ,in: For the first The next injection triggers the output time; The reference time for the expected injection effect into the SRAM-type in-memory computing chip under test; This is the injection trigger advance (from S10).

[0212] After receiving a trigger signal, the radiation-resistant injection and monitoring interface module 3 is activated by the programmable perturbation injection circuit 31 according to the injection parameter vector. Perform disturbance injection. Define the first... The actual perturbation waveform injected next time is Then it satisfies the following during the injection duration. ,in: For the first The amplitude representation of the injected disturbance waveform; To inject amplitude parameters; This is the injection duration parameter; The start time at which the disturbance actually acts on the tested SRAM-type in-memory computing chip 4.

[0213] Due to the delay in the triggering chain, the actual injection start time and trigger output time satisfy... ,in, The total delay of the injected link (derived from the measurement and compensation system of S10).

[0214] Real-time main control unit 2 generates injection event identifiers for each injection. ,in: Inject the planned version identifier (from S30); For the injection entry sequence number; To inject physical position coordinates; To trigger the output, the real-time main control unit 2 will... Write test data and version traceability management unit 9 to form an injection event index; simultaneously, write the injection parameters... It is stored in association with the corresponding entry index for event backtracking in subsequent judgments.

[0215] S402 enables condition triggering, disturbance injection execution, and injection event identifier generation within the running window.

[0216] S403: Synchronous acquisition and time calibration of computational output data and power domain transient data. Components involved: 2. Real-time main control unit; 3. Radiation-resistant injection and monitoring interface module; 4. SRAM-type in-memory computing chip under test; 7. Timing calibration and delay compensation unit; 9. Test data and version traceability management unit. Specifically:

[0217] In the Before and after the injection event occurs, the real-time main control unit 2 follows the sampling strategy. The organization collects data synchronously, and the collection time window is defined as follows: ,in: This is the length of the sampling window before injection; This is the length of the sampling window after injection.

[0218] The tested SRAM-type in-memory computing chip 4 outputs the calculation result data stream through the data output and debugging interface, defining the first... The output sequence associated with the second injection is ,in, The output sampling sequence number is used. The real-time main control unit 2 appends a timestamp to the output data and forms an output data record. ,in: For the first The second injection Each output timestamp; This corresponds to the output value or vector.

[0219] Radiation-resistant injection and monitoring interface module 3 acquires power domain current waveforms through high-bandwidth current monitoring circuit 32. The signal is then output to the real-time main control unit 2 via the analog signal acquisition interface 34 or directly to the subsequent analysis path. To unify the time reference, the real-time main control unit 2 compensates for the current sampling time axis, using the sampling time alignment compensation amount in S10. (Same as S10), the compensated current timestamp is defined as follows: ,in: This is the original timestamp for current sampling; The timestamp after compensation; This refers to the current sampling point number; This is used for sampling time alignment compensation. Current data is recorded based on this. ,in: For the first Current values ​​at each sampling point.

[0220] Real-time main control unit 2 will record the output data With current data recording With injection event identifier The event index system of the test data and version traceability management unit 9 is linked and written to ensure that the injected events, output changes and current transients are traceable on the same time axis.

[0221] The S403 microcontroller enables synchronous acquisition, time alignment, and event-related storage of the output and current transients before and after injection. (See reference...) Figure 5 , Figure 5 This is a schematic diagram of the runtime window alignment, injection, and sampling timing provided in the embodiments of this application.

[0222] S404: Current fingerprint feature extraction, spectrum analysis, and anomaly candidate flag generation. Components involved: Current fingerprint feature extraction and spectrum analysis unit 8, radiation-resistant injection and monitoring interface module 3, fault judgment and assessment processing unit 5, and test data and version traceability management unit 9. Specifically:

[0223] Current fingerprint feature extraction and spectrum analysis unit 8 receives the first Current data records associated with the secondary injection For the compensated current sequence Feature extraction and frequency domain / time-frequency analysis are performed. The time-domain feature vector is extracted by the current waveform feature extraction module 81. The frequency domain or time-frequency feature vector is extracted by the spectrum / time-frequency analysis module 82. , and combine them into the first The current characteristic vector of the secondary injection .

[0224] The fingerprint database matching and threshold determination module 83 will... Match the baseline characteristics of the normal operating current fingerprint established by S10 to calculate the first... Fingerprint deviation after injection The fingerprint deviation is defined as the feature distance. ,in, The baseline feature vector of the normal operating current fingerprint (from S10); : Norm 2 distance.

[0225] Let the current anomaly threshold be... (Threshold configuration items that are versioned and registered by traceability management unit 9) will then generate current anomaly candidate flags. .

[0226] The current fingerprint feature extraction and spectrum analysis unit 8 will... , , With injection event identifier After association, it is sent to the fault judgment and assessment processing unit 5, and simultaneously written into the test data and version traceability management unit 9 as an electrical-grade evidence index.

[0227] The S404 was used to realize the characteristic representation of transient current evidence in the power domain and the generation of anomaly candidate flags, providing input for subsequent fault decoupling decisions.

[0228] S405: Data caching and forwarding, event link registration, and execution status update. Components involved: Real-time main control unit 2, fault judgment and assessment processing unit 5, test data and version traceability management unit 9, and host computer control subsystem 1. Specifically:

[0229] Real-time main control unit 2 records the output data of each injection event through data caching and forwarding module 24. Current data recording and injection event identifier Encapsulate and generate the first One injected event data packet .

[0230] Event data packets The data is forwarded to the fault judgment and evaluation processing unit 5 for subsequent judgment triggering and evidence fusion, while its index entry is registered by the test data and version traceability management unit 9, forming an event chain. ,in: This is the test batch identifier (from S10). Injection plan identifier (from S30); This is a data indexing function used to point to a storage location or log entry.

[0231] When the After each injection entry is executed, the real-time main control unit 2 updates the execution status and writes the entry completion flag to the test data and version traceability management unit 9, and returns the execution progress information to the host computer control subsystem 1.

[0232] The S405 enables the encapsulation and forwarding of injected event data, event index registration, and execution status updates, providing a complete data and traceability link for subsequent fault diagnosis and assessment.

[0233] S50: Multi-source triggering, weighted readback, and fault decoupling decision. Components involved: 2. Real-time main control unit, 3. Radiation-resistant injection and monitoring interface module, 4. SRAM-type in-memory computing chip under test, 5. Fault decision and evaluation processing unit, 6. Address translation and physical mapping verification unit, 7. Current fingerprint feature extraction and spectrum analysis unit, 8. Test data and version traceability management unit. This step triggers and executes the fault decoupling decision process after each runtime injection event, based on "calculated output anomaly evidence + current fingerprint anomaly evidence + readback consistency evidence". This process distinguishes between single-event latch-up (SEL), stored soft errors (SEU), and computational soft errors (SET / computational transient faults) within the same test loop, and outputs fault labels, confidence levels, and a traceable evidence set, providing structured input for the subsequent quantitative evaluation of S60's radiation resistance performance.

[0234] Specifically, the S50 includes:

[0235] S501: Multi-source anomaly triggering criterion calculation and decision process initiated. Components involved: Fault decision and assessment processing unit 5, real-time main control unit 2, current fingerprint feature extraction and spectrum analysis unit 8, test data and version traceability management unit 9. Specifically:

[0236] Fault Judgment and Assessment Processing Unit 5 receives the first Data packets of the secondary injection event (From S40), and receives the current feature vector output by the current fingerprint feature extraction and spectrum analysis unit 8. Fingerprint deviation With current anomaly candidate flag (From S404).

[0237] Fault judgment and evaluation processing unit 5 quantifies the abnormality of the calculated output and defines the output reference sequence as follows. This is either a reference output for the same task under undisturbed conditions or a baseline output provided by the host computer control subsystem 1 (its version is registered in the traceability management unit 9). For the first... Output sequence under secondary injection , define the first The output error metric for the second injection is: ,in: The number of output samples used in error calculation; It is a 2-norm; This is the output after injection; This is for reference output.

[0238] Let the output anomaly threshold be... (If the version is registered by the test data and version traceability management unit 9), then define the output exception candidate flag. .

[0239] Fault Judgment and Assessment Processing Unit 5 combines the two types of candidate flags to form a judgment initiation flag. ,in: Represents a logical OR operation; This indicates the initiation of the fault decoupling decision process.

[0240] Fault Judgment and Assessment Processing Unit 5 will , , , , With injection event identifier Associate the write test data with version traceability management unit 9. When At that time, the fault judgment and evaluation processing unit 5 sends a judgment process start command to the real-time main control unit 2, carrying the injection entry sequence number. Corresponding physical position coordinates (from) ).

[0241] The S501 enables multi-source anomaly quantification, judgment initiation condition generation, and traceable trigger record establishment for single injection events.

[0242] S502: Run-through and Readback Control: Enters readback mode and locates the readback range. Components involved: Real-time main control unit 2, SRAM-type in-memory computing chip under test 4, Address translation and physical mapping verification unit 6, Test data and version traceability management unit 9. Specifically:

[0243] Upon receiving the decision process start command, the real-time main control unit 2 coordinates the tested SRAM-type in-memory computing chip 4 to enter the read-back state without disrupting the power supply, so as to perform a read-back of the in-memory computing array and determine whether a memory bit flip has occurred.

[0244] Real-time main control unit 2 uses the physical bit coordinates in the injected event identifier. Combined with readback strategy (Injection plan entry from S30) Determine the readback address range Reread range It can be defined as being based on The physical region set centered ,in: For the first The physical region for reading back from the next judgment; Physical distance function (same as S30); The readback radius parameter (configured by the readback strategy and registered in the traceability management unit 9).

[0245] Because the SRAM-type in-memory computing chip 4 under test may have address scrambling or bit interleaving, the real-time main control unit 2 requests the address translation and physical mapping verification unit 6 to read back the physical area. Convert into an executable list of readback physical addresses Define the conversion. ,in: For the first The list of physical addresses to be read back next time; : The address list generation function output by the address translation and physical mapping verification unit 6.

[0246] After completing the loading of the readback address list, the real-time main control unit 2 initiates a readback operation to the tested SRAM-type in-memory computing chip 4, and sends the readback request along with the injection event identifier. The test data is associated with and written to the version traceability management unit 9 to form an "injection-readback" link index.

[0247] The S502 enables the implementation of everything from injection location to readback range determination, readback address list generation, and readback control establishment, providing implementable readback objects for subsequent consistency verification.

[0248] S503: Weighted readback and bit-by-bit consistency verification, extracting bit-flipped sets. Components involved: 4. SRAM-type in-memory computing chip under test, 2. Real-time main control unit, 5. Fault judgment and evaluation processing unit, 9. Test data and version traceability management unit. Specifically:

[0249] The real-time main control unit 2 reads back the data set from the tested SRAM-type in-memory computing chip 4, denoted as The weight readback and consistency verification module 51 of the fault judgment and evaluation processing unit 5 obtains the original loaded reference weight data set. (This set is generated by the host computer control subsystem 1 during the model loading stage, and its version and index are recorded in the test data and version traceability management unit 9.)

[0250] Read back address list Each address in Define the reference bit value as The readback bit value is And define the bit-by-bit difference indicator. ,in: :address In the Difference indicator under subsequent readbacks; This indicates a bitwise XOR operation.

[0251] Definition of the first The set of bit-flipped addresses corresponding to the next injection event is .

[0252] Define the readback toggles count as ,in: Indicates the number of elements in the set.

[0253] The weighted readback and consistency verification module 51 will and With injection event identifier The test data is associated with the version traceability management unit 9 and provided to the fault type judgment module 54 as stored evidence input.

[0254] The S503 microcontroller enables bit-by-bit consistency verification between readback data and reference data, as well as the extraction of bit-flip sets, providing direct evidence for SEU-type fault identification. (Refer to...) Figure 6 , Figure 6 This is a schematic diagram illustrating the readback range positioning and address list generation provided in an embodiment of this application.

[0255] S504: Output error evidence and current evidence are fused to form a multi-source evidence vector. Components involved: Fault determination and assessment processing unit 5, current fingerprint feature extraction and spectrum analysis unit 8, radiation-resistant injection and monitoring interface module 3, test data and version traceability management unit 9. Specifically:

[0256] The fault judgment and evaluation processing unit 5's calculation output error analysis module 52 uses the output error metric obtained by S501. With output anomaly candidate flags As functional-level evidence, the current transient feature analysis module 53 uses the output of the current fingerprint feature extraction and spectrum analysis unit 8. , and current eigenvectors As electrical-grade evidence; the output of the weighted readback and consistency verification module 51. and As storage-level evidence. Define the first The multi-source evidence vector of the secondary injection event is The meaning of each component is consistent with the steps described above.

[0257] To associate current anomalies with latch-up risk, the fault decision and assessment processing unit 5 defines a latch-up risk indicator. This is the normalized result of the current deviation, where, This is the current anomaly threshold (in conjunction with S404).

[0258] Fault Judgment and Assessment Processing Unit 5 will and The corresponding evidence indexes (output data index, current data index, and readback data index) are written into the test data and version traceability management unit 9 to form a traceable set of evidence entries.

[0259] S504 enables unified expression and archiving of functional, electrical, and storage-level evidence in a single injection event, providing structured input for subsequent fault type determination.

[0260] S505: Fault type decoupling decision and tag output. Components involved: Fault decision and assessment processing unit 5, real-time main control unit 2, radiation-resistant injection and monitoring interface module 3, test data and version traceability management unit 9. Specifically:

[0261] The fault type determination module 54 of the fault determination and assessment processing unit 5 is based on multi-source evidence vectors. Latch risk indicator and readback flipped set Perform fault type decoupling decision and output fault label. With confidence level of judgment .

[0262] Let the latch decision threshold be... (Register its version in the test data and version traceability management unit 9); if the latch criterion is met. Then the fault label is determined to be ,in, For the first Fault label for the secondary injection event For single-event latch-up tags; if the latch-up criterion is not met and the readback flip count is satisfied. Then the fault label is determined to be ,in, Store soft error labels and flip the set. As evidence of the label's location; when the latching criterion is not met and At the same time, output the abnormal candidate flags to satisfy Then the fault label is determined to be ,in The label "computational soft error" (computational transient fault) indicates that the fault occurred in the computation path or during a transient simulation disturbance without causing a memory bit flip; if , ,and If so, it is determined to be a fault-free label. ,in, This indicates that no detectable fault was found.

[0263] Define confidence level It is a normalized combination of the strength of evidence to characterize the confidence level, where, The decision confidence level and its range of values. , , and The weighting coefficient (as a configuration parameter registered in the traceability management unit 9 version). To output the abnormal threshold, This is the current anomaly threshold. This represents the length of the readback address list; the meanings of the other variables are the same as in the previous steps.

[0264] when At that time, the fault judgment and assessment processing unit 5 outputs a protection control request to the real-time main control unit 2. The real-time main control unit 2 further drives the voltage and current protection unit 33 of the radiation-resistant injection and monitoring interface module 3 to perform protection actions, and writes the protection action flag and fault tag into the test data and version traceability management unit 9.

[0265] Fault Judgment and Assessment Processing Unit 5 will Write the test data and version traceability management unit 9 to form the final judgment record entry for a single injection event.

[0266] The S505 enables decoupled decision-making, confidence output, and coordinated protection actions for SEL, SEU, and SET within a single injection closed loop, establishing a traceable chain of decision evidence. (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of fault decoupling decision based on multi-source evidence fusion provided in an embodiment of this application.

[0267] S60: Quantitative assessment of radiation resistance performance, construction of degradation curves, and report output. Components involved: Host computer control subsystem 1, fault judgment and assessment processing unit 5, current fingerprint feature extraction and spectrum analysis unit 8, test data and version traceability management unit 9, and the tested SRAM-type in-memory computing chip 4. This step is used to summarize and statistically analyze the injection event data, fault tags, and evidence vectors generated from S40 to S50, obtain the occurrence characteristics of storage soft errors (SEU), computational soft errors (SET), and single-event latch-up (SEL) under different injection conditions, and construct a "injection intensity-computation correctness" mapping relationship at the application level, forming a computational correctness degradation curve and a multi-dimensional radiation resistance assessment index set, ultimately generating and outputting a traceable assessment report.

[0268] Specifically, the S60 includes:

[0269] S601: Fault event statistics and occurrence rate calculation. Components involved: Fault judgment and assessment processing unit 5, test data and version traceability management unit 9, current fingerprint feature extraction and spectrum analysis unit 8. Specifically:

[0270] Fault Judgment and Assessment Processing Unit 5 reads the injection plan version from Test Data and Version Traceability Management Unit 9. All injection event judgment records below and their corresponding injection parameters ,in (Same as S30), and read the single-judgment evidence vector. Deviation from current (From S50).

[0271] Define the event counts for SEU, SET, and SEL as follows: , , ,in: , , Count the corresponding fault events; This is an indicator function; it takes the value 1 if the condition is true, and 0 otherwise. : No. Secondary injection event failure label. Define the total number of injection events as... The occurrence rate of the three types of failures is defined as follows: , , ,

[0272] in: , , This represents the corresponding failure rate.

[0273] To demonstrate the impact of injection parameters on the failure rate, the injection amplitude parameter is used as the basis. Bucketing forms a set of injection conditions. ,in, Indicates falling into the first A set of injection event indices for each amplitude range. Calculate the condition occurrence rate for each bucket. , , ,in: The number of buckets; For the first The number of events within each bucket. The fault judgment and assessment processing unit 5 writes the overall occurrence rate and bucket-specific occurrence rate into the test data and version traceability management unit 9, and binds them. Threshold versions and decision configuration versions form traceable statistical result entries.

[0274] The S601 system enables the statistical analysis and quantification of the occurrence rate of fault events in both global and injection condition dimensions, providing a basic statistical measure for the construction of degradation curves.

[0275] S602: Calculation of computational correctness index and construction of degradation curve. Components involved: Host computer control subsystem 1, fault judgment and evaluation processing unit 5, test data and version traceability management unit 9, and the SRAM-type in-memory computing chip under test 4. This step is used to construct the "injection strength-computational correctness" mapping relationship and generate a computational correctness degradation curve. Specifically:

[0276] The host computer control subsystem 1 provides task-level reference output or reference accuracy benchmark, and the fault judgment and evaluation processing unit 5 calculates the output correctness index after the injected event and performs condition convergence.

[0277] Define the task reference correctness metric as It can be the accuracy of classification tasks, the mAP of detection tasks, or the proportion within the error threshold of regression tasks, etc. The definition method is determined by the host computer control subsystem 1 in the test configuration and its version is registered in the test data and version traceability management unit 9. For the first... The next injection event defines the corresponding task correctness metric as follows: .

[0278] To correspond with the output error metric of S50, a correctness mapping function based on the output error is defined. , making ,in: For the first Indicators of correctness after the first injection; For the first The output error metric for the next injection (from S50); A mapping function for outputting errors to accuracy indicators (its type and parameters are registered in traceability management unit 9). To ensure... Consistent with the degradation trend, a monotonically decreasing mapping can be defined. ,in: To output the abnormal threshold (from S50, with the same variable name); Constrained Within the range. Define the amount of degradation to be calculated as... ,in: For the first The amount of correctness degradation caused by each injection. Define the injection strength scalar. To uniformly represent the impact of injection conditions on degradation, let the relationship between injection intensity and injection parameters be: ,in: For the first Sub-injection intensity scalar; To inject amplitude parameters; For the injection duration parameter; the variable is related to S30. Consistency. Based on this, a set of degraded samples is formed. .

[0279] Divide the injection intensity into buckets (Same as S601), the average correctness of each bucket is defined as follows: And define the degradation curve as a discrete mapping. ,in: For the first Average injection intensity of each barrel; For the first The average accuracy of each bucket; To calculate the correctness degradation curve (discrete form).

[0280] The host computer control subsystem 1 and the fault judgment and evaluation processing unit 5 will and Write the test data and version traceability management unit 9, and bind it to the reference correctness indicator. Mapping function and its parameter versions.

[0281] S602 enables the calculation of task correctness indicators from injection event output error, the definition of injection strength scalar, and the construction of calculation correctness degradation curves.

[0282] S603: Generation and output of multi-dimensional radiation resistance assessment indicators. Components involved: Fault diagnosis and assessment processing unit 5, host computer control subsystem 1, test data and version traceability management unit 9, current fingerprint feature extraction and spectrum analysis unit 8. Specifically:

[0283] The fault diagnosis and assessment processing unit 5 generates a multi-dimensional set of radiation resistance evaluation indicators based on degradation curves and failure rate statistics. These indicators characterize the radiation resistance of the in-memory computing chip during operation. The in-memory failure ratio is defined as... ,in: The storage failure ratio describes the proportion of computational soft errors among all soft errors. , Count the events from S601.

[0284] Define latch-up risk index as , to be used to characterize latch-up risk, where: Fingerprint deviation (from S404 / S50); This is the current abnormality threshold (consistent with S404).

[0285] Define worst-case correctness as And define the worst-case degradation as To characterize the worst-case degradation, among which, , Same as S602.

[0286] Fault Judgment and Assessment Processing Unit 5 will set up the indicator set The data is output to the host computer control subsystem 1, which then generates an evaluation report data structure through the test data analysis and report generation module 15. This data is then written into the test data and version traceability management unit 9. Report data structure At least include: test batch identifier Injection plan identifier Quantization and mapping version number, threshold version number, fault statistics table, degradation curve data, key event index and its evidence link.

[0287] Test data and version traceability management unit 9 generates report identifiers for reports. and will and , Binding and registration create reproducible and traceable output records. The host computer control subsystem 1 will... The corresponding report content is output in the form of a file or data interface.

[0288] The S603 enables the generation of multi-dimensional radiation resistance assessment indicators, the reporting output of degradation curves and fault statistics, and the binding and traceability registration of the entire process version.

[0289] Based on the above, this embodiment focuses on the closed-loop operation-state injection and online evaluation of hardware-in-the-loop (HIL). It implements time-controlled and location-restricted disturbance / equivalent irradiation injection within the operation-state window of the SRAM-based computing chip, which performs real-world tasks such as neural network inference. Simultaneously, it collects information such as computational output and power domain current transients. After an anomaly is triggered, it further performs weight / address readback consistency verification, integrating multi-source evidence from "current-memory readback-computational output." This allows for decoupled judgment and independent characterization of failure mechanisms such as SEU, operational-state computation link transient faults (SET / computational soft errors), and SEL, under conditions of uninterrupted power supply and recoverable operation. Compared to static hold-state testing (which cannot cover operational-state dynamic faults) and pure software injection evaluation (which lacks physical realism), this embodiment can conduct tests under real electrical stress and timing sensitivity conditions, making it closer to engineering application scenarios. Meanwhile, this embodiment introduces a guided testing mechanism based on bit-level sensitivity maps and logic-physical mapping, transforming testing from blind testing of the entire array to efficient testing that "covers key sensitive bits with a limited number of tests." Furthermore, by establishing a calibration criterion based on a non-disruptive reference output and a normal operating current fingerprint baseline, the risk of misjudgment caused by inherent simulation errors / noise in SRAM-CIM is reduced. Further, this embodiment, through versioned registration and event indexing of key configurations such as injection plans, thresholds, and mapping tables, ensures good traceability and reproducibility of the testing process and conclusions, providing higher-confidence hardware-level evaluation support for radiation-hardened design verification, reliability screening, and on-orbit health assessment.

[0290] The following is a brief example illustrating the implementation of the SRAM in-memory radiation resistance testing method and system based on runtime injection in this embodiment.

[0291] In a simple example, a runtime injection test system based on a host computer, FPGA real-time main control, and injection / monitoring interface board is implemented. Specifically:

[0292] In terms of system composition, it includes:

[0293] Host computer: Used for model quantization and compilation, sensitivity analysis, injection plan generation, result statistics and report output;

[0294] Real-time control unit (FPGA): used for runtime window recognition, nanosecond-level triggering, sampling organization, event tagging, and data buffering and forwarding;

[0295] Radiation-resistant injection and monitoring interface module: includes a programmable disturbance injection circuit, a high-bandwidth current monitoring circuit, a voltage / current protection unit, and an analog acquisition interface;

[0296] DUT daughterboard: carries the SRAM-CIM chip under test and provides power decoupling, clock / reset / debug interface;

[0297] Judgment and evaluation processing: can be implemented on a host computer or independent computing unit to complete evidence fusion and fault decoupling.

[0298] The implementation steps include:

[0299] Step A: System initialization and baseline establishment, including: ① Power-on self-test and communication handshake; ② Load the operating point of the chip under test; ③ Load the logic-physical mapping and perform consistency verification; ④ Perform timing calibration on the injection and sampling links, and generate injection advance and sampling alignment compensation; ⑤ Run the inference task under undisturbed conditions, collect the power supply current and establish the normal operating current fingerprint baseline and threshold version.

[0300] Step B: Sensitivity analysis and injection target generation, including: ① performing fixed-point quantization on the neural network under test and compiling it into a loadable format; ② calculating the sensitivity at the weight bit level to form a sensitivity ranking / map; ③ combining logical-physical mapping to project the sensitivity onto physical bits to obtain a candidate set of physical sensitive bits; ④ filtering the injection target set based on Top-K / hierarchical quota / minimum spacing constraints.

[0301] Step C: Generation and distribution of runtime injection plan, including: generating an itemized plan for each injection target, which includes at least: injection location, runtime window / gating, triggering conditions, injection parameters, sampling strategy and readback strategy; distributing the plan to the FPGA and completing the loading confirmation.

[0302] Step D: Run-state execution, injection, and synchronous monitoring, including: ① The DUT executes inference tasks in in-memory mode; ② The FPGA identifies the run-state window and triggers injection as planned; ③ Output data and current transient data are collected synchronously and marked with injection event identifiers; ④ Fingerprint deviation of current characteristics is calculated and combined with output error to form anomaly candidates.

[0303] Step E: Readback and fault decoupling decision after abnormal triggering, including: ① Entering a readable state without disrupting power supply; ② Determining the readback range around the injection coordinates and generating a readback address list; ③ Verifying the consistency between the readback data and the reference weight bit by bit to obtain the bit flip set / flip count; ④ Integrating "current abnormality - readback flip - output error" to form a fault label (SEL / SEU / SET) and confidence level, and recording the evidence index.

[0304] Step F: Quantitative evaluation and report output, including: statistically analyzing the occurrence rate of SEU / SET / SEL for multiple injection events, constructing a "injection strength - calculation correctness / error" degradation curve, and outputting multi-dimensional reliability indicators and test reports.

[0305] Based on the above, guided injection and online monitoring can be completed in real-world operation, forming a traceable chain of evidence. This enables decoupled decision-making and quantitative evaluation of storage flip-flops, computational transients, and latch-up anomalies, making it suitable for hardening verification and screening.

[0306] In yet another simple example, pulsed laser scanning / microbeaming is used to achieve equivalent injection with stronger spatial positioning. Specifically:

[0307] In terms of system composition, it includes:

[0308] Based on the previous example, the programmable electrical disturbance injection circuit is replaced or supplemented with a pulsed laser point / area scanning device (or micro-beam irradiation device), while keeping the FPGA's runtime window gating and event marking mechanism unchanged.

[0309] The implementation steps include:

[0310] Convert the physical sensitive site candidate set / injection coordinates into laser scanning coordinates or microbeam positioning regions;

[0311] When the running window is open, apply one or more pulses to the target coordinates using the laser / microbeam according to the trigger conditions;

[0312] Synchronously acquire current and output data and read back for verification after an anomaly;

[0313] The decision on SEL / SEU / SET is based on multiple sources of evidence.

[0314] Based on the above, the improved injection spatial resolution makes it easier to verify the causal relationship between the "guiding sensitive bit" and the failure behavior, and improves the interpretability of fault location.

[0315] In another simple example, the specific implementation is a multi-batch guided test + fingerprint database comparison for reliability screening. Its application scenarios can be incoming material screening, process batch comparison, or before and after hardening verification for the same model of SRAM-CIM chip.

[0316] The implementation process includes:

[0317] First, fix the target network / task's quantization version, mapping version, and threshold version to form a standardized test configuration;

[0318] Generate a unified set of injection targets and injection plan versions based on sensitivity maps (ensuring batch comparability).

[0319] Perform running-state injection on each chip according to the same injection plan, collect current fingerprints and output errors, and read back after an anomaly;

[0320] Write the "current fingerprint deviation statistics, SEL risk index, SEU / SET / SEL occurrence rate, and correctness degradation curve" of each chip into the traceability unit;

[0321] Use fingerprint databases / statistical indicators as screening criteria: for example, set upper limits for latch-up risk, upper limits for worst-case degradation, and lower limits for correctness under specific injection strengths to achieve graded screening.

[0322] Based on the above, the test results are transformed from single-instance phenomena into a basis for batch comparison and screening decisions, and version-based traceability ensures the comparability and verifiability between different batches.

[0323] The following table summarizes the comparison between the SRAM in-memory radiation resistance testing method and system based on runtime injection in this embodiment and traditional methods:

[0324]

[0325] In summary, the SRAM in-memory computing radiation resistance testing method and system based on runtime injection in this embodiment achieves runtime window alignment between injection triggering and sampling through runtime window identification, timing calibration, and delay compensation. Under the condition of uninterrupted power supply and recoverable operation process, it collects computation output and power supply current transient information online, and performs readback consistency verification of relevant weights / addresses after abnormal triggering. It integrates multi-source evidence such as "current fingerprint - storage readback - computation output" to establish calibration criteria, reducing misjudgments caused by inherent simulation errors / noise. This allows for decoupling and quantitative evaluation of failure mechanisms such as SEU, runtime computing link transient faults (SET / computational soft errors), and SEL, meeting the requirements for accurate quantification and self-diagnosis of dual failure mechanisms of "storage" and "computation" in complex radiation environments for SRAM in-memory computing chips.

[0326] In the embodiments provided in this application, it should be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, code, or any suitable combination thereof. For hardware implementation, the processor may be implemented in one or more of the following: application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to implement the functions described herein, or combinations thereof. For software implementation, some or all of the processes of the embodiments may be performed by a computer program instructing the associated hardware. During implementation, the program may be stored in a computer-readable storage medium or transmitted as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of a computer program from one place to another. Storage media may be any available medium accessible to a computer. Computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code having the form of instructions or data structures and accessible to a computer.

[0327] Finally, it should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for testing the radiation resistance of SRAM memory based on runtime injection, characterized in that, The method includes: S10: System initialization, mapping preparation, and timing baseline establishment; used to complete the following before the test begins: system power-on self-test and communication establishment, working point configuration of the SRAM-type in-memory computing chip under test, availability confirmation of logical-physical address mapping relationship, timing calibration and delay compensation of injection / sampling links, establishment of normal operating current fingerprint baseline, and traceability registration of key versions and parameters; after completing S10, the system enters the ready state for executable model mapping and sensitivity analysis; S20: Model quantization compilation, sensitivity analysis, and physical bit candidate generation; used to complete the fixed-point processing of the neural network model, the organization and mapping of logical weights on the memory array, the sensitivity calculation and sorting at the quantization bit level before test execution, and to generate a set of physical sensitive bit candidates for subsequent runtime injection based on the logical-physical mapping relationship; after completing S20, the following are obtained: quantized model parameters, logical storage layout, sensitivity map, physical sensitive bit candidate set and its confidence and version traceability information, providing input for the runtime injection plan generation of S30; S30: Runtime Injection Plan Generation and Test Case Loading; used to generate a deterministic runtime injection plan based on the obtained physical sensitive bit candidate set; the injection plan takes the physical injection location, runtime window, trigger condition, injection parameters, sampling strategy, and readback strategy as core elements to form a set of structured test cases, and completes loading and traceability registration; after completing S30, all the necessary control information for executing runtime injection and synchronous monitoring is available in real time; S40: Run-state execution, disturbance injection, and synchronous monitoring and acquisition; used to inject disturbances into specified physical locations according to the run-state injection plan when the tested SRAM-type in-memory computing chip is performing real inference / in-memory computing tasks, and to perform synchronous data acquisition and event association labeling before and after the injection event occurs; the synchronously acquired data includes at least: calculation output data, chip running state data, and power domain current / voltage transient data, and evidence features are formed based on the current transient data; the acquisition and labeling results are written for fault decoupling decision of S50; S50: Multi-source triggering, weighted readback, and fault decoupling decision; used to trigger and execute the fault decoupling decision process based on computational output anomaly evidence, current fingerprint anomaly evidence, and readback consistency evidence after each running-state injection event; this process distinguishes between single-event latch-up, stored soft errors, and computational soft errors in the same test closed loop, and outputs fault labels, confidence levels, and traceable evidence sets, providing structured input for the quantitative evaluation of S60's radiation resistance performance; S60: Quantitative assessment of radiation resistance performance, construction of degradation curves and report output; used to summarize and statistically analyze the injection event data, fault tags and evidence vectors formed from S40 to S50, obtain the occurrence characteristics of stored soft errors, computational soft errors and single-event latch-up under different injection conditions, and construct the mapping relationship between injection intensity and computational correctness at the application level, forming a computational correctness degradation curve and a multi-dimensional radiation resistance assessment index set, generating a traceable assessment report and outputting it.

2. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S10 includes: S101: Power-on initialization, self-test and basic communication handshake; specifically: after the system is powered on, a self-test command is initiated and a basic communication link is established; S102: Loading and confirming the operating point and running status of the SRAM-type in-memory computing chip under test; specifically: loading the array structure parameters, operating voltage and operating frequency configuration of the SRAM-type in-memory computing chip under test, and entering the predetermined operating state; S103: Logical-Physical Address Mapping Loading and Consistency Verification; used to establish and confirm the logical-physical address mapping relationship required for subsequent injection and readback, specifically: loading the mapping table or mapping configuration data, and generating the mapping relationship; S104: Timing calibration and delay compensation loading for runtime window alignment; used to establish the alignment relationship between the disturbance injection trigger time and the runtime window of the SRAM-type in-memory computing chip under test, and to determine the delay compensation parameters of the injection link and the sampling link. S105: Establishment and registration of normal operating current fingerprint baseline and threshold configuration; used to establish a power domain current baseline fingerprint under undisturbed conditions as a reference input for subsequent anomaly identification and evidence fusion; S106: Initialize parameter vector registration and set system ready flag; after S101 to S105 are completed, summarize the key configuration and verification results generated by S10, form the initialization parameter vector, and write it.

3. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S20 includes: S201: Model Fixed-Point Quantization and Compilation Processing; used to perform fixed-point quantization and compilation processing on the neural network model to be tested, converting floating-point weights into fixed-point weight representations, and outputting the quantization scale and bit width configuration; S202: Logical storage layout generation and physical bit coordinate set acquisition; used to organize the quantized logical weights into a logical storage layout mapped to the SRAM storage array, and obtain the corresponding physical bit coordinate set, providing a basis for subsequent targeted injection positioning; S203: Bit-level sensitivity index calculation and sensitivity map generation; used to calculate the degree of influence of each logical bit coordinate on the correctness of the model output, form a sensitivity index, and generate a sensitivity ranking set and sensitivity map; S204: Physical domain projection, candidate screening, and retrospective registration of sensitivity maps; used to project sensitivity maps from the logical domain to the physical domain, and generate a set of candidate physical sensitive bits based on the mapping consistency coefficient and screening threshold.

4. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S30 includes: S301: Target set screening and injection sequence generation, including generating an injection target set and forming an injection sequence based on a candidate set of physically sensitive bits and a candidate entry set; S302: Determination of runtime time window and construction of trigger conditions; used to determine the runtime injection time window of each injection target during the execution of inference / in-memory computing tasks by the SRAM-type in-memory computing chip under test, and to construct the trigger conditions for determination; S303: Runtime Injection Plan Generation and Deployment; used to generate a structured runtime injection plan and deploy it for subsequent execution; S304: Injection plan and configuration version writing; used to register the versioning of the runtime injection plan and related configurations, so that the data and judgment results generated during the execution process can correspond one-to-one with a specific plan, a specific threshold, a specific sampling and readback strategy.

5. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S40 includes: S401: Start the running task of the SRAM-type in-memory computing chip under test and enter the running state monitoring; issue the task start command according to the task configuration of the neural network under test, and coordinate the SRAM-type in-memory computing chip under test to enter the in-memory computing mode and execute the inference / in-memory computing task; S402: Disturbance injection triggering and execution within the running window, including condition triggering, disturbance injection execution, and injection event identifier generation within the running window; S403: Calculate the synchronous acquisition and time calibration of output data and power domain transient data, including synchronous acquisition of output and current transients before and after injection, time alignment and event association storage; S404: Current fingerprint feature extraction, spectrum analysis and anomaly candidate flag generation, including the characteristic representation of transient current evidence in the power domain and the generation of anomaly candidate flags, providing input for subsequent fault decoupling decisions; S405: Data caching and forwarding, event link registration and execution status update, including encapsulation and forwarding of injected event data, event index registration and execution status update, providing a complete data and traceability link for subsequent fault judgment and assessment.

6. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S50 includes: S501: Multi-source anomaly triggering criterion calculation and judgment process initiation, including multi-source anomaly quantification for single injection events, judgment initiation condition generation and traceable trigger record establishment; S502: Run-through and Readback Control: Enter the read-through state and locate the readback range, including from injection location to readback range determination, readback address list generation and readback control establishment, providing implementable readback objects for subsequent consistency verification; S503: Weighted readback and bit-by-bit consistency verification, extraction of bit-flip set, including bit-by-bit consistency verification of readback data and reference data and extraction of bit-flip set, providing direct evidence for single-event flip fault determination; S504: Output error evidence and current evidence are fused to form a multi-source evidence vector, including a unified expression and archiving of functional, electrical and storage level evidence under a single injection event, providing structured input for subsequent fault type determination; S505: Fault type decoupling decision and tag output, including decoupling decision, confidence output and protection action linkage for single-event lockout, single-event flip, and single-event transient within a single injection closed loop, and establishing a traceable decision evidence link.

7. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 1, characterized in that, S60 includes: S601: Fault event statistics and occurrence rate calculation, including statistics and occurrence rate quantification of fault events in the global and injection condition dimensions, providing basic statistics for the construction of degradation curves; S602: Calculation of accuracy index and construction of degradation curve; used to construct the mapping relationship between injection intensity and calculation accuracy, and generate calculation accuracy degradation curve; S603: Generation and output of multi-dimensional radiation resistance evaluation indicators, including the generation of a set of multi-dimensional radiation resistance evaluation indicators based on degradation curves and failure rate statistics, to characterize the radiation resistance capability of in-memory computing chips in operation.

8. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 5, characterized in that, S404, specifically: Receive the Current data records associated with the secondary injection For the compensated current sequence Feature extraction and frequency domain / time-frequency analysis are performed, including: extracting time-domain feature vectors. Extract frequency domain or time-frequency feature vectors And combined into a current characteristic vector. ,in, For the first The characteristic vector of the injected current. For the first The time-domain feature vector injected in the second injection For the first The frequency domain / time-frequency feature vector injected next; Current characteristic vector The fingerprint deviation is calculated by matching the baseline characteristics of the normal operating current fingerprint established by S10. fingerprint deviation Specifically: fingerprint deviation is defined as the feature distance. ,in, The baseline feature vector of the normal operating current fingerprint is determined based on S10. The distance is the L2 norm. For the first Fingerprint deviation during secondary injection; The threshold for obtaining abnormal current is: Then, a candidate flag for current anomaly is generated. The mathematical expression is ; Will , , It is associated with the injected event identifier for fault diagnosis and evaluation, and is synchronously written as an electrical-grade evidence index.

9. The SRAM in-memory radiation resistance testing method based on runtime injection according to claim 6, characterized in that, S505, specifically: based on multi-source evidence vectors Latch risk indicator and readback flipped set Perform fault type decoupling decision and output fault label. With confidence level of judgment ,include: The threshold for obtaining latch decision is ; If satisfied The fault label is then determined to be... ,in, For the first Fault label for the secondary injection event Single-event latch tag; does not satisfy And the readback flip count satisfies Then the fault label is determined to be ,in Store soft error labels and flip the set. As evidence of the label's location; when not satisfied And storage-level evidence At the same time, output the abnormal candidate flags to satisfy Then the fault label is determined to be ,in This is a computational soft error label, indicating that the fault occurred in the computation path or a transient simulation disturbance without causing a memory bit flip; if , ,and If so, it is determined to be a fault-free label. ,in This indicates that no detectable fault was found. Define confidence level This confidence level is a normalized combination of the strength of evidence. The mathematical expression is: in: The confidence level is given, and its value ranges from [0,1]. , and These are preset weighting coefficients; The preset output anomaly threshold; This is the preset current anomaly threshold; Indicates the length of the readback address list; As a measure of output error; Fingerprint deviation; Storage-level evidence; when When necessary, output a protection control request, execute the protection action, and associate the protection action flag with the fault tag; Write to form the final decision record entry for a single injection event; where: injection event identifier , To inject the planned version identifier, For the injection entry sequence number, To inject physical position coordinates, The trigger time for output is; the multi-source evidence vector is... , As a measure of output error, To output anomaly candidate flags, For fingerprint deviation, As a candidate indicator for abnormal current, This is for the count of flips during readback.

10. A radiation resistance testing system for SRAM memory based on runtime injection, employing the radiation resistance testing method for SRAM memory based on runtime injection as described in any one of claims 1 to 9, characterized in that, The system includes a host computer control subsystem (1), a real-time main control unit (2), an anti-radiation injection and monitoring interface module (3), a tested SRAM-type in-memory computing chip (4), a fault judgment and evaluation processing unit (5), an address translation and physical mapping verification unit (6), a timing calibration and delay compensation unit (7), a current fingerprint feature extraction and spectrum analysis unit (8), and a test data and version traceability management unit (9). Among them, the host computer control subsystem (1) is responsible for test task planning and algorithm-side processing; the real-time main control unit (2) is responsible for timing execution and trigger control; the anti-radiation injection and monitoring interface module (3) is responsible for... The port module (3) is responsible for disturbance injection and power status monitoring; the SRAM-type in-memory computing chip under test (4) performs in-memory calculations as the test object in the running state; the fault judgment and evaluation processing unit (5) makes judgments and evaluations on multi-source data; the address translation and physical mapping verification unit (6) provides logical-physical coordinate bridging; the timing calibration and delay compensation unit (7) provides nanosecond-level alignment support; the current fingerprint feature extraction and spectrum analysis unit (8) provides current evidence of latch-up / transient / flip; the test data and version traceability management unit (9) is used to ensure the reproducibility and traceability of the test process and results.

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