Chip protection circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of circuits, in particular to a chip protection circuit, a chip and electronic equipment. The circuit comprises a power unit, a first switch unit, a second switch unit, a static discharge unit and a switch control circuit, wherein the switch control circuit is connected with the chip protection circuit, the first switch unit, the second switch unit and a grounding end; the first switch unit is connected with the power unit, the power unit is connected with the input end and the output end of the chip protection circuit and the static discharge unit, and the second switch unit is connected with the input end. When the input end is negative voltage, the switch control circuit controls the first switch unit and the second switch unit to be switched on and controls the power unit to be switched off, so that the chip is prevented from being damaged; and when the input end has no voltage and the static discharge unit outputs negative static discharge voltage or current, the switch control circuit controls the first switch unit and the second switch unit to be switched off and the power unit to be switched on, so that power failure of the output end is avoided. Therefore, the chip is prevented from being damaged and the output end is prevented from being powered down.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a chip protection circuit, a chip, and an electronic device. Background Technology

[0002] During the use of DC / DC chips or linear lithium battery charging chips, the chip input voltage may suddenly jump to a negative voltage (negative surge event), or there may be an electro-static discharge (ESD) event, or the chip's pre-stage voltage regulator circuit may malfunction and cause the input voltage to be negative. These factors can all lead to chip damage or power loss at the chip output.

[0003] Therefore, there is an urgent need for a protection solution that can prevent chip damage or power loss at the chip output. Summary of the Invention

[0004] The illustrative embodiments of this application provide a chip protection circuit, a chip, and an electronic device.

[0005] In a first aspect, this application provides a chip protection circuit, which includes a power unit, a first switching unit, a second switching unit, a static discharge unit, and a switch control circuit. A first terminal of the switch control circuit is connected to the output terminal of the chip protection circuit; a second terminal of the switch control circuit is connected to the first terminal of the first switching unit; a third terminal of the switch control circuit is connected to the first terminal of the second switching unit; and a fourth terminal of the switch control circuit is connected to the second terminals of the first and second switching units and a ground terminal. The third terminal of the first switching unit is connected to the first terminal of the power unit; the second terminal of the power unit is connected to the input terminal of the chip protection circuit; the third terminal of the power unit is connected to the output terminal and the first terminal of the static discharge unit; the second terminal of the static discharge unit is connected to the ground terminal; and the third terminal of the second switching unit is connected to the input terminal. When the input terminal has a negative voltage, the switch control circuit controls the first and second switching units to be in a conducting state, and the power unit to be in a closed state. When there is no voltage at the input terminal and the static discharge unit outputs a negative static discharge voltage or a negative static discharge current, the switch control circuit controls the first and second switching units to be in a closed state, and the power unit to be in a conducting state.

[0006] Based on the above-mentioned chip protection circuit, it is possible to quickly respond to negative ESD events and negative surge events, accurately distinguish between normal negative voltage input and abnormal negative voltage input, improve the reliability and adaptability of the protection circuit, and reduce chip damage and power failure at the output terminal.

[0007] In one possible implementation of the first aspect described above, the switch control circuit includes a third switch unit and a control unit; a first terminal of the third switch unit is used to connect to a first terminal of the first switch unit, a second terminal of the third switch unit is used to connect to a first terminal of the control unit, a third terminal of the third switch unit is used to connect to a second terminal of the control unit; a third terminal of the control unit is used to connect to an output terminal, a fourth terminal of the control unit is used to connect to a second terminal of the second switch unit, a second terminal of the first switch unit, and a ground terminal, and a fifth terminal of the control unit is used to connect to a first terminal of the second switch unit.

[0008] In one possible implementation of the first aspect described above, the third switching unit includes a first switching transistor and a first diode, and the control unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a second switching transistor, and a second diode; the first terminal of the first switching transistor is used to connect to the first terminal of the first switching unit and the first terminal of the first diode, the second terminal of the first switching transistor is used to connect to the first terminal of the first resistor, the first terminal of the first capacitor, and the first terminal of the second resistor, and the third terminal of the first switching transistor is used to connect to the second terminal of the first diode, the second terminal of the first capacitor, the third terminal of the second switching transistor, the first terminal of the second diode, and the first terminal of the second switching unit; the second terminal of the first resistor is used to connect to the output terminal, the second terminal of the second resistor is used to connect to the first terminal of the third resistor, the first terminal of the second switching transistor, the second terminal of the second switching transistor, and the second terminal of the second diode, and the second terminal of the third resistor is used to connect to the ground terminal, the second terminal of the second switching unit, and the second terminal of the first switching unit.

[0009] It is understood that in the embodiments of this application, the first switch and the second switch can be N-channel MOSFETs (NMOS). The first terminal of each of the first and second switches can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0010] In one possible implementation of the first aspect described above, the third switching unit includes a first switching transistor and a first diode, and the control unit includes a second resistor, a third resistor, a Zener diode, a first capacitor, a third switching transistor, a third diode, a current source, a fourth switching transistor, and a fourth diode; the first terminal of the first switching transistor is used to connect to the first terminal of the first switching unit and the first terminal of the first diode, the second terminal of the first switching transistor is used to connect to the first terminal of the third switching transistor, the first terminal of the third diode, the first terminal of the first capacitor, and the first terminal of the second resistor, the third terminal of the first switching transistor is used to connect to the second terminal of the first diode, the second terminal of the first capacitor, the third terminal of the fourth switching transistor, the first terminal of the fourth diode, the first terminal of the third resistor, the first terminal of the Zener diode, and the first terminal of the second switching unit; the second terminal of the third switching transistor is used to connect to a ground terminal, the third terminal of the third switching transistor is used to connect to the second terminal of the third diode and the first terminal of the current source, the second terminal of the current source is used to connect to an output terminal, and the second terminal of the second resistor is used to connect to the first terminal of the fourth switching transistor, the second terminal of the fourth switching transistor, and the second terminal of the fourth diode, wherein the second terminal of the third resistor is used to connect to the second terminal of the Zener diode and the ground terminal.

[0011] It is understandable that the third and fourth switching transistors can be N-channel field-effect transistors. The first terminal of each of the first, second, third, and fourth switching transistors can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0012] In one possible implementation of the first aspect described above, the chip protection circuit includes a first resistor unit, which includes a fourth resistor; a power unit includes a fifth switch and a fifth diode; a first switching unit includes a sixth switch and a sixth diode; a second switching unit includes a seventh switch and a seventh diode; and a static discharge unit includes a static discharge diode. The first terminal of the fifth switch is connected to the first terminal of the fifth diode, the first terminal of the static discharge diode, and the output terminal; the second terminal of the fifth switch is connected to the first terminal of the sixth switch and the first terminal of the sixth diode; the third terminal of the fifth switch is connected to the input terminal and the second terminal of the fifth diode; and the second terminal of the static discharge diode is connected to the ground terminal. The second terminal of the sixth switch is connected to the first terminal of the fourth resistor, the second terminal of the third resistor, and the second terminal of the seventh switch; the third terminal of the sixth switch is connected to the first terminal of the first switch and the first terminal of the first diode; and the second terminal of the fourth resistor is connected to the ground terminal. The first terminal of the seventh switch is connected to the input terminal and the first terminal of the seventh diode; and the third terminal of the seventh switch is connected to the third terminal of the first switch, the second terminal of the first diode, the third terminal of the second switch, and the second terminal of the second diode.

[0013] It is understood that in the embodiments of this application, the fifth, sixth, and seventh switching transistors can be N-channel field-effect transistors. The first terminal of each of the fifth, sixth, and seventh switching transistors can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0014] In one possible implementation of the first aspect above, when the input terminal is negative, the seventh switch, the first switch, and the sixth switch are turned on, and the fifth switch is turned off; when there is no voltage at the input terminal and the electrostatic discharge diode outputs a negative electrostatic discharge voltage, the seventh switch, the first switch, and the sixth switch are turned off, and the fifth switch is turned on.

[0015] In one possible implementation of the first aspect described above, the chip protection circuit includes a first resistor unit, which includes a fourth resistor; a power unit includes a fifth switch and a fifth diode; a first switching unit includes a sixth switch and a sixth diode; a second switching unit includes a seventh switch and a seventh diode; and a static discharge unit includes a static discharge diode. The first terminal of the fifth switch is connected to the first terminal of the fifth diode, the first terminal of the static discharge diode, and the output terminal; the second terminal of the fifth switch is connected to the first terminal of the sixth switch and the first terminal of the sixth diode; the third terminal of the fifth switch is connected to the input terminal and the second terminal of the fifth diode; wherein the second terminal of the static discharge diode is connected to the ground terminal; the second terminal of the sixth switch is connected to the first terminal of the fourth resistor, the second terminal of the third resistor, the second terminal of the Zener diode, and the second terminal of the seventh switch; the third terminal of the sixth switch is connected to the first terminal of the first switch, the first terminal of the first diode, and the first terminal of the sixth diode; the second terminal of the fourth resistor is connected to the ground terminal; the first terminal of the seventh switch is connected to the input terminal; and the third terminal of the seventh switch is connected to the third terminal of the first switch, the second terminal of the first diode, the third terminal of the fourth switch, the second terminal of the fourth diode, the first terminal of the third resistor, and the first terminal of the Zener diode.

[0016] In one possible implementation of the first aspect above, when the input terminal is negative, the seventh switch, the first switch, and the sixth switch are turned on, and the fifth switch is turned off; when there is no voltage at the input terminal and the electrostatic discharge diode outputs a negative electrostatic discharge current, the seventh switch, the first switch, and the sixth switch are turned off, and the fifth switch is turned on.

[0017] In one possible implementation of the first aspect described above, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are N-channel field-effect transistors.

[0018] Secondly, this application provides a chip that includes the chip protection circuit provided by the first aspect and various possible implementations of the first aspect.

[0019] Thirdly, this application provides an electronic device that includes the chip provided in the second aspect above.

[0020] The beneficial effects of the second and third aspects mentioned above can be referred to the relevant descriptions in the first aspect and its various possible implementations, which will not be repeated here. Attached Figure Description

[0021] Figure 1A According to some embodiments, a circuit diagram of an off-chip discrete device 10 is shown;

[0022] Figure 1B A schematic diagram of a negative voltage protection circuit 20 is shown according to some embodiments;

[0023] Figure 2A According to an embodiment of this application, a schematic diagram of a chip protection circuit 001 is shown;

[0024] Figure 2B According to an embodiment of this application, a schematic diagram of another chip protection circuit 001 is shown;

[0025] Figure 3 According to an embodiment of this application, a schematic diagram of a chip protection circuit 002 is shown;

[0026] Figure 4 According to an embodiment of this application, a schematic diagram of a chip protection circuit 003 is shown;

[0027] Figure 5 According to an embodiment of this application, a schematic diagram of a chip protection circuit 004 is shown.

[0028] Figure 6 According to an embodiment of this application, a schematic diagram of a chip protection circuit 005 is shown;

[0029] Figure 7 According to an embodiment of this application, a schematic diagram of a chip protection circuit 006 is shown. Detailed Implementation

[0030] The illustrative embodiments of this application include, but are not limited to, a chip protection circuit, a chip, and an electronic device.

[0031] The specific implementation process of the technical solution provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0032] As mentioned earlier, during the use of DC / DC chips or linear lithium battery charging chips, the chip's input voltage may momentarily jump to a negative voltage, an electrostatic discharge (ESD) event may occur, or a fault in the chip's pre-stage voltage regulator circuit may cause the input voltage to be negative, all of which can lead to chip damage or power loss at the chip's output. A negative ESD event refers to electrostatic discharge occurring when the chip is not powered on, where current flows from the ground terminal to the chip's output terminal, forming a high-energy negative pulse that causes a momentary negative electrostatic discharge shock at the output terminal.

[0033] To avoid the above problems, some implementation schemes use negative voltage protection circuits to protect the chip.

[0034] For example, Figure 1A A circuit diagram of an external discrete device 10 including a negative voltage protection circuit is shown. The external discrete device 10 includes a switch transistor M00, a capacitor C00, and a resistor R00. The first terminal of the switch transistor M00 is connected to the output terminal VOUT, the second terminal of the switch transistor M00 is connected to the input terminal VIN, and the third terminal of the switch transistor M00 is connected to the first terminal of both the capacitor C00 and the resistor R00. The second terminals of both the capacitor C00 and the resistor R00 are connected to ground.

[0035] Referring to 1A, when an input terminal is incorrectly connected or a fault in the pre-stage voltage regulator circuit causes a negative input voltage, the switching transistor MOO is turned off to prevent damage to the chip caused by the negative input voltage. However, during the period when the switching transistor MOO is turned off, the output voltage will be pulled low, resulting in a decrease in the output voltage, which may lead to problems such as power loss at the chip output and chip damage.

[0036] For example, Figure 1B A schematic diagram of a negative voltage protection circuit 20 is shown. The negative voltage protection circuit 20 includes switching transistors M01, M02, and M03, diodes D01, D02, and D03, capacitor C0, resistors R10 and R20, electrostatic discharge diode ESD0, Zener diode Zener10, Zener diode Zener20, and Zener diode Zener30.

[0037] Specifically, the first terminal of switch M01 is connected to the first terminal of diode D01, the output terminal VOUT, and the first terminal of electrostatic discharge diode ESD0. The second terminal of electrostatic discharge diode ESD0 is connected to ground. The second terminal of switch M01 is connected to the first terminal of switch M02 and the first terminal of diode D02. The third terminal of switch M01 is connected to the input terminal VIN and the second terminal of diode D01. The second terminal of switch M02 is connected to the first terminal of capacitor C0, the second terminal of Zener diode Zener20, the first terminal of Zener diode Zener30, the first terminal of resistor R10, and the second terminal of switch M03. The first terminal of Zener diode Zener20 is connected to the second terminal of Zener diode Zener10. The first terminal of Zener diode Zener10 is connected to the second terminal of resistor R10 and ground. The third terminal of switch M02 is connected to the second terminal of capacitor C0, the second terminal of Zener diode Zener30, the second terminal of diode D02, the first terminal of diode D03, and the third terminal of switch M03. The first terminal of the switching transistor M03 is connected to the second terminal of the diode D03 and the ground terminal.

[0038] Referring to 1B, when the input VIN is negative, switching transistors M02 and M03 are turned on, while switching transistor M01 is turned off. The state of switching transistor M01 is controlled by the RC time constant of the circuit composed of R10 and C0, which controls the rate of decrease of the gate voltage of switching transistor M01, ensuring that switching transistor M01 can be turned off in time and preventing the negative voltage at the input VIN from affecting the internal circuitry of the chip. When the electrostatic discharge diode ESD0 outputs a negative electrostatic discharge voltage, switching transistors M02 and M03 are turned off, while switching transistor M01 is turned on. The state of switching transistor M01 is controlled by the RC time constant, which controls the rate of increase of the gate voltage of switching transistor M01, ensuring that switching transistor M01 can be turned on in time to release the negative electrostatic discharge voltage and prevent the negative electrostatic discharge voltage from affecting the output.

[0039] However, due to the influence of process deviations and temperature changes on the RC time constant, it is impossible to quickly identify and respond to negative surge events (i.e., the input VIN is negative) or negative ESD events (i.e., the electrostatic discharge diode outputs a negative electrostatic discharge voltage or current). Furthermore, negative surge events typically involve a rapid, microsecond-level change in input voltage, while negative ESD events involve an even faster voltage change, typically on the nanosecond level. In other words, the response speed requirements for negative surge events and negative ESD events differ, and the RC time constant cannot accurately respond to different abnormal events. In summary, the negative voltage protection circuit 20 cannot quickly and accurately identify and respond to negative ESD events or negative surge events, and therefore cannot adaptively control the state of the switching transistor M01, thus failing to effectively prevent chip damage or power loss at the chip output.

[0040] In other words, none of the above solutions can effectively prevent chip damage or power loss at the chip output.

[0041] To address the aforementioned problems, this application provides a chip protection circuit, comprising a power unit, a first switching unit, a second switching unit, a static discharge unit, and a switch control circuit. The first terminal of the switch control circuit is connected to the output terminal of the chip protection circuit; the second terminal is connected to the first terminal of the first switching unit; the third terminal is connected to the first terminal of the second switching unit; and the fourth terminal is connected to the second terminals of the first and second switching units, as well as a ground terminal. The third terminal of the first switching unit is connected to the first terminal of the power unit; the second terminal of the power unit is connected to the input terminal of the chip protection circuit; the third terminal of the power unit is connected to the output terminal and the first terminal of the static discharge unit; the second terminal of the static discharge unit is connected to the ground terminal; and the third terminal of the second switching unit is connected to the input terminal. When the input terminal has a negative voltage, the switch control circuit controls the first and second switching units to be in a conducting state, and the power unit to be in a closed state. When there is no voltage at the input terminal and the static discharge unit outputs a negative static discharge voltage or a negative static discharge current, the switch control circuit controls the first and second switching units to be in a closed state, and the power unit to be in a conducting state.

[0042] It is understood that, based on the chip protection circuit provided in this application, when a negative voltage appears at the chip's input terminal, the switching control circuit can control the power unit to be in the off state, ensuring that the chip's output voltage is not affected by the negative voltage at the input terminal, thereby preventing the chip from being damaged or losing power due to the negative voltage at the input terminal. When the input voltage is zero and a negative electrostatic discharge voltage exists, the switching control circuit can control the power unit to be in the on state, so that the negative electrostatic discharge voltage is released, further protecting the chip's output terminal from the impact of the negative electrostatic discharge voltage.

[0043] Therefore, the chip protection circuit provided in this application can quickly and accurately identify and respond to negative ESD events and negative surge events, improve the reliability and adaptability of the protection circuit, and reduce chip damage and output power loss.

[0044] According to some embodiments of this application, Figure 2A A schematic diagram of a chip protection circuit 001 is shown.

[0045] refer to Figure 2A The chip protection circuit 001 may include a power unit 101, a first switching unit 102, a second switching unit 103, a static discharge unit 104, and a switching control circuit 105.

[0046] Specifically, the first terminal of the switch control circuit 105 is connected to the output terminal VOUT of the chip protection circuit 001; the second terminal of the switch control circuit 105 is connected to the first terminal of the first switch unit 102; the third terminal of the switch control circuit 105 is connected to the first terminal of the second switch unit 103; and the fourth terminal of the switch control circuit 105 is connected to the second terminals of the first switch unit 102, the second terminals of the second switch unit 103, and the ground terminal. The third terminal of the first switch unit 102 is connected to the first terminal of the power unit 101; the second terminal of the power unit 101 is connected to the input terminal VIN of the chip protection circuit; the third terminal of the power unit 101 is connected to the output terminal VOUT and the first terminal of the electrostatic discharge unit 104; the second terminal of the electrostatic discharge unit 104 is connected to the ground terminal; and the third terminal of the second switch unit 103 is connected to the input terminal VIN.

[0047] It is understood that the specific structures of the power unit 101, the first switching unit 102, the second switching unit 103, the static discharge unit 104, and the switching control circuit 105 will be described in detail below.

[0048] In some embodiments of this application, the specific structure of the switch control circuit 105 in different chip protection circuits may differ. (Corresponding to the above...) Figure 2A , Figure 2B A circuit diagram of another chip protection circuit 001 is shown.

[0049] refer to Figure 2B The switch control circuit 105 may include a third switch unit 1050 and a control unit 1051. A first terminal of the third switch unit 1050 is connected to a first terminal of the first switch unit 102, a second terminal of the third switch unit 1050 is connected to a first terminal of the control unit 1051, and a third terminal of the third switch unit 1050 is connected to a second terminal of the control unit 1051. A third terminal of the control unit 1051 is connected to an output terminal, a fourth terminal of the control unit 1051 is connected to a second terminal of the second switch unit 103, a second terminal of the first switch unit, and a ground terminal, and a fifth terminal of the control unit 1051 is connected to a first terminal of the second switch unit 103.

[0050] The circuit structure of the switch control circuit 105 may vary depending on the different embodiments provided in this application.

[0051] For example, Figure 3 A schematic diagram of a chip protection circuit 002 is shown.

[0052] refer to Figure 3As shown, in the chip protection circuit 002, the third switching unit 1050 includes a first switching transistor M1 and a first diode D1, and the control unit 1051 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C, a second switching transistor M2, and a second diode D2. The first terminal of the third switching unit 1050 can be formed by the first terminal of the first switching transistor M1 and the first terminal of the first diode D1; the second terminal of the third switching unit 1050 can be the second terminal of the first switching transistor M1; and the third terminal of the third switching unit 1050 can be formed by the second terminal of the first switching transistor M1 and the second terminal of the first diode D1. The first terminal of the control unit 1051 can be composed of the first terminal of the first resistor R1, the first terminal of the first capacitor C, and the first terminal of the second resistor R2. The second terminal of the control unit 1051 can be the second terminal of the first capacitor C. The third terminal of the control unit 1051 can be the second terminal of the first resistor R1. The fourth terminal of the control unit 1051 can be the second terminal of the third resistor R3. The fifth terminal of the control unit 1051 can be composed of the third terminal of the second switch and the second terminal of the second diode D2.

[0053] It is understood that in other embodiments of this application, the third switching unit 1050 and the control unit 1051 may further include components based on... Figure 3 Other more or fewer devices shown are not specifically limited in this application.

[0054] The first terminal of the first switching transistor M1 is connected to the first terminal of the first switching unit 102 and the first terminal of the first diode D1. The second terminal of the first switching transistor M1 is connected to the first terminal of the first resistor R1, the first terminal of the first capacitor C, and the first terminal of the second resistor R2. The third terminal of the first switching transistor M1 is connected to the second terminal of the first diode D1, the second terminal of the first capacitor C, the third terminal of the second switching transistor M2, the first terminal of the second diode D2, and the first terminal of the second switching unit 103. The second terminal of the first resistor R1 is connected to the output terminal VOUT. The second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3, the first terminal of the second switching transistor M2, the second terminal of the second switching transistor M2, and the second terminal of the second diode D2. The second terminal of the third resistor R3 is connected to the ground terminal, the second terminal of the second switching unit 103, and the second terminal of the first switching unit 102.

[0055] It is understood that in the embodiments of this application, the first switch M1 and the second switch M2 can be N-channel MOSFETs (NMOS). The first terminal of each of the first switch M1 and the second switch M2 can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0056] For example, Figure 4 A schematic diagram of a chip protection circuit 003 is shown.

[0057] refer to Figure 4 As shown, in the chip protection circuit 003, the third switching unit 1050 includes a first switching transistor M1 and a first diode D1, and the control unit 1051 includes a second resistor R2, a third resistor R3, a Zener diode, a first capacitor C, a third switching transistor M3, a third diode D3, a current source IREF, a fourth switching transistor M4, and a fourth diode D4. The first terminal of the third switching unit 1050 can be formed by the first terminal of the first switching transistor M1 and the first terminal of the first diode D1; the second terminal of the third switching unit 1050 can be formed by the second terminal of the first switching transistor M1; and the third terminal of the third switching unit 1050 can be formed by the second terminal of the first switching transistor M1 and the second terminal of the first diode D1. The first terminal of the control unit 1051 can be composed of the first terminal of the third switch M3, the first terminal of the first capacitor C, and the first terminal of the second resistor R2. The second terminal of the control unit 1051 can be the second terminal of the first capacitor C. The third terminal of the control unit 1051 can be the second terminal of the current source IREF. The fourth terminal of the control unit 1051 can be composed of the first terminal of the third resistor R3 and the first terminal of the Zener diode. The fifth terminal of the control unit 1051 can be composed of the third terminal of the fourth switch M4, the second terminal of the second diode D2, the second terminal of the third resistor R3, and the second terminal of the Zener diode.

[0058] It is understood that in other embodiments of this application, the third switching unit 1050 and the control unit 1051 may further include components based on... Figure 4 Other more or fewer devices shown are not specifically limited in this application.

[0059] The first terminal of the first switch transistor M1 is connected to the first terminal of the first switch unit 102 and the first terminal of the first diode D1. The second terminal of the first switch transistor M1 is connected to the first terminal of the third switch transistor M3, the first terminal of the third diode D3, the first terminal of the first capacitor C, and the first terminal of the second resistor R2. The third terminal of the first switch transistor M1 is connected to the second terminal of the first diode D1, the second terminal of the first capacitor C, the third terminal of the fourth switch transistor M4, the first terminal of the fourth diode D4, the first terminal of the third resistor R3, the first terminal of the Zener diode Zener, and the first terminal of the second switch unit 103. The second terminal of the third switch transistor M3 is connected to the ground terminal. The third terminal of the third switch transistor M3 is connected to the second terminal of the third diode D3 and the first terminal of the current source IREF. The second terminal of the current source IREF is connected to the output terminal VOUT. The second terminal of the second resistor R2 is connected to the first terminal of the fourth switch transistor M4, the second terminal of the fourth switch transistor M4, and the second terminal of the fourth diode D4. The second terminal of the third resistor R3 is connected to the second terminal of the Zener diode Zener and the ground terminal.

[0060] It is understood that in the embodiments of this application, the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 can be N-channel MOSFETs (NMOS). The first terminal of each of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0061] In some embodiments of this application, in conjunction with the above... Figure 2B The chip protection circuit 001 shown is... Figure 5 A schematic diagram of a chip protection circuit 004 is shown.

[0062] refer to Figure 5 In the chip protection circuit 004, the chip protection circuit 005 includes a first resistor unit 106, which includes a fourth resistor R4. The third switching unit 1050 includes a first switching transistor M1 and a first diode D1. The power unit 101 includes a fifth switching transistor M5 and a fifth diode D5. The first switching unit 102 includes a sixth switching transistor M6 and a sixth diode D6. The second switching unit 103 includes a seventh switching transistor M7 and a seventh diode D7. The electrostatic discharge unit 104 includes an ESD diode.

[0063] It is understood that the first resistor unit 106 may include one or more resistors. In this embodiment, the first resistor unit 106 includes a fourth resistor R4 as an example for illustration.

[0064] It is understood that in other embodiments of this application, the power unit 101, the first switching unit 102, the second switching unit 103, and the static discharge unit 104 may further include components based on... Figure 5 Other more or fewer devices are shown, but this application does not specifically limit them.

[0065] Specifically, the first terminal of the fifth switch M5 is connected to the first terminal of the fifth diode D5, the first terminal of the electrostatic discharge diode ESD, and the output terminal VOUT; the second terminal of the fifth switch M5 is connected to the first terminal of the sixth switch M6 and the first terminal of the sixth diode D6; the third terminal of the fifth switch M5 is connected to the input terminal VIN and the second terminal of the fifth diode D5; and the second terminal of the electrostatic discharge diode ESD is connected to the ground terminal. The second terminal of the sixth switch M6 is connected to the first terminal of the fourth resistor R4, the fourth terminal of the control unit 1051, and the second terminal of the seventh switch M7; the third terminal of the sixth switch M6 is connected to the first terminal of the first switch M1 and the first terminal of the first diode D1; and the second terminal of the fourth resistor R4 is connected to the ground terminal. The first terminal of the seventh switch M7 is connected to the input terminal VIN and the first terminal of the seventh diode D7; and the third terminal of the seventh switch M7 is connected to the third terminal of the first switch M1, the second terminal of the first diode D1, and the fifth terminal of the control unit 1051.

[0066] In some embodiments of this application, in conjunction with the above... Figure 3 The chip protection circuit 002 shown is shown. Figure 6 A schematic diagram of a chip protection circuit 005 is shown.

[0067] Understandable. Figure 6 The switch control circuit 105 can be referenced as described above. Figure 3 The corresponding descriptions will not be repeated here.

[0068] refer to Figure 6 In the chip protection circuit 005, the chip protection circuit 005 includes a first resistor unit 106, which includes a fourth resistor R4; the power unit 101 includes a fifth switch M5 and a fifth diode D5; the first switch unit 102 includes a sixth switch M6 and a sixth diode D6; the second switch unit 103 includes a seventh switch M7 and a seventh diode D7; and the electrostatic discharge unit 104 includes an electrostatic discharge diode ESD.

[0069] The first terminal of the fifth switch M5 is connected to the first terminal of the fifth diode D5, the first terminal of the electrostatic discharge diode ESD, and the output terminal VOUT. The second terminal of the fifth switch M5 is connected to the first terminal of the sixth switch M6 and the first terminal of the sixth diode D6. The third terminal of the fifth switch M5 is connected to the input terminal VIN and the second terminal of the fifth diode D5. The second terminal of the electrostatic discharge diode ESD is connected to the ground terminal. The second terminal of the sixth switch M6 is connected to the first terminal of the fourth resistor R4, the second terminal of the third resistor R3, and the second terminal of the seventh switch M7. The third terminal of the sixth switch M6 is connected to the first terminal of the first switch M1 and the first terminal of the first diode D1. The second terminal of the fourth resistor R4 is connected to the ground terminal. The first terminal of the seventh switch M7 is connected to the input terminal VIN and the first terminal of the seventh diode D7. The third terminal of the seventh switch M7 is connected to the third terminal of the first switch M1, the second terminal of the first diode D1, the third terminal of the second switch M2, and the second terminal of the second diode D2.

[0070] It is understood that in the embodiments of this application, the fifth switch M5, the sixth switch M6, and the seventh switch M7 can be N-channel field-effect transistors. The first terminal of each of the fifth switch M5, the sixth switch M6, and the seventh switch M7 can represent the source, the second terminal can represent the gate, and the third terminal can represent the drain.

[0071] In some embodiments of this application, when the input terminal VIN is negative, the seventh switch M7, the first switch M1, and the sixth switch M6 are turned on, and the fifth switch M5 is turned off; when there is no voltage at the input terminal VIN and the ESD diode outputs a negative static discharge voltage, the seventh switch M7, the first switch M1, and the sixth switch M6 are turned off, and the fifth switch M5 is turned on. Specifically:

[0072] On one hand, when the voltage at the input terminal VIN of the chip protection circuit 005 jumps to a negative voltage instantaneously, a negative surge event occurs at the input terminal VIN (indicating that the input voltage jumps to a negative voltage instantaneously). Since the seventh switch M7 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the seventh switch M7 is the ground voltage (0V), and the voltage at the third terminal (source voltage) of the seventh switch M7 is a negative voltage. The voltage at the second terminal (gate voltage) of the seventh switch M7 is greater than the voltage at the third terminal (source voltage) of the seventh switch M7, so the seventh switch M7 is turned on. When the seventh switch M7 is turned on, the voltage at the third terminal of the first switch M1 is also negative. Since the second terminal of the first switch M1 is connected to the first resistor R1, the first capacitor C, and the second resistor R2, and the voltage drop between the first resistor R1 and the second resistor R2 is small and the first capacitor C is not fully charged, the voltage at the second terminal of the first switch M1 is close to the ground voltage (0V). Since the first switch M1 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the first switch M1 is greater than the voltage at the third terminal (source voltage) of the first switch M1, so the first switch M1 is turned on. When both the seventh switch M7 and the first switch M1 are turned on, the voltage at the third terminal of the sixth switch M6 is also negative. The second terminal of the sixth switch M6 is connected to ground through the fourth resistor R4, which is a current-limiting resistor. Therefore, the voltage at the second terminal of the sixth switch M6 is close to the ground voltage (0V). Since the sixth switch M6 is a field-effect transistor (FET), its second terminal voltage (gate voltage) is greater than the third terminal voltage (source voltage) of the second switch M2, thus the sixth switch M6 is turned on. When the sixth switch M6 is turned on, the voltage at the second terminal of the fifth switch M5 is VIN. The third terminal of the fifth switch M5 is connected to the input terminal VIN, and its third terminal voltage is negative. Since the fifth switch M5 is also a FET, its second terminal voltage (gate voltage) is not greater than the third terminal voltage (source voltage), thus the fifth switch M5 is turned off. This prevents the negative voltage at the input terminal VIN from being output to the output terminal VOUT.

[0073] On the other hand, when there is no voltage at the input terminal VIN of the chip protection circuit 005 and the ESD diode outputs a negative ESD voltage, a negative ESD event occurs (indicating that ESD occurs when the chip is not powered on). Since the seventh switch M7 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the seventh switch M7 is the ground terminal voltage (0V), and the voltage at the third terminal (source voltage) of the seventh switch M7 is also 0. The voltage at the second terminal (gate voltage) of the seventh switch M7 is not greater than the voltage at the third terminal (source voltage) of the seventh switch M7, so the seventh switch M7 is turned off. When the seventh switch M7 is off, the voltage at the third terminal of the first switch M1 is also 0. The second terminal of the first switch M1 is connected to the first resistor R1, the first capacitor C, and the second resistor R2. Since the voltage drop across the first resistor R1 and the second resistor R2 is small and the first capacitor C is not charged, the voltage at the second terminal of the first switch M1 is close to the ground voltage (0V). Because the first switch M1 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the first switch M1 is not greater than the voltage at the third terminal (source voltage) of the first switch M1, so the first switch M1 is off. When both the seventh switch M7 and the first switch M1 are off, the voltage at the third terminal of the sixth switch M6 is also 0. The second terminal of the sixth switch M6 is connected to the ground terminal through the fourth resistor R4. The voltage at the second terminal of the sixth switch M6 is close to the ground voltage (0V). Because the sixth switch M6 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the sixth switch M6 is not greater than the voltage at the third terminal (source voltage) of the second switch M2, so the sixth switch M6 is off. When the sixth switch M6 is turned off, the voltage at the second terminal of the fifth switch M5 is 0. Based on the fifth diode D5 and the parasitic capacitance CGD of the first switch M1 (used to leave charge on the gate of the first switch M1), the fifth switch M5 can be turned on. In this way, the negative electrostatic discharge voltage on the ESD diode can be led from the first terminal of the fifth switch M5 to the ground terminal, thereby avoiding the output terminal VOUT from being affected by the negative electrostatic discharge voltage.

[0074] It can be understood that the fifth diode D5 is a parasitic diode (body diode) inside the fifth switching transistor M5. In this embodiment, since the voltage at the first terminal of the fifth switching transistor M5 is 0, the positive terminal of the fifth diode D5 is 0. Since the voltage at the third terminal of the fifth switching transistor M5 is negative, the negative terminal of the fifth diode D5 is negative. Therefore, the positive terminal voltage of the fifth diode D5 is greater than the negative terminal voltage, causing the fifth diode D5 to conduct.

[0075] In some embodiments of this application, the second switch M2 is used to protect the voltage between the second and third terminals of the sixth switch M6 and the voltage between the second and third terminals of the seventh switch M7, so as to prevent damage to the seventh switch M7 and the sixth switch M6.

[0076] It is understandable that, in the above Figure 6 In the chip protection circuit 005 shown, the first terminal of the electrostatic discharge diode ESD is the negative terminal, and the second terminal is the positive terminal. The positive terminal of the electrostatic discharge diode ESD is connected to ground, and the negative terminal is connected to the first terminal of the fifth switch M5. Therefore, when there is no voltage at the input terminal VIN of the chip protection circuit 002 and the electrostatic discharge diode ESD outputs a negative electrostatic discharge voltage, based on the above analysis, it is determined that after the fifth switch M5 is turned on, the negative electrostatic discharge voltage on the electrostatic discharge diode ESD is led from the first terminal of the fifth switch M5 to the ground terminal because the positive terminal of the electrostatic discharge diode ESD is connected to ground and the negative terminal is connected to the first terminal of the fifth switch M5.

[0077] In other embodiments of this application, corresponding to Figure 6 The chip protection circuit 005 shown can also connect the positive terminal of the electrostatic discharge diode ESD in chip protection circuit 002 to the first terminal of the fifth switch M5, and the negative terminal of the electrostatic discharge diode ESD to the ground terminal. Based on this, when there is no voltage at the input terminal VIN and the electrostatic discharge diode ESD outputs a negative electrostatic discharge voltage, since the positive terminal of the electrostatic discharge diode ESD is connected to the first terminal of the fifth switch M5 and the negative terminal is connected to the ground terminal, the negative electrostatic discharge voltage on the electrostatic discharge diode ESD is then led from the first terminal of the fifth switch M5 to the input terminal VIN.

[0078] Based on the above Figure 6 The provided chip protection circuit 005 can quickly respond to negative ESD events and negative surge events, effectively distinguish between normal negative voltage input and abnormal negative voltage input, prevent chip damage and output power failure, and improve the reliability and adaptability of the protection circuit.

[0079] In some embodiments of this application, in conjunction with the above... Figure 4 The chip protection circuit 003 shown is shown. Figure 7 A schematic diagram of a chip protection circuit 006 is shown. It can be understood that... Figure 7 The switch control circuit 105 can be referenced as described above. Figure 4 The corresponding descriptions will not be repeated here.

[0080] refer to Figure 7In the chip protection circuit 006, the chip protection circuit also includes a first resistor unit 106, which includes a fourth resistor R4; the power unit 101 includes a fifth switch M5 and a fifth diode D5; the first switch unit 102 includes a sixth switch M6 and a sixth diode D6; the second switch unit 103 includes a seventh switch M7 and a seventh diode D7; and the electrostatic discharge unit 104 includes an electrostatic discharge diode ESD.

[0081] Specifically, the first terminal of the fifth switch M5 is connected to the first terminal of the fifth diode D5, the first terminal of the electrostatic discharge diode ESD, and the output terminal VOUT; the second terminal of the fifth switch M5 is connected to the first terminal of the sixth switch M6 and the first terminal of the sixth diode D6; the third terminal of the fifth switch M5 is connected to the input terminal VIN and the second terminal of the fifth diode D5; and the second terminal of the electrostatic discharge diode ESD is connected to the ground terminal. The second terminal of the sixth switch M6 is connected to the first terminal of the fourth resistor R4, the second terminal of the third resistor R3, the second terminal of the Zener diode Zener, and the second terminal of the seventh switch M7; the third terminal of the sixth switch M6 is connected to the first terminal of the first switch M1, the first terminal of the first diode D1, and the first terminal of the sixth diode D6; and the second terminal of the fourth resistor R4 is connected to the ground terminal. The first terminal of the seventh switch M7 is connected to the input terminal VIN; and the third terminal of the seventh switch M7 is connected to the third terminal of the first switch M1, the second terminal of the first diode D1, the third terminal of the fourth switch M4, the second terminal of the fourth diode D4, the first terminal of the third resistor R3, and the first terminal of the Zener diode Zener.

[0082] In some embodiments of this application, when the input terminal VIN is negative, the seventh switch M7, the first switch M1, and the sixth switch M6 are turned on, and the fifth switch M5 is turned off; when there is no voltage at the input terminal VIN and the ESD diode outputs a negative static discharge current, the seventh switch M7, the first switch M1, and the sixth switch M6 are turned off, and the fifth switch M5 is turned on. Specifically:

[0083] On one hand, when the voltage at the input terminal VIN of the chip protection circuit 006 jumps to a negative voltage instantaneously, a negative surge event occurs at the input terminal VIN (indicating that the input voltage jumps to a negative voltage instantaneously). Since the seventh switch M7 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the seventh switch M7 is the ground voltage (0V), and the voltage at the third terminal (source voltage) of the seventh switch M7 is a negative voltage. The voltage at the second terminal (gate voltage) of the seventh switch M7 is greater than the voltage at the third terminal (source voltage) of the seventh switch M7, so the seventh switch M7 is turned on. When the seventh switch M7 is turned on, the voltage at the third terminal of the first switch M1 is also negative. The second terminal of the first switch M1 is connected to the first resistor R1, the first capacitor C, and the second resistor R2. The voltage drop between the first resistor R1 and the second resistor R2 is small, and the first capacitor C is not fully charged. Therefore, the voltage at the second terminal of the first switch M1 is close to the ground voltage (0V). Since the first switch M1 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the first switch M1 is greater than the voltage at the third terminal (source voltage) of the first switch M1, so the first switch M1 is turned on. When both the seventh switch M7 and the first switch M1 are turned on, the voltage at the third terminal of the sixth switch M6 is also negative. The second terminal of the sixth switch M6 is connected to ground through the fourth resistor R4, which is a current-limiting resistor. Therefore, the voltage at the second terminal of the sixth switch M6 is close to the ground voltage (0V). Since the sixth switch M6 is a field-effect transistor (FET), its second terminal voltage (gate voltage) is greater than the third terminal voltage (source voltage) of the second switch M2, thus the sixth switch M6 is turned on. When the sixth switch M6 is turned on, the second terminal voltage of the fifth switch M5 is negative. The third terminal of the fifth switch M5 is connected to the input terminal VIN, and its third terminal voltage is also negative. Since the fifth switch M5 is a FET, its second terminal voltage (gate voltage) is not greater than the third terminal voltage (source voltage), thus the fifth switch M5 is turned off. This prevents the negative voltage at the input terminal VIN from being output to the output terminal VOUT.

[0084] It is understandable that when the input terminal VIN is negative, the voltage drop occurs across the first and second terminals of the fifth switch M5 and the first resistor R1. The third switch M3 and the fourth switch M4 can be used to protect the voltage between the second and third terminals of the first switch M1, and the Zener diode is used to clamp the voltage between the second and third terminals of the seventh switch M7, thus making the negative voltage withstand range of the input terminal VIN wider.

[0085] It should be understood that the transmission and processing of current in a circuit generally requires less energy loss than the transmission and processing of voltage. Therefore, based on considerations of circuit power consumption, it differs from... Figure 6In the chip protection circuit 005, the presence of a negative ESD event is determined by the negative ESD voltage of the electrostatic discharge diode. Figure 7 In the chip protection circuit 006, the negative ESD current based on the electrostatic discharge diode determines the presence of a negative ESD event.

[0086] On the other hand, when there is no voltage at the input terminal VIN of the chip protection circuit 006 and the ESD diode outputs a negative ESD current, a negative ESD event occurs (indicating that ESD occurs when the chip is not powered on). Since the seventh switch M7 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the seventh switch M7 is the ground terminal voltage (0V), and the voltage at the third terminal (source voltage) of the seventh switch M7 is also 0. The voltage at the second terminal (gate voltage) of the seventh switch M7 is not greater than the voltage at the third terminal (source voltage) of the seventh switch M7, so the seventh switch M7 is turned off. When the seventh switch M7 is turned off, the voltage at the third terminal of the first switch M1 is also 0. Since the second terminal of the first switch M1 is connected to the first resistor R1, the first capacitor C, and the second resistor R2, and the voltage drop between the first resistor R1 and the second resistor R2 is small and the first capacitor C is not charged, the voltage at the second terminal of the first switch M1 is close to the ground voltage (0V). Since the first switch M1 is a field-effect transistor, the voltage at the second terminal (gate voltage) of the first switch M1 is not greater than the voltage at the third terminal (source voltage) of the first switch M1, so the first switch M1 is turned off. At this time, the voltage between the second and third terminals of the first switch M1 is IREF*R3+VGS4, where VGS4 is the voltage between the second and third terminals of the fourth switch M4, and IREF can be the negative static discharge current. When both the seventh switch M7 and the first switch M1 are off, the voltage at the third terminal of the sixth switch M6 is also 0. The second terminal of the sixth switch M6 is connected to ground through the fourth resistor R4, and its voltage is close to the ground voltage (0V). Since the sixth switch M6 is a field-effect transistor, its second terminal voltage (gate voltage) is not greater than the third terminal voltage (source voltage) of the second switch M2, therefore the sixth switch M6 is off. When the sixth switch M6 is off, the voltage at the second terminal of the fifth switch M5 is 0, and the fifth diode D5, acting as the body diode of the fifth switch M5, can control the fifth switch M5 to conduct. This allows the negative electrostatic discharge current on the ESD diode to be drawn from the first terminal of the fifth switch M5 to ground, thus preventing the output terminal VOUT from being affected by the negative electrostatic discharge current.

[0087] It is understandable that the third resistor R3 is used to control the voltage across the Zener diode to ensure that the Zener diode does not conduct in the forward direction.

[0088] It is understandable that, in the above Figure 7 In the chip protection circuit 006 shown, the first terminal of the electrostatic discharge diode ESD is the negative terminal, and the second terminal is the positive terminal. The positive terminal of the ESD diode ESD is connected to ground, and the negative terminal is connected to the first terminal of the fifth switch M5. Therefore, when there is no voltage at the input terminal VIN of the chip protection circuit 006 and the ESD diode ESD outputs a negative electrostatic discharge current, based on the above analysis, it is determined that after the fifth switch M5 is turned on, the negative electrostatic discharge current on the ESD diode is led from the first terminal of the fifth switch M5 to the ground because the positive terminal of the ESD diode is connected to ground and the negative terminal is connected to the first terminal of the fifth switch M5.

[0089] In other embodiments of this application, corresponding to Figure 7 The chip protection circuit 006 shown can also connect the positive terminal of the electrostatic discharge diode ESD in the chip protection circuit 006 to the first terminal of the fifth switching transistor M5, and the negative terminal of the electrostatic discharge diode ESD to the ground terminal. Based on this, when there is no voltage at the input terminal VIN and the electrostatic discharge diode ESD outputs a negative electrostatic discharge current, since the positive terminal of the electrostatic discharge diode ESD is connected to the first terminal of the fifth switching transistor M5 and the negative terminal of the electrostatic discharge diode ESD is connected to the ground terminal, the negative electrostatic discharge current on the electrostatic discharge diode ESD is led from the first terminal of the fifth switching transistor M5 to the input terminal VIN.

[0090] Based on the above Figure 7 The provided chip protection circuit 006 can quickly respond to negative ESD events and negative surge events, effectively distinguish between normal negative voltage input and abnormal negative voltage input, prevent chip damage and output power failure, and improve the reliability and adaptability of the protection circuit.

[0091] In some embodiments of this application, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are N-channel field-effect transistors.

[0092] This application also provides a chip, including the chip protection circuit provided in the embodiments of this application.

[0093] This application also provides an electronic device, including the chip provided in the embodiments of this application.

[0094] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0095] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0096] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the mentioned element.

[0097] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A chip protection circuit, characterized in that, The chip protection circuit includes a power unit, a first switching unit, a second switching unit, a static discharge unit, and a switching control circuit. The first terminal of the switch control circuit is used to connect to the output terminal of the chip protection circuit, the second terminal of the switch control circuit is used to connect to the first terminal of the first switch unit, the third terminal of the switch control circuit is used to connect to the first terminal of the second switch unit, and the fourth terminal of the switch control circuit is used to connect to the second terminal of the first switch unit, the second terminal of the second switch unit, and the ground terminal. The third terminal of the first switching unit is connected to the first terminal of the power unit, the second terminal of the power unit is connected to the input terminal of the chip protection circuit, the third terminal of the power unit is connected to the output terminal and the first terminal of the electrostatic discharge unit, the second terminal of the electrostatic discharge unit is connected to the ground terminal, and the third terminal of the second switching unit is connected to the input terminal. When the input terminal is negative, the switch control circuit controls the first switch unit and the second switch unit to be in the on state, and the power unit to be in the off state. When there is no voltage at the input terminal and the static discharge unit outputs a negative static discharge voltage or a negative static discharge current, the switch control circuit controls the first switch unit and the second switch unit to be in the off state, and the power unit to be in the on state.

2. The chip protection circuit according to claim 1, characterized in that, The switch control circuit includes a third switch unit and a control unit; the first end of the third switch unit is used to connect to the first end of the first switch unit, the second end of the third switch unit is used to connect to the first end of the control unit, and the third end of the third switch unit is used to connect to the second end of the control unit. The third terminal of the control unit is used to connect to the output terminal, the fourth terminal of the control unit is used to connect to the second terminal of the second switch unit, the second terminal of the first switch unit and the ground terminal, and the fifth terminal of the control unit is used to connect to the first terminal of the second switch unit.

3. The chip protection circuit according to claim 2, characterized in that, The third switching unit includes a first switching transistor and a first diode, and the control unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a second switching transistor, and a second diode. The first terminal of the first switching transistor is used to connect to the first terminal of the first switching unit and the first terminal of the first diode; the second terminal of the first switching transistor is used to connect to the first terminal of the first resistor, the first terminal of the first capacitor and the first terminal of the second resistor; and the third terminal of the first switching transistor is used to connect to the second terminal of the first diode, the second terminal of the first capacitor, the third terminal of the second switching transistor, the first terminal of the second diode and the first terminal of the second switching unit. The second end of the first resistor is used to connect to the output terminal. The second end of the second resistor is used to connect to the first end of the third resistor, the first end of the second switching transistor, the second end of the second switching transistor, and the second end of the second diode. The second end of the third resistor is used to connect to the ground terminal, the second end of the second switching unit, and the second end of the first switching unit.

4. The chip protection circuit according to claim 2, characterized in that, The third switching unit includes a first switching transistor and a first diode, and the control unit includes a second resistor, a third resistor, a Zener diode, a first capacitor, a third switching transistor, a third diode, a current source, a fourth switching transistor, and a fourth diode. The first terminal of the first switching transistor is used to connect to the first terminal of the first switching unit and the first terminal of the first diode. The second terminal of the first switching transistor is used to connect to the first terminal of the third switching transistor, the first terminal of the third diode, the first terminal of the first capacitor, and the first terminal of the second resistor. The third terminal of the first switching transistor is used to connect to the second terminal of the first diode, the second terminal of the first capacitor, the third terminal of the fourth switching transistor, the first terminal of the fourth diode, the first terminal of the third resistor, the first terminal of the Zener diode, and the first terminal of the second switching unit. The second terminal of the third switch is used to connect to the ground terminal, the third terminal of the third switch is used to connect to the second terminal of the third diode and the first terminal of the current source, the second terminal of the current source is used to connect to the output terminal, the second terminal of the second resistor is used to connect to the first terminal of the fourth switch, the second terminal of the fourth switch and the second terminal of the fourth diode, wherein the second terminal of the third resistor is used to connect to the second terminal of the Zener diode and the ground terminal.

5. The chip protection circuit according to claim 3, characterized in that, The chip protection circuit includes a first resistor unit, and the first resistor unit includes a fourth resistor; The power unit includes a fifth switching transistor and a fifth diode, the first switching unit includes a sixth switching transistor and a sixth diode, the second switching unit includes a seventh switching transistor and a seventh diode, and the static discharge unit includes a static discharge diode. The first terminal of the fifth switch is connected to the first terminal of the fifth diode, the first terminal of the electrostatic discharge diode, and the output terminal; the second terminal of the fifth switch is connected to the first terminal of the sixth switch and the first terminal of the sixth diode; the third terminal of the fifth switch is connected to the input terminal and the second terminal of the fifth diode; and the second terminal of the electrostatic discharge diode is connected to the ground terminal. The second terminal of the sixth switch is connected to the first terminal of the fourth resistor, the second terminal of the third resistor, and the second terminal of the seventh switch; the third terminal of the sixth switch is connected to the first terminal of the first switch and the first terminal of the first diode; and the second terminal of the fourth resistor is connected to the ground terminal. The first terminal of the seventh switch is connected to the input terminal and the first terminal of the seventh diode, and the third terminal of the seventh switch is connected to the third terminal of the first switch, the second terminal of the first diode, the third terminal of the second switch, and the second terminal of the second diode.

6. The chip protection circuit according to claim 5, characterized in that, When the input terminal is at a negative voltage, the seventh switch, the first switch, and the sixth switch are turned on, while the fifth switch is turned off. When there is no voltage at the input terminal and the electrostatic discharge diode outputs a negative electrostatic discharge voltage, the seventh switch, the first switch, and the sixth switch are cut off, and the fifth switch is turned on.

7. The chip protection circuit according to claim 4, characterized in that, The chip protection circuit also includes a first resistor unit, which includes a fourth resistor. The power unit includes a fifth switching transistor and a fifth diode, the first switching unit includes a sixth switching transistor and a sixth diode, the second switching unit includes a seventh switching transistor and a seventh diode, and the static discharge unit includes a static discharge diode. The first terminal of the fifth switching transistor is connected to the first terminal of the fifth diode, the first terminal of the electrostatic discharge diode, and the output terminal. The second terminal of the fifth switching transistor is connected to the first terminal of the sixth switching transistor and the first terminal of the sixth diode. The third terminal of the fifth switching transistor is connected to the input terminal and the second terminal of the fifth diode. The second terminal of the electrostatic discharge diode is connected to the ground terminal. The second terminal of the sixth switch is connected to the first terminal of the fourth resistor, the second terminal of the third resistor, the second terminal of the Zener diode, and the second terminal of the seventh switch. The third terminal of the sixth switch is connected to the first terminal of the first switch, the first terminal of the first diode, and the first terminal of the sixth diode. The second terminal of the fourth resistor is connected to the ground terminal. The first terminal of the seventh switch is connected to the input terminal, and the third terminal of the seventh switch is connected to the third terminal of the first switch, the second terminal of the first diode, the third terminal of the fourth switch, the second terminal of the fourth diode, the first terminal of the third resistor, and the first terminal of the Zener diode.

8. The chip protection circuit according to claim 7, characterized in that, When the input terminal is at a negative voltage, the seventh switch, the first switch, and the sixth switch are turned on, while the fifth switch is turned off. When there is no voltage at the input terminal and the static discharge diode outputs a negative static discharge current, the seventh switch, the first switch, and the sixth switch are turned off, and the fifth switch is turned on.

9. The chip protection circuit according to claim 5 or 7, characterized in that, The first, second, third, fourth, fifth, sixth, and seventh switching transistors are N-channel field-effect transistors.

10. A chip, characterized in that, Includes the chip protection circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, Includes the chip described in claim 10.

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