Multi-machine parallel cooperative control method and system of lightweight converter

Abstract

The invention discloses a multi-machine parallel cooperative control method and system of a lightweight converter, and relates to the field of power electronics and electrical transmission. The method comprises the following steps: collecting local voltage and current time sequence data; extracting higher harmonic information through harmonic analysis, constructing and identifying an equivalent admittance model of the parallel system, and estimating a potential high-frequency circulating current vector; therefore, multi-frequency compensation voltage signals with opposite phases and matched amplitudes are generated and are superposed with the fundamental wave reference voltage to form a composite modulation wave, and a power device is driven to realize circulation feed-forward offset. According to the method, control over high-frequency circulation feed-forward suppression can be achieved without global communication, the problem of control failure caused by communication delay under a distributed control architecture is solved, and therefore the stability and reliability of the multi-machine parallel light-weight converter unit are improved.

Description

Technical Field

[0001] This invention belongs to the field of power electronics and electrical drives, and specifically relates to a method and system for multi-machine parallel coordinated control of a lightweight converter. Background Technology

[0002] With the rapid development of new energy power generation, energy storage systems, and electric transportation, lightweight converters have been widely used in distributed energy systems due to their high power density and compact structure. Parallel operation of multiple converters, as a key means to improve system capacity and redundancy, has become an important architectural form of modern power electronic systems. This architecture achieves power sharing and load balancing by connecting multiple converter units in parallel to a common bus, thereby meeting the engineering requirements of high reliability and scalability.

[0003] Multi-unit parallel systems using lightweight converters typically employ distributed control strategies to avoid single-point-of-failure risks. These strategies rely on local information for autonomous adjustment, with typical schemes including droop control and its adaptive improvements. The basic principle is to simulate the frequency-active and voltage-reactive characteristics of a synchronous generator, allowing each converter to dynamically adjust its output based on local measurements to achieve power sharing. However, in real-world systems, unavoidable minor differences exist between converters in terms of component parameters, line impedance, and control delays, making it difficult for the output voltage phase and amplitude to be perfectly synchronized, thus generating high-frequency circulating currents between parallel units.

[0004] In existing technologies, some adaptive droop control methods attempt to suppress circulating current by introducing a global communication mechanism to correct parameter deviations in real time. However, such solutions not only increase system complexity and cost, but also struggle to respond promptly to high-frequency dynamic circulating currents due to communication latency and bandwidth limitations. Especially under lightweight design constraints, heat dissipation capacity is limited, and persistent high-frequency circulating currents can easily cause local overheating, accelerating the aging of power devices and even leading to thermal failure. Furthermore, traditional control frameworks that rely entirely on periodic sampling and continuous communication cannot balance response speed and resource efficiency, and face stability risks in scenarios without communication or with communication interruptions. Therefore, there is an urgent need for an active circulating current suppression mechanism that does not require global communication, is based solely on local instantaneous electrical quantities, and possesses event-driven characteristics, in order to achieve efficient and reliable collaborative operation of lightweight multi-machine parallel systems. Summary of the Invention

[0005] To address the shortcomings of existing technologies, one of the objectives of this invention is to provide a multi-machine parallel collaborative control method for lightweight converters. This method can achieve high-frequency circulating current feedforward suppression control without global communication, thereby eliminating control failures caused by communication delays in distributed control architectures and improving the stability and reliability of multi-machine parallel lightweight converter units.

[0006] The second objective of this invention is to provide a system for implementing the multi-machine parallel coordinated control method of the lightweight converter.

[0007] This invention provides a multi-machine parallel coordinated control method for a lightweight converter, which includes the following steps:

[0008] S1. Real-time acquisition of voltage timing data and current timing data of the local output ports of each parallel converter unit; the sampling frequency of the acquisition process is set to 20 to 50 times the switching frequency of the parallel converter unit;

[0009] S2. Perform harmonic analysis on the collected voltage and current time-series data to extract electrical information of several harmonic components within a preset high-frequency band; the electrical information includes voltage amplitude, voltage phase, current amplitude, and current phase information;

[0010] S3. Based on the electrical information of the harmonic components, construct the multi-node admittance matrix of the parallel converter unit, and use the recursive least squares method to identify the matrix parameters online, and solve the system state equation characterizing the high-frequency dynamic characteristics of the entire parallel system.

[0011] S4. Using the system state equation, calculate the amplitude and phase angle of the potential high-frequency circulating current superimposed on the common AC bus induced by the inherent parameter differences between each parallel converter unit, and form the feedforward compensation target vector;

[0012] S5. Based on the feedforward compensation target vector, synthesize a multi-frequency superimposed digital compensation voltage signal;

[0013] Each frequency component of the digital compensation voltage signal is 180 degrees out of phase with the corresponding frequency component of the potential high-frequency circulating current, and its amplitude is proportional to the product of the corresponding frequency component of the potential high-frequency circulating current and the equivalent impedance of the common AC bus.

[0014] S6. The digital compensation voltage signal is digitally added point by point to the fundamental sinusoidal reference voltage signal of the parallel converter unit to generate a composite modulation reference signal;

[0015] S7. The composite modulation reference signal is input to the pulse width modulator and compared with a fixed-frequency triangular carrier wave to generate a pulse width modulation signal sequence that drives the power semiconductor switching devices inside the parallel converter unit, thereby realizing injection-type cancellation control of potential high-frequency circulating current.

[0016] Step S1 specifically includes the following steps:

[0017] A sampling voltage signal that is linearly proportional to the output voltage is obtained by using a high-impedance precision resistor voltage divider network connected in parallel with the output terminal of the parallel converter unit.

[0018] A high-bandwidth current sensor based on the closed-loop fluxgate principle, connected in series in the output circuit of the parallel converter unit, is used to acquire a sampled current signal that is linearly proportional to the output current.

[0019] The sampled voltage signal and sampled current signal are respectively input to a dual-channel, 16-bit resolution, synchronous sampling analog-to-digital converter with a sampling rate of more than 1 million times per second for quantization processing to generate discrete digital voltage sequences and digital current sequences.

[0020] Step S2 specifically includes the following steps:

[0021] A field-programmable gate array is set as a coprocessor, which has a fast Fourier transform algorithm core for fixed-point arithmetic embedded inside.

[0022] The digital voltage sequence and the digital current sequence are sent into the field-programmable gate array in the form of fixed-length data frames;

[0023] The Fast Fourier Transform algorithm transforms each data frame and outputs complete spectrum data covering the DC component to the Nyquist frequency. The spectrum data includes amplitude and phase frequency information at each frequency point.

[0024] From the spectrum data, the odd-numbered harmonic frequencies of the switching frequency are extracted, specifically the complex representations of harmonic voltage and harmonic current at 3 times, 5 times, 7 times, 9 times, and 11 times the switching frequency.

[0025] Step S3 specifically includes the following steps:

[0026] Each parallel converter unit is equivalent to a combination of a controlled current source and parallel admittance at a specific harmonic frequency.

[0027] The common AC bus is equivalent to an impedance node with lumped parameters;

[0028] Based on Kirchhoff's current law, a set of linear equations is established to describe the relationship between the harmonic currents of all parallel converter units and the harmonic voltage of the common AC bus.

[0029] The coefficient matrix of the equation system is the multi-node admittance matrix, where the diagonal elements are the self-admittances of each unit and the off-diagonal elements are the mutual admittances between units.

[0030] Using a Kalman filter, the locally measured harmonic voltage and harmonic current are taken as observations, and the elements of the multi-node admittance matrix are taken as state variables to be estimated. Through an iterative filtering process, the accurate admittance matrix parameters are identified in real time, thereby obtaining the system state equation that can accurately reflect the current operating conditions of the system.

[0031] Step S5 is as follows:

[0032] Inside the digital signal processor, an independent digital sine wave generator is instantiated for each harmonic frequency that needs to be compensated;

[0033] The amplitude and phase angle of each harmonic frequency in the feedforward compensation target vector are respectively set as the amplitude control word and phase control word of the corresponding digital sine wave generator;

[0034] All digital sine wave generators are started synchronously, and their output discrete sine wave sequences are accumulated point by point to form the final digital compensation voltage signal time sequence containing multiple harmonic components, thus obtaining a multi-frequency superimposed digital compensation voltage signal.

[0035] The present invention also provides a system for implementing the multi-machine parallel cooperative control method of the lightweight converter, including a high-frequency transient data acquisition module, a virtual impedance state observation module, a predictive harmonic injection compensation module, and a local pulse width modulation signal generation module; the system is applied in a parallel AC unit;

[0036] The input terminal of the high-frequency transient data acquisition module is electrically connected to the output terminal of the parallel converter unit, and is used to synchronously acquire the voltage and current waveforms output by the parallel converter unit and convert them into a high-precision digital time series.

[0037] The virtual impedance state observation module is connected to the data output terminal of the high-frequency transient data acquisition module. It is used to perform harmonic analysis on the received digital time series and identify the equivalent network model of the entire parallel system online based on the analysis results, thereby calculating the potential high-frequency circulating current vector.

[0038] The predicted harmonic injection compensation module is connected to the data output terminal of the virtual impedance state observation module, and is used to generate a digital compensation voltage waveform that cancels out the potential circulating current based on the potential high-frequency circulating current vector.

[0039] The local pulse width modulation signal generation module has two input terminals. Input terminal 1 is used to receive an externally given fundamental reference voltage command, and input terminal 2 is used to receive the digital compensation voltage waveform generated by the predictive harmonic injection compensation module. The local pulse width modulation signal generation module superimposes the two input signals and generates the final pulse width modulation control signal for driving the power devices of the parallel converter unit based on the superimposed composite signal.

[0040] The high-frequency transient data acquisition module includes a Hall effect current sensor, a resistive voltage divider, and an analog-to-digital converter (ADC). The Hall effect current sensor is connected in series with the output phase line of the converter. The resistive voltage divider is connected across the output line and the neutral line of the converter. The ADC has an 18-bit conversion accuracy, and its sampling clock is provided by a local crystal oscillator calibrated with a GPS timing signal to ensure that the data acquisition of all parallel units is synchronized at the sub-microsecond level on the time base.

[0041] The core of the virtual impedance state observation module is a digital signal processor, which is pre-configured with a Goertzel algorithm module for harmonic decomposition and an extended Kalman filter algorithm module for system parameter identification. The Goertzel algorithm module is configured to calculate only a few preset high-order harmonic frequencies to reduce computational complexity. The extended Kalman filter algorithm module uses locally measured harmonic voltage and current as input to perform state estimation on a nonlinear state-space model describing the harmonic interaction behavior of a parallel system, and outputs accurate estimates of the system interconnect impedance and circulating current sources.

[0042] The predictive harmonic injection compensation module includes a lookup table unit and a waveform synthesis unit. The lookup table unit stores parameters of the optimal compensation harmonic components corresponding to different circulating current amplitudes and phases, calculated in advance. The predictive harmonic injection compensation module first retrieves the optimal set of compensation harmonic parameters from the lookup table unit based on the input potential high-frequency circulating current vector. Then, the waveform synthesis unit generates a multi-frequency composite compensation voltage digital waveform in real time based on the parameter set using direct digital frequency synthesis technology.

[0043] The local pulse width modulation signal generation module is a digital circuit implemented in a field-programmable gate array (FPGA), comprising a digital adder, a fundamental sine read-only memory, a digital comparator, and a high-frequency counter. The fundamental sine read-only memory outputs fundamental reference voltage sampling points according to external frequency and amplitude commands. The digital adder adds the fundamental reference voltage sampling points to the compensation voltage sampling points output by the predictive harmonic injection compensation module. The high-frequency counter generates a high-precision digital triangular wave carrier sequence. The digital comparator compares the added composite signal with the digital triangular wave carrier sequence, and its output is the high-resolution pulse width modulation signal.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] 1. The method of the present invention completely eliminates the physical communication link between parallel units by adopting a control method of pure local measurement and calculation, fundamentally eliminating the control lag problem caused by communication delay and network congestion, so that the response speed of circulating current suppression is only limited by the local processor's operation cycle, and achieves near-instantaneous suppression of high-frequency circulating current.

[0046] 2. The method of this invention transforms passive feedback suppression into active feedforward prediction compensation. By using a virtual impedance state observation module, the physical root cause of the system circulating current, namely parameter inconsistency, is accurately identified and quantified online. Thus, before the circulating current has formed a significant amplitude, an accurate cancellation component is injected, which greatly reduces the current stress and thermal stress borne by the power devices and avoids local overheating.

[0047] 3. This invention has a high degree of plug-and-play capability and system scalability. Since the control decisions of each converter unit are completely independent, adding or removing units does not require any modification to the control parameters or communication topology of existing units, which significantly improves the modularity, flexibility and ease of on-site maintenance of the system.

[0048] 4. The method of the present invention reduces the electromagnetic interference level of the system by effectively suppressing high-frequency circulating current, improves the output power quality, avoids additional power loss caused by circulating current, improves the operating efficiency and grid compatibility of the entire parallel system, extends the service life of the equipment, and ensures the long-term stable and reliable operation of the distributed energy system.

[0049] 5. By introducing reduced-order Kalman filtering and anti-saturation prediction algorithms, the method of this invention significantly reduces computational resource overhead and power consumption while maintaining high-precision circulating current suppression. This further enhances the lightweight design, enabling the converter unit to operate efficiently on resource-constrained embedded platforms and expanding its application scenarios to a wider range of industrial fields.

[0050] 6. This invention utilizes an adaptive event-triggered communication mechanism, enabling the system to intelligently initiate short-term data exchange under critical conditions without the need for conventional communication. This achieves the optimal balance between global coordination and local autonomous control, thereby maintaining the stability and reliability of the system under extreme conditions and avoiding the risk of loss of control that may occur in traditional non-communication systems. Attached Figure Description

[0051] Figure 1 This is a flowchart illustrating the method of the present invention;

[0052] Figure 2 This is a schematic diagram of the system architecture of the present invention;

[0053] Figure 3This is a flowchart illustrating the logic of high-frequency transient data acquisition and harmonic component extraction in this invention.

[0054] Figure 4 This is a flowchart illustrating the logical flow of multi-node admittance matrix construction and online identification of system state equations in this invention. Detailed Implementation

[0055] This invention provides a multi-machine parallel coordinated control method for a lightweight converter, the flowchart of which is shown below. Figure 1 As shown, it includes the following steps:

[0056] S1. Real-time acquisition of voltage timing data and current timing data of the local output ports of each parallel converter unit; the sampling frequency of the acquisition process is set to 20 to 50 times the switching frequency of the parallel converter unit;

[0057] In step S1, voltage timing data and current timing data of the local output ports of each parallel converter unit are acquired in real time. This step is specifically implemented by: obtaining a sampled voltage signal linearly proportional to the output voltage through a high-impedance precision resistor divider network connected in parallel with the output terminals of the parallel converter units; this resistor divider network consists of two metal film resistors with a temperature coefficient of less than ten ppm per degree Celsius, and its voltage division ratio is precisely set according to the rated output voltage range of the converter to ensure that the output signal does not exceed the input range of the subsequent analog-to-digital converter throughout the entire operating range.

[0058] Simultaneously, a high-bandwidth current sensor based on the closed-loop fluxgate principle, connected in series in the output circuit of the parallel converter unit, acquires a sampled current signal linearly proportional to the output current. This current sensor has a bandwidth higher than 500 kHz, a nonlinearity of less than 0.01%, and good DC bias suppression capability to accurately capture transient current waveforms containing high-frequency harmonic components. Subsequently, the sampled voltage signal and sampled current signal are respectively input to a dual-channel, 16-bit resolution, synchronous sampling analog-to-digital converter with a sampling rate higher than 1 million times per second for quantization processing to generate discrete digital voltage and digital current sequences.

[0059] The sampling clock of this analog-to-digital converter is provided by a local crystal oscillator calibrated with a GPS timing signal, ensuring that the data acquisition of all parallel converter units is synchronized at the sub-microsecond level on the time base, thereby eliminating phase errors introduced by sampling time deviations and providing high-fidelity raw data for subsequent harmonic analysis.

[0060] S2. Perform harmonic analysis on the collected voltage and current time-series data to extract the electrical information of several harmonic components within a preset high-frequency band. The schematic diagram is shown below. Figure 3 As shown;

[0061] The electrical information includes voltage amplitude, voltage phase, current amplitude, and current phase information;

[0062] In step S2, harmonic analysis is performed on the acquired voltage and current time-series data to extract the voltage amplitude, voltage phase, current amplitude, and current phase information of multiple harmonic components within a preset high-frequency band. This step is specifically implemented by setting a field-programmable gate array (FPGA) as a coprocessor, which internally contains a fixed-point Fast Fourier Transform (FFT) algorithm core. This algorithm core employs a radix-2 time decimation structure, supports data frame processing of 1024 points, and has a fixed computation latency of 10 microseconds.

[0063] The digital voltage and current sequences are fed into the field-programmable gate array (FPGA) in fixed-length data frames. Each data frame contains 1024 continuously acquired sampling points, with a 50% overlap between frames to improve spectral resolution and temporal continuity. The Fast Fourier Transform (FFT) algorithm transforms each data frame, outputting complete spectral data covering the DC component to the Nyquist frequency. This spectral data includes amplitude and phase information for each frequency point and is stored in complex form in the internal dual-port random access memory (DRAM).

[0064] Subsequently, from the spectral data, odd-numbered harmonic frequencies at the switching frequency are extracted, specifically the complex representations of harmonic voltages and currents at 3, 5, 7, 9, and 11 times the switching frequency. These frequencies are selected as key observation targets because they are primarily excited by the non-ideal switching behavior of power switching devices and parameter mismatch of filter inductors and capacitors in lightweight converters, representing the main energy concentration areas of high-frequency circulating currents. The extraction process directly accesses the complex storage units corresponding to the frequency points through address mapping, avoiding redundant calculations and ensuring real-time data processing.

[0065] Furthermore, in order to enhance the global stability of the lightweight converter multi-machine parallel collaborative control system of the present invention while maintaining the lightweight requirement, an adaptive communication triggering sub-step is introduced after the spectrum analysis and decomposition step is completed. This adaptive communication triggering, through intelligent event detection and dynamic decision-making mechanism, enables short-term communication to be triggered only when the system is abnormal, effectively optimizing resource utilization and improving response efficiency.

[0066] The adaptive communication triggering sub-step enables intelligent event-triggered communication by supporting frequency domain processing and dynamic decision-making of harmonic components through real-time analysis of high-frequency sampled local voltage and current data. This sub-step is based on real-time analysis of local electrical signals, including high-frequency sampled voltage and current data. It monitors circulating current trends through frequency domain processing of harmonic components, and uses an adaptive timer for triggering decisions. Finally, it executes data exchange through a lightweight wireless protocol. The specific implementation includes the following:

[0067] 1. In the event detection phase, harmonic components of voltage and current, such as the 3rd, 5th, and 7th harmonics, are first extracted from local high-frequency sampling data. These extracted harmonic components are directly related to the circulating current dynamics between parallel converter units. Frequency domain analysis is performed on the harmonic amplitude sequence, calculating its Discrete Fourier Transform (DFT), with a focus on the changing trend of the fundamental frequency harmonic component. The DFT calculation is defined as follows: for a sequence containing N sampling points… Transformation results It can be expressed by the following formula: ;

[0068] Where k is the frequency index and j is the imaginary unit, N is typically set to 64 to balance computational accuracy and real-time performance. Based on this, the system calculates the harmonic attenuation threshold RSS_FFT, which is dynamically updated using the sliding window mean of historical data. E[X(1)] represents the historical expected value of the fundamental harmonic component X(1), which is calculated by the moving average of the most recent 100 sampling points. The initial value is set to 5% of the fundamental amplitude. For a typical system, when the fundamental voltage is 220V, the initial threshold value is 11V to ensure sensitive detection of circulating current deterioration.

[0069] For example, a sequence containing 64 sampling points is set up, and the harmonic attenuation threshold is calculated using the transformation results. This threshold is dynamically adjusted based on the sliding window mean of historical data to reflect real-time fluctuations in the system state. When the harmonic amplitude falls below the threshold, it indicates an increased risk of circulation, and the system enters the trigger decision phase. The event detection process ensures the sensitivity and adaptability of detection, avoiding misjudgments or delays that might occur with a fixed threshold.

[0070] 2. The trigger decision phase employs a dynamic dwell timer mechanism, the core of which is to optimize the trigger timing by comprehensively considering the circulation trend and communication interval factor. The timer's base dwell time is set to... Seconds, and based on the influence factor of the circulation change rate. and communication interval influence factor Make dynamic adjustments.

[0071] The calculation is based on the change in the amplitude of the most recent 10 harmonics. First, calculate Where harmonic(i) represents the harmonic amplitude at time i; if (Indicating a deteriorating circulation trend), then (STEP is the step size, set to 0.1), otherwise .

[0072] The calculation depends on the communication interval: define the switching interval threshold K = 5 control cycles, and calculate the time interval between the current and the last trigger. (in terms of the number of cycles); if ,but ,otherwise The final trigger condition is that the duration t of the current state (starting from the last trigger) satisfies the inequality. And at the same time, harmonic amplitude N is the sequence length, ensuring that communication is activated only when the risk of circulation is high.

[0073] For example, by monitoring the changes in the amplitude of the last 10 harmonics, a trend factor is calculated. If the high-frequency circulating current deteriorates, the triggering tendency is increased, and vice versa. Simultaneously, the communication interval factor is based on a comparison between the last trigger time and a preset threshold (e.g., 5 control cycles) to prevent frequent communication. The final triggering condition must simultaneously satisfy both the harmonic attenuation threshold criterion and the timer condition, ensuring that communication is only activated when the system is in a critical state, such as a sudden change in circulating current amplitude or an excessive power deviation, thereby reducing unnecessary resource overhead.

[0074] 3. The communication execution section involves the use of lightweight wireless protocols, such as Zigbee technology, whose low power consumption and low latency characteristics meet the lightweight objective of this application. After triggering, the system exchanges key data with neighboring converter nodes, including local circulating current harmonic amplitude, instantaneous active and reactive power values, and estimated admittance matrix parameters. This key data is used to correct local control strategies, such as compensation signal generation.

[0075] The communication duration is a short pulse of less than 5 milliseconds, with the duty cycle strictly controlled below 1%. The system immediately resumes a no-communication mode afterward, ensuring extremely low average communication overhead. The entire sub-step is seamlessly integrated into a multi-machine parallel collaborative control system via an event-driven approach, effectively reducing triggering frequency and improving circulating current suppression, thereby enhancing system robustness while maintaining a lightweight design.

[0076] S3. Based on the electrical information of the harmonic components, construct the multi-node admittance matrix of the parallel converter unit, and use the recursive least squares method to identify the matrix parameters online, and solve the system state equation characterizing the high-frequency dynamic characteristics of the entire parallel system. Its schematic diagram is shown below. Figure 4 As shown;

[0077] In step S3, based on the electrical information of the harmonic components, a multi-node admittance matrix of the parallel converter unit is constructed, and the matrix parameters are identified online using the recursive least squares method to solve the system state equation characterizing the high-frequency dynamic characteristics of the entire parallel system. This step specifically includes: equating each parallel converter unit at a specific harmonic frequency with a combination of a controlled current source and parallel admittance; wherein the controlled current source represents the harmonic current command generated by the local control strategy, and the parallel admittance characterizes the output impedance characteristics of the unit at that frequency, including the combined effects of filter inductance, capacitance, and parasitic parameters.

[0078] The common AC bus is equivalent to an impedance node with lumped parameters, whose impedance value is determined by the bus length, cross-sectional area, and material, exhibiting inductive characteristics at high frequencies. Based on Kirchhoff's current law, a system of linear equations describing the relationship between the harmonic currents of all parallel converter units and the harmonic voltage of the common AC bus is established. For a system with N parallel units, at the k-th harmonic frequency, this system of equations can be expressed as: ;in, It is an N-dimensional harmonic current vector. It is a harmonic voltage scalar on the common bus (assuming it is a single-phase system or a three-phase symmetrical system). This is an N-dimensional multi-node admittance matrix. The coefficient matrix of the equation system is the multi-node admittance matrix, and its diagonal elements... Let i be the self-admittance of the i-th unit, and let the off-diagonal elements be the self-admittance. The mutual admittance between element i and element j should theoretically be zero, but due to the existence of bus impedance, it actually exhibits weak coupling.

[0079] To accurately identify the matrix, a Kalman filter is used. The locally measured harmonic voltage and harmonic current are taken as observations, and the elements of the multi-node admittance matrix are taken as state variables to be estimated. Through an iterative filtering process, the accurate admittance matrix parameters are identified in real time.

[0080] The state transition equation of the Kalman filter assumes that the admittance matrix changes slowly over a short timescale, the process noise covariance matrix is ​​dynamically adjusted based on historical identification errors, and the observation noise covariance is set according to sensor accuracy. After several iterations, the filter outputs a convergent estimate of the admittance matrix, thus obtaining a dynamic state equation that accurately reflects the current operating condition of the system, providing a physical model basis for circulation prediction.

[0081] In addition, in order to improve the efficiency of parameter identification of the system while maintaining the lightweight characteristics of low computational load, this invention adopts the reduced-order Kalman filter technique for the estimation of key state variables, thereby significantly reducing complexity while maintaining estimation accuracy.

[0082] The purpose of reduced-order Kalman filtering is to reduce the dimensionality of the state vector, estimating only the variables that play a dominant role in the system dynamics, rather than covering the entire state. In this invention, the system state originally includes the impedance parameters, harmonic components, and environmental variables of all converter nodes, which have a high dimensionality. Therefore, this invention uses sensitivity analysis or prior knowledge to screen out key state variables. These key state variables are directly related to the main harmonic components of the circulating current, such as the equivalent resistance and reactance parameters corresponding to the 5th, 7th, and 11th harmonics.

[0083] Specifically, the state dimension is reduced from n-dimensional to k-dimensional (k is much smaller than n, for example, k=6, corresponding to 6 key impedance parameters), thereby reducing the computational complexity from cubic level ( Reduced to linear level ( ), where k is a fixed small value. The order reduction processing is based on the observability theory of system dynamics, that is, in most systems only a few states have a significant impact on the output; ignoring minor states can reduce redundant computation without sacrificing core performance. Specific implementation methods include the following:

[0084] 1. Selection of Key State Variables: Based on the characteristics of the multi-machine parallel system of this invention, the impedance parameters corresponding to the dominant circulating current harmonics are determined through offline analysis or online learning. For example, through statistical analysis of historical data, the equivalent resistance, reactance, resistance, reactance, resistance, and reactance of the 5th harmonic, 7th harmonic, 11th harmonic, and 11th harmonic are selected as key state variables, k=6. These parameters are directly derived from the relationship between harmonic voltage and current, and their selection is based on their contribution to the circulating current amplitude. Through contribution factor calculation, states with a sensitivity coefficient greater than the threshold of 0.1 are retained.

[0085] 2. Construction of the Reduced-Order State-Space Model: Simplified state equations and observation equations are established. The state equations describe the evolution of key state variables; for example, assuming the impedance parameter changes slowly over time, a first-order autoregressive model is used. The state equation expression is: ,in, It is the state transition matrix (dimension) ), which is usually set as a diagonal matrix, with the diagonal elements representing the autocorrelation strength of the parameters; It is the process noise vector (dimension) Its covariance matrix is (dimension) The initial values ​​are determined using historical data. The observation equation then linearly correlates the system output with the key state variables; the expression for the observation equation is: ,in, It is the observation matrix (dimension) This is derived from the linear relationship between harmonic voltage and current; It is the observation noise vector (dimension) Its covariance matrix is ​​(dimensions 1-1). The initial value is set to 0.1I to reflect measurement uncertainty. Model parameters are initialized through system identification or physical derivation, such as the state transition matrix and observation matrix, and are adaptively updated at runtime.

[0086] 3. Algorithm execution flow: The following sub-steps are executed in each cycle:

[0087] 3.1 State Prediction: Using the key state estimates from the previous time step, the predicted value for the current time step is calculated through the state transition matrix. The state transition matrix is ​​usually set as a diagonal matrix, and the diagonal elements represent the autocorrelation strength of the parameters (e.g., 0.95 indicates high correlation).

[0088] 3.2 Measurement Correction: Real-time harmonic voltage and current data are acquired, observed values ​​are calculated, and compared with predicted values. The Kalman gain is dynamically calculated based on the prediction error covariance and measurement noise covariance, and is used to correct the predicted values. The noise covariance is calibrated using historical data, such as setting the process noise covariance to 0.01 and the measurement noise covariance to 0.1, to reflect system uncertainty.

[0089] 3.3 Covariance Update: Update the error covariance matrix to provide a basis for the next period's prediction. Due to the reduced dimensionality, the speed of operations such as matrix inversion is improved.

[0090] 4. Integration and Scheduling: The reduced-order Kalman filter module is deployed as an independent unit and runs once every 100 control cycles to avoid frequent calls. The running results are only used to enhance state estimation and do not replace the original filter output, ensuring backward compatibility.

[0091] It should be noted that the order reduction method reduces computation by focusing on critical states; in multi-machine parallel systems, the circulating current is mainly dominated by a few harmonics, so the order reduction estimation does not significantly lose accuracy. Actual test data shows that in similar systems, order reduction filtering can shorten the computation time from 10 milliseconds to 1 millisecond while keeping the estimation error within 5%.

[0092] S4. Using the system state equation, calculate the amplitude and phase angle of the potential high-frequency circulating current superimposed on the common AC bus induced by the inherent parameter differences between each parallel converter unit, and form the feedforward compensation target vector;

[0093] In step S4, the amplitude and phase angle of the potential high-frequency circulating current superimposed on the common AC bus, induced by the inherent parameter differences between the parallel converter units, are calculated using the system state equation, forming the feedforward compensation target vector. This calculation is based on the principle that if all unit parameters are completely identical and the control is synchronized, the harmonic currents output by each unit will cancel each other out on the common bus, resulting in zero circulating current. However, in actual systems, due to factors such as filter inductance deviations, switching dead time differences, and inconsistent drive circuit delays, the harmonic currents generated by each unit under the same fundamental frequency command exhibit phase and amplitude deviations, leading to a net harmonic voltage on the common bus, which in turn drives the circulating current.

[0094] Using the identified admittance matrix and locally measured harmonic current The harmonic voltage of the common bus can be deduced. (Assuming the effects of other units are already included) (In the middle), then calculate the induced current in other units due to this voltage, and finally obtain the circulating current component flowing through unit i and other units. This circulating current vector is represented in the complex plane as: , which is the feedforward compensation target vector.

[0095] S5. Based on the feedforward compensation target vector, synthesize a multi-frequency superimposed digital compensation voltage signal;

[0096] Each frequency component of the digital compensation voltage signal is 180 degrees out of phase with the corresponding frequency component of the potential high-frequency circulating current, and its amplitude is proportional to the product of the corresponding frequency component of the potential high-frequency circulating current and the equivalent impedance of the common AC bus.

[0097] In step S5, a multi-frequency superimposed digital compensation voltage signal is synthesized based on the feedforward compensation target vector. This step specifically includes: Within the digital signal processor, an independent digital sine wave generator is instantiated for each harmonic frequency requiring compensation (3 times, 5 times, 7 times, 9 times, and 11 times the switching frequency); each generator consists of a phase accumulator, a sine lookup table, and an amplitude scaling unit. The amplitude and phase angle corresponding to each harmonic frequency in the feedforward compensation target vector are set as the amplitude control word and phase control word of the corresponding digital sine wave generator, respectively; the phase control word is used to initialize the initial value of the phase accumulator, ensuring that the generated compensation waveform is strictly out of phase with the circulating current. All digital sine wave generators are started synchronously, and their output discrete sine sequences are accumulated point by point to form the final digital compensation voltage signal time sequence containing multiple harmonic components. The mathematical expression of this compensation voltage signal is: ;in, The converter switching frequency, This is the equivalent impedance of the common bus under the k-th harmonic, and its value can be derived by inverse derivation of the admittance matrix or obtained through offline calibration. The negative sign ensures phase reversal, and the amplitude is proportional to the product of the circulating current and the bus impedance to achieve precise cancellation.

[0098] S6. The digital compensation voltage signal is digitally added point by point to the fundamental sinusoidal reference voltage signal of the parallel converter unit to generate a composite modulation reference signal;

[0099] In step S6, the digitally compensated voltage signal is digitally added point-by-point to the fundamental sinusoidal reference voltage signal of the parallel converter unit to generate a composite modulation reference signal. The fundamental reference voltage signal is generated by the upper-level energy management system or the local voltage loop controller, and is typically a standard sine wave with a frequency of 50 Hz or 60 Hz. The digital adder performs fixed-point addition on the current sampling points of the two signals in each control cycle, and outputs the result after saturation processing to prevent overflow and modulation distortion.

[0100] Specifically, saturation processing, as a passive mechanism, can lead to signal distortion under dynamic operating conditions because hard truncation introduces nonlinear distortion, affecting the accuracy of circulating current suppression. To effectively improve the performance of saturation processing, this invention introduces an anti-saturation prediction algorithm. This algorithm dynamically detects potential overflow risks through a predictive mechanism and compresses the dynamic range of the signal in advance, thereby avoiding distortion while maintaining the compensation effect.

[0101] The core idea of ​​the anti-saturation prediction algorithm is to monitor the trend of the input signal in real time before the digital adder performs the addition operation, predict whether the future sampling point may overflow, and dynamically adjust the amplitude of the compensation signal to ensure that the addition result is always within the effective range of the digital representation, such as the range of [-1, 1] of a 16-bit fixed-point number.

[0102] The implementation of the anti-saturation prediction algorithm comprises three key parts: signal trend prediction, overflow risk assessment, and dynamic gain adjustment. All operations are implemented in a digital signal processor (DSP) or FPGA, resulting in low computational overhead and ensuring real-time performance. Specific implementation methods include the following:

[0103] 1. Signal trend prediction stage: Through a sliding window linear prediction model, the changing trends of the compensation voltage signal and the fundamental reference voltage signal are analyzed in real time to identify potential spillover risks in advance.

[0104] During algorithm initialization, the sliding window size is set to N sampling points, corresponding to a window duration of 100 microseconds at a sampling rate of 100kHz. The most recent N sampled values ​​of the compensated voltage signal and the fundamental reference voltage signal are stored. For each new sampling point n, the algorithm calculates the linear trends of the compensated signal sequence and the fundamental signal sequence within the window, i.e., the trend slopes of the compensated voltage signal and the fundamental reference voltage signal.

[0105] The mean of the index and the mean of the signal within the window are calculated as basic statistics; and the trend slope is calculated based on the statistics to predict the compensation signal value of the next sampling point.

[0106] The prediction process relies on the historical variation patterns of the signal, assuming that the signal exhibits approximately linear changes within a short time window, making it suitable for the characteristics of power electronic signals under high-frequency sampling. The prediction results are directly used for subsequent risk assessment, ensuring real-time response.

[0107] 2. Overflow Risk Assessment: Using the predicted signal value, determine whether the summation result may exceed the representation range of the digital system. The digital system uses fixed-point representation, with a normalization range of [-1, 1]. The overflow threshold is the fixed-point representation range, for example, an overflow threshold of 0.95, reserving a 5% margin to cope with uncertainty.

[0108] The risk coefficient is assessed by adding the predicted value of the compensated signal to the predicted value of the fundamental signal. This risk coefficient quantifies the severity of the potential spillover. Risk levels are categorized as low, medium, and high, each corresponding to different response strategies. The assessment process is executed every 10 control cycles to balance computational overhead and response speed. The risk coefficient formula is as follows: In the formula, R is the risk coefficient; To predict the sum; R represents the overflow threshold. If R > 0, it indicates a risk of overflow; otherwise, there is no risk.

[0109] For example, if the forecast shows a rapid rise in the signal, indicating a high risk factor, gain adjustment is triggered immediately; otherwise, normal operation is maintained.

[0110] 3. Dynamic gain adjustment stage: The compression gain is dynamically applied to the compensation signal according to the risk level. The risk coefficient R is used as the input error signal. The proportional-integral (PI) controller is used to dynamically adjust the compression gain to ensure that the summation result does not overflow. At the same time, the circulating current cancellation effect is maintained by phase holding.

[0111] The algorithm uses a proportional-integral controller to calculate the gain value and adjusts it in real time based on the risk coefficient. Gain adjustment is smooth, avoiding distortion introduced by abrupt changes; once the risk is eliminated, the gain slowly recovers to its normal value. During integration, the adjusted compensation signal is fed into the adder, while the original saturation processing is retained as a backup mechanism. Gain adjustment is activated only when the risk level is medium or high; after the risk is eliminated, the gain slowly recovers to 1, avoiding distortion introduced by abrupt changes, with a recovery time constant set to 10ms. Furthermore, the entire process is implemented in a digital signal processor, resulting in low computational overhead and only increasing the processor load by approximately 1%.

[0112] S7. The composite modulation reference signal is input to the pulse width modulator and compared with a fixed-frequency triangular carrier wave to generate a pulse width modulation signal sequence that drives the power semiconductor switching devices inside the parallel converter unit, thereby realizing injection-type cancellation control of potential high-frequency circulating current.

[0113] In step S7, the composite modulation reference signal is input to the pulse width modulator and compared with a fixed-frequency triangular carrier wave to generate a pulse width modulated signal sequence that drives the power semiconductor switching devices inside the parallel converter unit. This pulse width modulator is a digital circuit implemented in a field-programmable gate array (FPGA), comprising a digital adder, a fundamental sinusoidal read-only memory (WSROM), a digital comparator, and a high-frequency counter. The WSROM outputs fundamental reference voltage sampling points according to external frequency and amplitude commands. The digital adder adds the fundamental reference voltage sampling points to the compensation voltage sampling points output by the predictive harmonic injection compensation module. The high-frequency counter generates a high-precision digital triangular carrier wave sequence with a frequency equal to the converter switching frequency and a resolution of 12 bits. The digital comparator compares the added composite signal with the digital triangular carrier wave sequence, and its output is the high-resolution pulse width modulated signal.

[0114] This signal is directly connected to the gate drive circuit to control the on and off states of the insulated gate bipolar transistor or silicon carbide metal oxide semiconductor field-effect transistor, thereby reconstructing a voltage waveform containing a compensation component at the output and actively canceling high-frequency circulating current.

[0115] This invention also provides a system for implementing the multi-machine parallel cooperative control method of the lightweight converter, the architecture of which is shown in the figure below. Figure 2 As shown, the system includes a high-frequency transient data acquisition module, a virtual impedance state observation module, a predictive harmonic injection compensation module, and a local pulse width modulation signal generation module; the system is applied in a parallel AC converter unit.

[0116] The input terminal of the high-frequency transient data acquisition module is electrically connected to the output terminal of the parallel converter unit, and is used to synchronously acquire the voltage and current waveforms output by the parallel converter unit and convert them into a high-precision digital time series.

[0117] The virtual impedance state observation module is connected to the data output terminal of the high-frequency transient data acquisition module. It is used to perform harmonic analysis on the received digital time series and identify the equivalent network model of the entire parallel system online based on the analysis results, thereby calculating the potential high-frequency circulating current vector.

[0118] The predicted harmonic injection compensation module is connected to the data output terminal of the virtual impedance state observation module, and is used to generate a digital compensation voltage waveform that cancels out the potential circulating current based on the potential high-frequency circulating current vector.

[0119] The local pulse width modulation signal generation module has two input terminals. Input terminal 1 is used to receive an externally given fundamental reference voltage command, and input terminal 2 is used to receive the digital compensation voltage waveform generated by the predictive harmonic injection compensation module. The local pulse width modulation signal generation module superimposes the two input signals and generates the final pulse width modulation control signal for driving the power devices of the parallel converter unit based on the superimposed composite signal.

[0120] The high-frequency transient data acquisition module includes a Hall effect current sensor, a resistive voltage divider, and an analog-to-digital converter (ADC). The Hall effect current sensor is connected in series with the output phase line of the converter. The resistive voltage divider is connected across the output line and the neutral line of the converter. The ADC has an 18-bit conversion accuracy, and its sampling clock is provided by a local crystal oscillator calibrated with a GPS timing signal to ensure that the data acquisition of all parallel units is synchronized at the sub-microsecond level on the time base.

[0121] The core of the virtual impedance state observation module is a digital signal processor, which is pre-configured with a Goertzel algorithm module for harmonic decomposition and an extended Kalman filter algorithm module for system parameter identification. The Goertzel algorithm module is configured to calculate only a few preset high-order harmonic frequencies to reduce computational complexity. The extended Kalman filter algorithm module uses locally measured harmonic voltage and current as input to perform state estimation on a nonlinear state-space model describing the harmonic interaction behavior of a parallel system, and outputs accurate estimates of the system interconnect impedance and circulating current sources.

[0122] The predictive harmonic injection compensation module includes a lookup table unit and a waveform synthesis unit. The lookup table unit stores parameters of the optimal compensation harmonic components corresponding to different circulating current amplitudes and phases, calculated in advance. The predictive harmonic injection compensation module first retrieves the optimal set of compensation harmonic parameters from the lookup table unit based on the input potential high-frequency circulating current vector. Then, the waveform synthesis unit generates a multi-frequency composite compensation voltage digital waveform in real time based on the parameter set using direct digital frequency synthesis technology.

[0123] The local pulse width modulation signal generation module is a digital circuit implemented in a field-programmable gate array (FPGA), comprising a digital adder, a fundamental sine read-only memory, a digital comparator, and a high-frequency counter. The fundamental sine read-only memory outputs fundamental reference voltage sampling points according to external frequency and amplitude commands. The digital adder adds the fundamental reference voltage sampling points to the compensation voltage sampling points output by the predictive harmonic injection compensation module. The high-frequency counter generates a high-precision digital triangular wave carrier sequence. The digital comparator compares the added composite signal with the digital triangular wave carrier sequence, and its output is the high-resolution pulse width modulation signal.

[0124] This embodiment achieves high-frequency circulating current feedforward suppression without communication through the aforementioned method and system. Each converter unit relies solely on local high-precision, high-sampling-rate voltage and current measurements, combined with efficient harmonic analysis and system identification algorithms, to autonomously complete circulating current prediction and compensation, achieving a response speed at the microsecond level, significantly outperforming feedback control schemes that rely on communication. This solution improves system reliability, scalability, and electromagnetic compatibility, making it suitable for multi-machine parallel applications in data centers, new energy power plants, and ship power systems, where lightweight design and high reliability are stringent requirements.

Claims

1. A method for multi-machine parallel coordinated control of a lightweight converter, characterized in that, Includes the following steps: S1. Real-time acquisition of voltage timing data and current timing data of the local output ports of each parallel converter unit; S2. Perform harmonic analysis on the collected voltage and current time-series data to extract electrical information of several harmonic components within a preset high-frequency band; the electrical information includes voltage amplitude, voltage phase, current amplitude, and current phase information; S3. Based on the electrical information of the harmonic components, construct the multi-node admittance matrix of the parallel converter unit, and use the recursive least squares method to identify the matrix parameters online, and solve the system state equation characterizing the high-frequency dynamic characteristics of the entire parallel system. S4. Using the system state equation, calculate the amplitude and phase angle of the potential high-frequency circulating current superimposed on the common AC bus induced by the inherent parameter differences between each parallel converter unit, and form the feedforward compensation target vector; S5. Based on the feedforward compensation target vector, synthesize a multi-frequency superimposed digital compensation voltage signal; S6. The digital compensation voltage signal is digitally added point by point to the fundamental sinusoidal reference voltage signal of the parallel converter unit to generate a composite modulation reference signal; S7. The composite modulation reference signal is input to the pulse width modulator and compared with a fixed-frequency triangular carrier wave to generate a pulse width modulation signal sequence that drives the power semiconductor switching devices inside the parallel converter unit, thereby realizing injection-type cancellation control of potential high-frequency circulating current.

2. The multi-machine parallel cooperative control method for lightweight converters according to claim 1, characterized in that, In step S1, the sampling frequency of the acquisition process is set to 20 to 50 times the switching frequency of the parallel converter unit.

3. The multi-machine parallel coordinated control method for lightweight converters according to claim 1, characterized in that, Step S1 specifically includes the following steps: A sampling voltage signal that is linearly proportional to the output voltage is obtained by using a high-impedance precision resistor voltage divider network connected in parallel with the output terminal of the parallel converter unit. A high-bandwidth current sensor based on the closed-loop fluxgate principle, connected in series in the output circuit of the parallel converter unit, is used to acquire a sampled current signal that is linearly proportional to the output current. The sampled voltage signal and sampled current signal are respectively input to a dual-channel, 16-bit resolution, synchronous sampling analog-to-digital converter with a sampling rate of more than 1 million times per second for quantization processing to generate discrete digital voltage sequences and digital current sequences.

4. The multi-machine parallel coordinated control method for lightweight converters according to claim 1, characterized in that, Step S2 specifically includes the following steps: A field-programmable gate array is set as a coprocessor, which has a fast Fourier transform algorithm core for fixed-point arithmetic embedded inside. The digital voltage sequence and the digital current sequence are sent into the field-programmable gate array in the form of fixed-length data frames; The Fast Fourier Transform algorithm transforms each data frame and outputs complete spectrum data covering the DC component to the Nyquist frequency. The spectrum data includes amplitude and phase frequency information at each frequency point. From the spectrum data, the odd-numbered harmonic frequencies of the switching frequency are extracted, specifically the complex representations of harmonic voltage and harmonic current at 3 times, 5 times, 7 times, 9 times, and 11 times the switching frequency.

5. The multi-machine parallel coordinated control method for lightweight converters according to claim 1, characterized in that, Step S3 specifically includes the following steps: Each parallel converter unit is equivalent to a combination of a controlled current source and parallel admittance at a specific harmonic frequency. The common AC bus is equivalent to an impedance node with lumped parameters; Based on Kirchhoff's current law, a set of linear equations is established to describe the relationship between the harmonic currents of all parallel converter units and the harmonic voltage of the common AC bus. The coefficient matrix of the equation system is the multi-node admittance matrix, where the diagonal elements are the self-admittances of each unit and the off-diagonal elements are the mutual admittances between units. Using a Kalman filter, the locally measured harmonic voltage and harmonic current are taken as observations, and the elements of the multi-node admittance matrix are taken as state variables to be estimated. Through an iterative filtering process, the accurate admittance matrix parameters are identified in real time, thereby obtaining the system state equation that can accurately reflect the current operating conditions of the system.

6. The multi-machine parallel coordinated control method for lightweight converters according to claim 1, characterized in that, Step S5 is as follows: Inside the digital signal processor, an independent digital sine wave generator is instantiated for each harmonic frequency that needs to be compensated; The amplitude and phase angle of each harmonic frequency in the feedforward compensation target vector are respectively set as the amplitude control word and phase control word of the corresponding digital sine wave generator; All digital sine wave generators are started synchronously, and their output discrete sine wave sequences are accumulated point by point to form the final digital compensation voltage signal time sequence containing multiple harmonic components, thus obtaining a multi-frequency superimposed digital compensation voltage signal.

7. The multi-machine parallel coordinated control method for lightweight converters according to claim 6, characterized in that, Each frequency component of the digital compensation voltage signal is 180 degrees out of phase with the corresponding frequency component of the potential high-frequency circulating current, and its amplitude is proportional to the product of the corresponding frequency component of the potential high-frequency circulating current and the equivalent impedance of the common AC bus.

8. A system for implementing the multi-machine parallel cooperative control method for the lightweight converter according to any one of claims 1 to 7, characterized in that, The system includes a high-frequency transient data acquisition module, a virtual impedance state observation module, a predictive harmonic injection compensation module, and a local pulse width modulation signal generation module; the system is applied in a parallel AC unit. The input terminal of the high-frequency transient data acquisition module is electrically connected to the output terminal of the parallel converter unit, and is used to synchronously acquire the voltage and current waveforms output by the parallel converter unit and convert them into a high-precision digital time series. The virtual impedance state observation module is connected to the data output terminal of the high-frequency transient data acquisition module. It is used to perform harmonic analysis on the received digital time series and identify the equivalent network model of the entire parallel system online based on the analysis results, thereby calculating the potential high-frequency circulating current vector. The predicted harmonic injection compensation module is connected to the data output terminal of the virtual impedance state observation module, and is used to generate a digital compensation voltage waveform that cancels out the potential circulating current based on the potential high-frequency circulating current vector. The local pulse width modulation signal generation module has two input terminals. Input terminal 1 is used to receive an externally given fundamental reference voltage command, and input terminal 2 is used to receive the digital compensation voltage waveform generated by the predictive harmonic injection compensation module. The local pulse width modulation signal generation module superimposes the two input signals and generates the final pulse width modulation control signal for driving the power devices of the parallel converter unit based on the superimposed composite signal.

9. The system according to claim 8, characterized in that, The high-frequency transient data acquisition module includes a Hall effect current sensor, a resistive voltage divider, and an analog-to-digital converter (ADC). The Hall effect current sensor is connected in series with the output phase line of the converter. The resistive voltage divider is connected across the output line and the neutral line of the converter. The ADC has an 18-bit conversion accuracy, and its sampling clock is provided by a local crystal oscillator calibrated with a GPS timing signal to ensure that the data acquisition of all parallel units is synchronized at the sub-microsecond level on the time base. The core of the virtual impedance state observation module is a digital signal processor, which is pre-configured with a Goertzel algorithm module for harmonic decomposition and an extended Kalman filter algorithm module for system parameter identification. The Goertzel algorithm module is configured to calculate only a few preset high-order harmonic frequencies to reduce computational complexity. The extended Kalman filter algorithm module uses locally measured harmonic voltage and current as input to perform state estimation on a nonlinear state-space model describing the harmonic interaction behavior of a parallel system, and outputs accurate estimates of the system interconnection impedance and circulating current sources. The predictive harmonic injection compensation module includes a lookup table unit and a waveform synthesis unit. The lookup table unit stores parameters of the optimal compensation harmonic components corresponding to different circulating current amplitudes and phases, calculated in advance. The predictive harmonic injection compensation module first retrieves the optimal set of compensation harmonic parameters from the lookup table unit based on the input potential high-frequency circulating current vector. Then, the waveform synthesis unit generates a multi-frequency composite compensation voltage digital waveform in real time based on the parameter set using direct digital frequency synthesis technology. The local pulse width modulation signal generation module is a digital circuit implemented in a field-programmable gate array (FPGA), comprising a digital adder, a fundamental sine read-only memory, a digital comparator, and a high-frequency counter. The fundamental sine read-only memory outputs fundamental reference voltage sampling points according to external frequency and amplitude commands. The digital adder adds the fundamental reference voltage sampling points to the compensation voltage sampling points output by the predictive harmonic injection compensation module. The high-frequency counter generates a high-precision digital triangular wave carrier sequence. The digital comparator compares the added composite signal with the digital triangular wave carrier sequence, and its output is the high-resolution pulse width modulation signal.

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